VLSIShriVithal

Design Education & Research Institute‟s LY-BTECH

COLLEGE OF ENGINEERING, PANDHARPUR
P.B. No. 54, Gopalpur - Ranjani Road, Gopalpur, Tal.:Pandharpur- 413304, Dist.:Solapur (MH)
Contact No.: 9545553888, 9545553757, E-mail:coe@sveri.ac.in, Website:www.sveri.ac.in
Approved by A.I.C.T.E., New Delhi and affiliated to PunyashlokAhilyadeviHolkarSolapur University, Solapur
NAAC A+ with 3.46 CGPA out of 4.00, AnISO 9001-2015 Certified Institute,Accredited by the Institution of
Engineers, Kolkata and TCS, Pune.

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING

LIST OF EXPERIMENT
SUBJECT: VLSI Design- ET413
CLASS: LY B.Tech SEM-I A.Y.: 2023-24

Sr.No Name of Experiment CO BL PI

Design and Implementation of half adder and full adder using
1 ET413.2 BL 6 4.2.1
Verilog HDL and write test bench
Design and Implementation of 4 bit adder using structural style
2 ET413.2 BL 6 4.2.1
modeling using Verilog HDL and write test bench
Design and Implementation of code converters using Verilog
3 ET413.2 BL 6 4.2.1
HDL and write test bench
Design and Implementation of comparators using Verilog
4 ET413.2 BL 6 4.2.1
HDL and write test bench
Design and Implementation of encoder and decoder using
5 ET413.2 BL 6 4.2.1
Verilog HDL and write test bench
Design and Implementation of multiplexer and de-multiplexer
6 ET413.2 BL 6 4.2.1
using Verilog HDL and write test bench
Design and Implementation of flip flops using Verilog HDL
7 ET413.3 BL 6 4.2.1
and write test bench
Design and Implementation of asynchronous and synchronous
8 ET413.3 BL 6 4.2.1
counters using Verilog HDL and write test bench
9 Design and Implementation of Logic Gates using CMOS Logic ET413.5 BL 6 4.2.1
Design and Implementation of Universal Logic Gates using
10 ET413.5 BL 6 4.2.1
CMOS Logic

(Ms. S. A. Atole) (Mr. S. D. Indalkar) Dr.Mrs.M.M.Pawar

Practical Teacher HOD E&TC

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VLSI Design CO statements

SR. CO Co Statement Blooms PI

NO. Level

Explain the different syntax of Verilog BL 2

1 ET413-1 2.1.2,4.3.2
HDL language. UNDERSTAND

Analyze combinational circuits using BL 4

2.1.2,2.4.2,3.4.1,
2 ET413-2 Verilog HDL. ANALYZE
4.2.1,4.3.2
BL 6 CREATE

Analyze sequential logic circuits using BL 4

2.1.2,2.4.2,3.4.1,
3 ET413-3 Verilog HDL. ANALYZE
4.2.1,4.3.2
BL 6 CREATE

Describe MOS transistor theory and BL 2

4 ET413-4 behavior of E-MOSFET UNDERSTAND 2.1.2,4.3.2
BL 6 CREATE

Analyze combinational logic circuit BL 4 2.1.2,2.4.2,3.4.1,

5 ET413-5
design using E-MOSFETs. ANALYZE 4.2.1,4.3.2

Describe the architecture and internal BL 2

6 ET413-6 2.1.2
components of CPLD and FPGA. UNDERSTAND

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EXPERIMENT NO.1

AIM: Design and Implementation of half adder and full adder using Verilog HDL and write test
bench

SOFTWARE: VERILOG HDL COMPILER(Jdoodle online compiler/ iverilog Verilog

Compiler)

OBJECTIVE:

 To Study and develop Verilog codes in behavioral modeling style.

 To study and implement half adder and full adder using Verilog HDL along with
testbench.

OUTCOMES:
Students will be able to implement combinational logic circuits using Verilog HDL

THEORY:
Verilog Compiler
A Verilog compiler, often referred to as a Verilog simulator or Verilog synthesis tool, is a
software tool used in digital circuit design to process and analyze Verilog hardware description
language (HDL) code. Verilog is a popular HDL used for describing digital systems and circuits
at various levels of abstraction, from behavioral to gate-level.

The primary purposes of a Verilog compiler include:

Simulation: Verilog compilers enable engineers to simulate the behavior of digital circuits
described in Verilog. Simulation allows designers to verify the correctness of their designs,
identify potential bugs, and analyze the circuit's performance under different conditions.

Synthesis: Verilog code can be synthesized into hardware representations, such as gate-level
netlists or field-programmable gate array (FPGA) configurations. Synthesis tools map the high-
level design described in Verilog to actual hardware components, optimizing for factors like
timing, area, and power consumption.

Testbench Development: Verilog Test benches are used to simulate and analyze designs
without the need for any physical hardware or any hardware device. The most significant

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advantage of this is that you can inspect every signal /variable (reg, wire in Verilog) in the
design. This certainly can be a time saver when you start writing the code or loading it onto the
FPGA. In reality, only a few signals are taken out to the external pins. Though, you could not
get this all for free. Firstly, you need to simulate your design; you must first write the design
corresponding test benches. A test bench is, in fact, just another Verilog file, and this Verilog file
or code you write as a testbench is not quite the same as the Verilog you write in your designs.
Because Verilog design should be synthesizable according to your hardware meaning, but the
Verilog testbench you write in a testbench does not need to be synthesizable because you will
only simulate it.

The file to be included and the name of the module changes, but the basic structure of the
testbench remains the same in all the three modeling styles i.e. Behavioral, Data flow, Gate
Level

Behavioral modeling

Behavioral modeling is the highest level of abstraction in the Verilog HDL. Behavioral models
in Verilog contain procedural assignment statements, which control the simulation and
manipulate variables of the data types. This level of abstraction simulates the behavior of the
circuits without specifying the details.

Part-A

Half Adder

The simplest digital circuit used to implement the binary addition is the half adder which has two
inputs and two outputs. Each input of the half adder represents the binary digit to be added. The
two output bits of the half adder are called SUM and CARRY; SUM bit represents the sum of the
two digits and as the name suggests the carry bit represents the carry of the addition of two
binary digits. The digital logic circuit that implements the operation of the half adder is as shown

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Truth Table

Example using Verilog HDL

//Verilog Code for half adder
modulehalf_adder_d ( input a,b,outputsum,carry);
assign sum = a ^ b;
assign carry = a & b;
endmodule
//testbench
modulehalf_adder_tb;
rega,b;
wiresum,carry;
half_adder_duut(a,b,sum,carry);
initial begin
a = 0; b = 0;
#10 a = 0; b = 1;
#10 a = 1; b = 0;
#10 a = 1; b = 1;
#10
$finish();
end
initial begin
$display ("Displaying results for half adder");
$monitor ("time%t | a = %d| b = %d| sum = %d| carry = %d", $time, a, b, sum, carry);
end
endmodule

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Output

Part-B
Full Adder
A Full Adder is the digital Circuit which implements addition operation on three binary digits.
Two of the three binary digits are significant digits A and B and one is the carry input (C-In) bit
carried from the previous-less significant stage. Thus the Full Adder operates on these three
binary digits to generate two binary digits at its output referred to as Sum (SUM) and Carry-Out
(C-out). The truth table of the Full Adder is as shown in the following figure

Truth Table

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Example using Verilog HDL

//Verilog code for full adder
`timescale 1ns / 1ps
module full_adder( A, B, Cin, S, Cout);
input wire A, B, Cin;
outputreg S, Cout;
always @(A or B or Cin)
begin
S = A ^ B ^ Cin;
Cout = A&B | (A^B) &Cin;
end
endmodule
//testbench
//timescale directive
`timescale 1ns / 1ps
modulefull_adder_tb;
//declare testbench variables
reg A, B, Cin;
wire S, Cout;
//instantiate the design module and connect to the testbench variables
full_adder instantiation(A,B,Cin,S,Cout);
initial
begin
//set stimulus to test the code
A=0;
B=0;
Cin=0;
#100 $finish;
end
//provide the toggling input (just like truth table input)
//this acts as the clock input
always #10 A=~A;

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always #20 B=~B;

always #40 Cin=~Cin;
//display output if there‟s a change in the input event
always @(A or B or Cin)
$monitor("At TIME(in ns)=%t, A=%d B=%d Cin=%d S = %d Cout = %d", $time, A, B,
Cin, S, Cout);
endmodule

Output

Conclusion-

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EXPERIMENT NO.2

AIM: Design and Implementation of 4 bit adder using structural style modeling using
Verilog HDL and write test bench

SOFTWARE:VERILOG HDL COMPILER(Jdoodle online compiler/ iverilog Verilog

Compiler)

OBJECTIVE:

 To Study and develop Verilog codes in behavioral modeling style.

 To study and implement 4 bit adder using structural style modeling using Verilog HDL
along with testbench.

OUTCOMES:
Students will be able to implement combinational logic circuits using Verilog HDL

THEORY:
4 Bit Adder
4 bit Adder is a digital circuit that has two four bit inputs and a 4 bit sum as output. It generates a
1 bit carry at the output. In the shown block diagram, we have used the Full adder for making a 4
bit adder. The Full adder has been instantiated four times in the main module. The Full adder
takes two inputs as „A‟ and „B‟ and „cin‟ as the third input.
The equations of the Full adder are :-Sum = (a xor b xor cin) = a^b^cin
Cout = (a and b ) or (b and cin ) or (cin and a ) = (a & b) | ( b & cin ) | ( cin & a )

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 The 'A' and 'B' are the augend, and addend bits are defined by the subscript numbers. The
subscripts start from right to left, and the lower-order bit is defined by subscript '0'.
 The C0, C1, C2, and C3 are the carry inputs which are connected together as a chain
using Full Adder. The C4 is the carry output produced by the last Full-Adder.
 The Cout of the first Adder is connected as the Cin of the next Full-Adder.
 The S0, S1, S2, and S3 are the sum outputs that produce the sum of augend and addend
bits.

Example using Verilog HDL

//Verilog Code for 4 bit adder
module adder_four_bit(
output [3:0]sum,
output cout ,
input [3:0]a,b);
wire c1,c2,c3,c4;
full_3 ad0( .a(a[0]), .b(b[0]),.cin(1'b0), .s(sum[0]), .cout(c1));
full_3 ad1( .a(a[1]), .b(b[1]),.cin(c1), .s(sum[1]), .cout(c2));
full_3 ad2( .a(a[2]), .b(b[2]),.cin(c2), .s(sum[2]), .cout(c3));
full_3 ad3( .a(a[3]), .b(b[3]),.cin(c3), .s(sum[3]), .cout(c4));
assign cout= c4;
endmodule
module full_3(a,b,cin,s,cout);
input a,b,cin;
output s, cout;
assign s=a^b^cin;
assign cout = (a&b) | (b&cin) | (cin&a);
endmodule

//Test Bench
//The test bench check that each combination of select lines connects the appropriate input to the
output. The test bench code in Verilog for 4 Bit Adder using Full Adder is given below :
`timescale 1ns / 1ps
module adder_4bit_test;
reg [3:0] a;
reg [3:0] b;
assign cin=1'b0;

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wire [3:0] s;
wire cout;
adder_four_bit testadd(.sum(s),.cout(cout),.a(a),.b(b));
initial
begin
a=4'b0000;
b=4'b0001;
#30
a=4'b0001;
b=4'b0001;
#30
a=4'b0010;
b=4'b0001;
#30;
a=4'b0100;
b=4'b0101;
#30;
a=4'b1100;
b=4'b1101;
#30;
$finish;
end
initial begin
$display ("Displaying results for half adder");
$monitor(" time=%0d A=%b B=%b Cin=%b Sum=%b Cout=%b",$time,a,b,cin,s,cout);
end
endmodule

Output

Conclusion-

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EXPERIMENT NO.3

AIM: Design and Implementation of code converters using Verilog HDL and write test
bench

SOFTWARE: VERILOG HDL COMPILER(Jdoodle online compiler/ iverilog Verilog

Compiler)

OBJECTIVE:

 To Study and develop Verilog codes in behavioral modeling style.

 To study and implement 4-bit Binary to Gray Code converter using Verilog HDL along
with testbench.

OUTCOMES:
Students will be able to implement combinational logic circuits using Verilog HDL

THEORY:
Binary to Gray Converter
Binary to Gray code conversion is a technique used in digital electronics to transform
binary numbers into their equivalent Gray code representation. Gray code is a binary numeral
system where each successive value differs by only one bit position, making it useful in
applications where errors in counting or sensing can occur due to noise or interference.
The conversion process involves taking the binary code and performing exclusive OR
(XOR) operations between adjacent bits to obtain the corresponding Gray code.
The most significant bit (MSB) of the Gray code is the same as that of the binary code,
while the remaining bits are obtained by XORing adjacent bits of the binary code. For example,
the 4-bit binary number 1101 can be converted to its equivalent Gray code as follows:

Binary: 1 1 0 1
Gray: 1 0 1 1
 MSB is 1, so it remains the same.
 The second bit is obtained by XORing the first and second bits of the binary code: 1
XOR 1 = 0.
 The third bit is obtained by XORing the second and third bits of the binary code: 1 XOR
0 = 1.
 The fourth bit is obtained by XORing the third and fourth bits of the binary code: 0 XOR
1 = 1.
The resulting Gray code is 1011.

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Truth Table

4-Bit Binary Code 4-Bit Gray Code

0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
1010 1111
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000
G4=∑m(8,9,10,11,12,13,14,15)

G3=∑m(4,5,6,7,8,9,10,11)

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G2=∑m(2,3,4,5,10,11,12,13)

G1=∑m(1,2,5,6,9,10,13,14)

Binary to Gray Code Converter Using Logic Gates

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Example using Verilog HDL

//Verilog Code 4-bit Binary to Gray by using Behavioural Modelling
`timescale 1ns / 1ps
module Binary_to_Gray( input [3:0] b,output reg[3:0] g);
always@(b)
begin
g[0]=b[1]^b[0];
g[1]=b[2]^b[1];
g[2]=b[3]^b[2];
g[3]=b[3];
end
endmodule
//techtbench
`timescale 1ns / 1ps
module Binary_to_Gray_tb;
reg [3:0]b;
wire [3:0]g;
Binary_to_Gray uut (b,g);
initial begin
b=4'b0000;
#10 b=4'b0001;
#10 b=4'b0010;
#10 b=4'b0011;
#10 b=4'b0100;
#10 b=4'b0101;
#10 b=4'b0110;
#10 b=4'b0111;
#10 b=4'b1000;
#10 b=4'b1001;
#10 b=4'b1010;
#10 b=4'b1011;
#10 b=4'b1100;
#10 b=4'b1101;
#10 b=4'b1110;
#10 b=4'b1111;
end
initial begin
$display ("Displaying results for 4-Bit Binary To Gray Code Converter");
$monitor(" time=%0d Binary=%b Equivalent Gray=%b ",$time,b,g);
end
endmodule

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Output

Conclusion-

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EXPERIMENT NO.4

AIM: Design and Implementation of comparators using Verilog HDL and write test
bench

SOFTWARE: VERILOG HDL COMPILER(Jdoodle online compiler/ iverilog Verilog

Compiler)

OBJECTIVE:

 To Study and develop Verilog codes in behavioral modeling style.

 To study and implement 4-bit comparator using Verilog HDL along with testbench.

OUTCOMES:
Students will be able to implement combinational logic circuits using Verilog HDL

THEORY:
Magnitude Comparator
A magnitude digital Comparator is a combinational circuit that compares two digital or
binary numbers in order to find out whether one binary number is equal, less than, or greater than
the other binary number. We logically design a circuit for which we will have two inputs one for
A and the other for B and have three output terminals, one for A > B condition, one for A = B
condition, and one for A < B condition.

The circuit works by comparing the bits of the two numbers starting from the most
significant bit (MSB) and moving toward the least significant bit (LSB). At each bit position, the
two corresponding bits of the numbers are compared. If the bit in the first number is greater than
the corresponding bit in the second number, the A>B output is set to 1, and the circuit
immediately determines that the first number is greater than the second. Similarly, if the bit in
the second number is greater than the corresponding bit in the first number, the A<B output is set
to 1, and the circuit immediately determines that the first number is less than the second.

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If the two corresponding bits are equal, the circuit moves to the next bit position and
compares the next pair of bits. This process continues until all the bits have been compared. If at
any point in the comparison, the circuit determines that the first number is greater or less than the
second number, the comparison is terminated, and the appropriate output is generated.

If all the bits are equal, the circuit generates an A=B output, indicating that the two
numbers are equal.

Example using Verilog HDL

//declare the Verilog module - The inputs and output signals.

module comparator(Data_in_A,//input A

Data_in_B,//input B

less,//high when A is less than B

equal,//high when A is equal to B

greater//high when A is greater than B

);//what are the input ports.

input [3:0]Data_in_A;
input [3:0]Data_in_B;//What are the output ports.

output less;
output equal;
output greater;//Internal variables

reg less;
reg equal;
reg greater;//When the inputs and A or B are changed execute this block

always @(Data_in_A or Data_in_B)

begin
if(Data_in_A > Data_in_B)
begin//check if A is bigger than B.
less = 0;

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equal = 0;
greater = 1;
end
else if(Data_in_A == Data_in_B)
begin //Check if A is equal to B

less = 0;
equal = 1;
greater = 0;
end
else
begin//Otherwise - check for A less than B.
less = 1;
equal = 0;
greater = 0;
end
end
endmodule

module comparator_tb;

// Declare signals for testbench

reg [3:0] Data_in_A;
reg [3:0] Data_in_B;
wire less;
wire equal;
wire greater;

// Instantiate the comparator module

comparator UUT (
.Data_in_A(Data_in_A),
.Data_in_B(Data_in_B),
.less(less),
.equal(equal),
.greater(greater)
);

// Stimulus generation
initial begin
$display("Testing Comparator");
$display("Data_in_A Data_in_B less equal greater");

// Test case 1: A > B

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Data_in_A = 4'b1101;
Data_in_B = 4'b1010;
#10; // Wait for a few simulation time units
$display("%b %b %b %b %b", Data_in_A, Data_in_B, less, equal, greater);

// Test case 2: A == B
Data_in_A = 4'b0101;
Data_in_B = 4'b0101;
#10;
$display("%b %b %b %b %b", Data_in_A, Data_in_B, less, equal, greater);

// Test case 3: A < B

Data_in_A = 4'b0010;
Data_in_B = 4'b1011;
#10;
$display("%b %b %b %b %b", Data_in_A, Data_in_B, less, equal, greater);

// Add more test cases as needed

$finish; // Finish simulation

end

endmodule

Output

Conclusion-

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EXPERIMENT NO.5

AIM: Design and Implementation of encoder and decoder using Verilog HDL and write test
bench
SOFTWARE: VERILOG HDL COMPILER(Jdoodle online compiler/ iverilog Verilog
Compiler)

OBJECTIVE:

 To Study and develop Verilog codes in behavioral modeling style.

 To study and implement encoder and decoder using Verilog HDL along with testbench.

OUTCOMES:
Students will be able to implement combinational logic circuits using Verilog HDL

THEORY:

Encoder
An encoder is a digital circuit that converts a set of binary inputs into a unique
binary code. The binary code represents the position of the input and is used to identify
the specific input that is active. Encoders are commonly used in digital systems to
convert a parallel set of inputs into a serial code.
The basic principle of an encoder is to assign a unique binary code to each
possible input. For example, a 2-to-4 line encoder has 2 input lines and 4 output lines
and assigns a unique 4-bit binary code to each of the 2^2 = 4 possible input
combinations. The output of an encoder is usually active low, meaning that only one
output is active (low) at any given time, and the remaining outputs are inactive (high).
The active low output is selected based on the binary code assigned to the active input.
There are different types of encoders, including priority encoders, which assign a
priority to each input, and binary-weighted encoders, which use a binary weighting
system to assign binary codes to inputs. In summary, an encoder is a digital circuit that
converts a set of binary inputs into a unique binary code that represents the position of
the input. Encoders are widely used in digital systems to convert parallel inputs into
serial codes.
An Encoder is a combinational circuit that performs the reverse operation of
a Decoder. It has a maximum of 2^n input lines and ‘n’ output lines, hence it encodes
the information from 2^n inputs into an n-bit code. It will produce a binary code

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equivalent to the input, which is active High. Therefore, the encoder encodes 2^n input
lines with „n‟ bits.

Binary decoder
A binary decoder is a digital circuit that converts a binary code into a set of
outputs. The binary code represents the position of the desired output and is used to
select the specific output that is active. Binary decoders are the inverse of encoders and
are commonly used in digital systems to convert a serial code into a parallel set of
outputs.
The basic principle of a binary decoder is to assign a unique output to each
possible binary code. For example, a binary decoder with 4 inputs and 2^4 = 16 outputs
can assign a unique output to each of the 16 possible 4-bit binary codes.
The inputs of a binary decoder are usually active low, meaning that only one
input is active (low) at any given time, and the remaining inputs are inactive (high). The
active low input is used to select the specific output that is active.
There are different types of binary decoders, including priority decoders, which
assign a priority to each output, and error-detecting decoders, which can detect errors in
the binary code and generate an error signal.
In summary, a binary decoder is a digital circuit that converts a binary code into
a set of outputs. Binary decoders are the inverse of encoders and are widely used in
digital systems to convert serial codes into parallel outputs.

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Encoder Example using Verilog HDL

module encoder_4_2(a,b,c,d,x,y);
output x,y;
input a,b,c,d;
assign x = b | d;
assign y = c | d;
endmodule
module encoder_4_2_test;
reg a,b,c,d;
wire x,y;
encoder_4_2 encoder_4_2_test(a,b,c,d,x,y);
initial
begin
#000 a=0; b=0;c=0;d=1;
#100 a=0; b=0;c=1;d=0;
#100 a=0; b=1;c=0;d=0;
#100 a=1; b=0;c=0;d=0;
end
initial
begin
$display("Displaying Results for Encoder");
$monitor($time,"a=%b,b=%b,c=%b,d=%b,x=%b,y=%b",a,b,c,d,x,y);
end
endmodule

Output

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Decoder Example using Verilog HDL

module decoder_2_4(a,b,w,x,y,z);
output w,x,y,z;
input a,b;
assign w = (~a) & (~b);
assign x = (~a) & b;
assign y = a & (~b);
assign z = a & b;
endmodule
module decoder_2_4_test;
reg a,b;
wire w,x,y,z;
decoder_2_4 decoder_2_4_test(a,b,w,x,y,z);
initial
begin
#000 a=0; b=0;
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;
end
initial
begin
$display("Displaying Results for Decoder");
$monitor($time,"a=%b,b=%b,w=%b,x=%b,y=%b,z=%b",a,b,w,x,y,z);
end
endmodule

Output

Conclusion-

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VLSI Design LY-BTECH

EXPERIMENT NO.6

AIM: Design and Implementation of multiplexer and de-multiplexer using Verilog HDL and
write test bench

SOFTWARE: VERILOG HDL COMPILER(Jdoodle online compiler/ iverilog Verilog

Compiler)

OBJECTIVE:

 To Study and develop Verilog codes in behavioral modeling style.

 To study and implement multiplexer and de-multiplexer using Verilog HDL along with
testbench.

OUTCOMES:
Students will be able to implement combinational logic circuits using Verilog HDL

THEORY:

Multiplexter
Multiplexer is a data selector which takes several inputs and gives a single output.In
multiplexer we have 2n input lines and 1 output lines where n is the number of selection
lines.

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De-Multiplexter
Demultiplexer is a data distributor which takes a single input and gives several
outputs.In demultiplexer we have 1 input and 2n output lines where n is the selection
line.

Multiplexer Example using Verilog HDL

module mux_beh(a,b,select,y);
input a,b,select;
output y;
reg y;
always @ (select, a , b)
begin
if (select == 0)
begin
y = a;
end
else
begin
y=b;
end
end
endmodule

module mux_beh_test;
reg a,b,select;
wire y ;
mux_beh mux_test(a,b,select,y);
initial
begin
select=0;a=0;b=0;

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#100 select=0;a=0;b=1;
#100 select=0;a=1;b=0;
#100 select=0;a=1;b=1;
#100 select=1;a=0;b=0;
#100 select=1;a=0;b=1;
#100 select=1;a=1;b=0;
#100 select=1;a=1;b=1;
end
initial
begin
$display("Displaying Results for 2:1 Multiplexter");
$monitor($time,"a=%b,b=%b,select=%b,y=%b",a,b,select,y);
end
endmodule

Output

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De-Multiplexer Example using Verilog HDL

module demux1_2_Behave(Din,E,SO,Y0,Y1);
input Din,E,S0;
output Y0,Y1;
assign Y0 = (E & Din &(~S0));
assign Y1 = (E & Din & S0);
endmodule
module demux1_2_test;
reg Din,E,S0;
wire Y0,Y1;
demux1_2 demux1_2_test(Din,E,S0,Y0,Y1);
initial
begin
#000 E=1'b0;Din=1'bX;S0=1'bX;
#100 E=1'b1;Din=1'b0;S0=1'b0;
#100 E=1'b1;Din=1'b1;S0=1'b0;
#100 E=1'b1;Din=1'b0;S0=1'b1;
#100 E=1'b1;Din=1'b1;S0=1'b1;
end
initial
begin
$display("Displaying Results for 1:2 De-Multiplexter");
$monitor($time,"Din=%b,E=%b,S0=%b,Y0=%b,Y1=%b,",Din,E,S0,Y0,Y1);
end
endmodule

Output

Conclusion-

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VLSI Design LY-BTECH

EXPERIMENT NO.7

AIM: Design and Implementation of flip flops using Verilog HDL and write test bench

SOFTWARE: VERILOG HDL COMPILER(Jdoodle online compiler/ iverilog Verilog

Compiler)

OBJECTIVE:

 To Study and develop Verilog codes in behavioral modeling style.

 To study and implement SR & JK Flip Flop using Verilog HDL along with testbench.

OUTCOMES:
Students will be able to implement combinational logic circuits using Verilog HDL

THEORY:
D Flip Flop
The D flip is also known as Delay Flip Flop. It is the delay device or a latch that is used to store
1 bit of the memory information.
The input data appears at the output at the end of the clock pulse. Thus, transfer of data from the
input to the output is delayed and hence the name delay (D) flip-flop.
The DFF operates based on the rising edge or falling edge of the clock input. When the clock
signal transitions from low to high (rising edge), the DFF stores the value of the data input D.
The stored value appears at the output Q. The complemented output ~Q always has the opposite
value of the normal output Q.

Truth Table of D Flip Flop

A D flip-flop is a type of flip-flop circuit that stores a single bit of data. The output value of the
flip-flop depends on the input value and the clock signal.
Here is the truth table for a D flip-flop:

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JK flip-flop
A JK flip-flop is a type of sequential logic circuit that can store a single bit of information,
commonly known as a binary digit (or a bit). It is widely used in digital electronics and
computing, and is often found in microprocessors, memory chips, and other digital circuits.
The JK flip-flop is a modification of the basic SR (Set-Reset) flip-flop, and it has two inputs: J
(for “set”) and K (for “reset”). The output of the flip-flop is denoted by Q, and the complement
of Q is denoted by Q‟.

The truth table of a JK flip-flop is shown below:

The behavior of the JK flip-flop can be analyzed using the characteristic equation:
Q(t+1) = J.Q'(t) + K‟.Q(t)

D Flip Flop
module d_flip_flop (Q,D,clk,reset);
input D;
input clk;
input reset;
output reg Q;
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1 )

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Q <= 1'b0;
else
Q <= D;
end
endmodule
module tb; // Testbench for D Flip Flop
reg D;
reg clk;
reg reset;
wire Q;
d_flip_flop d1(Q,D,clk,reset);
initial
begin
clk = 1'b0;
forever #20 clk = ~clk ;
end
initial
begin
reset = 1'b1;
#40;
reset = 1'b0;
#40;
D = 1'b0;
#40;
D = 1'b1;
#40;
$finish ;
end
initial
begin
$display ("Displaying results for D Flip Flop");//
$monitor(" time=%0d reset=%b clk=%b D=%b Q=%b ",$time,reset,clk,D,Q);
end
endmodule

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JK Flip Flop
`timescale 1ns / 1ps
module jk_flipflop(j,k,clk,reset,Q,Q_bar);
input j,k,clk,reset;
output reg Q,Q_bar;
always@(posedge clk)
begin
if({reset})
{Q,Q_bar}<={1'b0,1'b1};
else
begin
case({j,k})
2'b00:{Q,Q_bar}<={Q,Q_bar};
2'b01:{Q,Q_bar}<={1'b0,1'b1};
2'b10:{Q,Q_bar}<={1'b1,1'b0};
2'b11:{Q,Q_bar}<={~Q,Q};
default:begin end
endcase
end
end
endmodule
// JK FF Test bench
module jk_ff_test_bench();
reg clk,rst,j,k;
wire q_n,q_n_bar;
jk_flipflop test_design(j,k,clk,rst,q_n,q_n_bar);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
rst=1;
#10;
rst=0;
#10;
j = 1'b0;
k = 1'b0;
#10;
j = 1'b0;
k = 1'b1;
#10;
j = 1'b1;

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k = 1'b0;
#10;
j = 1'b1;
k = 1'b1;
#10;
$finish;
end
initial
begin
$display ("Displaying results for JK Flip Flop");//
$monitor(" time=%0d reset=%b clk=%b J=%b K=%b Q=%b
Qbar=%b",$time,rst,clk,j,k,q_n,q_n_bar);
end
endmodule

Conclusion-

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VLSI Design LY-BTECH

EXPERIMENT NO.8

AIM: Design and Implementation of asynchronous and synchronous counters using Verilog
HDL and write test bench

SOFTWARE: VERILOG HDL COMPILER (Jdoodle online compiler/ iverilog Verilog

Compiler)

OBJECTIVE:

 To Study and develop Verilog codes in behavioral modeling style.

 To study and implement asynchronous and synchronous counters using Verilog HDL
along with test bench.

OUTCOMES:
Students will be able to implement combinational logic circuits using Verilog HDL

THEORY:
Asynchronous Counter
In asynchronous counter we don‟t use universal clock, only first flip flop is driven by main clock
and the clock input of rest of the following flip flop is driven by output of previous flip flops. We
can understand it by following diagram-

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Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives
each flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it does
not have cumulative delay because of same clock is given to each flip flop. It is also called as
parallel counter.

Design of Synchronous Counter

A synchronous counter is a type of counter in which all the flip flops are triggered
simultaneously by the same clock pulse. The systematic procedure of designing a synchronous
counter is explained below.
Step (1) − Determine the number of flip-flops required
Step (2) − Draw the state diagram
Step (3) − Selection of flip-flops and excitation table
Step (4) − Obtain the minimized expression for excitations
Step (5) − Draw the logic diagram

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Asynchronous Counter
module asynchronous_counter_mod ( input clk, input clear,output reg [3:0] q);
always @(posedge clk or posedge clear) begin
if (clear)
q <= 4'b0000;
else
q[0] <= ~q[0];
end
always @(posedge q[0] or posedge clear) begin
q[1] <= ~q[1];
end
always @(posedge q[1] or posedge clear) begin
q[2] <= ~q[2];
end
always @(posedge q[2] or posedge clear) begin
if (clear)
q <= 4'b0000;
else
q[3] <= ~q[3];
end
endmodule
module asynchronous_counter_t_b;
reg clk;
reg clear;
wire [3:0] q;
asynchronous_counter_mod uut (
.clk(clk),
.clear(clear),
.q(q)
);
initial begin
clk = 0;
clear = 0;
#5 clear = 1;
#5 clear = 0;
end
always #5 clk = ~clk;
initial begin
$monitor("Time = %0t: clk = %b, clear = %b, q = %b", $time, clk, clear, q);
#180 $finish;
end
endmodule

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OUTPUT:

Time = 0: clk = 0, clear = 0, q = xxxx

Time = 5: clk = 1, clear = 1, q = 0000
Time = 10: clk = 0, clear = 0, q = 0000
Time = 15: clk = 1, clear = 0, q = 1111
Time = 20: clk = 0, clear = 0, q = 1111
Time = 25: clk = 1, clear = 0, q = 1110
Time = 30: clk = 0, clear = 0, q = 1110
Time = 35: clk = 1, clear = 0, q = 1101
Time = 40: clk = 0, clear = 0, q = 1101
Time = 45: clk = 1, clear = 0, q = 1100
Time = 50: clk = 0, clear = 0, q = 1100
Time = 55: clk = 1, clear = 0, q = 1011
Time = 60: clk = 0, clear = 0, q = 1011
Time = 65: clk = 1, clear = 0, q = 1010
Time = 70: clk = 0, clear = 0, q = 1010
Time = 75: clk = 1, clear = 0, q = 1001
Time = 80: clk = 0, clear = 0, q = 1001
Time = 85: clk = 1, clear = 0, q = 1000
Time = 90: clk = 0, clear = 0, q = 1000
Time = 95: clk = 1, clear = 0, q = 0111
Time = 100: clk = 0, clear = 0, q = 0111
Time = 105: clk = 1, clear = 0, q = 0110
Time = 110: clk = 0, clear = 0, q = 0110
Time = 115: clk = 1, clear = 0, q = 0101
Time = 120: clk = 0, clear = 0, q = 0101
Time = 125: clk = 1, clear = 0, q = 0100
Time = 130: clk = 0, clear = 0, q = 0100
Time = 135: clk = 1, clear = 0, q = 0011
Time = 140: clk = 0, clear = 0, q = 0011
Time = 145: clk = 1, clear = 0, q = 0010
Time = 150: clk = 0, clear = 0, q = 0010
Time = 155: clk = 1, clear = 0, q = 0001
Time = 160: clk = 0, clear = 0, q = 0001
Time = 165: clk = 1, clear = 0, q = 0000
Time = 170: clk = 0, clear = 0, q = 0000
Time = 175: clk = 1, clear = 0, q = 1111
Time = 180: clk = 0, clear = 0, q = 1111

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Synchronous Counter
module synchronous_counter(input clk, rst, input ce, output reg [3:0] counterout);
always @(posedge clk or posedge rst) begin
if (rst)
counterout <= 4'b0;
else if (ce)
counterout <= counterout + 1;
end
endmodule
module tb_synchronous_counter;
reg clk;
reg rst;
reg ce;
wire [3:0] counterout;
synchronous_counter uut (
.clk(clk),
.rst(rst),
.ce(ce),
.counterout(counterout)
);
// Clock generation
always begin
#5 clk = ~clk; // Toggle the clock every 5 time units
end
// Reset and ce generation
initial begin
clk = 0;
rst = 1; // Apply reset
ce = 0; // Disable counter
#10 rst = 0; // De-assert reset after 10 time units
#10 ce = 1; // Enable counter
#175; // Run simulation for 100 time units
$finish; // Finish the simulation
end
// Monitor for counterout and control signals
initial
begin
$display ("Displaying results for 4-Bit Synchronous Counter");
$monitor("Time = %t: clk = %b, rst = %b, ce = %b, counterout = %b", $time, clk, rst, ce,
counterout);
end
endmodule

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OUTPUT:-
Displaying results for 4-Bit Synchronous Counter
Time = 0: clk = 0, rst = 1, ce = 0, counterout = 0000
Time = 5: clk = 1, rst = 1, ce = 0, counterout = 0000
Time = 10: clk = 0, rst = 0, ce = 0, counterout = 0000
Time = 15: clk = 1, rst = 0, ce = 0, counterout = 0000
Time = 20: clk = 0, rst = 0, ce = 1, counterout = 0000
Time = 25: clk = 1, rst = 0, ce = 1, counterout = 0001
Time = 30: clk = 0, rst = 0, ce = 1, counterout = 0001
Time = 35: clk = 1, rst = 0, ce = 1, counterout = 0010
Time = 40: clk = 0, rst = 0, ce = 1, counterout = 0010
Time = 45: clk = 1, rst = 0, ce = 1, counterout = 0011
Time = 50: clk = 0, rst = 0, ce = 1, counterout = 0011
Time = 55: clk = 1, rst = 0, ce = 1, counterout = 0100
Time = 60: clk = 0, rst = 0, ce = 1, counterout = 0100
Time = 65: clk = 1, rst = 0, ce = 1, counterout = 0101
Time = 70: clk = 0, rst = 0, ce = 1, counterout = 0101
Time = 75: clk = 1, rst = 0, ce = 1, counterout = 0110
Time = 80: clk = 0, rst = 0, ce = 1, counterout = 0110
Time = 85: clk = 1, rst = 0, ce = 1, counterout = 0111
Time = 90: clk = 0, rst = 0, ce = 1, counterout = 0111
Time = 95: clk = 1, rst = 0, ce = 1, counterout = 1000
Time = 100: clk = 0, rst = 0, ce = 1, counterout = 1000
Time = 105: clk = 1, rst = 0, ce = 1, counterout = 1001
Time = 110: clk = 0, rst = 0, ce = 1, counterout = 1001
Time = 115: clk = 1, rst = 0, ce = 1, counterout = 1010
Time = 120: clk = 0, rst = 0, ce = 1, counterout = 1010
Time = 125: clk = 1, rst = 0, ce = 1, counterout = 1011
Time = 130: clk = 0, rst = 0, ce = 1, counterout = 1011
Time = 135: clk = 1, rst = 0, ce = 1, counterout = 1100
Time = 140: clk = 0, rst = 0, ce = 1, counterout = 1100
Time = 145: clk = 1, rst = 0, ce = 1, counterout = 1101
Time = 150: clk = 0, rst = 0, ce = 1, counterout = 1101
Time = 155: clk = 1, rst = 0, ce = 1, counterout = 1110
Time = 160: clk = 0, rst = 0, ce = 1, counterout = 1110
Time = 165: clk = 1, rst = 0, ce = 1, counterout = 1111
Time = 170: clk = 0, rst = 0, ce = 1, counterout = 1111
Time = 175: clk = 1, rst = 0, ce = 1, counterout = 0000
Time = 180: clk = 0, rst = 0, ce = 1, counterout = 0000
Time = 185: clk = 1, rst = 0, ce = 1, counterout = 0001
Conclusion-

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