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Abstract—With recent technological advancements, modern states [7]–[9]. Only one machine state can be active at a
societies are becoming more and more dependent on the given instant. It is done as a function of the inputs
automated machines. It is in order to cope with their fast-going combination, previous sate and the system memory elements
lives. Modern automated machines adapt their sequence of status [7].
actions depending on their environment and events. The FSM The FSM can be modeled by either FSM model
(Finite state machine) is used to mathematically express those designing or by ASM (Algorithmic State Machines) method,
sequences of actions or instructions. In this article two FSM which is mainly used for designing FSMs and for digital
machines types, Moore and Mealy, are discussed. Showing
integrated circuits diagram representation by flowcharts
different results in order to demonstrate the importance of
methodology [12], [13]. ASM shares conceptual similarities
FSM modeling. An edge detector circuit is designed by
employing both Moore and Mealy machines. It is a FSM design
with FSM modeling except that ASM is easier for
example, can be used for students concepts building and understanding due to its informality as shown on Figure 1,
demonstration. These designs are implemented in VHDL. A illustrating modulo three counters [14]. ASM can be
comparison is also made based on both implementations. compiled by using ASM++ compiler. Moreover, certain
other interesting state machine synthesizers examples are
Keywords-FSM;, automation; VHDL;, Xilinx-ISE;, timing available in the literature [15], [16].
diagram; computer aided design
I. INTRODUCTION
Because of ever wanted features, the DSP (Digital Signal
Processing) has replaced the analog processing in most of the
modern systems [1]–[3]. A smart digital signal processing
design can lead towards an efficient solution and vice versa
[1]–[3].
Information in digital systems is classified as, data or
control information [4]. Data is known as discrete element
of information that can be altered in order to preform
arithmetic, logic and other data-processing tasks which is
implemented with digital components such as decoders,
adders and counters [5]. While control information provides
command signals that supervises the operations held in the Figure 1. Modulo three counters
data section to ensure the desired output [4], [5].
There are two distinct modules of all digital processing II. THE FSM PRINCIPLE
system. One is dealing with the performance of data The FSM is typically used as a type of control system
processing by designing the suitable digital circuit. The other where knowledge is represented in the states and actions are
part deals with the design of the operation supervisor, the constrained by rules [17]. The general FSM model is shown
control circuit [5]. on Figure 2.
The control logic uses status conditions from the data Figure 2, illustrates the form and function of a state
processor to serve as decision variables to determine the machine. Usually drawn as a bubble-and-arrow diagram.
sequence of control signals. The control logic provides a State is a uniquely identifiable set of values measured at
sequence of time signals, which is essential for operation various points in a digital system. Where next State is the
initiation in the data processor, and also the determination of state to which the state machine makes the next transition,
the next state of the control subsystem [6]. determined by the inputs present when the device is clocked.
Finite state machine FSM [7]–[9] or also known as finite- Branch explains the change from present state to next state.
state automaton FSA [10], [11]. The word automaton For any given state, there is a finite number of possible next
expresses a machine that functions based on already stored states. On each clock cycle, the state machine branches to
and determined coded instructions, with a wide range of the next state. One of the possible next states becomes the
programmed capabilities based on different circumstances new present state, depending on the inputs present on the
[10], [11]. It simplifies the meaning of FSM to be a clock cycle [7], [17].
mathematical model of computation that is based on a
hypothetical machine that consists of a finite number of
rized licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on October 12,2023 at 10:43:09 UTC from IEEE Xplore. Restrictions a
The state machine diagram of a Mealy machine based
edge detector is shown on Figure 6. The zero and one states
have similar meaning. When the FSM is in the zero state and
the input changes to high, the output is asserted immediately.
The FSM moves to the one state at the rising edge of the next
clock and the output is de-asserted.
Figure 11. The Mealy machine based edge detector Timing Diagram.
rized licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on October 12,2023 at 10:43:09 UTC from IEEE Xplore. Restrictions a
machine based circuit. Therefore, the Mealy machine based [5] M. M. Mano, Digital design. EBSCO Publishing, Inc., 2002.
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rized licensed use limited to: Vignan's Foundation for Science Technology & Research (Deemed to be University). Downloaded on October 12,2023 at 10:43:09 UTC from IEEE Xplore. Restrictions a