Lecture 2

8086 CPU Architecture,

Addressing Modes

Topics
 Intel Microprocessors
 8086 CPU Architecture
 Addressing Modes of 8086

2
 List of Some Intel Microprocessors
Data Address
Maximum
Bus Bus CPU
Microprocessor RAM
Width Width Frequency
(Bytes)
(Bits) (Bits)

8085 8 16 64 KB 3 MHz

8086 16 20 1 MB 5 MHz

80386 16 24 16 MB 16 MHz

80486 32 32 4 GB 25 MHz

Pentium 4 64 36 64 GB 1.4 GHz

Core i9 64 37 128 GB 3 GHz

Registers in
All Intel Microprocessors

CPU
CPU
Data Bus Register Names
Category Name
Width

8085 8 bit AH, AL, BH, BL, CH, CL, DH, DL

8086
16 bit AX, BX, CX, DX, SP, BP, SI, DI CPU

x86 EAX, EBX, ECX, EDX,

32 bit ESP, EBP, EDI, ESI
x86-64 (E prefix stands for Extended)
RAX, RBX, RCX, RDX,
RSP, RBP, RDI, RSI,
x64 64 bit
R8, R9, R10, R11, R12, R13, R14, R15
(R prefix stands for Register)

4
 Intel x86-64
Register Widths 8086 CPU

Intel x86-64
Register Widths 8086 CPU

6
 Topics
 Intel Microprocessors
 8086 CPU Architecture
 Addressing Modes of 8086

8086 CPU Functional Diagram

8
 8086 CPU Architecture ADDRESS BUS
20-BIT

AH AL AX
General Address
Purpose BH BL BX
Generation
Registers CH CL CX DATA BUS
DH DL DX 16-BIT
Segment Address
SP Offset Address
Index & CS
Pointer BP Segment DS
Registers SI Registers
SS
DI BUS
ES CONTROL
ALU DATA BUS 16-BIT IP LOGIC

TEMPORARY REGISTERS

Instruction
Decoder
1 2 3 4 5 6
and Queue Bus
ALU EU CONTROL 8-bit
INSTRUCTION QUEUE
6 BYTES

FLAGS REGISTER

EXECUTION BUS INTERFACE

UNIT (BIU) 9
UNIT (EU)

Bus Interface Unit (BIU)

●
BIU performs all external bus operations.
●
Fetches instructions from memory.
●
Reads data operands from memory and input/output peripheral ports.
●
Writes data to memory and IO ports.
●
It is also responsible for instruction queuing and address generation.
●
BIU contains segment registers (CS, DS, SS, ES), instruction pointer (IP),
instruction queue, address generation unit, and bus control unit.
●
BIU generates the 20-bit physical memory address.
●
Address Generation unit (Address Adder) is used to produce 20-bit pysical
address, by using content of CS register and IP register.
Phyical Address = CS*16 + IP

10
 BIU: Instruction Queue
●
To speed up the execution, 6-bytes of instruction are fetched in
advance, and kept in a 6-byte Instruction Queue called pipe-lining.

●
The queue is used to prefetch and store at the maximum of 6 bytes of
instruction code from the memory.
●
Overlapping the instruction-fetch with the instruction-execution
increases the processing speed.

11

BIU: Memory Segment Registers

●
In 8086 microprocessor, the memory is divided into four segments.
●
The segments are Data Segment, Code Segment,
Stack Segment, and Extra segment.
●
Each segment is of 64 kilo bytes.
●
BIU has four segment registers (each is 16 bit).
●
Code Segment (CS) register
●
Data Segment (DS) register
●
Stack Segment (SS) register
●
Extra Segment (ES) register
●
The segment registers are used to hold four segment base addresses.

12
 Execution Unit (EU)
●
EU is responsible for decoding and executing instructions.
●
It consists of the arithmetic logic unit (ALU), status and control flags,
general purpose registers, and temporary-operand registers.
●
Arithmetic Logic Unit (ALU) can add, subtract, AND, OR, XOR,
increment, decrement, complement or shift binary numbers (8-bit or 16-bit).
●
EU accesses instructions from the output end of the instruction queue
and data from the general purpose registers or memory.
●
It reads one instruction byte after the other from the output of the queue.
●
Decodes the instruction.
●
Generates data addresses if necessary.
●
Passes the addresses to the BIU.
●
Requests the BIU to perform the read or write operations to memory or I/O.
●
Performs the operation specified by the instruction.

13

Execution Unit (EU)

●
EU executes instructions that have already been fetched by the BIU.
●
BIU and EU function independently (parallel).
●
The instruction queue is a FIFO (First-In-First-Out) group of registers.
- The size of queue is 6 bytes.
- BIU fetches instruction code from the memory and stores it in the queue.
- EU fetches instruction codes from the queue.
●
EU receives program instruction codes and data from the BIU,
executes these instructions, and store the results in the general registers.
It receives data and outputs data through the BIU.
●
An instruction decoder circuit in the EU translates instructions fetched from
memory into a series of actions which the EU carries out.

14
 8086 CPU Registers
16 bits

8 bits 8 bits

Accumulator AX AH AL
Base register BX BH BL
General purpose registers
Counter CX CH CL
Data DX DH DL
Stack Pointer SP
Pointers
Base Pointer BP
Instruction Pointer IP
Source Index SI
Index registers Address
Destination Index DI registers
Code Segment CS
Data Segment DS
Segment registers
Stack Segment SS
Extra Segment ES
FLAGS Status register
15

General Purpose Registers

Registe Special Implicit
Register
r General Usages Usages in
Name
Symbol Operations

Stores the 16-bit results of arithmetic calculations,

and logic operations.

Consists of two 8-bit registers AL and AH, which

can be combined together and used as a 16-bit Word multiply, Word
Accumulator
AX register AX. divide, Word I/O.
(16-bit)
(1 word = 2 bytes)
AX register is where most arithmetic and logical
computations take place, although you can do
most arithmetic and logical operations in other
registers too.

Byte multiply, Byte

Accumulator Low byte of AX register. divide, Byte I/O,
AL Low Stores the 8-bit results of arithmetic and logic Translate (XLAT
(8-bit) operations. instruction), Decimal
Arithmetic
Accumulator
Byte multiply, Byte
AH High Low byte of AX register.
divide
(8-bit)
16
 General Purpose Registers
Register Special Implicit
Register Name General Usages
Symbol Usages in Operations

Mostly used as index register for MOVE

instruction.
Translate (XLAT
BX Base register Used to hold base value in Base Addressing
instruction)
Mode to access memory data.This is the only
general purpose register taht can be used for
addressing the memory.

Used as a counter in
Mosltly used as counter for loopings.
string operations, and
CX Counter register Used to hold the count value in SHIFT,
in LOOP instruction.
ROTATE instructions.

Counter Low Variable for shift and

CL Low byte of CX register.
register rotate.
Used to hold data for multiplication and
division operations. Word multiply, Word
DX Data register
Also can be used as a port number in divide, indirect I/O.
IN / OUT operations.

17

Memory Segments in 8086

●
Intel 8086 CPU is a 16-bit processor.
●
It has 16-bit data bus and 20-bit address bus.
●
The lower 16- bit address lines and 16-bit data lines are multiplexed (shared).
●
Since 20-bit address lines are available, 8086 can access up to
1 Mega bytes of physical memory locations ( 220 ).
●
However, internal address registers of 8086 CPU are just 16-bits wide.
●
Therefore 8086 uses memory segmentation.
●
It treats the 1 Mbyte of memory as divided into 4 segments.
●
Segment Names:
Code Segment, Data Segment, Stack Segment, Extra Segment.
●
Size of each segment can vary.
●
Maximum size of each segment is 64 KB.
●
Segments may be overlapped or non-overlapped.
●
There can be also multiple usages of CS,DS,ES segments.
●
But only one SS segment can be used.

18
 Segment Registers
●
Each segment register is 16-bit, containing address of 64 KB related segment.
●
The segment registers point to the starting location address of a particular segment.
Segment
Segment
Register Description
Register Name
Symbol
Points to base of segment containing machine language code.

Programs instruction codes are stored in code segment.

Processor uses CS segment register for all accesses to instructions
CS Code Segment
referenced by Instruction Pointer (IP) register.

CS register points at the beginning address of segment containing

the current program instructions.
Points to base of segment containing data.

Data referenced by general registers (AX, BX, CX, DX) and

DS Data Segment
index register (SI, DI) is usually stored in the data segment.

DS register points at segment where variables are defined.

Points to base of an extra data segment.
ES Extra segment
Extra segment can be used as an extra data segment.
DI register references the ES segment in string manipulation instructions.
Points to base of segment containing the stack.

SS Stack Segment Data related with stack operations are stored in the stack segment.
All data referenced by the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment.
19

Memory Organization of Segments

Segment
Registers
ES
SS
CS
DS

00000H
20
 Pointer Registers
●
Pointer registers and index registers are 16-bit registers.
●
They are used to store offset addresses of memory locations relative to segment registers.
●
They act as memory pointers.
●
CPU (Address Adder Unit) adds these registers to the shifted segment registers,
in order to obtain the physical memory addresses.

Register Register
Description
Symbol Name
Points to top of stack.
SP Stack Pointer
Used to hold the offset address of top of stack in memory.
The actual stack address is computed by adding content of SP and SS.
Points to base of some data in stack.

BP register is usually used for Based, Based Indexed, or

BP Base Pointer Register Indirect addressing modes.
Data may exist in stack. To access such data in stack segment, BP register is used.
BP register points to data address in stack segment, and is used with SS register.
BP is also used as a general purpose register.
Points to the next instruction to be run.

IP register holds the 16-bit address of the next instruction code to be

fetched within the Code Segment memory.
IP Instruction Pointer
The value contained in the IP is referred to as an offset.
This value (offset) is added by CPU to the segment base address in CS,
to produce the required 20-bit physical address.
IP register cannot be modified by the programmer.
21

Index Registers
Register Register
Description
Symbol Name
Points to a source in array operations.

SI register is used for Indexed, Based Indexed, and Register Indirect

Addressing modes.
SI Source Index
Content of SI register is added to content of DS register by CPU,
to get the actual source address of data.
SI is also used to hold index value of source operand data for string
manipulation instructions.
Points to a destination in array operations.

DI register is used for Indexed, Based Indexed, and Register Indirect

Addressing modes.
Content of DI is added to content of ES register by CPU,
DI Destination Index
to get the actual destination address of data.
DI is also used to hold index value of destination operand data for
string instructions.

Both SI and DI can also be used as general purpose registers.

22
 Default and Alternative
Segment Registers

Type of memory
Default segment Alternative segment Offset value
reference
Instruction fetch CS None IP
Stack operation SS None SP, BP
Immediate data DS CS, ES, SS Effective address
String source DS CS, ES, SS SI
String destination ES None DI
Pointer (address in BX) DS CS, ES, SS Effective address

23

Logical Address Notation

The following is the general notation for logical addresses.

Segment Register Name : Offset Register name

Logical Address
Example:
Notation Examples
Suppose content of CS register is = 3482h,
and content of IP register is = 17C6h.
CS : IP
The Logical Address notation can be written as:
SS : SP CS : IP
SS : BP 3482h : 17C6h

DS : BX Hexadecimal is the default numbering for addresses.

DS : SI The h suffix can be omitted for addresses.
3482 : 17C6
DS : DI

ES : DI

24
 Physical Memory Address Generation
●
Step1: The Address Adder unit in CPU multiplies the segment address with 16.
In other words, it appends 4 zero bits to the right of segment register,
so that 20 bits width is obtained.
●
Step2: Address Adder unit adds the offset value to the appended value of segment address,
the result is physical memory address (20-bits).

Physical Address = (Segment Register) * 16 + (Offset Value)

Segment Register (16 bits) 0000 Offset Value (16 bits)

(4 zero bits
appended)

ADDRESS
ADDER

Physical Address (20 bits)

25

Example1: Generation of 20-bit Physical Address

from CS and IP registers
●
Suppose content of CS register is 3482h,
and content of IP register is 17C6h.
●
Step1: Contents of the CS register are multiplied by 16 34820h
(It is performed by appending 4 zero bits to right of CS). (Start of CS)
The value after appending hex zero to CS is 34820h.
(Content of CS is not changed by this operation.) IP= 17C6h
(Offset)
●
Step: Offset value (content of IP register) is added to
the appended CS value, to generate 20-bit physical address.

35FE6h
Physical Address = CS * 16 + IP

Step1) Append zero to CS = 34820h

Step2) Add the offset (IP) = 17C6h
+ (End of CS)
Physical Adress = 35FE6h

26
 Example2: Generation of 20-bit Physical Address
from SS and SP registers
●
Stack Pointer (SP) register contains the 16-bit offset value from the start of stack
segment to the top of stack.
●
For a stack operation, physical address is produced by adding the content of stack
pointer register to the appended segment base address in SS register.
●
Suppose content of SP = 9F20H , and SS = 4000H.
The physical address (20 bit) is calculated as follows.
(End of SS)
The value after appending zero to SS is 40000H
(Content of SS is not changed by this operation.)

49F20h
(Top of Stack)

Physical Address = SS * 16 + SP
SP= 9F20h
(Offset)
Step1) Append zero to SS = 40000h
Step2) Add the offset (SP) = 9F20h
+ 40000h
Physical Adress = 49F20h (Start of SS)

27

Status Flags Register (16-bit)

in 8086

x : Not used

28
 Status Flags Register
●
The flag register is a 16-bit register, containing nine status flags (each flag is 1-bit).
●
Flag bits are changed (set to 1) by the results of many Assembly instructions
such as arithmetic, logical, shift/rotate operations.
Flag Bit
Flag Bit Name Description
Symbol
It is set (assigned "1") automatically by ALU, if the result of arithmetic
operation is too large positive number, or is too small negative
OF Overflow Flag
number to fit into destination operand.
OF=1 means there is an overflow.
If set then string manipulation instructions will auto-decrement index
DF Direction Flag registers. If cleared (assigned "0") then the index registers will be
auto-incremented.
IF Interrupt-enable Flag Setting this bit enables maskable interrupts.
TF Single-step Trap Flag If set then single-step interrupt will occur after the next instruction.
Set if the most significant bit of the result is set.
SF Sign Flag SF=0 means the result is positive.
SF=1 means the result is negative.
Set if the result is zero.
ZF Zero Flag
ZF=1 means the result is zero, ZF=0 means the result is not zero.
Set if there was a carry from or borrow to bits 0-3 in the AL register
AF Auxiliary carry Flag
during BCD operation.
Set if parity (the number of "1" bits) in the low-order byte of the result
PF Parity Flag
is even.
Set if there was a carry from or borrow to the most significant bit
CF Carry Flag
during last result calculation. CF=1 means there is a Carry or Borrow. 29

Topics
 Intel Microprocessors
 8086 CPU Architecture
 Addressing Modes of 8086

30
 Descriptions of Addresses
●
ADDRESSING MODE :
An instruction consists of an operation code (opcode) and an operand.
The operand may reside in the accumulator, or in a general purpose register,
or in a memory location.
The method in which an operand is specified (or referred to) in an
instruction is called addressing mode.

●
Base Segment Address :
The 16-bit content of one of the four segment registers (CS, DS, ES, SS)
are base segment addresses.

●
Offset Address (Effective address) :
It is contained in the 16-bit registers IP, BP, SP, BX, SI or DI.

●
Physical Address (Real Address) :
Offset and base segment addresses are combined to form a
20-bit physical address that is used to access the memory.
The 20-bit physical address is put on the address bus
(AD0 – AD15 , and A16-A19) by the CPU.

31

Addressing Modes of 8086

1. Register operand addressing
Non-memory
2. Immediate operand addressing operands

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Memory
6. Indexed Addressing operands

7. Based Indexed Addressing

8. Based Indexed plus displacement

32
 Generation of Physical Addresses
for different addressing modes
●
Physical address for the operand is the address from which either
a read or write operation is initiated.
●
Effective address, for its generation, can have as many as three elements:
Base register, Index register and Displacement.
●
Both of these addresses are calculated automatically by CPU as follows.

Effective address = Base Register + Index Register + Displacement

Physical address = Segment Base * 16 + Effective Address

33

1. Register Addressing Mode

●
Either an 8-bit or a 16-bit general purpose register contains the operand.
●
Source and destination registers must have equal bit lengths.
●
In examples below, all operands are registers.
Examples:

MOV AX, BX ; Move (copy) BX register to AX register

ADD AL, BL ; Add BL register to AL register

CLC ; Clear Carry flag bit to zero in the Flags register.

(Implied Addressing Mode: Instruction has no explicit operands.)

34
 2. Immediate Addressing Mode
●
The operand (immediate data) is contained in the instruction itself,
i.e., the operand forms a part of the instruction itself.
●
The operand can be either 8-bit or 16-bit in length.

Examples:

MOV AL, 12h ; Move 8-bit immediate data to AL register

ADD AX, 1234h ; Add 16-bit immediate data to AX register

35

3. Direct Addressing Mode

●
The effective address is written after the instruction opcode.
●
Phycical Address (P.A.) is generated as follows.

Physical address = Segment base : Direct Address

●
By default, the segment base register is DS.
P.A. = DS : EA
●
A segment prefix can be used in the instruction.
●
General format:
Example1: MOV DS:[2000h], AX
Moves contents of AL to offset address 2000h
(relative to data segment register DS).
Also moves AH contents to address 20001h.
Memory address is supplied within the instruction.

Segment Example2: MOV AX, DS:[2000h]

prefix 36
 Examples: Direct Addressing Mode
●
Most common addressing mode is the Direct Addressing mode.
●
Direct mode consists of a 16-bit constant that specifies the address of
the source or target location.
●
Example1: The instruction MOV AL , DS : [2000h] loads the AL register
with a copy of the byte at memory location 2000h in data segment.
●
Example2: The instruction MOV DS : [3000h] , DL stores the value
of the DL register to memory location 3000h in data segment.

MEMORY

MOV AL , DS : [2000h] AL 2000h

MOV DS : [3000h] , DL 3000h

DL

37

Using Segment Prefixes in Instructions

●
By default, CPU uses the Data Segment for all offset values used in
instructions.
●
To provide an offset into a different segment, other than the data segment,
a segment override prefix should be used before the offset address.
●
Example : Accessing location 2000h in the extra segment (ES).
MOV AL, ES : [2000h]
●
Example: Accessing location 2000h in the code segment (CS).
MOV AL, CS : [2000h]

38
 Example: Direct Addressing Mode
(Accessing a Word data from memory)
●
The example below accesses a Word data (2-byte data) from memory.
●
First byte of data in memory (at address 5001h) is copied to AL register.
(AL is low byte of AX register).
●
Second byte of data in memory (at address 5002h) is copied to AH register.
(AH is high byte of AX register).
●
Storing the low byte of data in low memory address, and high byte of data in high
memory address is called as Little Endian data storage convention.
●
All Intel CPU’s use the Little Endian convention.
●
The opposite is Big Endian convention. Example: Used by Motorola CPU’s.

MEMORY Logical
MOV AX , DS : [5001h] Addresses

AX
5001h Low address
AH AL
5002h High address
High Byte Low Byte
of Data of Data

39

Example: Generation of Physical Address

in Direct Addressing Mode
●
Suppose Data Segment register is DS = 0300h,
and the address assigned to NUM variable is 5001h.
●
The Physical Address (P.A.) (20 bit) is generated automatically as follows.
PA = DS * 16 + Address of NUM
= 0300h * 16 + 5001h
= 03000h + 5001h
= 08001h
●
Data contained in physical memory addresses 08001h and 08002h will be
copied to AL and AH registers respectively.
NUM DW 1234h ; Define Word (Variable containing 2-bytes) initialized with data

MOV AX, [NUM] ; Move (copy) data from the variable to the register

Data in Phycical address

Memory of NUM variable
AX
34h 08001h
12h 34h
AH AL 12h 08002h
Little Endian
Data Storage
Convention 40
 4. Register Indirect Addressing Mode
●
Effective Address can reside in either base registers (BX or BP),
or index registers (SI or DI).
●
The default segment register is DS, but by using a segment override
prefix (SEG), any of the four segment registers can be referenced.
●
General format:

Base register, or

Example:
MOV AX, [SI]
Moving 16-bit content of memory location
having its offset value in SI, from the beginning
of the current data segment , to the AX register.
Memory address is supplied in an SI index register.

41

Examples: Register Indirect Addressing Mode

Example1 : Using [BX]

(DS is default segment for BX usage)

Example2 : Using [BP]

42
(SS is default segment for BP usage)
 5. Based Addressing Mode
●
The physical address is generated by adding either an 8-bit or 16-bit
displacement to contents of either base register BX or base pointer register BP,
and the current value in DS or SS respectively.

Physical address = Segment base : Base + Displacement

●
General format:

Example:

MESAFE equ 09h

MOV [BX] + MESAFE , AL
MOV [BX + MESAFE] , AL ;Same as above
MESAFE denotes displacement (can be 8 bit or 16 bit). BX is the base register.
They give Effective Address of the destination operand. 43

Example: Based Addressing Mode

Using [BX + disp]

disp : Displacement

44
 6. Indexed Addressing Mode
●
Indexed mode is very similar to the Based Addressing Mode.
●
The difference is that the SI and DI registers are used, instead of BX and BP.

Physical address = Segment base : Index + Displacement

●
General format:

Example:

MOV [SI] + MESAFE , AL

MOV [SI + MESAFE] , AL ;Same as above
SI is used as index register.

45

7. Based Indexed Addressing Mode

●
It is a combination of Based and Indexed addressing modes.
●
The physical address in this case is generated as follows.
●
The BX and BP registers are used for data and stack segments respectively.
●
Physical memory address is the sum of an index register and a base register.

Physical address = Segment base : Base + Index

●
General format:
Example:
MOV AL, [BX] [SI]
MOV AL, [BX + SI] ;Same as above

Suppose DS = 3000h, BX = 1000h and SI = 1234h.

Then PA = 03000h + 1000h + 1234h = 05234h

On executing this instruction, the value stored in
memory location 05234h will be
stored in AL register.

46
 Example: Based Indexed Addressing Mode

Using [BX + SI].

MOV AL, [BX] [SI] ;Same as [BX+SI]

47

8. Based Indexed plus Displacement

Addressing Mode
●
It is a combination of based addressing mode and indexed addressing mode,
along with an 8 or 16-bit displacement.
●
It can be used to access a two dimensional (m × n) array (matrix).
●
Effective address can be calculated from the contents of base and
index registers and the fixed displacement.

Physical address = Segment base : Base + Index + Displacement

●
General format:

48
Example: Based Indexed plus Displacement
Addressing Mode

Using [BX + SI + disp]

49

Example : Generation of Physical Address

in Based Indexed plus Displacement Mode
Example:

MOV AL, [BX] [SI] + MESAFE

Assuming: DS = 0300h, BX = 1000h,

SI = 1234h and
MESAFE (displacement) = 0012h.

PA = 0300h*16 + 1000h + 1234h +

0012h = 05246h.

On executing th instruction, the value

stored in memory location 05246h
(source operand) will be stored in AL
register.

The memory address is the sum of an

index register, a base register and an
8 or 16-bit displacement within the
instruction.

50
 Summary: Examples of Addressing Modes
Suppose: EBX = 00000300H, ESI = 00000200H, ARRAY = 1000H, and DS = 1000H

51

Example : Program for testing Addressing Modes

The following is an example 8086 Assembly program for
testing different Addressing Modes of memory operands.
Part1
.model small
.data
NUM DW 1234h
mesafe equ 09h ;Displacement value
.code
Basla PROC
.STARTUP
MOV AX, BX ;1. Register Addressing Mode
MOV AL, 73h ;2. Immediate Addressing Mode

MOV DS : [0205h], AL ;3. Direct Addressing Mode

MOV DS:[0205h], AX
MOV AL , DS:[0205h]
MOV AX , DS:[0205h]
;Illegal MOV DS:[1200h], 07h
;Illegal MOV AL , [1200h]
MOV AX, [NUM]
MOV [NUM], AX
MOV [NUM], 07h
;3. Direct Addressing Mode
;3. Direct Addressing Mode
;3. Direct Addressing Mode
;3. Direct Addressing Mode
;3. Direct Addressing Mode
;3. Direct Addressing Mode
;3. Direct Addressing Mode
;3. Direct Addressing Mode
52
 Part2
MOV AL , [BX] ;4. Register Indirect Addressing Mode
MOV [BX], AL ;4. Register Indirect Addressing Mode
;Illegal MOV [BX], 07h ;4. Register Indirect Addressing Mode
MOV AX , [SI] ;4. Register Indirect Addressing Mode
MOV AL , [BP] ;4. Register Indirect Addressing Mode

MOV AL , [BX+mesafe] ;5. Based Addressing Mode

MOV AL , [BX]+mesafe ;5. Based Addressing Mode
MOV [BX]+mesafe, AL ;5. Based Addressing Mode
;Illegal MOV [BX]+mesafe, 07h ;5. Based Addressing Mode

53

Part3
MOV AL , [SI+mesafe] ;6. Indexed Addressing Mode
MOV [SI+mesafe], AL ;6. Indexed Addressing Mode
;Illegal MOV [SI+mesafe], 07h ;6. Indexed Addressing Mode

MOV AL, [BX][SI] ;7. Based Indexed Addressing Mode

MOV AL, [BX+SI] ;7. Based Indexed Addressing Mode
MOV [BX+SI], AL ;7. Based Indexed Addressing Mode
;Illegal MOV [BX+SI], 07h ;7. Based Indexed Addressing Mode

MOV AL, [BX+SI+mesafe] ;8. Based Indexed plus Displacement

MOV [BX+SI+mesafe], AL ;8. Based Indexed plus Displacement
;Illegal MOV [BX+SI+mesafe], 07h ;8. Based Indexed plus Displacement
.EXIT
Basla ENDP
END

54