3.unit 01

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE, PUDUCHERRY
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
Subject Name: Analog and Digital Integrated Circuits Subject Code: EE T52
Prepared By:
Mr. B. Parthiban, Associate Professor/EEE
Mr.S.JohnPowl, Assistant Professor/EEE
Verified by: Approved by:
UNIT I
IC Fabrication AND Logic Families
Monolithic IC technology–planar process–Bipolar junction transistor–FET fabrication–
CMOS technology. DIGITAL IC's . Logic families; DTL, HTL, RTL, TTL, ECL, PMOS,
CMOS, I2L performance criteria -Comparison, applications, advantages.
2 Marks
TWO MARKS QUESTION & ANSWERS:
1. Classify IC’s on the basic application, device used and chip technology. (April-14)
a) Classification of ICs (Integrated Circuits)
Below is the classification of different types of ICs basis on their chip size.
 SSI: Small scale integration. 3 – 30 gates per chip.

 MSI: Medium scale integration. 30 – 300 gates per chip.
 LSI: Large scale integration. 300 – 3,000 gates per chip.
 VLSI: Very large scale integration. More than 3,000 gates per chip.
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UNIT- I IC Fabrication AND Logic Families
b)Types of ICs technology (Integrated Circuits)
Based on the method or techniques used in manufacturing them, types of ICs can be
divided into three classes:
1. Thin and thick film ICs

2. Monolithic ICs
3. Hybrid or multichip ICs
c) On the basis of applications ICs are of two types namely:
 Linear Integrated Circuits

 Digital Integrated Circuits.
2. List the basic process used in the silicon planar technology. (April-14),( Nov-15)
What are the processes involving in IC fabrication?
 Wafer preparation.
 Epitaxial growth.
 Oxidation.
 Photolithography.
 Diffusion.
 Ion implantation.
 Isolation Technique.
 Metallization.
 Assembly and Packaging.
3. Name the different types of IC packages. (April-15)
 Through-hole package.
 Surface mount.
 Chip carrier.
 Pin grid arrays.
 Flat packages.
 Small outline packages.
 Chip-scale packages.
 Ball grid array.
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4. What are the popular IC packages available? (Nov-15A)
a)Through-Hole Technology
 DIP(Dual inline Package) are the most commercial application
b)Surface Mount Technology
 SOIC (Small outline IC)
 QFP (Quad Flat Pack)
 PLCC (Plastic Leaded chip carrier)
5. List the advantage of integrated circuit(IC) over discrete component circuit. (April-
15)
Advantages of Integrated Circuits

 Miniature in size. As fabrication process is used for the integration of active and
passive components on to a silicon chip, the IC becomes a lot smaller. When
compared to a discrete circuit, it may be at least a thousand times smaller.
 Due to small size, the weight of the IC also reduces, when compared to the discrete
circuit.
 To produce hundreds of discrete circuits on a PCB for the same logic takes more
time and increase the cost factor. But for the production of hundreds of IC’s the cost
of production will be very low and less time consuming.
 The PCB consisting soldered joints will be less reliable. This problem is omitted in
IC’s because of no soldered joints, with fewer interconnections, and thus highly
reliable.
 The small size of IC’s causes lesser power consumption and lesser power loss.
 In a discrete circuitry, if a single transistor becomes faulty, the whole circuit may fail
to work. This transistor has to be de-soldered and replaced. It is difficult to find out
which component has failed. This problem can be omitted in an IC by replacing an
entire IC as it is low in cost.
 Increased operating speed because of absence of parasitic capacitance effect.
 As the IC’s are produced in bulk the temperature coefficients and other parameters
will be closely matching.
 As all the components are fabricated very close to each other in an IC, they are
highly suitable for small signal operation, as there won’t be any stray electrical
pickup.
 As all the components are fabricated inside the chip, there will not be any external
projections.
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6. List the disadvantage of integrated circuit(IC) over discrete component circuit.

(April-15)
Disadvantages of Integrated Circuits
 Some complex IC’s maybe costly. If such integrated circuits are used roughly and
become faulty, they have to be replaced by a new one. They cannot be repaired as the
individual components inside the IC are too small.
 The power rating for most of the IC’s does not exceed more than 10 watts. Thus it is
not possible to manufacture high power IC’s.
 Some components like transformers and inductors cannot be integrated into an IC.
They have to be connected externally to the semiconductor pins.
 High grade P-N-P assembly is not possible.
 The IC will not work properly if wrongly handled or exposed to excessive heat.
 It is difficult to achieve low temperature coefficient.
 It is difficult to fabricate an IC with low noise.
 It is not possible to fabricate capacitors that exceed a value of 30pF. Thus, high value
capacitors are to be connected externally to the IC.
 There is a large value of saturation resistance of transistors.
7. What are the advantages of CMOS logic family? (Nov-15)
 Dissipates low power: The power dissipation is dependent on the power supply
voltage, frequency, output load, and input rise time. CMOS logic takes very little
power when held in a fixed state. The current consumption comes from switching as
those capacitors are charged and discharged. Even then, it has good speed to power
ratio compared to other logic types.
 Short propagation delays: Depending on the power supply, the propagation delays
are usually around 25 ns to 50 ns
 High imput impedance. The input signal is driving electrodes with a layer of
insulation (the metal oxide) between them and what they are controlling. This gives
them a small amount of capacitance, but virtually infinite resistance. The current into
or out of a CMOS input held at one level is just leakage, usually 1 µA or less.
8. What is the purpose of oxidation? (Nov-15A)
Oxidation is a process by which a metal or semiconductor is converted to an oxide. The

chemical reaction between oxygen and silicon to generate SiO 2 is usually driven by a
high-heat environment. Silicon dioxide layers are mainly used as high quality insulators
or masks for ion implantation and the ability to form high quality silicon dioxide is the
main reason why silicon is still the dominating material for IC fabrication
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9. Define noise margin. (Nov-13)
 The noise immunity of a logic circuit refers to the circuits ability to tolerate the
noise without causing spurious changes in the output voltage
 Noise margin is the amount by which a signal exceeds the minimum amount for
proper operation. In communications system engineering, noise margin is the ratio
by which the signal exceeds the minimum acceptable amount.
10. List the various steps used in the preparation of silicon wafers. (Nov-13)
11. What is meant by FAN-IN & FAN-OUT?
 The fan-in of a digital logic gate refers to the number of inputs. A logic designer has to
select the fan-in to accommodate the number of inputs. e.g 2 input NOR gate has a fan-
in of 2.
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 Fan-out is a term that defines the maximum number of digital inputs that the output of a
single logic gate can feed. Most transistor-transistor logic ( TTL ) gates can feed up to 10
other digital gates or devices. Thus, a typical TTL gate has a fan-out of 10.
12. What is the propagation delay?
Propagation delay is otherwise called as Gate delay. It is basically the time interval
between the application of an input pulse and the occurrence of the resulting output pulse, at the
time same it limits the speed at which they can operate.
13. What is power dissipation?

The amount of power than an IC can dissipates when an certain amount of electrical power is
applied for the operation. This power is supplied by one or more power supply voltages
connected the power pin(s) on the chip.
14.Define TTL.
Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT) and resistors. It is called transistor–transistor logic because both the logic gating
function (e.g., AND) and the amplifying function are performed by transistors (contrast with
resistor–transistor logic (RTL) and diode–transistor logic (DTL)).
15. Define ECL.

Emitter Coupled Logic has been developed which prevents transistor saturation, thereby
increasing overall switching speed by using a radically different circuit’s structure, called
Current Mode Logic (CML).
16. Define RTL.
Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as the
input network and bipolar junction transistors (BJTs) as switching devices. The primary
advantage of RTL technology was that it used a minimum number of transistors.
The disadvantage of RTL is its high power dissipation when the transistor is switched on, by
current flowing in the collector and base resistors. This requires that more current be supplied to
and heat be removed from RTL circuits.
17. Define Tri-State TTL.
The tristate configuration is a third type of TTL output configuration. It utilizes the high-speed
operation of the totem-pole arrangement while permitting outputs to be wired-ANDed(connected
together).TTL allows three possible output stages: HIGH, LOW and low impedance.
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18. What is totem-pole?
Capacitance is rapidly charged or discharged through the low output impedance. Totem pole
transistor is used because they produce a LOW output impedance. This means that the output
voltage can change quickly from one state to the other because any stray output.
19.Define Schottky TTL.
Schottky Diode is that it has very little capacitance and fast recovery time. So it can be switched
rapidly without storage time delays. Hence Schottky TTL uses smaller resistor values to help
improve switching times. This increase the average power dissipation to about 20mW.
20. Explain the TTL characteristics.
 The operation of input circuit is similar to the DTL gate.

 A typical transfer characteristics is as the input voltage is increased from zero, the output
remains constant till the input approaches one diode drop.
 The TTL output characteristics is when the output stage of TTL serves as a source of
current to the load.
21. Explain the characteristics of ECL.(or)What are the advantages of ECL over TTL?
 It is the fastest of logic families. The popular 10K and 100K ECL families offer
propagation delay as short as 1ns.
 Transistor are not allowed to go into the complete saturation and thus eliminates the
storage delays.
 Switching transients are less because power supply current is more stable than in TTL
and CMOS circuits.
22. Explain the characteristics of Digital IC.
 Logic flexibility.
 Operating speed.
 Availability of complex functions.
 Power dissipation.
 Supply voltage.
 Noise immunity and Noise generation.
 Fan-in and Fan-out.
22. What are the disadvantages of ECL.
 As logic levels are kept close to each other, noise margin is reduced and it is difficult to
achieve good noise immunity.
 Power consumption is more because transistors are not completely saturated.
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24.Define DTL.
The DTL is a low-cost saturated logic type digital IC family, which is almost an extension of
discrete logic circuits, It makes use of diodes and BJTs.
25.What are the advantages and disadvantages of DTL?
Advantages:
 Compatability with TTL ICs: this improves flexibility in system design.

 Availability of many functions:AND,NAND,OR,NOR,Exclusive-OR,etc are
available.
 Ease of interfacing with discrete circuits.
 Low power dissipation.
Disadvantages:
 Limited operating speed- The DTL propagation delay is relatively large. When the
transistor goes into saturation from all inputs being high, charge is stored in the base
region. When it comes out of saturation (one input goes low) this charge has to be
removed and will dominate the propagation time
 Low noise immunity,therefore not usefull in industrial applications.
 High temperature sensitivity of threshold voltage.
 Useful for SSI.
26. what are the application of DTL?
 Counters,shift registers,etc.
 Small computers.
 Instrumentation.
27. what is I2L ?
Integrated injection logic (IIL, I2L, or I2L) is a class of digital circuits built with multiple
collector bipolar junction transistors (BJT). It has speed comparable to TTL with almost as low
power as CMOS, making it ideal for use in VLSI (and larger) integrated circuits.
28.Define CMOS.
CMOS circuit contains both NMOS and PMOS devices to speed the switching of capacitive
loads. It consumes low power and can be operated at high voltages, resulting in improved noise
immunity.
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29. Sketch the typical CMOS characteristics.
 Operating speed: Slower than TTL series.(25ns to 100ns)

 Every CMOS is vulnerable to the building up of electrical charge on its insulated gate.
30.What are the restrictions of totem-pole circuits in open collector TTL IC?
They are not suitable for the following areas,
 Extending the gates to perform complex functions in an IC chip.

 OR-tieing of output leads of different gates to perform additional functions.
 Driving non-standard loads(e.g.electromechanical relays).
31.Classify the basic families of MOS.
 PMOS- uses only P-channel enhancement MOSFETs.

 NMOS-uses only N-channel enhancement MOSFETs.
 CMOS(complementary MOS- uses both P- and N- channel devices.
32.What are the types of digital IC families.
 DTL-Diode Transistor Logic

 HTL-High threshold Logic.
 TTL-Transistor transistor Logic.
 RTL-Resistor Transistor Logic.
 ECL-Emitter Coupled Logic.
33.What is I2L IC’s?
It is abbreviated as Integrated Injection Logic(IIL), sometimes also called as Merged Transistor

Logic(MTL), this process is quite attractive for LSI/VLSI realization. Its important features are:
a.The circuit is similar to RTL,except that there are no base resistors used.
b.The circuit uses BJTs, both pnp and npn. Therefore the operating speed is quite high.
34. What are the advantage and disadvantages of HTL?
Advantages of HTL
 Increased Noise Margin
 Spike Control
 High Noise Threshold Value
Disadvantage of HTL
 Slow speed due to increased supply voltage resulting in use of high value resistors.
 High power drawn
 High cost
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35. List the application of HTL.
It is useful for all circuit applications in industrial environment employing motors, high voltage
switches, ON-OFF control circuits, etc.
36. What is the difference between CMOS and TTL?
CMOS:
 The input cannot be left open.

 Power dissipation is very less
 Fan out is more than TTL, typically 50.
 More susceptible to noise.
TTL:
 The input can be left open.

 Power dissipation is more than CMOS,but it is constant depend on switching speed.
 Fan out for TTL is 10.
 Less susceptible to noise.
37.How the impurity doping is controlled during the IC fabrication?
The impurity doping is controlled by varying the concentration of chlorides of impurity

elements in the epitaxial reaction chamber.
11 marks
1. Explain the fundamental of monolithic IC technology (April-14)
All the IC’s have interconnected discrete devices inside the chip and the corresponding external
connecting terminals outside. Each pin may have each function and may vary according to the
manufacturer’s design. In order to make the circuit fully operative, the pins in the IC must be
used for supply voltage, input and output connections, and also some external components
according to the needs of the manufacturer.
a) ICs can be classified on the basis of their chip size as given below:
 Small scale integration (SSI)—3 to 30 gates/chip.

 Medium scale integration (MSI)—30 to 300 gates/chip.
 Large scale integration (LSI)—300 to 3,000 gates/chip.
 Very large scale integration (VLSI)—more than 3,000 gates/chip.
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b) On the basis of applications ICs are of two types namely:
 Linear Integrated Circuits

Linear IC’s are used in cases when the relationship between the input and output of a
circuit is linear. An important application of linear IC is the operational amplifier
commonly referred to as op-amp.
 Digital Integrated Circuits.
When the circuit is either in on-state or off-state and not in between the two, the circuit is
called a digital circuit. IC’s used in such circuits are called digital IC’s. They find wide
applications in computers and logic circuits.
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c) Classification of integrated circuits based on the fabrication techniques
i. Monolithic Integrated Circuits
The word ‘monolithic’ comes from the Greek words ‘monos’ and ‘lithos’ which
means ‘single’ and ’stone’. As the name suggests, monolithic IC’s refer to a
single stone or a single crystal. The single crystal refers to a single chip of silicon
as the semiconductor material, on top of which all the active and passive
components needed are interconnected. This is the best mode of manufacturing
IC’ as they can be made identical, and produces high reliability. The cost factor is
also low and can be manufactured in bulk in very less time. They have been found
applicable for C’s used for AM receivers, TV circuits, computer circuits, voltage
regulators, amplifiers and so on.
Monolithic-IC in can type Enclosure
Being as it is, monolithic IC’s have some limitations as well.
1. Monolithic IC’s have low power rating. They cannot be used for low power
applications as they cannot have a power rating of more than 1 watt.
2. The isolation between the components inside the IC is poor.
3. Components like inductor cannot be fabricated to the IC.
4. The passive components that are fabricated inside the IC will be if small value. For
higher values they have to be connected externally to the IC pins.
5. It is difficult to make a circuit flexible for any kind of variation; a new set of
masks is required.
ii. Thin and Thick Film Integrated Circuit
Thick and thin film IC’s are comparatively larger than monolithic IC’s and smaller
than discrete circuits. They find their use in high power applications. Though it is a
little large in size, these IC’s cannot be integrated with transistors and diodes. Such
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devices have to be externally connected on to its corresponding pins. Passive

components like resisters and capacitors can be integrated.
Both thick and thin film IC’s are explained in detailed below. Though both the IC’s have similar
appearance, properties, and general characteristics, the main difference between the two of them
is the manner in which the film is deposited on to the IC
 Thin Film Integrated Circuits
This IC is fabricated by depositing films of conducting material on the surface of a

glass or ceramic base. The resistors are fabricated by controlling the width and
thickness of the films and by using different materials selected for their resistivity.
For capacitors, a film of insulating oxide is sandwiched between two conducting
films. A spiral form of film is deposited onto the IC to create an inductor.
Mainly two methods are used for producing thin films. One method, called vacuum
evaporation is used in which vaporized material is deposited on a substrate contained
in a vacuum. The other method is called cathode sputtering in which atoms from a
cathode made of the desired film material are deposited on a substrate located
between a cathode and an anode.
 Thick Film Integrated Circuits
They are also commonly called as printed thin film circuits. The desired circuit
pattern is obtained on a ceramic substance by using a manufacturing process called
silk-screen printing technique.
The inks used for printing are usually materials that have resistive, conductive, or
dielectric properties. They are selected accordingly by the manufacturer. The screens
are actually made of fine stainless steel wire mesh. The films are fused to the
substrate after printing by placing them in hot high temperature furnaces.
The fabrication techniques used for thin film passive components are adopted for
thick films as well. As with thin-film circuits, active components are added as
separate devices. A portion of thick-film circuit is given in the figure below.
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When compared to monolithic IC’s, thick and thin film IC’s do have some advantages.
They have the advantage of better tolerance, better isolation between components, and
greater flexibility in circuit design that further helps in providing high frequency
performance. But, these are the only factors that must be considered for the application
of such IC’s as they are costly in making, and has higher dimensions than monolithic
IC’s. They also cannot be used to fabricate active components which further increase
the size.
iii. Hybrid or Multi-chip Integrated Circuits

As the name suggests, the circuit is fabricated by interconnecting a number of
individual chips. Hybrids ICs are mostly used for high power audio amplifier
applications from 5 Watts to more than 50 Watts. The active components are diffused
transistors or diodes. The passive components may be group of diffused resistors or
capacitors on a single chip, or they may be thin-film components. Interconnection
between the individual chips is made by wiring process or a metallized pattern.
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The diagram of a hybrid or multi-chip IC is shown in the figure above. Hybrid IC’s are
also known to provide a better performance than monolithic IC’s. Although the process
is too expensive for mass production, multi-chip techniques are quite economical for
small quantity production and are more often used as prototypes for monolithic ICs.
Based upon the active devices employed the ICs can be classified as bipolar ICs using
bipolar active devices (BJT) and unipolar IC’s using unipolar active devices like FET
2.Explain the basic process used to fabricate ICs using silicon planar technology. (April-15)
(Nov-15A) (May 2017)
Monolithic IC Manufacturing Process
For the manufacture and production of the monolithic IC, all circuit components and their
interconnections are to be formed in a single thin wafer. The different processes carried out for
achieving this are explained below.
1. P-layer Substrate Manufacture
Being the base layer of the IC, the P-type is silicon is first built for the IC. A silicon crystal of P-
type is grown in dimensions of 250mm length and 25mm diameter. The silicon is then cut into
thin slices with high precision using a diamond saw. Each wafer will precisely have a thickness
of 200 micrometer and a diameter of 25 mm. These thin slices are termed wafers. These wafers
may be circular or rectangular in shape with respect to the shape of the IC. After cutting
hundreds of them each wafer is polished and cleaned to form a P-type substrate layer.
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2. N-type Epitaxial Growth
The epitaxial growth process of a low resistive N-type over a high resistive P-type is to be
carried out. This is done by placing the n-type layer on top of the P-type and heating then inside
a diffusion furnace at very high temperature (nearly 1200C). After heating, a gas mixture f
Silicon atoms and pentavalent atoms are also passed over the layer. This forms the epitaxial layer
on the substrate. All the components required for the circuit are built on top of this layer. The
layer is then cooled down, polished and cleaned.
3. The Silicon Dioxide Insulation Layer
As explained above, this layer is required contamination of the N-layer epitaxy. This layer is
only 1 micrometer thin and is grown by exposing the epitaxial layer to oxygen atmosphere at
1000 0C. A detailed image showing the P-type, N-type epitaxial layer and SiO2 layer is given
below.
Monolithic IC-Substrates and Layers
4. Photolithographic Process for SiO2
To diffuse the impurities with the N-type epitaxial region, the silicon dioxide layer has to be
etched in selected areas. Thus openings must be brought at these areas through photolithographic
process. In this process, the SiO2 layer is coated with a thin layer of a photosensitive material
called photoresist. A large black and white pattern is made in the desired patter, where the black
pattern represents the area of opening and white represents the area that is left idle. This pattern
is reduced in size and fit to the layer, above the photoresist. The whole layer is then exposed to
ultraviolet light. Due to the exposure, the photoresist right below the white pattern becomes
polymerized. The pattern is then removed and the wafer is developed using a chemical like
trichloroethylene. The chemical dissolves the unpolymerized portion of the photoresist film and
leaves the surface. The oxide not covered by polymerized photoresist is then removed by
immersing the chip in an etching solution of HCl. Those portions of the Si02 which are protected
by the photoresist remain unaffected by the acid. After the etching and diffusion process, with
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the help of chemical solvents like sulphuric acid, the resist mask is then removed by mechanical
abrasion. The appropriate impurities are then diffused through oxide free windows.
Monolithic IC - Photolithographic-Process
5. Isolation Diffusion
After photolithographic process the remaining SiO2 layer serves as a mask for the diffusion of
acceptor impurities. To get a proper time period for allowing a P-type impurity to penetrate into
the N-type epitaxial layer, isolation diffusion is to be carried out. By this process, the P-type
impurity will travel through the openings in SiO2 layer, and the N-type layer and thus reach the
P-type substrate, Isolation junctions are used to isolate between various components of the IC.
The temperature and time period of isolation diffusion should be carefully monitored and
controlled. As a result of isolation diffusion, the formation of N-type region called Isolation
Island occurs. Each isolated island is then chosen to grow each electrical component. From the
figure below you can see that the isolation islands look like back-to-back P-N junctions. The
main use if this is to allow electrical isolation between the different components inside the IC.
Each electrical element is later on formed in a separate isolation island. The bottom of the N-type
isolation island ultimately forms the collector of an N-P-N transistor. The P-type substrate is
always kept negative with respect to the isolation islands and provided with reverse bias at P-N
junctions. The isolation will disappear if the P-N junctions are forward biased.
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Monolithic IC - Isolation Diffusion
An effect of capacitance is produced in the region where the two adjoining isolation islands are
connected to the P-type substrate. This is basically a parasitic capacitance that will affect the
performance of the IC. This kind of capacitance is divided into two. As shown in the figure C1
is one kind of capacitance that forms from the bottom of the N-type region to the substrate and
capacitance C2 from the sidewalls of the isolation islands to the P-region. The bottom component
C1 is essentially due to step junction formed by epitaxial growth and, therefore, varies as the
square root of the voltage V between the isolation region and substrate. The sidewall capacitance
C2 is associated with a diffused graded junction and so varies as (-1/2) exponential of V. The
total capacitance is of the order of a few picoFarads.
6. Base Diffusion
The working of base diffusion process is shown in the figure below. This process is done to
create a new layer of SiO2 over the wafer. P-regions are formed under regulated environments by
diffusing P-type impurities like boron. This forms the base region of an N-P-N transistor or as
well as resistors, the anode of diode, and junction capacitor. In this case, the diffusion time is so
controlled that the P-type impurities do not reach the substrate. The resistivity of the base layer is
usually much higher than that of the isolation regions.
Monolithic IC - Base Diffusion
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The isolation regions will have a lot lesser resistivity than that of the base layer.
7. Emitter Diffusion
Masking and etching process is again carried out to form a layer of silicon dioxide over the entire
surface and opening of the P-type region. The transistor emitters, the cathode regions for diodes,
and junction capacitors are grown by diffusion using N-type impurities like phosphorus through
the windows created through the process under controlled environmental process. As shown in
the figure below there are two additional windows: W1 and W2. These windows are made in the
N-region to carry an aluminum metallization process.
Emitter Diffusion
8. Aluminum Metallization
The windows made in the N-region after creating a silicon dioxide layer are then deposited with
aluminum on the top surface. The same photoresist technique that was used in photolithographic
process is also used here to etch away the unwanted aluminum areas. The structure then provides
the connected strips to which the leads are attached. The process can be better understood by
going through the figure below.
Aluminium Metallization
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9. Etching and Mounting
This is the final stage of the IC manufacturing process. After the metallization process, the
silicon wafer is then scribed with a diamond tipped tool and separated into individual chips. Each
chip is then mounted on a ceramic wafer and is attached to a suitable header. Next the package
leads are connected to the IC chip by bonding of aluminum or gold wire from the terminal pad
on the IC chip to the package lead. Thus the manufacturing process is complete. Thus, hundreds
of IC’s is manufactured simultaneously on a single silicon wafer.
EXAMPLE:
A) Diodes
They are also fabricated by the same diffusion process as transistors are. The only difference is
that only two of the regions are used to form one P-N junction. In figure, collector-base junction
of the transistor is used as a diode. Anode of the diode is formed during the base diffusion of the
transistor and the collector region of the transistor becomes the cathode of the diode. For high
speed switching emitter base junction is used as a diode.
B) Resistors
The resistors used in IC’s are given their respective ohmic value by varying the concentration of
doping impurity and depth of diffusion. The range of resistor values that may be produced by the
diffusion process varies from ohms to hundreds of kilohms. The typical tolerance, however, may
be no better than ± 5%, and may even be as high as ± 20%. On the other hand, if all the resistors
are diffused at the same time, then the tolerance ratio may be good. Most resistors are formed
during the base diffusion of the integrated transistor, as shown in figure below. This is because it
is the highest resistivity region. For low resistance values, emitter region is used as it has much
lower resistivity.
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Another diffusion technique is also used for the growth of IC resistors. It is basically a thin-film
technique. In this process a metal film is deposited on a glass or Si0 2 surface. The resistance
value can be controlled by varying thickness, width and length of the film. Since diffused
resistors can be processed while diffusing transistors. This technique is more economic and less
time consuming and therefore, the most widely used.
C) Capacitors
The figure below shows the P and N-regions forming the capacitor plates. The dielectric of the
capacitor is the depletion region between them.
Monolithic IC - Diffused Capacitor Fabrication
All P-N junctions have capacitance so capacitors may be produced by fabricating junctions. The
amount of change in the reverse bias varies the value of junction capacitance and also the
depletion width. The value may be as less as 100 picoFarads.
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Monolithic IC - Thin Plate Capacitor
Using the silicon dioxide as a dielectric may also be a way to fabricate capacitors. One plate of
the capacitors is formed by diffusing a heavily doped N-region. The other plate of the capacitor
is formed by depositing a film of aluminium on the silicon dioxide dielectric on the wafer
surface. For such a capacitor, a voltage of any polarity can be used, and when comparing a
diffused capacitor with such a capacitor the diffused capacitor may have very small values of
breakdown voltage.
3. With neat diagram, explain the fabrication of BJT transistor.(7) ( Nov-13)
Transistors
The fabrication process of a transistor is shown in the figure below. A P-type substrate is first
grown and then the collector, emitter, and base regions are diffused on top of it as shown in the
figure. The surface terminals for these regions are also provided for connection.
1. 22
Monoilithic IC - Transistor Fabrication
Both transistors and diodes are fabricated by using the epitaxial planar diffusion process that is
explained earlier. In case of discrete transistors, the P-type substrate is considered as the
collector. `But this is not possible in monolithic IC’s, as all the transistors connected on one P-
type substrate would have their collectors connected together. This is why separate collector
regions are diffused into the substrate.
Even though separate collector regions are formed, they are not completely isolated from the
substrate. For proper functioning of the circuit it is necessary that the P-type substrate is always
kept negative with respect to the transistor collector. This is achieved by connecting the substrate
to the most negative terminal of the circuit supply. The unwanted or parasitic junctions, even
when reverse-biased, can still affect the circuit performance adversely. The junction reverse
leakage current can cause a serious problem in circuits operating at very low current levels. The
capacitance of the reverse-biased junction may affect the circuit high-frequency performance,
and the junction break down voltage imposes limits on the usable level of supply voltage. All
these adverse effects can be reduced to the minimum if highly resistive material is employed for
the substrate. If the substrate is very lightly doped, it will behave almost as an insulator.
4. With neat diagram, explain the fabrication of CMOS.
The CMOS can be fabricated using different processes such as:
 N-well process for CMOS fabrication

 P-well process
 Twin tub-CMOS-fabrication process
CMOS can be obtained by integrating both the NMOS and PMOS transistors on the same chip
substrate. For integrating these NMOS and PMOS devices on the same chip, special regions
called as wells or tubs are required in which semiconductor type and substrate type are opposite
to each other.
A P-well has to be created on a N-substrate or N-well has to be created on a P-substrate. In this

article, the fabrication of CMOS is described using the P-substrate, in which the NMOS
transistor is fabricated on a P-type substrate and the PMOS transistor is fabricated in N-well.
The fabrication process involves twenty steps, which are as follows: IC Fabrication Process:
Step1: Substrate
Primarily, start the process with a P-substrate.
1. 23
Step2: Oxidation
The oxidation process is done by using high-purity oxygen and hydrogen, which are exposed in
an oxidation furnace approximately at 1000 degree centigrade.
Step3: Photoresist
A light-sensitive polymer that softens whenever exposed to light is called as Photoresist layer. It
is formed.
Step4: Masking
The photoresist is exposed to UV rays through the N-well mask
1. 24
Step5: Photoresist removal
A part of the photoresist layer is removed by treating the wafer with the basic or acidic solution.
Step6: Removal of SiO2 using acid etching
The SiO2 oxidation layer is removed through the open area made by the removal of photoresist
using hydrofluoric acid.
Step7: Removal of photoresist
The entire photoresist layer is stripped off, as shown in the below figure.
Step8: Formation of the N-well
By using ion implantation or diffusion process N-well is formed
Step9: Removal of SiO2
1. 25
Using the hydrofluoric acid, the remaining SiO2 is removed.
Step10: Deposition of polysilicon
Chemical Vapor Deposition (CVD) process is used to deposit a very thin layer of gate oxide.
Step11: Removing the layer barring a small area for the Gates
Except the two small regions required for forming the Gates of NMOS and PMOS, the
remaining layer is stripped off.
Step12: Oxidation process
Next, an oxidation layer is formed on this layer with two small regions for the formation of the
gate terminals of NMOS and PMOS.
Step13: Masking and N-diffusion
By using the masking process small gaps are made for the purpose of N-diffusion.
1. 26
The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the
formation of the terminals of NMOS.
Step14: Oxide stripping
The remaining oxidation layer is stripped off.
Step15: P-diffusion
Similar to the above N-diffusion process, the P-diffusion regions are diffused to form the
terminals of the PMOS.
Step16: Thick field oxide
A thick-field oxide is formed in all regions except the terminals of the PMOS and NMOS.
1. 27
Step17: Metallization
Aluminium is sputtered on the whole wafer.
Step18: Removal of excess metal
The excess metal is removed from the wafer layer.
Step19: Terminals
The terminals of the PMOS and NMOS are made from respective gaps.
Step20: Assigning the names of the terminals of the NMOS and PMOS
1. 28
5. With neat diagram, explain the fabrication of FET.
 The epitaxial layer which formed the collector of BJT is used as the n-channel of JFET
 p+ gate is formed by diffusion or ion implantation
 n+ region have been formed under the drain and source contact region to provide good
ohmic contact.
1. 29
6. With neat diagram, explain the fabrication of MOSFET.
 There are two type of MOSFET devices-enhancement and depletion type

 Metallic gate G is separated by insulating Sio 2 layer

The insulating layer of silicon dioxide gives high input resistance for the MOSFET.
The value of threshold voltage for MOSFET fabricated is typically 3 to 6 V and power
supply voltage of 12 V is used for drain supply.
Use of silicon nitride:
It has superior masking properties compared to silicon dioxide.
It is sandwiched between two silicon dioxide layers and provide necessary barrier to prevent
impurities penetrating through the silicon dioxide layer.
The dielectric constant of silicon nitride is 7.5 whereas silicon dioxide is 4.
This increased dielectric constant reduces threshold voltage.
Polysilicon when doped with phosphorous is conductive and is used as gate electrode
instead of aluminium .
This reduces the threshold voltage to about 1 to 2 V.Such devices are called silicon gate
MOS transistors.
The process is as follows:

Silicon nitride is first coated on the entire surface of a p type wafer.
Silicon nitride is then etched away from the surface outside the transistor region.
Now p+ impurities are ion implanted in the exposed p substrate.
These p+ regions serve to isolate various devices .Next a thick silicon dioxide layer called
field oxide is grown over p+ regions. Silicon nitride layer however remains unaffected by the
oxidation.
1. 30
The silicon nitride is now removed by selective etching and then silicon dioxide is thermally
grown over the transistor area.
Polycrystalline silicon commonly called polysilicon is now deposited over the entire wafer.
The polysilicon gate is no formed by selective removal of polysilicon.
The n+ source and drain regions are formed by ion implantation.
The field oxide and the polysilicon gate prevent the penetration of dopants below the
regions.
The thin oxide layer however allows the penetration of dopants and thus drain and source
regions are formed.
After this entire wafer is covered with a protective isolating layer usually of silicon dioxide.
The contact areas are next defined using photolithographic process.
Finally aluminium is evaporated over the entire wafer and another mark is used to pattern
the circuit connections.
7. Explain briefly about the logic families of digital IC’s. (Nov-15A)
Digital Logic Families
Logic families can be classified broadly according to the technologies they are
built with. The various technologies are listed below.
 DL : Diode Logic.
 RTL : Resistor Transistor Logic.
 DTL : Diode Transistor Logic.
 HTL : High threshold Logic.
 TTL : Transistor Transistor Logic.
 I2L : Integrated Injection Logic.
 ECL : Emitter coupled logic.
 MOS : Metal Oxide Semiconductor Logic (PMOS and NMOS).
 CMOS : Complementary Metal Oxide Semiconductor Logic.
Among these, only CMOS is most widely used by the ASIC (Chip) designers.
Basic Concepts
o Fan-in.
o Fan-out.
o Noise Margin.
o Power Dissipation.
1. 31
o Gate Delay.
o Wire Delay.
o Skew.
o Voltage threshold
Fan – in:
Fan-in is the number of inputs a gate has, like a two input AND gate has fan-in of two, a
three input NAND gate as a fan-in of three. So a NOT gate always has a fan-in of one.
The figure below shows the effect of fan-in on the delay offered by a gate for a CMOS
based gate. Normally delay increases following a quadratic function of fan-in.
Fan – out:
The number of gates that each gate can drive, while providing voltage levels in the
guaranteed range, is called the standard load or fan-out. The fan-out really depends on the
amount of electric current a gate can source or sink while driving other gates. The effects
of loading a logic gate output with more than its rated fan-out has the following effects.
o In the LOW state the output voltage VOL may increase above VOLmax.
o In the HIGH state the output voltage VOH may decrease below VOHmin.
o The operating temperature of the device may increase thereby reducing the
reliability of the device and eventually causing the device failure.
o Output rise and fall times may increase beyond specifications
o The propagation delay may rise above the specified value.
Normally as in the case of fan-in, the delay offered by a gate increases with the increase
in fan-out.
1. 32
Gate Delay
Gate delay is the delay offered by a gate for the signal appearing at its input, before it
reaches the gate output. The figure below shows a NOT gate with a delay of "Delta",
where output X' changes only after a delay of "Delta". Gate delay is also known as
propagation delay.
Gate delay is not the same for both transitions, i.e. gate delay will be different for low to
high transition, compared to high to low transition.Low to high transition delay is called
turn-on delay and High to low transition delay is called turn-off delay.
Wire Delay
Gates are connected together with wires and these wires do delay the signal they carry,
these delays become very significant when frequency increases, say when the transistor
sizes are sub-micron. Sometimes wire delay is also called flight time (i.e. signal flight
time from point A to B). Wire delay is also known as transport delay.
1. 33
Skew
The same signal arriving at different parts of the design with different phase is known as
skew. Skew normally refers to clock signals. In the figure below, clock signal CLK
reaches flip-flop FF0 at time t0, so with respect to the clock phase at the source, it has at
FF0 input a clock skew of t0 time units. Normally this is expressed in nanoseconds.
The waveform below shows how clock looks at different parts of the design.
1. 34
Logic levels
Logic levels are the voltage levels for logic high and logic low.
 VOHmin : The minimum output voltage in HIGH state (logic '1'). VOHmin is 2.4 V for
TTL and 4.9 V for CMOS.
 VOLmax : The maximum output voltage in LOW state (logic '0'). VOLmax is 0.4 V for
TTL and 0.1 V for CMOS.
 VIHmin : The minimum input voltage guaranteed to be recognised as logic 1. VI Hmin is
2 V for TTL and 3.5 V for CMOS.
 VILmax : The maximum input voltage guaranteed to be recognised as logic 0. VI Lmax is
0.8 V for TTL and 1.5 V for CMOS.
Current levels
 IOHmin: The maximum current the output can source in HIGH state while still
maintaining the output voltage above VOHmin.
 IOLmax : The maximum current the output can sink in LOW state while still
maintaining the output voltage below VOLmax.
 IImax : The maximum current that flows into an input in any state (1µA for CMOS).
Noise Margin
Gate circuits are constructed to sustain variations in input and output voltage levels.
Variations are usually the result of several different factors.
 Batteries lose their full potential, causing the supply voltage to drop
 High operating temperatures may cause a drift in transistor voltage and current
characteristics
 Spurious pulses may be introduced on signal lines by normal surges of current in
neighbouring supply lines.
All these undesirable voltage variations that are superimposed on normal operating
voltage levels are called noise. All gates are designed to tolerate a certain amount of noise
on their input and output ports. The maximum noise voltage level that is tolerated by a
gate is called noise margin. It derives from I/P-O/P voltage characteristic, measured
under different operating conditions. It's normally supplied from manufacturer in the gate
documentation.
1. 35
 LNM (Low noise margin): The largest noise amplitude that is guaranteed not to
change the output voltage level when superimposed on the input voltage of the logic
gate (when this voltage is in the LOW interval). LNM=VI Lmax-VOLmax.
 HNM (High noise margin): The largest noise amplitude that is guaranteed not to
change the output voltage level if superimposed on the input voltage of the logic gate
(when this voltage is in the HIGH interval). HNM=VOHmin-VIHmin
tr (Rise time)
The time required for the output voltage to increase from V ILmax to VIHmin.
tf (Fall time)
The time required for the output voltage to decrease from VIHmin to VILmax.
tp (Propagation delay)
The time between the logic transition on an input and the corresponding logic transition
on the output of the logic gate. The propagation delay is measured at midpoints.
Power Dissipation
Each gate is connected to a power supply VCC (VDD in the case of CMOS). It draws a
certain amount of current during its operation. Since each gate can be in a High,
Transition or Low state, there are three different currents drawn from power supply.
 ICCH: Current drawn during HIGH state.

 ICCT: Current drawn during HIGH to LOW, LOW to HIGH transition.
 ICCL: Current drawn during LOW state.
For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If
we assume that ICCH and ICCL are equal then,
Average Power Dissipation = Vcc * (ICCH + ICCL)/2
For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the
Average power dissipation is calculated as below.
Average Power Dissipation = Vcc * ICCT.
So for TTL like logics family, power dissipation does not depend on frequency of
operation, and for CMOS the power dissipation depends on the operation frequency.
1. 36
Power Dissipation is an important metric for two reasons. The amount of current and
power available in a battery is nearly constant. Power dissipation of a circuit or system
defines battery life: the greater the power dissipation, the shorter the battery life. Power
dissipation is proportional to the heat generated by the chip or system; excessive heat
dissipation may increase operating temperature and cause gate circuitry to drift out of its
normal operating range; will cause gates to generate improper output values. Thus power
dissipation of any gate implementation must be kept as low as possible.
Moreover, power dissipation can be classified into Static power dissipation and Dynamic
power dissipation.
 Ps (Static Power Dissipation): Power consumed when the output or input are not
changing or rather when clock is turned off. Normally static power dissipation is
caused by leakage current. (As we reduce the transistor size, i.e. below 90nm,
leakage current could be as high as 40% of total power dissipation).
 Pd (Dynamic Power Dissipation): Power consumed during output and input
transitions. So we can say Pd is the actual power consumed i.e. the power
consumed by transistors + leakage current.
Total power dissipation = static power dissipation + dynamic power dissipation.
8. Explain briefly about Diode logic, DTL,RTL
a)Diode logic
Diode logic was used extensively in the construction of early computers, where semiconductor
diodes could replace bulky and costly active vacuum tube elements.
i. OR logic gate
If any input A OR B OR C is 1, the output will be 1. Only if all inputs, A and B

and C are 0 will the output be 0.
1. 37
This is the definition of a logic OR. The truth table on the right of the image
shows the output for all combinations of inputs.
If any input switches to a positive voltage (logic 1), current flowing through the
now forward-biased diode will pull the output voltage up, providing a positive
voltage at the output, a logic 1. Any positive voltage will represent a logic 1
state; the summing of currents through multiple diodes does not change the logic
level. The other diodes are reverse biased and conduct no current.
ii. AND logic gate
The diode AND is basically the same as the OR except it is turned upside down.
The diodes are reversed so that the cathodes are connected to the inputs and the
anodes are connected together to provide the output.
R is connected to +12 volts to provide the forward bias current for the diodes and
current for output drive.
b)Diode–transistor logic (DTL)
The DTL circuit shown in the picture consists of three stages: an input diode logic stage
(D1, D2 and R1), an intermediate level shifting stage (R3, R4 and V−) and an output common-
emitter amplifier stage (Q1 and R2). If both inputs A and B are high (logic 1; near V+), then the
diodes D1 and D2 are reverse biased. Resistors R1 and R3 will then supply enough current to
turn on Q1 (drive Q1 into saturation) and also supply the current needed by R4. There will be a
small positive voltage on the base of Q1 (VBE about 0.3 V for germanium and 0.6 V for silicon
transistors).
1. 38
The turned on transistor's collector current will then pull the output Q low (logic 0;
VCE(sat) usually less than 1 volt). If either or both inputs is low, then one of the input diodes
conducts and pulls the voltage at the anodes to a value less than about 2 volts. R3 and R4 then
act as a voltage divider that makes Q1's base voltage negative and consequently turns off Q1.
Q1's collector current will be essentially zero, so R2 will pull the output voltage Q high (logic 1;
near V+).
c)Resistor Transistor Logic
a) One-transistor RTL NOR gate
The logical operation OR is performed by applying consecutively the two arithmetic

operations addition and comparison (the input resistor network acts as a parallel voltage summer
with equally weighted inputs and the following common-emitter transistor stage as a voltage
comparator with a threshold about 0.7 V). The equivalent resistance of all the resistors connected
to logical "1" and the equivalent resistance of all the resistors connected to logical "0" form the
two legs of a composed voltage divider driving the transistor.
1. 39
The base resistances and the number of the inputs are chosen (limited) so that only one
logical "1" is sufficient to create base-emitter voltage exceeding the threshold and, as a result,
saturating the transistor. If all the input voltages are low (logical "0"), the transistor is cut-off.
The pull-down resistor R1 biases the transistor to the appropriate on-off threshold. The output is
inverted since the collector-emitter voltage of transistor Q1 is taken as output, and is high when
the inputs are low. Thus, the analog resistive network and the analog transistor stage perform the
logic function NOR
b)Multi-transistor RTL NOR gate
In this configuration, the inputs are completely separated and the number of inputs is limited
only by the small reverse saturation current of the cut-off transistors at output logical "1".
9. Explain the feature of TTL and ECL logic families. Also discuss their advantage and
disadvantage. (Nov-15) &
Explain the working of totem – pole TTL 2 input NAND gate.(8) ( Nov-13)
a)Transistor Transistor Logic
Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar junction
transistors (BJT) and resistors. It is called transistor–transistor logic because both the logic gating
function (e.g., AND) and the amplifying function are performed by transistors
TTL is notable for being a widespread integrated circuit (IC) family used in many applications
such as computers, industrial controls, test equipment and instrumentation, consumer electronics,
synthesizers, etc.
1. 40
Fundamental TTL gate:
TTL inputs are the emitters of a multiple-emitter transistor. This IC structure is functionally
equivalent to multiple transistors where the bases and collectors are tied together. The output is
buffered by a common emitter amplifier.
Two-input TTL NAND gate with a simple output stage
Inputs both logical ones:
When all the inputs are held at high voltage, the base–emitter junctions of the multiple-emitter
transistor are reverse-biased. Unlike DTL, a small “collector” current (approximately 10µA) is
drawn by each of the inputs. This is because the transistor is in reverse-active mode. An
approximately constant current flows from the positive rail, through the resistor and into the base
of the multiple emitter transistor. This current passes through the base-emitter junction of the
output transistor, allowing it to conduct and pulling the output voltage low (logical zero).
An input logical zero:
 Base-collector junction of the multiple-emitter transistor and the base-emitter junction of

the output transistor are in series between the bottom of the resistor and ground. If one
input voltage becomes zero, the corresponding base-emitter junction of the multiple-
emitter transistor is in parallel with these two junctions.
 A phenomenon called current steering means that when two voltage-stable elements with
different threshold voltages are connected in parallel, the current flows through the path
with the smaller threshold voltage. That is, current flows out of this input and into the
zero (low) voltage source.
 As a result, no current flows through the base of the output transistor, causing it to stop
conducting and the output voltage becomes high (logical one). During the transition the
input transistor is briefly in its active region; so it draws a large current away from the
1. 41
base of the output transistor and thus quickly discharges its base. This is a critical
advantage of TTL over DTL that speeds up the transition over a diode input structure
The main disadvantage of TTL with a simple output stage is the relatively high output
resistance at output logical "1" that is completely determined by the output collector resistor. It
limits the number of inputs that can be connected (the fanout).
b)TTL with a "totem-pole" output stage
To solve the problem with the high output resistance of the simple output stage the second
schematic adds to this a "totem-pole" ("push–pull") output.
Standard TTL NAND with a "totem-pole" output stage
It consists of the
 two n-p-n transistors V3 and V4,
 "lifting" diode V5
 current-limiting resistor R3
 When V2 is "off", V4 is "off" as well and V3 operates in active region as a voltage

follower producing high output voltage (logical "1").
 When V2 is "on", it activates V4, driving low voltage (logical "0") to the output. V 2
and V4 collector–emitter junctions connect V4 base–emitter junction in parallel to the
1. 42
series-connected V3 base–emitter and V5 anode–cathode junctions. V3 base current is

deprived; the transistor turns "off" and it does not impact on the output.
 In the middle of the transition, the resistor R3 limits the current flowing directly
through the series connected transistor V3, diode V5 and transistor V4 that are all
conducting.
 It also limits the output current in the case of output logical "1" and short connection
to the ground. The strength of the gate may be increased without proportionally
affecting the power consumption by removing the pull-up and pull-down resistors
from the output stage
Advantage of TTL with a "totem-pole" output stage is the low output resistance at
output logical "1". It is determined by the upper output transistor V3 operating in
active region as a voltage follower. The resistor R3 does not increase the output
resistance since it is connected in the V3 collector and its influence is compensated by
the negative feedback.
Disadvantage of the "totem-pole" output stage is the decreased voltage level (no
more than 3.5 V) of the output logical "1" (even if the output is unloaded). The reason
of this reduction is the voltage drops across the V3 base–emitter and V5 anode–cathode
junctions
c) Emitter coupled logic
1. 43
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1. 45
10. Explain the feature of MOS families.
1. 46
Truth table of NAND Gate NMOS
1. 47
1. 48
1. 49
11. Explain the features of IIL logic family.(Nov-15)
1. 50
1. 51
12. Comparison of Logic Families
1. 52
13.Additional notes
1. 53
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1. 59
14. Explain in details about HTL logic.
High Threshold Logic (HTL) is a variant of Diode–transistor logic which is used in such
environments where noise is very high
Operation
The threshold values at the input to a logic gate determine whether a particular input is
interpreted as a logic 0 or a logic 1.(e.g. anything less than 1 V is a logic 0 and anything above 3
V is a logic 1. In this example, the threshold values are 1V and 3V). HTL incorporates Zener
diodes to create a large offset between logic 1 and logic 0 voltage levels. These devices usually
ran off a 15 V power supply and were found in industrial control, where the high differential was
intended to minimize the effect of noise.
Advantages
 Increased Noise Margin

 Spike Control
 High Noise Threshold Value
Disadvantage
 Slow speed due to increased supply voltage resulting in use of high value resistors.
 High power draw
Usage
it is used extensively in industrial environments. e.g.
 Logic Controllers with heavy noise

 Heavy Process Machinery
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SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE, PUDUCHERRY

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

Verified by: Approved by:

a) Classification of ICs (Integrated Circuits)

 SSI: Small scale integration. 3 – 30 gates per chip.

b)Types of ICs technology (Integrated Circuits)

divided into three classes:

1. Thin and thick film ICs

c) On the basis of applications ICs are of two types namely:

 Linear Integrated Circuits

What are the processes involving in IC fabrication?

3. Name the different types of IC packages. (April-15)

4. What are the popular IC packages available? (Nov-15A)

 DIP(Dual inline Package) are the most commercial application

b)Surface Mount Technology

 SOIC (Small outline IC)

 QFP (Quad Flat Pack)

 PLCC (Plastic Leaded chip carrier)

Advantages of Integrated Circuits

6. List the disadvantage of integrated circuit(IC) over discrete component circuit.

Disadvantages of Integrated Circuits

7. What are the advantages of CMOS logic family? (Nov-15)

8. What is the purpose of oxidation? (Nov-15A)

Oxidation is a process by which a metal or semiconductor is converted to an oxide. The

9. Define noise margin. (Nov-13)

11. What is meant by FAN-IN & FAN-OUT?

12. What is the propagation delay?

13. What is power dissipation?

15. Define ECL.

17. Define Tri-State TTL.

18. What is totem-pole?

19.Define Schottky TTL.

20. Explain the TTL characteristics.

 The operation of input circuit is similar to the DTL gate.

22. Explain the characteristics of Digital IC.

22. What are the disadvantages of ECL.

25.What are the advantages and disadvantages of DTL?

 Compatability with TTL ICs: this improves flexibility in system design.

26. what are the application of DTL?

27. what is I2L ?

29. Sketch the typical CMOS characteristics.

 Operating speed: Slower than TTL series.(25ns to 100ns)

They are not suitable for the following areas,

 Extending the gates to perform complex functions in an IC chip.

31.Classify the basic families of MOS.

 PMOS- uses only P-channel enhancement MOSFETs.

32.What are the types of digital IC families.

 DTL-Diode Transistor Logic

33.What is I2L IC’s?

It is abbreviated as Integrated Injection Logic(IIL), sometimes also called as Merged Transistor

34. What are the advantage and disadvantages of HTL?

35. List the application of HTL.

36. What is the difference between CMOS and TTL?

 The input cannot be left open.

 The input can be left open.

37.How the impurity doping is controlled during the IC fabrication?

The impurity doping is controlled by varying the concentration of chlorides of impurity

 Small scale integration (SSI)—3 to 30 gates/chip.

b) On the basis of applications ICs are of two types namely:

 Linear Integrated Circuits

c) Classification of integrated circuits based on the fabrication techniques

i. Monolithic Integrated Circuits