Erlangen Classification Scheme

In its simplest form, this classification scheme adds one more level of details to the internal structure of
a computer, compared to Flynn’s scheme. In particular, this scheme considers that in addition to the
control (CNTL) and processing (ALU) units, a third subunit, called the elementary logic unit (ELU), can be
used to characterize a given computer architecture. The ELU represents the circuitry required to
perform the bit-level processing within the ALU. An architecture is characterized using a three-tuple
system (k, d, w) such that k ¼ number of CNTLs, d ¼ number of ALU units associated with one control
unit, and w ¼ number of ELUs per ALU (the width of a single data word). For example, in one of its
models, the ILLAC-IV was made up of a mesh connected array of 64 64-bit ALUs controlled by a
Burroughs B6700 computer. According to Erlangen, this model of the ILLAC-IV is characterized as (1, 64,
64). Postulating that pipelining can exist at all three levels of hardware processing, the

classification includes three additional parameters. These are w0 ¼ the number of pipeline stages per
ALU, d0 ¼ the number of functional units per ALU, and k0 ¼ the number of ELUs forming the control
unit. Given the expected multi-unit nature of each of the three hardware processing levels, a more
general six-tuple can be used to characterize an architecture as follows: (kk0, dd0, ww0). Figure 11.4
illustrates the Erlangen classification system. More complex systems can still be characterized using the
Erlangen system

by using two additional operators, the AND operator, denoted by , and the ALTERNATIVE operator,
denoted as _. For example, an architecture consisting of two computational subunits each having a six-
tuple (k0k0

0, d0d0 0, w0w0 0) and (k1k0 1, d1d0 1, w1w0 1) is characterized using both subunits as (k0k0 0, d0d0 0,
w0w0 0)(k1k0 1, d1d0 1, w1w0 1), while an architecture that can be242 INTRODUCTION TO
MULTIPROCESSORS Figure 11.4 The Erlangen classification scheme expressed using either of the two
subunits is characterized as ,k0k0 0, d0d0 0, w00w0 0. _ ,k1k0 1, d1d0 1, w1w0 1. . For example, a later
design of the ILLAC-IV consisted of two DEC PDP-10 as the

front-end controller where data can only be accepted from one PDP-10 at a time. This version of the
ILLAC-IV can be characterized as (2, 1, 36)(1, 64, 64). Now, since the ILLAC-IV can also work in a half-
word mode whereby there are 128 32-bit processors rather than the 64 64-bit processors, then an
overall characterization of the ILLAC-IV is given by (2, 1, 36)[(1, 64, 64) _ (1, 128, 32)]. As can be seen,
this classification scheme can be regarded as a hierarchical classification that puts more emphasis on the
internal structure of the processing hardware. It does not provide any basis for the classification and/or
grouping of computer architectures. In particular, the classification overlooks the interconnection
among different units.