Power-Electronics-News December-2022 HIGH

DEC
2022
Space-Saving
and Easy to Use:
Interference-Free
Power Supply
with Isolated
MicroModules
VIEWPOINT
TAKING THE NOISE

OUT OF E-MOBILITY
Power Supply
Design
The dependability and interference immunity of power sources are highly regarded requirements in
contemporary industrial facilities. Typically, the plant components are supplied by DC bus systems. Galvanic
isolation prevents transient interference from the supply voltage from propagating into the bus and disrupting
its operation. In this issue, Timur Uludag, senior technical marketing manager at Würth Elektronik, presents a
low-interference bipolar supply in the low-voltage range. Moreover, the latest-generation electronic devices
are extremely compact and with increasingly advanced features. Usually battery-powered, they require high
energy efficiency, starting with basic components like inductors found in DC/DC converters. Because the
efficiency of an inductor is strictly dependent on the core and winding losses, it shall absorb ripple current
while minimizing losses. Stefano Lovati, technical writer for EEWeb, will present a novel power inductor design
to be used in compact and large-current DC/DC converters, suitable to operate even at high frequencies. Low-
power applications, such as wearables and smart devices, require efficient power-conversion systems. In the
case of ultra-low–power devices, with average load current of hundreds of microamps, losses are mainly
due to the control system, whose power absorption shall be minimized and adapted to the load condition.
In this issue, we propose an innovative control architecture that maximizes efficiency by achieving low bias
© eiSos
current (tens of nanoamps) and a frequency-dependent power consumption that is proportional to the load
demands. Other topics are fast-charging solutions in plug-in electric vehicles, silicon carbide and gallium
nitride technology for power design, gallium oxide as a next-generation semiconductor for power devices,
and digital control for power supplies. Growing computational power and miniaturization of electronics in
computing and data centers is increasingly putting pressure on 48-V power delivery and conversion systems.
In this issue, we show the key design parameters and components in a 48-V to 12-V LLC converter using GaN
solutions.
Noise free e-mobility Highlights Yours Sincerely,

e-Mobility is no longer a question of tomorrow and the number of e-vehicles is • Large portfolio of EMC components
increasing day by day. Handling EMI noise is becoming more and more crucial, • Design-in-support Maurizio Di Paolo Emilio
when it comes to design new electronic devices and systems. Würth Elektronik • Samples free of charge
offers a wide range of EMC components, which support the best possible EMI • Orders below MOQ Editor-in-Chief, Power Electronics News
suppression for all kinds of e-mobility applications. With an outstanding design-in • Design kits with lifelong free refill
support, catalogue products ex stock and samples free of charge, the time to
market can significantly be accelerated. Besides ferrites for assembly into cables or
harnesses, Würth Elektronik offers many PCB mounted ferrites and common mode
chokes as well as EMI shielding products.
www.we-online.com/emobility
#EMCFOREMOBILITY
DECEMBER 2022 | www.powerelectronicsnews.com 3

Contents
VIEWPOINT POWER SUPPLIES NEWS VIDEO & PODCAST
Power Supply Design 3 Putting the Power Supply User in Jaguar Land Rover partners with Enhancing Electrification and
COVER STORY — DESIGN

Control 45 Wolfspeed for SiC usage Sustainability with Battery
DESIGN
on next-gen EVs 70 Technology 71
Space-Saving and Easy to Use:
Interference-Free Power Supply with SiC MOSFET Reliability Studies Keysight Technologies Delivers New GaN Devices for Space Applications –
Isolated MicroModules 6 at Ohio State: Short-Circuit High-Power DC Emulator for EV Fast Podcast 71
Capability 49 Charging Applications 70
DESIGN Wine Down Friday with Rob Weber,
AUTOMOTIVE New ZVS Power-Supply ICs Combine Product Line Director at
Transformerless Fast-Charging
Programmability, High Efficiency and Microchip 71
Solutions for PEVs 15 How Toyota Is Diversifying Its
Small Size 70
Strategies for Next-Gen Fusion Energy:
POWER SUPPLIES
Vehicles 57 Mercedes-Benz to Source Lithium What’s next? – Podcast 71
A Novel Inductor Design Boosts Hydroxide from Rock Tech
SEMICONDUCTORS
Efficiency in DC/DC Lithium 70
Converters 22 Power GaN for Better Power-Conversion
SEMICONDUCTORS
Efficiency 61
Approaching the Perfect Switch with

SiC JFETs 26
DESIGN
A Novel Efficient Step-Down Converter

Design for Low-Power
Applications 31
SEMICONDUCTORS
Gallium Oxide: A Next-Gen

Semiconductor for Power
Devices 36
DESIGN
eGaN FETs Enable More Than 4-kW/in.3

Power Density for 48-V to 12-V Power
Conversion 40
4 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 5

COVER STORY — DESIGN Cover Story — Design
presses generally require the use of a selection of the following elements for safe operation:
▶ Isolation amplifiers, analog-to-digital converters (ADCs)
▶ Isolation of digital circuits
▶ Interfaces/bus isolation — RS232, RS485, CAN, Interbus, Profibus
▶ Measurement and data acquisition
All of these applications have one thing in common: the isolation of their supply voltage from the
bus voltage. Why should you galvanically isolate a supply from a bus or from switching components?
Galvanic isolation prevents transient interference from the supply voltage from propagating into
the bus and disrupting its operation.
MICROMODULE WITH HIGH EFFICIENCY

As an isolated DC/DC converter, a power module with galvanic isolation provides a reliable supply
for an ADC in industrial applications. The isolated µModule 1769205132 of the Fixed Isolated
MicroModule (FIMM) series uses chiplet SiP technology to reduce the dimensions by 80%, resulting
in a module with the dimensions 9 × 7 × 3.1 mm3. The board space requirements are reduced by
Space-Saving and Easy more than 50% compared with a standard SMT-8 power module (9 × 7 mm2 versus 13.2 × 12.2 mm2).
to Use: Interference-
The MagI³C power module 1769205132 is based on a full-bridge topology. The module integrates
a switching power stage, control circuitry, rectifier diodes, input and output capacitors, and a
Free Power Supply with

transformer (Figure 1). Because there is no feedback path from the output to the input, the duty
Isolated MicroModules
Modern industrial plants place high demands
on the reliability and interference immunity
of power supplies. Typically, the industrial
components are supplied by DC bus systems.
This article presents a low-interference
bipolar supply in the low-voltage range.
By Timur Uludag, senior technical marketing manager in the MagI³C Power
Modules business unit at Würth Elektronik eiSos Group
Figure 1: Structure of the isolated MicroModule 1769205132 of the FIMM series. It comprises a semiconductor IC, rectifier
Industrial plants like warehouse logistics, filling plants, rolling mills, conveyor belts, and printing
diodes, input and output capacitors, and a transformer.

Cover Story — Design Cover Story — Design
cycle is fixed at 50% and is independent of the load. The output voltage is unregulated and is The resolution that an ADC can provide, i.e., how many bits it effectively makes available, depends,
determined by the transformer turns ratio. The output power of 1 W can be provided up to an among other things, on the noise component of the supply voltage.
ambient temperature of TA = 100˚C without any output current derating. The parasitic coupling
capacitance between the primary and secondary side has a typical value of 8 pF due to the design. The red circuit board in the application in Figure 2 generates a galvanically isolated dual voltage of
With an efficiency of 91%, it is the “best in class” in Würth Elektronik’s complete isolated power ±5 V from an input voltage of 5 V.
module portfolio.
Special features of the circuit are:
Galvanically isolated DC/DC converters are specifically designed to implement voltage isolation ▶ Very low residual ripple at the output
within distributed power supply systems. The FIMM module is particularly suitable for applications ▶ Broadband decoupling between input and output
sensitive to supply interference, such as analog low-frequency circuits and relay-controlled circuits.
The low parasitic capacitance between the primary and secondary sides of the circuitry ensure The dual-voltage supply consists broadly of four functional blocks (Figure 3):
a high degree of decoupling from high-frequency interference. Furthermore, this low parasitic ▶ Input protection circuit: The protection circuit integrates reverse-polarity protection and
capacitance mitigates the potential for common-mode interference to propagate from the primary voltage-transient protection.
switching side to the secondary side of the converter. ▶ Input filter: The first filter stage serves to attenuate conducted interference levels.
Harmonics generated by the switching operations of the DC/DC converter, in the direction
SUPPLYING SENSITIVE SENSORS of the supplying source, are reduced in their amplitude. On the other hand, interference
Applications such as measurement and data acquisition are often built with ADCs, which convert can reach the power module via the power supply and is attenuated by the filter.
the analog measured values, such as a temperature value or a current, into a digital quantity. ▶ The power supply (2 FIMM modules): The power modules convert the voltage and provide
For the acquisition of positive and negative measurement signals, a dual-voltage supply is required. galvanic isolation between the input and output.
Usually, a supply of ±5 V is used in such applications. ▶ Output filter: The current supplied by the power module is a superposition of a DC
current with an AC component. The AC component is the part that is reduced in
amplitude by the filter to provide a “clean” DC voltage for the application to be supplied,
such as an ADC.
Figure 3: The decoupled dual-voltage supply (red board in Figure 2) includes a protection circuit on the input side, a
Figure 2: Example of a sensor application using a decoupled dual-voltage supply (red board) filter on the input side, a power supply (2 FIMM modules),, and a filter on the output side.

Cover Story — Design Cover Story — Design
INPUT PROTECTION CIRCUIT OUTPUT FILTER

The protective circuit on the input side has a two-stage design (Figure 3 left). Diode D1 fulfills Due to its principle of operation, the output voltage of a DC/DC converter does not provide a pure
two tasks: It protects the input from negative transient interference and prevents damage to DC voltage as, for example, with a linear regulator. It is rather a combination of a DC voltage with
the input of the power module in case of reverse-voltage polarity. With a forward voltage of a superimposed AC component. The AC component is specified in the datasheet as an “output
0.3 V at 0.3 A, it clamps the voltage to a value below the maximum operating value specified for voltage ripple and noise” value in mVPP, indicating the peak-to-peak amplitude of the output voltage.
the power module. ADC circuits are sensitive here, as they can only work optimally with a small interference signal from
their supply, which must be lower than the resolution of the ADC.
Diode D2 protects the circuit from positive voltage transients. At a positive voltage transient
between 6 and 9 V from the cathode to the anode, D2 conducts. The effective clamping voltage The circuit shown in Figure 3 on the right is a filter that reduces the interference voltage of the
is then typically 5.7 V and thus in the range of the absolute maximum rating of the power module. FIMM on the output side. The linear two-port filter is constructed from a coupled inductance, with
windings L2a/L2b and capacitors C3 and C4.
INPUT FILTER
The power module operates with a typical Winding L2a conducts the DC component to the load (like a “smoothing choke”), while the AC
internal switching frequency of 300 kHz. The component flows to ground via winding L2b and capacitor C4. The impedance behavior of capacitor
upstream power supplies typically have a C4 causes it to discharge the high-frequency component to ground.
switching frequency of 50 to 500 kHz. This
results in a filter combination that already The magnetic coupling between the two windings, i.e., the negative feedback inductance, which is
has an attenuation of approximately 50 to described by the coupling factor k, is essential for the filter function.
75 dB at approximately 100 kHz to filter
the transient interferences. Due to the winding orientation of the two windings of the coupled inductance, the AC portion of the
current flowing through winding L2b is transferred to winding L2a. The AC portion of the current
The combination of C1, L1, and C2 forms is then superimposed on the DC (AC) current, whereby the AC portion is cancelled out in the load
a pi filter structure. The values of the current as well as compensated via the magnetic coupling and thus reduced.
individual filter components were chosen
with the aim of providing an insertion loss The factor k is used to indicate the coupling between two coil windings, with a value of
of approximately 50 dB starting at 100 kHz. 1 indicating 100% coupling between the two windings. Due to the circuit design, which is similar to a
second-order filter, coupled inductors should be used whose k value is <0.99; otherwise, the circuit
Figure 4 shows the curve of the insertion will easily get into a series resonance (notch filter) and will show a lower filter effect in the frequency
loss of the first filter stage. Here, it can range above the resonant frequency. Ideally, a k of less than 0.98 should be used. The coupled
be clearly seen that from 50 kHz, an inductor WE-DD 744877220 used here has a coupling factor of approximately 0.98. The capacitors
attenuation of approximately 80 dB is used must have the lowest possible ESR value to achieve the desired filter effect. For example,
achievable. the aluminum polymer capacitor WCAP-PTHR 870055673002, which has an ESR value of less than
Figure 4: Plot of the insertion loss of the first filter stage 100 mΩ in the frequency range from 1 kHz to 50 MHz, can be used here as a 22-µF capacitor.
as a simulation in RedExpert. One can clearly see here that
The calculation/simulation can be carried
already from 50 kHz, an attenuation of approximately 80 dB is
achieved. out with the filter designer in RedExpert.1 Measurements have shown that for the ripple voltage of the +5-V branch, a reduction of up to 50%
The tool uses the real properties of of the AC component — related to the unfiltered value — could be achieved.
the components based on measurements for the calculation. This way, the simulated results
correspond better with the real components. The calculation of the insertion loss was carried FIMM LAYOUT RECOMMENDATION
out with a source and load impedance of 50 Ω. Essential for a high insertion loss in practice is an Care has to be taken that the FIMM module has two separate ground connections: pins 1 and 2 for
RF-compatible design that avoids coupling between the components. the primary side and pins 3 and 4 for the secondary side.

Cover Story — Design
From a layout point of view, it must be ensured that the primary and secondary sides are capacitively
decoupled from each other. The input and output capacitors (CIN and COUT) must be placed as closely
as possible to the input and output terminals of the module, respectively. This minimizes the
current-conduction loops, limiting the area of copper, which experiences large changes in current
during operation of the module. Inserting distance between the power module and the input filter
reduces the effect of radiated coupling from the switching circuitry and the filter capacitor CF in the
LC input filter. In practice, a distance of roughly 2.5 cm is sufficient. More detailed information on
the layout can be found in the datasheet of the FIMM2 in the section “DESIGN EXAMPLE”. A layout
recommendation for ALTIUM can be downloaded from the online catalog in the “DOWNLOADS”
section.
References
▶ 1RedExpert Filter Designer
▶ 2
Würth Elektronik. (September 2022). “MagI³C-FIMM Fixed Isolated
MicroModule.” Datasheet.
Timur Uludag, Würth Elektronik

DESIGN
Transformerless
Fast-Charging
Solutions for PEVs
By Stefano Lovati, technical writer for EEWeb
In a plug-in electric-vehicle (PEV) system, chargers can be classified into three levels: AC Level
1 (<1.92 kW), AC Level 2 (<19.2 kW), and DC Level 3 (>19.2 kW).1 Due to their volume and weight,
on-board chargers are not recommended in high-power Level 3 systems.
This article will propose two topologies for off-board non-isolated DC fast chargers with power up
to 22 kW. The typical block scheme of this charger includes an AC/DC rectifier stage, followed by a
DC/DC converter. The AC/DC stage is usually implemented using a single-phase or a three-phase
application, depending on the grid requirements. The three-phase option provides the benefit
of sharing the same hardware for both the grid interface and the DC/DC stage. Read the original
article here.

Design Design
LEAKAGE CURRENT To sum it up, the design of the two-stage bidirectional non-isolated DC fast charger has been based
Leakage current is a typical issue of non-isolated DC fast chargers. The red line in Figure 1 represents on the configuration options shown in Figure 2.
the path of the leakage current that can flow through the ground of the grid and the EV chassis. 2,3
A common solution to this issue lies in the introduction — the power-conversion stages — of
an isolated transformer. However, compared with non-isolated topologies, the isolated system is
significantly more expensive and heavier/larger in bulk. Additionally, the transformer will cause
additional power losses, reducing efficiency.
According to the standard IEC 61851-1, a transformer is not mandatory for EV chargers,4 and if the
residual current device (RCD) is included in the EV system, no additional electrical separation is
necessary. Based on the aforementioned factors, a non-isolated DC fast-charger type is suggested
to address the leakage current issue without using an additional transformer.
Figure 2: Fast DC charger configuration options
THE TOPOLOGIES
Two topologies, single-phase and three-phase, are introduced for the proposed charging solution.
Figure 1: Path of the leakage current in an EV charging system

For the single-phase topology, the phase current can be determined using the equation in Figure 3,
where Ugrid, Igrid, and α are the single-phase voltage, current, and power factor, respectively. Based
on this equation, the required current can be calculated, given the power requirement and the grid
THE CHARGER CONFIGURATION voltage.
The proposed charger solution meets both international (IEC) and U.S. (IEEE, NEMA) standards. For
the IEC standard, the mains voltage is 240 V or 400 V (three-phase), with a line frequency of 50 Hz.
In the proposed DC charger, 390 V and 650 V are selected as the minimum DC bus.
The basic two-level switch arm, Supper and Slower, and LC filter make up the proposed charger.
Given their high ratings for current and voltage, Wolfspeed C2M0025120D SiC MOSFETs are chosen
as the circuit’s principal switches. A 32-Arms–rated switch-arm current is selected for the grid
interface side, taking into account the Power Level 3 requirement of rapid charging and the device’s
rated current. The next section explains the rationale behind selecting the rated current value Figure 3: Phase-current calculation for single-phase topology
(32 ).
Arms

Design Design
The corresponding topology is shown in Figure 4.
Two switch arms combine to form a full-bridge rectifier on the AC/DC side. Only one switch arm is
needed for the DC/DC converter to supply the battery with DC power (up to 8 kW).
Figure 6: Topology of the non-isolated three-phase charger
HARDWARE DESIGN
The experimental hardware consists of the following parts:
▶ Three-phase inverter board, based on six C2M0025120D SiC MOSFETs, six CRD-001 gate
drivers, nine DC bus capacitors (B32774D8505K), and a DC voltage sensor (RP1215D)
Figure 4: Topology of the non-isolated single-phase charger ▶ Component board, based on nine three-phase capacitors (B32774D8126K000, 12 μF),
three voltage sensors (RP1215D), three current sensors (CKSR 25-NP), and three power
relays (T9SV1K15-12)
Similar to the previous case, when the power rate and grid voltage are known, the phase current ▶ Three-phase planar inductors, specifically designed for non-isolated fast-charger
may be determined, as shown in Figure 5. The total number of paralleled switch arms (32 ) can
Arms
applications
then be evaluated. ▶ Microcontrollers: A TMS320F28377S MCU is used to generate the PWM signals for both
the AC/DC converter and DC/DC converter.
▶ Protection devices: To automatically cut off the connection between the output and the
battery, a DC breaker (M9U21240) is installed between the battery itself and the
DC/DC converter. Between the grid interface and the AC/DC converter, a circuit breaker
(F204A-63/0.03) and RCD (M9F22463) are attached. The AC breaker will prevent
overcurrent from occurring in the AC current flowing between the grid and the interface.
If the current leakage from the grid exceeds the threshold, the RCD detects it and
Figure 5: Power calculation for three-phase topology
disconnects the grid from the inverter.
In Figure 6, the relevant topology is shown. Three switch arms make up the AC/DC side of a The sketch of the symmetric circuit on the AC/DC side is shown in Figure 7. The inverter board and
three-phase rectifier. Three switch arms are paralleled for the DC/DC converter to supply the the component board are separated by the high-voltage area by a minimum distance of 8 mm,
battery with DC power (up to 22 kW). providing an 800-V isolation.
As can be seen, AC/DC and DC/DC converters share the same DC bus. In addition to the hardware protection, software protection is used to disable the charger when
unexpected circumstances arise.

Design Design
The peak efficiency reaches 99.3%, while at rated power of 22 kW, the peak efficiency is 98.8%.
The average efficiency at rated power is 98.5%. The zero-sequence current control can avoid the
leakage current because the common point of the grid-side capacitors is connected to the DC bus.
Leakage current will be limited to a low level and fulfill the standards’ requirements.
References
▶ 1Yilmaz, M., and Krein, P.T. (May 2013). “Review of Battery Charger Topologies,
Charging Power Levels, and Infrastructure for Plug-In Electric and Hybrid
Figure 7: Sketch of the three-phase charger on the grid side
Vehicles.” IEEE Transactions on Power Electronics, Vol. 28, No. 5,
pp. 2151–2169.
ADVANTAGES OF THE PROPOSED TOPOLOGIES
Both the proposed non-isolated topologies are transformerless, which considerably reduces ▶ 2
Zhou, L., and Preindl, M. (2018). “Bidirectional Transformerless EV Charging
the space and weight of the charging system. All the components can be placed in a
System via Reconfiguration of 4x4 Drivetrain.” 2018 IEEE Energy Conversion
450 × 400 × 200-mm package, while the estimated power density of 0.6 kW/L is significantly higher
than the competitive fast-charging equipment currently on the market. Congress and Exposition (ECCE), pp. 3923–3927.
The proposed topology improves efficiency by eliminating the losses caused by the transformer in ▶ 3
Zhou, L., and Preindl, M. (2018). “Bidirectional Transformerless EV Charging
comparison with the standalone charger. Figure 8 displays the DC/DC conversion stage’s evaluated System with Low Device Cost and Leakage Current.” 2018 IEEE Energy
efficiency.
Conversion Congress and Exposition (ECCE), pp. 7203–7208.
▶ 4
IEC. “IEC 61851-1:2017: Electric vehicle conductive charging system - Part 1:
General requirements.”
▶ 5
Zhou et al. (2021). “Design of Transformerless Electric Vehicle Charger
with Symmetric AC and DC Interfaces.” 2021 IEEE Applied Power Electronics
Conference and Exposition (APEC).
Figure 8: Tested DC/DC stage efficiency

POWER SUPPLIES Power Supplies
Reduced volume not only enhances the user experience, but it also lowers manufacturing and delivery
expenses. To achieve higher power densities, a common practice is to increase the switching frequency,3
which also helps to reduce the size of both inductors and capacitors.4,5 Operating at a higher frequency,
however, affects the overall efficiency and thermal management. As a result, power inductors should
be able to work under a large current with minimal power loss.
On the market, there are two main types of power inductors: ferrite and metal composite. Due
to its high permeability, wire-wound ferrite is an ideal choice for high-inductance applications.
However, its small saturation flux density limits the size reduction of power inductors and involves
thermal management issues. On the other hand, a higher saturation flux density is provided by
a metal-composite–type inductor, usually built with alloy powder and organic binders with coil
molded inside. At a higher temperature, however, performance deteriorates due to the presence of
organic resin, while power losses are higher than in a ferrite inductor.
THE NOVEL INDUCTOR DESIGN
A Novel Inductor Design

The new inductor employs as magnetic material an Fe-based alloy powder named NPA-F, characterized
by low loss and high saturation. The material is manufactured in a spherical shape using the gas
Boosts Efficiency in
atomization method. That ensures low eddy current loss even at high frequency and protects against
insulation layer cracking.
DC/DC Converters The static magnetization curve of NPA-F,

shown in Figure 1, demonstrates how the
saturation magnetization of this material
is suitable for also handling large currents.
Moreover, alloy powder materials feature a
The inductor is a key component in DC/DC converters due to its ability to suppress the AC ripple thermal conductivity 10× greater than that of
current, providing in output a smoothed DC current. The latest-generation electronic devices are ferrite, meaning they can remove heat more
extremely compact and with increasingly advanced features. Usually battery-powered, they require high easily.
energy efficiency, starting with basic components like inductors found in DC/DC converters. Because
the efficiency of an inductor is strictly dependent on the core and winding losses, it shall absorb ripple The basic structure of the novel inductor
current while minimizing losses. is shown in Figure 2. The core, composed
of metal alloy powder NPA-F, is enclosed
This article will present a novel power inductor design to be used in compact and large current in an embedded single-turn copper
DC/DC converters, suitable to operate even at high frequencies. This inductor, based on an iron Figure 1: Static magnetization curve of NPA-F
winding. The overall size is very compact
(Fe)-based alloy powder, exhibits excellent performance with increased efficiency and smaller size (11 × 7 × 6.5 mm), while the inductance at
compared with a conventional ferrite inductor. Read the original article here. 6
100 kHz is approximately 173 nH with a DC resistance of 0.17 mΩ.
PERFORMANCE VS. SIZE Because this has a relatively high permeability, only a single-turn winding is needed to provide the
Today, engineers are demanded to design smaller power supplies with improved efficiency for desired inductance. Additionally, the structure leaves no gap between winding and magnetic materials,
powering ICs like FPGAs and GPUs, which notoriously operate at a lower voltage and larger current. 1,2
increasing the thermal conductivity and mitigating flux leakage issues.

Power Supplies Power Supplies
THE TEST BENCH The results indicate that, in general, the metal inductor provides better performance. At 500 kHz,
To assess the performance of the inductor, efficiency is improved all over the load range, from 10 A up to 80 A. Moreover, the average temperature
an off-the-shelf DC/DC converter evaluation rise of the metal inductor is 4K lower compared with the ferrite inductor. At higher frequencies, the
board (including a couple of Texas metal inductor still achieves greater efficiency, with an improvement of about 0.7% at 900 kHz and
Instruments TPS546D24A devices) has been 0.5% at 1.5 MHz.
used as a test bench. The TPS546D24A is a
high-efficiency 40-A buck converter providing The test results show also that power loss induced by the NPA-F core is competitive, and the proposed
12 selectable switching frequencies, from inductor can operate efficiently at high frequencies, helping to reduce weight and size and providing
225 kHz up to 1.5 MHz. The evaluation board excellent thermal management.
generates a regulated 0.8-V output voltage
with a maximum current of 80 A. References
Two commercial shielded power inductors

(SLC1480-151MLD from Coilcraft) are
Figure 2: Measured inductance vs. frequency ▶ 1Saito, Y., Yamauchi, H., & Tabata, T. (March 2009). “The ‘MPCG Series’ of
mounted on this evaluation board. The
SLC1480-151MLD has a ferrite core, overall Large-Current Choke Coils Using the Low-Loss Metallic Magnetic Material
size of 12.95 × 13.46 × 8 mm, 150-nH inductance at 100 kHz, and 0.15-mΩ DC resistance. Due to the high ‘Senntix.’” NEC Technical Journal, Vol. 4, pp. 71–75.
permeability of ferrite, an air gap of 0.5 mm is required to delay flux saturation. As can be deduced from
the examination of Figure 3, the metal inductor’s volume and weight are only 43.9% and 64.6% of the ▶ 2
Hudgins, D. (2010). “Power Supply Design Considerations for Modern FPGAs.”
ferrite inductor, respectively — a key factor for reducing the converter’s size.
EE Times.
The measured inductance versus frequency,

▶ 3
Kelly et al. (2007). “Core Materials for High Frequency VRM Inductors.” IEEE
shown in Figure 2, has been obtained by
testing the two types of inductors using an Power Electronics Specialists Conference, pp. 1767–1772.
LCR meter. The metal inductor characteristics
keep increasing until 500 kHz, thus providing ▶ 4
Zhu, F., Li, Q., & Lee, F.C. (2020). “20MHz, Two Phase Negative Coupled
a much higher inductance compared with the Inductor Design for Integrated Voltage Regulator in Smartphone Applications.”
ferrite inductor at 100 kHz. Both inductances
IEEE Applied Power Electronics Conference and Exposition (APEC),
drop quickly above 2 MHz.
pp. 181–187.
The measured inductance versus load
current, at 1 MHz, is shown in Figure 3. Due ▶ 5
Sullivan et al. (2016). “On size and magnetics: Why small efficient power
to the effect of the 0.5-mm air gap, the inductors are rare,” International Symposium on 3D Power Electronics
Figure 3: Measured inductance versus load current at 1 MHz inductance of the ferrite inductor remains
Integration and Manufacturing (3D-PEIM), pp. 1–23.
practically constant up to 80 A. After this
saturation point, it drops rapidly. That might be an issue in case an unexpected current surge occurs.
▶ 6
A Novel Power Inductor and Its Application for Compact, Large Current
That can’t happen with the metal inductor, as the saturation flux density of NPA-F is almost 3× that
of ferrite. The converter efficiency has been tested initially on the original evaluation board with two DC-DC Converters, 2021 IEEE Applied Power Electronics Conference and
SLC1480-151MLD inductors and then replaced with two proposed inductors. Exposition (APEC), Yunfan Zhang; Xiongzhi Guo; Guohua Wang; Qiang Xiao.

SEMICONDUCTORS Semiconductors
The cascode configuration

makes the part convenient to
use with easy gate drive but
diminishes controllability. The
cascode switching speed is
largely defined by the JFET
gate-drain capacitance and
the internal series resistor
RG from JFET gate to the
Si-MOSFET source. RG is
a predefined value and is
inaccessible. The Si-MOSFET
gate has limited effect on
speed because there is
virtually no JFET drain-source
capacitance which would
otherwise feed current back to
Approaching the
the MOSFET gate through its
Figure 1: Theoretical limit of RDS(on) × A with breakdown voltage for switch
own gate-drain capacitance, technologies
Perfect Switch with

to allow slew rate control with
a MOSFET gate resistor. For hard-switching, slew rate control is achieved by adding an external
snubber, which can be a viable solution, with little additional power dissipation. UnitedSiC provides
SiC JFETs recommended snubber and gate resistor values for cascodes a SiC FET “User Guide”.2
Another characteristic of the cascode

By Jonathan Dodge, senior applications engineer at UnitedSiC/Qorvo
arrangement is that there is a significant reverse
recovery effect, when cascodes in series form
SiC JFETs are robust, with high-energy avalanche and short-circuit withstand ratings, and significantly, the leg of a bridge. This is not from a parasitic
they beat all other technologies for the FOM on-resistance per unit die area RDS(on) × A, achieving a body diode, but rather from a short overlap in
value close to the theoretical limit for the material (Figure 1). This figure of merit directly relates to conduction due to the delay in the freewheeling
the practical performance of the switch and its economy, with more die per wafer for comparable cascode’s JFET switching off as its gate
performance than competing technologies. capacitance discharges. The result is reverse
recovery charge that is largely independent of
CAN WE DO BETTER STILL? temperature and current. This recovery charge
SiC cascodes from UnitedSiC (now Qorvo) have a significant edge in many applications, but can they
1
directly affects turn-on switching loss.
be better? The device comprises a SiC JFET and Si-MOSFET in a cascode arrangement to achieve
a normally-off characteristic. Looking at the detail, a cascode is formed as in Figure 2 with the The JFET on its own would be a better switch
Si-MOSFET switching the source of the SiC JFET so that when the Si-MOSFET is off, the JFET source in some respects, most importantly: simple
floats positive, turning the JFET off. When the MOSFET is on, the JFET gate and source are effectively control of slew rates, even lower on-resistance,
shorted, turning it on. and lower reverse recovery charge.
Figure 2: The normal cascode arrangement of SiC FETs

Semiconductors Semiconductors
ISOLATING THE SiC JFET GATE FOR GREATER FLEXIBILITY positive, further enhancing the JFET channel, resulting in about a 15% reduction in RDS(on), faster turn-on,
For lower switching frequency applications, a better arrangement is to bring the JFET gate out to an and no effect on turn-off. A positive 2 V drive is below the “knee” of the JFET gate-source PN junction
external connection, as in Figure 3. The Si-MOSFET can now be seen as simply an “enable,” which can at all operating temperatures, so only a small gate current will flow. This current is in the order of a
be used to ensure an off-state on start-up or during abnormal loss of control power. few milliamps, so minority carrier injection is negligible. This is a simple way to achieve a significant
reduction in conduction loss.
When controlling the JFET gate directly, with no drain-source capacitance, output capacitance
COSS is effectively the JFET gate-drain capacitance CGD, charged entirely by the gate driver instead There is yet another benefit of positive gate drive: the JFET gate-source diode voltage drop can be
of the load. This means switching speed can used as a temperature sensitive parameter for real time, on-chip temperature measurement. For
be directly controlled by gate resistors, and example, -3.22 mV/°C is the linear VGS temperature coefficient for UnitedSiC Gen 3 1200 V JFETs.
paralleling is simplified. An external snubber Die temperature can therefore be directly sensed by measuring the gate-source voltage and the
is now optional, saving space and cost. gate current in the on-state.
When used in a bridge circuit, the recovery
charge effect is from charging the output An even easier way to determine die temperature is to measure the gate leakage current of the
capacitance (CGD) of the freewheeling JFET; Si-MOSFET. Note however that this requires calibration due to part-to-part variation. As with
its gate voltage is unchanged. Thus, the the JFET VGS, MOSFET gate leakage (which is small) directly correlates to temperature. With the
reverse recovery effect is greatly reduced Si-MOSFET die stacked on top of the JFET die, it is an accurate measure of both MOSFET and JFET
with consequent reduction in EON. Turn-off temperatures. The Si-MOSFET is normally kept on, so measurement of the static voltage across its
speed is significantly less than that of the gate resistor with a differential amplifier is an easy way to sense the temperature.
conventional cascode, which is desirable
for example in motor drive and SSCB/SSR A PRACTICAL CIRCUIT ILLUSTRATES THE TECHNIQUE
applications but would probably have too Figure 3: The SiC JFET + Si MOSFET “dual gate,” UnitedSiC Driving the gate of the JFET may seem unfamiliar, with a negative voltage required for the off state and
(now Qorvo) part
much EOFF loss for DC/DC converter and ≥ 0 volts for the on state, but in practice it can be very similar to driving a silicon or SiC MOSFET, which
other SMPS applications. are often driven negative anyway (Figure 4).
THE THIRD-QUADRANT TRADEOFF

A directly driven JFET functions differently in the third quadrant when current flows from source to
drain with the gate off. The standard cascode reverse conducts through the Si-MOSFET body diode
and causes the JFET channel to turn on, resulting in low VSD: a Si-diode drop plus JFET on-resistance.
With the dual gate part, reverse current will flow through the JFET if its gate is on, or the JFET
gate-drain voltage exceeds its threshold voltage. In other words, during the bridge circuit dead time, VSD
will comprise a “knee voltage” equal to the voltage the gate is driven more negative than the threshold
voltage plus the JFET on-resistance. This can be several volts. This deadtime power loss is insignificant
in a motor drive switching at 10 to 20 kHz, and completely irrelevant in SSCB/SSR applications.
For higher frequency SMPS applications, an anti-parallel SiC diode would need to be added.
An anti-parallel diode can be small as it only carries peak currents during the dead time.
THERE ARE MORE GAINS TO BE HAD

So far, we have direct control of switching speed and greatly reduced reverse recovery charge, but
there is another easily achieved advantage. In a standard cascode, the JFET is turned on by its gate
Figure 4: Interfacing to a cascode JFET gate directly with standard drivers and a buffer
being shorted by the Si-MOSFET source. With a dual gate part, the turn-on voltage can be set a little

Semiconductors DESIGN
In the circuit, the only additional element is the buffer Q1, which level-shifts the standard driver
U1 on-state output from +15 V for example, to +2 V supplied through a voltage regulator. The lower
MOSFET in Q1 is optional – the driver IC shown has an off-state output which could be used directly,
but the MOSFET in U1 gives increased current capacity, which could be useful with paralleled
devices. The Si-MOSFET in the dual gate part is controlled by another isolated driver. In the case
that the DC link is energized but the driver loses power, zener diodes D2 and D3 ensure that the
JFET reverts to cascode operation and remains off. Traditional DESAT detection is often included in
drivers, and this can be implemented with the JFET through R4 and D1 in the schematic.
CONCLUSION
To summarize, with little effort, a bond-wire change to the already-class-leading SiC JFET
stacked-chip cascode can be configured to extract all the advantages of a single SiC JFET: simple
switching speed control, even lower on-resistance, and much lower reverse-recovery charge, along
with the bonus feature of real-time temperature-sensing options. With this, the perfect switch gets
a little closer.
A Novel Efficient
Step-Down Converter
Design for Low-Power
Applications
Low-power applications, such as wearables and smart devices, require efficient power-conversion
systems. In the case of ultra-low–power devices, with average load current of hundreds of microamps,
losses are mainly due to the control system, whose power absorption shall be minimized and adapted
References to the load condition.
This article will propose an innovative control architecture that maximizes efficiency by achieving low
▶ 1www.unitedsic.com bias current (tens of nanoamps) and a frequency-dependent power consumption that is proportional
to the load demands. Read the original article here.
▶ www.unitedsic.com/application-notes
2
In ultra-low–power applications, each subsystem needs to be properly interfaced with the main battery1
to reduce overall losses and maximize power adapting.2

Design Design
In such devices, a controller normally operates toggling between two phases: normal operation with
low power absorption and high-current pulses during wireless data transmission.3,4 Because the
constant-current–consumption controller proves to be inefficient in one of the two phases, a different
solution based on an internal VCO is proposed. The VCO remains active with a very small bias current
(20–100 nA), which corresponds to the minimum current consumption of the system at the given
frequency.
To minimize power consumption, appropriate signal timing is generated by an internal digital circuit
composed of a PI regulator driving the VCO to obtain the required frequency. This approach allows the
system to self-calibrate, meeting the effective load power demand.
The power consumption of the analog circuitry is minimized by lowering the bias of each element (like
op amps) or by switching them on for a short time during each cycle and sampling the output value or
their mean value.
THE PROPOSED ARCHITECTURE

The block diagram of the proposed solution is shown in Figure 1. It consists of the following parts:
▶ Bandgap reference: This provides a reference voltage by using sub-threshold MOSFETs.5
Figure 1: Block diagram of the proposed solution
With temperature compensated and enabled for a short time during each cycle, this
reference voltage is used to charge a huge external capacitor, implementing a low-cost All digital blocks are implemented in domino logic, while analog components are either biased with
soft-start feature. small current or switched on for a short time.
▶ PI regulator: This block is also activated for a short time at each cycle to limit current
consumption. The IC can be powered through the voltage VCAP provided by a supercapacitor, or through the voltage
▶ Overpower detector: When the PI regulator’s output exceeds a predefined threshold for VBAT of a Li-ion battery connected to the buck converter inputs. An internal battery management
a certain time, it means that the load is demanding more current. This block notifies this regulator interfaces with these two power supply sources, handling their connection with VDD,
condition to the output. which represents the supply of the internal circuitry.
▶ VCO: This block generates the system clock, and its bias current is selected through an
external resistor. When VCAP is higher than VBAT, VDD is connected to VCAP and VBAT is regulated to a fixed voltage.
▶ One-shot sync signals: These generate a sequence of timing pulses for the dedicated Otherwise, VCAP is isolated and VDD is connected to VBAT.
internal circuitry. These pulses are used both for timing synchronization and as enable
signals for current-demanding circuitry to limit consumption. EXPERIMENTAL RESULTS
▶ Modulator: This block adapts the system clock to the buck-switching pulses. When The following blocks can be recognized: power MOSFETs with driving circuit (upper part), bandgap
output voltage is above a certain threshold, the switching pulses are generated on reference (lower-left corner), and digital-analog control logic (lower part).
each clock rising edge. Otherwise, a switching pulse is generated every n clock cycles
(depending on the output voltage value), thus achieving lower switching frequencies. The waveform of the phase voltage is measured with an oscilloscope in light load (10 μA) and heavy
▶ TON control: An external resistor is used to set the on time (TON), while another resistor load (1 mA).
allows the fine tuning of TON depending on the difference between VIN and VOUT. If this
difference is small, TON is increased to reduce the number of commutations. A magnified view of the phase voltage during a single switching pulse for a 500-μA load current is
▶ Low-side manage: This optional block enables a MOSFET on the low side in place of a shown in Figure 2.
reverse diode. The low-side activation timing (ZCS) is managed by external circuitry.

Design Design
The measurement of IC CONCLUSION

efficiency on load-current This article has proposed an innovative DC/DC switching architecture for ultra-low–power applications.
variations for an input voltage The solution provides high efficiency (90% peak) on a wide range of load current (100 μA to 1 mA)
of 4.5 V and an output voltage while maintaining a low bias current (100 nA) in the idle state. Due to its internal design, the converter
of 3.3 V is shown in Figure 3. remains in a low-frequency commutation state during most of the operation, increasing the operating
In the typical idle working frequency and, consequently, the power consumption only when more power is demanded by the load.
region (100–500 μA), efficiency Internal circuitry manages the energy provided by a battery or a supercapacitor, ensuring availability of
is near 90%, while below this a power source in all operating conditions.
condition, the efficiency drops
because the output current
Figure 2: Phase voltage during single switching pulse is comparable with the global References
control idle current.
▶ 1Amerasekera, A. (2010). “Ultra low power electronics in the next decade.”

2010 ACM/IEEE International Symposium on Low-Power Electronics and
Design (ISLPED), pp. 237–237, doi: 10.1145/1840845.1840892.
▶ 2
Kim, J., and Chu, C. (2014). “Analysis of energy consumption for
wearable ECG devices.” IEEE SENSORS 2014, pp. 962–965, doi: 10.1109/
ICSENS.2014.6985162.
▶ 3
Ghamari et al. (2015). “Comparison of low-power wireless communication
technologies for wearable health-monitoring applications.” 2015 International
Conference on Computer, Communications, and Control Technology (I4CT),
pp. 1–6, doi: 10.1109/I4CT.2015.7219525.
▶ 4
Ting, Y., and Lin, F. J. (2017). “A comparison and evaluation of different
BLE connection methods for wearable devices.” 2017 IEEE Conference on
Standards for Communications and Networking (CSCN), pp. 240–245, doi:
10.1109/CSCN.2017.8088628.
Figure 3: Overall efficiency in function of load current
▶ 5
Li et al. (2011). “A subthreshold MOSFET bandgap reference with ultra-low
The setup used for the efficiency measurement has been optimized for an application with a typical power supply voltage.” 2011 9th IEEE International Conference on ASIC,
load current of 400 μA. In case of different load requirements, the efficiency can still be maximized by pp. 862–865, doi: 10.1109/ASICON.2011.6157341.
tuning some parameters of the architecture, such as the VCO bias and the high-side TON.

SEMICONDUCTORS Semiconductors
To maximize the potential of a novel semiconductor technology, the industry must make a concerted
effort to solve technical obstacles that hinder performance. Significant technological advancement
has taken place in the field of ultra-wide–bandgap semiconductors since 2016, when Flosfia, a
spinoff from Kyoto University specialized in R&D and commercialization of gallium oxide thin films,
concluded that gallium oxide warranted development.
The semiconductor industry is increasingly moving toward implementing devices built from
wide-bandgap materials such as silicon carbide and gallium nitride, but the cost of those materials
remains relatively high. In response, researchers more recently have pursued development of
beta-gallium oxide (β-Ga2O3), a stable phase of the compound. β-Ga2O3 development is a
result of an increased focus on materials research to improve the overall performance of
power-electronic devices over the junction-based approaches of the past. β-Ga2O3 stands out for its
intrinsic properties, including an ultra-high bandgap (an energy gap of 5 eV), good conductivity and
field-holding capacity, and high critical field strength, with the highest ever demonstrated being
5.5 MV/m.
Processing the material in different ways can result in a variety of properties, demonstrating its
flexibility. For example, doping the material from a melt results in a resistivity of 10 mΩ-cm; silicon
implantation can decrease it to 1 mΩ-cm. Halide vapor epitaxy on the material can be controlled to
have a doping concentration in the range of 1015 to 1019 cm–3.
Fabricating standard
features onto β-Ga2O3
Gallium Oxide: A is also relatively

For example, ohmic and
easy.
Next-Gen
Schottky contacts can
be made using standard
metals like titanium,
Semiconductor for aluminum, and nickel at

relatively low annealing
Power Devices
temperatures.
Wafering and lapping of

By Maurizio Di Paolo Emilio the material can be done
using standard production
In the past decade, gallium oxide has seen fast technical development, propelling it to the forefront tools. Different dielectric Figure 1: A top-level view of the technology progress for various sectors toward
of ultra-wide–bandgap semiconductor technologies. The major targeted application space is power materials, such as Al2O3 commercialization of β-Ga2O3 applications as of October 2021 (Source: Link)
electronics, in which gallium oxide’s intrinsic material properties — high critical field strength, deposited using the
widely tunable conductivity, low mobility, and melt-based bulk growth — promise to deliver the atomic layer deposition method, can be used as gate dielectrics (Figure 1).
required high performance at low cost.

THE PROPERTIES OF GALLIUM OXIDE 200 mm. β-Ga2O3 fabrication must move toward these larger wafer sizes to take advantage of the
The high critical field and relatively low mobility of β-Ga2O3 enable it to demonstrate better performance advanced fabrication infrastructure already in place. Moreover, there is no reliability data available for
than SiC and GaN. The properties of the material grown from a melt make it possible to fabricate devices made from β-Ga2O3, as research into this aspect remains in its infancy.
high-quality crystals at a lower-cost bulk GaN, SiC, and diamond. The prime transistor figure of merit
for β-Ga2O3 is approximately 3× that of 4H-SiC and 20% better than the prime transistor FoM for GaN. There are also economic factors that need to be addressed, such as the loss of some parts of
the expensive precious-metal crucibles (in the case of manufacturing methods like edge-defined,
These advantages over existing wide-bandgap materials position β-Ga2O3 as a viable and low-cost film-fed growth [EFG], and the iridium crucibles used with the Czochralski [CZ] method) during the
alternative with increased performance. There are challenges, however, that are holding back its bulk manufacturing of β-Ga2O3 crystals. Increasing the size of the substrate, as demanded by the
large-scale commercialization. state-of-the-art technologies of other semiconductor materials, tends to worsen the problem and
accelerate the decline of these crucibles. Researchers in China have reportedly developed methods
In the context of material properties, the very low thermal conductivity of β-Ga2O3 stands in the that can mitigate the problem
way of efficient heat transfer, a critical aspect of power-electronic devices. Achieving thin β-Ga2O3 and thereby decrease the cost
dies will be central to the efforts to improve the material’s thermal conductivity and develop better of the manufacturing process
heat-removal techniques for β-Ga2O3 devices. by about 10×, but large-
scale implementation of this
The material also has a flat valence band, which results in negligible hole transport, meaning a lack of technology is yet to be seen.
p-type junctions. This prevents the formation of avalanching p-n junctions and therefore is a concern Methods suitable for epitaxial
for devices deployed in regions with noisy power supply or applications involving the need to rapidly take layer growth for vertical β-Ga2O3
over large inductive loads, such as uninterruptible power supplies. The electric fields at the die edge devices require technology not
can affect the device rating: Poor management can result in decreased performance and reliability, and present on state-of-the-art
the lack of a p-type may worsen the problem. Lack of a p-type also imposes restrictions on the design machines.
of e-mode transistors.
THE ROAD TO
Various die termination methods are under VIABLE DEVICES
investigation, such as bevel termination and There is a great deal of
termination using p-type oxides. However, interest and research in the
current solutions to mitigate this problem design, development, and Figure 3: Calculated theoretical performance (RON vs VBK ) for vertical power
devices. Assumptions used in the calculation are listed on the right. The
involve tight process controls, casting a commercialization of devices model takes into account the contact, channel, drift, and substrate
ray of doubt over the material’s viability fabricated with β-Ga2O3. This resistances; p denotes the cell pitch. (Source: Link)
(Figure 2). interest is driving the impressive

growth of substrate-fabrication technologies as companies move toward commercialization.
The small wafer size of β-Ga2O3 relative to
other semiconductors is also a problem, as Although there have been many device demonstrations, considerable optimization work remains to
larger wafer sizes can help decrease the cost be done to address the aforementioned challenges. Nonetheless, β-Ga2O3 technology has reached an
of fabrication while increasing crystal quality exciting moment in its maturity, where the material is readily available and the challenges holding it
and lowering the defect rate. Current methods back from being utilized in devices are well-known and well-documented.
to fabricate β-Ga2O3 devices use a maximum
wafer size of 100 mm, whereas theindustry- A concerted industry effort must first take root, but successful development of technologies for
standard semiconductor wafer diameter is large-scale, economically viable β-Ga2O3 manufacturing would open the door to commercialization,
Figure 2: A typical semiconductor wafer (Source: Tip3X)

150 mm, with more companies heading toward yielding high-reliability devices that fully utilize the material’s advantages.

DESIGN Design
CONVERTER OVERVIEW
The LLC resonant converter presented here features a primary full-bridge and a center-tapped
full-wave synchronous rectifier for the secondary, as shown in Figure 1 (left). Both are coupled with a
planar transformer having a 4:1 turns ratio. The power FETs used in the primary and secondary, together
with the transformer and printed-circuit boards, are the key components of the module. Figure 1 (right)
shows a photo of the overall module assembled.
eGaN FETs Enable More

Than 4-kW/in.3 Power
Density for 48-V to
12-V Power Conversion
GaN transistors in a chip-scale package Figure 1: Topology of the LLC converter (left); photo of the assembled LLC power converter module (right)
enable higher than 4-kW/in.3 power density for POWER TRANSISTORS AND GATE DRIVERS
48-V to 12-V power conversion using an LLC For the primary circuit, four 100-V–rated 3.2-mΩ EPC2218s5 are used in conjunction with two
uP1966Es 6, a half-bridge gate-driver IC. For the secondary rectifier, a total of six 40-V–rated 1.55-mΩ
resonant converter with up to 1-kW capability. EPC2067s7 are used as synchronous rectifiers. These six transistors are divided into two branches,
where each branch consists of an LMG10208 low-side gate driver controlling a parallel array of three
By Alejandro Pozo, senior applications engineer at Efficient Power Conversion EPC2067s. All power transistors and gate drivers are in CSP format for minimum size and lowest
parasitic elements.
Growing computational power and miniaturization of electronics in computing and data centers
is increasingly putting pressure on 48-V power delivery and conversion systems. High-efficiency The choice of eGaN transistors is especially advantageous in the primary given the low RDS(on) × COSS
and high-power–density converters enable a reduction in power losses at the system level while figure of merit compared with equivalent Si MOSFETs. This is because for a similar RDS(on) and voltage
allowing smaller form factors. In this context, LLC resonant topologies combined with GaN rating, GaN transistors offer lower COSS, therefore minimizing the magnetizing current needed to achieve
technology succeed to deliver outstanding performance, as it has been demonstrated with multiple ZVS in as short a transition time as possible. As a result, the frequency can be increased to the 1-MHz
examples.1–4 This article will show the key design parameters and components to achieve beyond range, enabling size reductions in the passive components while maintaining high efficiency.
4 kW/in. of power density in a 48-V to 12-V LLC converter using eGaN FETs. This work is an evolution
3
of Reference 2 and was first introduced in Reference 1, demonstrating 96.3% peak efficiency and The uP1966E half-bridge gate drivers used for the primary are an ideal match for this application, in
93.8% when delivering 1 kW into a 12-V load and with module dimensions of 17.5 × 22.8 × 7.7 mm. which a minimum of 80-V rating and minimum size and external components are key features. Similarly,

Design Design
the LMG1020 offers a tailored solution for this socket, given its minimum footprint and supporting PCB DESIGN
circuitry required, as well as sufficient strength capable of driving the three paralleled EPC2067 FETs With the transformer core dimensions defined, the primary and secondary windings were distributed
without compromising speed. over 16 layers routing the current around the center post of the transformer core. A single 3 ounces per
layer was dedicated to each primary turn and three 3-oz. layers and one 2-oz. layer were paralleled for
While the components listed above enable very high operating frequencies in a very compact form, each branch of the secondary. The inner 12 layers are fabricated with standard PCB technology, whereas
some challenges arise from the different propagation delays between primary and secondary gate HDI technology was utilized for the outer layers. This way, the primary and secondary components can
drivers. To overcome these mismatches, three unique PWM generators with independent dual edge be placed on the top and bottom sides of the board and the current efficiently routed down into the
control are used to align the desired synchronization between primary and secondary circuits. Such transformer windings.
configuration provides the programmable flexibility needed to ensure a balanced square waveform in
the primary, with control of the deadtime to realize ZVS in the primary and maintain ZVS/ZCS in the TESTING RESULTS AND NEXT STEPS
rectifier transistors and minimize circulating energy. To test the converter described in the previous sections, a motherboard was developed to provide
input/output connections for the module, additional bus capacitance, housekeeping power supplies,
TRANSFORMER DESIGN sense connections for accurate efficiency measurements, and a connector for the controller board.
The transformer design and choice of core material are driven by the converter requirements, A photo of the setup is provided in Figure 3 (left), along with waveforms at full load (center) and the
input/output voltage ratio of 4:1, desired output power of 1 kW at 1-MHz resonant frequency, and efficiency curve (right). Peak efficiency of 96.3% could be measured at 25 A and 93.8% at 84 A (1 kW).
maximum size of 17.5 × 23 mm. Building on the experience from previous work 1,2
and aided by
finite-element simulations, a core shape with a single 6-mm–diameter center post and four satellite
flux return legs was designed and shown in Figure 2 (right). The 6-mm diameter for the center post
was found to be the optimal dimension considering conduction losses in the copper windings and core
losses, as analyzed in Reference 1. The final dimensions of the top and bottom side caps of the core
shown in Figure 2 (left) are a compromise between flux density and magnetic core utilization, to open
areas for placing components without increasing core losses. Note that the PCB real state close to
the transformer windings is of utmost interest to minimizing parasitic inductance. As reported in the
literature, this parasitic inductance in the secondary is detrimental to the performance by as much as
30%.4
ML91S,9 the same soft-ferrite

material used in prior work,2
Figure 3: Photo of the test system assembled (left); measured waveforms (center); measured efficiency curve at
was used for the transformer VIN = 48 V (right)
core. It provides good
stability over temperature
and frequency, even beyond In the next iteration of the converter, the controller and housekeeping power supplies will be integrated
1 MHz, as well as less than in the module while maintaining the same overall size. Moreover, a small resonant inductor will be
200 kW/m 3
of flux density added in series with the transformer to increase the Q factor while maintaining the same resonant
volumetric power loss. frequency. The PCB will also experience changes, as the 16-layer board will be replaced with a two-PCB
The airgap between the solution to reduce copper losses and improve manufacturability of the overall system.
two core halves was tuned
to realize a magnetizing CONCLUSION
Figure 2: Top view and dimensions of optimized core (left); full FEA model of inductance of approximately The module presented in this article demonstrates that GaN FETs can enable unprecedented levels of
the core showing the flux density throughout the core (right) 1.8 µH. power density (>4 kW/in.3) in 48-V to 12-V power converters, such as those needed in data centers with

Design POWER SUPPLIES
a 48-V architecture. In particular, the combination of GaN technology featuring chip-scale packaging,
such as those of eGaN transistors, and carefully designed magnetics allows 1-kW load capability at
1-MHz frequency with peak efficiencies and full-load efficiency of 96.3% and 93.8%, respectively.
References
▶ 1de Rooij, M. and Negahdari, A. (2022). “Beyond 4 kW/in3 Power-Density for

48 V to 12 V Conversion using eGaN FETs in an LLC DC-DC Bus Converter.”
PCIM Europe 2022; International Exhibition and Conference for Power
Electronics, Intelligent Motion, Renewable Energy and Energy Management,
pp. 1–9, doi: 10.30420/565822013.
Putting the Power
Supply User in Control
▶ 2
de Rooij et al. (2021). “A 1 kW eGaN FET-based LLC Resonant Converter
in them 1/8th Power Brick Size for 48 V Server Applications.” PCIM Europe
digital days 2021; International Exhibition and Conference for Power
By Caleb Lander, senior product manager at XP Power
Electronics, Intelligent Motion, Renewable Energy and Energy Management,
pp. 1–8.
Traditionally, AC/DC power supply designs could only be optimized for specific load and line conditions.
▶ 3
Ahmed, M.H., Lee, F.C., and Li, Q. (February 2021). “Two-Stage 48-V VRM This stems from classic analog control and simple pulse-width–modulation techniques at a fixed
With Intermediate Bus Voltage Optimization for Data Centers.” IEEE Journal of frequency that has been commonly used, and those constraints typically result in higher component
stresses at the extremes of operating ranges. Datasheets for PSUs often showed heavy derating with
Emerging and Selected Topics in Power Electronics, Vol. 9, No. 1, pp. 702–715,
low input voltages, and outputs were limited to fixed values that could be adjusted by perhaps ±10%
doi: 10.1109/JESTPE.2020.2976107.
at best. Operation adjustable down to zero output voltage and true, accurate constant-current output
▶ 4
Huang, D., Ji, S., and Lee, F.C. (August 2014). “LLC Resonant Converter With were typically confined to expensive laboratory supplies that did not have to be particularly compact
or efficient. Similarly, characteristics like control-loop response, reaction to overloads, and thresholds
Matrix Transformer.” IEEE Transactions on Power Electronics, Vol. 29, No. 8,
of fault detection were “baked into” the design along with any control and monitoring signal levels,
pp. 4339–4347, doi: 10.1109/TPEL.2013.2292676. functionality, and polarities.
▶ 5
EPC. (2021). “EPC2218 datasheet.”
The result of this has been that users have had to work around available power supplies, find the
▶ 6
uPI SEMI. (2021). “uP1966E datasheet.” best compromise, then stock various types for different products. For established end products,
upgrades and changes could be limited to what the power supply would allow; even the need for a
▶ EPC. (2021). “EPC2067 datasheet.”
7
small adjustment to output voltage could entail a major re-specification of the power system design.
▶ 8
Texas Instruments. (2018). “LMG1020 datasheet.” Many applications also specifically require the PSU to be variable in some way, LED constant-current
loads often need to be dimmable, or the output voltage to an electrolysis process might need to be
▶ 9
Hitachi. Material characteristics of ML91S.
programmable to determine a reaction rate. In these cases, the solution has often been an expensive
custom design.

Power Supplies Power Supplies
Customers should not expect the power supply to dictate what their end products can achieve, so requirements: Frequency can be lowered or PFC phases “shed” for better light-load efficiency, and
suppliers of PSUs have always attempted to make their products as versatile as possible. However, the output voltage can be altered “on the fly” for “dynamic voltage scaling” to reduce load power
available technology in the past forced tradeoffs, in price or some other performance parameter, such consumption when idling, loop compensation can be optimized for a particular load resistance and
as size or efficiency. Now, with high power density a prime directive for many good reasons, the tradeoff parallel capacitance for best transient response, and much more. Modern conversion topologies also
might be unacceptable. lend themselves to bidirectional operation, and this becomes a realistic option to configure without
changing hardware with true digital control, even dynamically, for applications like EV charging and
‘DIGITAL’ AND TRUE DIGITAL POWER CONVERSION energy “back-feeding” to the grid.
When they first appeared, “digital” power supplies seemed to promise the flexibility of “software
controlled” power, but the first products simply had digital interfaces to the discrete electronics and With digital control, it becomes trivial to configure levels of output voltage and current along
analog controller. This just allowed easier access to information about how the product behaved rather with monitoring and control characteristics for timing/delays, thresholds, and polarities.
than improved its versatility. Over the last few years, advances in design techniques and semiconductor A serial communications bus is easy to implement so that users can set up the converter via a
technology have improved efficiency and power density, so the derating issue over the line and load manufacturer-supplied GUI as wished, or experiment with settings and, when optimized, request
variation has been alleviated. For example, the “totem-pole bridgeless PFC” stage with wide-bandgap the manufacturer to ship a product with those settings pre-installed. With an appropriate controller,
semiconductors is achieving better than 99% peak efficiency and about 97.5% even at the low line, functionality can even be dynamically changed in use in the application as required.
so line rectification and PFC is no longer a derating “bottleneck” and users can take full power from
a PSU using this technique for any line voltage worldwide. Modern isolated converter stages like the The serial interface is typically I2C with PMBus protocol but could also optionally be RS232 or RS485,
“phase-shift full bridge” are also capable of wide output operating ranges at high efficiency and precise CANopen, MODBUS, or SCPI buses for full flexibility. For users who need it, analog control inputs are
control of constant-current operation for a more versatile product (Figure 1). typically optional as well; for example, 0- to 5-V linear programming output voltage or current (Figure 2).
Figure 1: A typical modern, high-efficiency AC/DC outline with true digital control using a bridgeless PFC stage,
phase-shift full-bridge converter, synchronous output rectification, and wide-bandgap switches
Figure 2: A digital PSU will often still allow analog programming through an A-D interface.
The conversion topologies described have complex control requirements for best performance, and
this has been enabled by true digital control, where the drive to all switches is generated by software A CASE STUDY
algorithms, in what are now low-cost but high-performance controllers, such as the ARM Cortex An example of how digital control has provided a huge benefit is in an application in which a manufacturer
range. Now under software control, many parameters can be altered dynamically to suit application of electrochemical synthesis equipment found their existing PSU incompatible with worldwide supplies

Power Supplies DESIGN
due to derating required at low AC nominals. It was also limited in functionality and controllability,
requiring inconvenient and expensive external hardware and modifications to the PSU. A better solution
was the HPA1K5 from XP Power, a 1,500-W PSU based on a DSP platform that operates on single-phase
80–264 VAC, with near-zero impact on output rating, for operation in any market. The digital control
eliminated the external circuitry and PSU hardware modifications and added functionality including,
critically, safe shutdown if the system enables signal fails. When proven by the user, through the
supplied GUI, the settings were then factory-configured by XP Power before product shipment. The
customer was able to leverage extra value from the PSU’s I2C bus by interfacing to a credit-card–sized
single-board computer, which in turn provided a gateway to the user’s cloud network and enabled
monitoring of the end-product power-rail performance globally, from a European control center. The
user has a more competitive product with a component count, cost, and footprint reduced, with
enhanced reliability a welcome bonus.
Products like the HPA1K5 extend their applicability with worldwide ITE and medical (2 × MOPP) safety
approvals and high power density. Nominal outputs can be configured as constant voltage, programmable
0% to 105% of rated nominal, or as constant current 0% to 110% of the rated maximum. Features also
include remote sense, current share for parallel units,
a 5-V standby supply, and a temperature-controlled
SiC MOSFET Reliability

fan.
Similar products in the “HP” range with DSP

functionality from XP Power include the HPL5K0 range,
rated at 5 kW with three-phase 180- to 264-VAC input, Studies at Ohio State:
Short-Circuit Capability
intended for higher-output-voltage applications, with
optional nominals of 60 V, 100 V, or 200 VDC. Another
example is the HPT5K0, also rated at 5 kW but with
a three-phase 180- to 528-VAC input, again with high By Sonu Daryanani, contributing writer to Power Electronics News
nominal output-voltage options and two case-style
variants. Both the HPL and HPT ranges include all The superior performance of silicon carbide MOSFETs in high-power switching applications has led to
of the digital control and monitoring described and its widespread usage in some key growth areas, such as in the control of industrial motor drives. One of
fast output slew rates, useful for challenging test the key performance metrics for power semiconductor devices in this application is their short-circuit
applications (Figure 3). (SC) withstand capability. The harsh environment that motor drives operate in can result in overcurrent
levels from fault conditions like inverter shoot-through events and insulation breakdown in the motor
Figure 3: The HP range of products from XP and
their programming GUI
CONCLUSION windings. Hence, SC capability is one of the reliability tests that device manufacturers perform on their
The era of “software-defined power” is finally with us, parts. The test is unique because the device is subject to high voltage and high current for particular
with AC/DC products available in which output voltage, current, and all functionality can be controlled stress intervals with the gate pulsed on.
and optimized simply by the user, then embedded in firmware for production, all without compromising
cost and efficiency. Products can operate globally with certifications for a wide range of end applications Professor Agarwal and his team at The Ohio State University have been at the forefront of conducting
and be upgraded or reprogrammed for new ones with a simple connection to a laptop using software reliability studies on various aspects of SiC devices.1–5 In this article, we will review some of the findings
and a GUI available from the manufacturer, putting the user now firmly in control. from their work and highlight some improvements in SC capability by various groups.

Design Design
The short-circuit withstand time (SCWT) is a key metric used to gauge the device’s ability to withstand The short Lch can create
SC. Silicon IGBTs traditionally used in such applications have superior SCWTs, as shown in Table 1. high output conductance
and saturation current (Idsat)
because of drain-induced
barrier lowering at high Vds,
resulting in higher power
dissipation and lower SCWT.
Table 1: SCWT specs comparing Si IGBT and SiC MOSFETs, all at a 1,200-V rating Figure 3 shows an event flow
within the device from an SC
The response to an SC event in a SiC MOSFET is shown in Figure 1. These are from simulations for a event. It’s clear that lowering the
1.2-kV SiC MOSFET and show the high currents and temperatures as a result of the SC event.
1
device Idsat and the consequent
Figure 2: SiC planar MOSFET cross-sections showing areas of weakness5
temperature increase would be
FACTORS LIMITING key to improving its robustness
SiC MOSFET SCWT to withstand such an event.
Figure 2 shows a cross-section
of a SiC planar VDMOS device. METHODS TO IMPROVE SC ROBUSTNESS
As shown, three weak points
have been identified in this Channel length (Lch), JFET width (WJFET), gate-oxide thickness (Tox),
device.
5
drift-layer thickness
Increasing Lch, decreasing WJFET, and increasing Tox can lower the device Idsat. A simulation of the
The top metal of the device is response to Lch and WJFET variations1,6 is shown in Figure 4. WJFET variation has remarkable influence
typically aluminum, which has on SC current. A thicker Tox would also make the gate more robust against source-to-gate leakage
a melting point of 660˚C. The current (Igss). A thicker drift region could help device thermal capacitance and reduce the possibility of
high power densities during reach-through at high Vds bias. All of these changes would unfortunately also increase the device’s RDS(on).
Figure 1: A simulated SC event — a SiC MOSFET showing current and die
temperature an SC event can result in
temperatures exceeding this. Vds, Vgs voltage de-rating, drive conditions
The aluminum can melt and diffuse through grain boundaries in the passivation layer underneath, A higher Vds or higher Vgs
potentially creating catastrophic device damage. reduces the device SCWT,5
as shown in Figures 5(a)
Because the inversion channel mobility in SiC is much lower than that of Si due to interface state traps, and 5(b), respectively. These
the gate-oxide thickness used in SiC (typically 40–50 nm) is much lower than the 100 nm typically used plots are obtained from SC
in Si for similar gate-source voltage (Vgs) ratings. As a result, the electric field across the oxide can be measurements taken on
much higher under maximum drain-source voltage (Vds) conditions and can create tunneling across 1,200-V SiC MOSFETs from
the gate oxide, which in turn can lead to trapped charge in the oxide and shift the device threshold different device manufacturers
voltage (Vth). Higher on-state device resistance (RDS(on)) as a result can also lead to a positive feedback (shown as D, E, and F in Figure
of increased device temperature. This will increase the SC current. 5(b)). The response versus
Figure 3: SC event flow
Vds, done at a Vgs of 20 V, also
The channel length (Lch) in SiC MOSFETs is typically in the 0.5-µm or lower range, much less than the shows the tailing down of the
1 µm or so typically used in power Si MOSFETs. This is also to compensate for the lower channel mobility. Vgs waveform with time at the higher Vds, indicating Igss leakage. Figure 5(b) is collected at a Vds of

Design Design
800 V and shows data from a 1,200-V Si IGBT device as a comparison. The disadvantage of this but with a P+ shield included. Comparing the data between Figures 4 and 6, the shield lowers the
de-rating is increased RDS(on) or die area. Idsat of the device and increases SCWT. The advantage of this method is that the RDS(on) should not
be affected.
Well engineering
Using a much deeper P-well
serves as a quasi-field plate,
lowering the electric field
at the gate-oxide interface
in the JFET region, and also
suppresses channel leakage
at high Vds. A novel method
to achieve this using a
channeling implant at a tilt of
4˚ has yielded very promising
Figure 6: SC current density vs. Lch with P+ shield

results,9 not just in improving
Figure 4: SC event current density and temperature vs. (a) Lch and (b) 1/2 WJFET from TCAD simulations 6
the static characteristics

like the breakdown voltage
An interesting study found improved SCWTs of 10% to 20% when a negative Vgs turn-off was used
7
and channel leakage at high Vds, even with a small Lch, but also in the SCWT. Figure 7 illustrates
on the device compared with 0 V, with the thinking that the added inductance from the negative the concept of the much deeper P-well and Figure 8 shows the SCWT improvement achieved.
gate driver was helping to reduce the peak SC current. A significant advantage is that very little tradeoff in the RDS(on) is shown, with a dramatic ~4× SCWT
improvement to 8 µs.
Trench MOSFET
In the trench SiC MOSFET,
the gate is less likely to be
exposed to the maximum
electric field. Therefore, the
SCWT is better than that
achieved in planar MOSFETs.
Studies7 have shown SC
withstand energies (∫Vds × Ids
over the time period of the SC
event) of about 50% greater
Figure 5: (a) SCWT vs. Vds; (b) SCWT vs. Vgs
for trench FETs with similar
ratings to a planar device. In Figure 7: Showing the conventional well and the new channeled well profiles9
Use of a P shield region under the P-well
+
addition, improvements in the
The use of an implanted P region under the P-well shown in Figure 1 will serve to limit the drain
+
fundamental trench structure
voltage reach-through under high Vds bias, effectively shielding the JFET region of the device and can yield improved RDS(on) while also lowering Idsat and improving SCWT. An example of this is ROHM’s
lowering Idsat. 6,8
Figure 6 shows the simulation versus Lch, similar to the simulations used in Figure 4 newly announced fourth-generation SiC double-trench MOSFETs.10

Design Design
Embedded source
resistor
Short-circuit currents can
be suppressed by replacing a
part of the channel resistance
with an additional embedded
source resistance (Rs), as
shown in Figure 9. It has been
11
demonstrated that MOSFETs

with the Rs region can have
not only high resistance in
short-circuit but also low
Figure 8: Showing SC response with channeled deeper well at Vds 800 V, Vgs Figure 10: Measured SCWTs for commercial SiC MOSFETs from different vendors
20 V on a 1,200-V SiC MOSFET9 resistance at a practical
temperature range. Using a
metal with a strong positive temperature coefficient between the source junction and the top
aluminum metal can also help limit the rise of Idsat with temperature.
References
Several other circuit-based

methods to improve SCWT have
been demonstrated that will not ▶ 1Maddi et al. (2021). “The Road to a Robust and Affordable SiC Power MOSFET
be discussed here. Also, the gate Technology.” Energies 2021.
drivers must work hand in hand
with the MOSFETs to ensure ▶ 2
Liu et al. (2020). “Gate oxide reliability studies of commercial 1.2 kV 4H-SiC
that the drive is shut off within power MOSFETs.” IEEE International Reliability Physics Symposium (IRPS).
the specification limits of the
▶ 3
Xing et al. (2019). “Current saturation characteristics and single-pulse
MOSFET. Hence, fast-detection
gate drivers will be a key part of short-circuit tests of commercial SiC MOSFETs.” IEEE Energy Conversion
this development effort. Congress and Exposition (ECCE).
▶ 4
Xing et al. (2020). “3.3-kV SiC MOSFET performance and short-circuit
Variation of SCWT for a
given vendor capability.” IEEE Workshop on Wide Bandgap Power Devices and Applications
The SCWTs for commercial SiC in Asia (WiPDA-Asia).
MOSFETs from different vendors
▶ 5
Xing et. al. (2022). “1200-V SiC MOSFET Short-Circuit Ruggedness Evaluation
have been tested by Professor
Agarwal’s group at The Ohio Figure 9: Schematic cross-section of SiC MOSFETs with the Rs region11 and Methods to Improve Withstand Time.” IEEE Journal of Emerging and
State University. For each vendor, Selected Topics in Power Electronics.
multiple devices were tested. The
SCWT variation for each vendor is plotted in Figure 10. Significant SCWT variation is observed for a
▶ 6
Suvendu et al. (2022). “Non-isothermal simulation of SiC DMOSFET short
given vendor. Most likely, these variations in SCWT are due to process related variations in channel circuit capability.” Japanese Journal of Applied Physics.
length and JFET width.

Design AUTOMOTIVE
▶ 7
Bashar et al. (2021). “Comparison of Short Circuit Failure Modes in SiC Planar
MOSFETs, SiC Trench MOSFETs and SiC Cascode JFETs.” IEEE 8th Workshop
on Wide Bandgap Power Devices and Applications (WiPDA).
▶ 8
Nguyen et al. (2015). “Gate oxide reliability issues of SiC MOSFETs under
short-circuit operation.” IEEE Transactions on Power Electronics.
▶ 9
Kim et al. (2021). “Improved Short-Circuit Ruggedness for 1.2kV 4H-SiC
MOSFET Using a Deep P-Well Implemented by Channeling Implantation.” IEEE
Electron Device Letters.
▶ 10
Some details on Rohm’s fourth-generation trench SiC MOSFETs can be
found at www.rohm.com/products/sic-power-devices/sic-mosfet.
How Toyota Is
▶ 11
Hatta et al. (2017). “Suppression of Short-Circuit with Embedded Source
Diversifying Its
Strategies for Next-Gen
Resistance in SiC-MOSFET.” International Conference on Silicon Carbide and
Related Materials.
Vehicles
By Maurizio Di Paolo Emilio, editor-in-chief of Power Electronics News
The automotive industry is going through a significant change. Automakers must change to prepare
for tomorrow’s vehicles — including electric vehicles, hydrogen-fueled vehicles, and autonomous
vehicles — to comply with increased CO2 emission rules, and to offer safer AVs.
As one of the first companies to commercialize an EV, Toyota now produces a remarkable variety of
vehicles, such as fuel-cell EVs (FCEVs), battery EVs (BEVs), and hybrid vehicles. A comprehensive IP
strategy that covers most of the technologies involved in next-generation vehicles is a significant
supporter of such a reorientation. Figure 1 provides a summary of Toyota’s patent strategies for the
next generation of automobiles.
HYDROGEN-BASED FCEVs
With more than 12,000 patented inventions issued in over 20 years of work, the Toyota Group has
created the largest fuel-cell patent portfolio in the world. In the 2000s, the corporation made significant
investments in technology linked to FCEVs, considering their advantages over other types of vehicles in
terms of impact on the environment, autonomy, speed, and ease of recharging.

Automotive Automotive
To develop FCEV technology, market, Toyota exhibits a great readiness to participate in the enhancement of battery characteristics
Toyota Motor, which accounts (energy and power density, charging speed, life duration, etc.). To accomplish these goals, Toyota has
for about 75% of these patent decided to focus on two primary leads: improving Li-ion batteries, the technology already present in
filings, can rely on all of its EVs, and creating new battery technologies with superior properties.
affiliates and subsidiaries.
To speed up the inventive On one side, the company is developing new and existing materials for Li-ion batteries. These materials
advances over the years, Toyota include solid electrolytes, NMC/NCA, lithium metal, lithium titanate (LTO/Li4Ti5O12), and silicon.
nevertheless strengthens Considering its strong IP position throughout the whole supply chain, Toyota is presently the most
its expertise in particular significant patent assignee for solid-state batteries.
disciplines and establishes an
industrial model by establishing Toyota, on the other side, is looking at new battery technologies that theoretically perform better than
external alliances, typically with Li-ion batteries. The business works on both established post-Li-ion technologies, including Li-air, Li-S,
regional Japanese businesses, and Na-ion batteries, as well as more cutting-edge ones like Mg-, F-, Al-, Ca-, K-, and Zn-ion batteries.
Figure 1: The Toyota patent strategy for next-generation vehicles (Source:
KnowMade) universities, and research
institutions. To promote FCEVs SiC POWER DEVICES FOR EVs
and aid the sector’s growth, the Japanese carmaker granted royalty-free use of its then 5,000+ FCEV- Denso is a leading company in the development of the silicon carbide MOSFET since 2018. By
related patent licenses in 2015. transferring its essential patents to Denso, Toyota Motor anticipated the integration of SiC MOSFETs in
next-generation EVs. The entire supply chain, from SiC materials to SiC power devices, modules, and
The company doesn’t concentrate on a single fuel-cell technology. To maintain the flexibility to use circuits, is covered by Toyota and Denso’s patent activity (Figure 2). Toyota’s IP activity focuses on ideas
any type of fuel cell, most of its patents cover generic fuel-cell technologies. Initially, the company that give the corporation a competitive edge in EV applications as it moves down the SiC supply chain.
created electrocatalysts, membrane electrode assemblies, and stacking configurations for fuel-cell
components. Toyota has been expanding its research and development efforts along the entire FCEV Up the supply chain, Toyota’s patent portfolio covers a wide range of technologies, including both cutting-
supply chain and examining new areas since 2016. One of these is the regulation of running parameters edge SiC crystal growth technology (PVT) and unconventional techniques (CVD, solution growth). Toyota
during fuel-cell operation. has the capacity to overcome the majority of technological hurdles associated with SiC materials in
terms of cost, quality, or wafer size in the mid or long term, thanks to this extensive coverage of SiC
From hydrogen’s manufacture to the installation of infrastructure and its application in Toyota’s FCEV, substrate technology.
the Toyota Group has implemented a process of vertical innovation integration. The Toyota Group is also
working on the development of several cutting-edge hydrogen production technologies, including solid It’s interesting to note that Toyota Motor has been a leader in the development of the TLP bonding
oxide electrolysis cells, high-performance proton exchange membrane electrolyzers, and photocatalytic technique for die-attach technology since 2010. This process offers a promising substitute for traditional
water splitting. Additionally, it also engages in patenting hydrogen carriers for storage and transportation, soldering methods and silver or copper sintering methods for high-temperature operation.
such as metal-organic frameworks.
AUTONOMOUS VEHICLES
BATTERY INNOVATIONS The second revolution for which the automotive industry is preparing is related to AVs and robotaxis.
Toyota foresaw the transition to hybrid vehicles and BEVs decades before it became a commercial While the introduction of hybrid vehicles and BEVs has already solidified electrification, the introduction
focus. The company has created a wide range of battery-related technologies throughout the years, of robotaxis and fully autonomous vehicles is taking a little longer.
which are one of the major factors affecting EV performance (autonomy, speed, and safety). Toyota has
collaborated extensively on batteries, both in Japan and abroad, as part of its research plan. As a result, The Toyota Group’s IP activity in the areas of advanced driver-assistance systems and AV technologies
the company secured its IP position in major production and commercialization locations for batteries is one of the most active in the organization. Such a rise in R&D activity is required to compete not only
and EVs, and its battery inventions now cover the whole supply chain for both present and future with established automakers but with upstart robotaxi manufacturers.
potential technologies (Japan, Korea, China, Europe, and the U.S.). To satisfy the demands of the EV

Automotive SEMICONDUCTORS
Figure 2: Time evolution of Toyota Group’s patent publications related to SiC. Patents published up to August 2021.
Power GaN for Better
Power-Conversion
(Source: KnowMade)
Efficiency
Being that cameras, radar, and LiDAR are regarded as the three primary technologies that must be
coupled to create 3D mapping of the vehicle environment, Toyota Group’s early patenting work in
these areas has benefited the company’s modern technological advancements. However, the Japanese
company has decided to scale back its LiDAR R&D efforts in favor of systems that integrate and manage By Dilder Chowdhury, director of strategic marketing for power GaN
numerous sensors, particularly cameras, in a vehicle. technology at Nexperia
CONCLUSION Power gallium nitride FETs are increasingly making their way into mainstream markets by providing
Toyota’s effort in filing patents reflects its desire to play a significant role in the creation of cars of the best power efficiency and most compact solution size. Brave innovators already benefit from
the future. Toyota has submitted a considerable number of patent applications to cover everything having disruptive GaN high-electron–mobility transistor (HEMT) technology as a key component
from materials to systems, including devices, control circuits, and packaging, in all key disciplines for their applications, as it offers the fastest transition/switching capability (highest dV/dt and
(such as batteries, fuel cells, sensors, and power electronics). Furthermore, Toyota has broadened its di/dt) and delivers the best efficiency, regardless of whether it is for low- or high-power–conversion
technological scope to establish itself as a leader in critical technologies of the past, present, and applications. Additionally, Nexperia power GaN FETs bring enhanced power density through improved
future. efficiency as a result of reduced conduction and switching losses combined with low-inductance
copper-clip packaging (CCPAK).
References GaN FETs display the best performance in all power-conversion applications: server, computing,
industrial automation, telecom infrastructure, and automotive. In the volume/cost/performance
spectrum, power GaN FETs using standard silicon-based manufacturing infrastructure that is easily
▶ 1KnowMade. (Sept. 27, 2022). “Insights on Toyota’s patent strategy for
scalable to larger-diameter wafers (200 mm) are at the forefront. And power GaN FET products are
next-generation vehicles.” Press release. being manufactured aggressively to address the volume and cost demands to support mainstream
challenges.

This paper describes the power-conversion efficiency improvement using power GaN FETs, looking at POWER GaN FET FOR EFFICIENCY
the performance benefits of GaN FETs over other incumbent technologies, including Si technology. High-voltage power semiconductor switches are the fundamental building blocks of any power
While the biggest driver for innovation is efficient power conversion, reduction in power losses is a conversion. To date, Si-based superjunction (SJ) and IGBTs have been the main contributors.
key challenge that the industry faces. Societal pressures, such as the EU Ecodesign Directive and However, the significant maturity of Si SJ and Si IGBTs limits further developments and only very
government legislation for reduced harmful greenhouse gas (CO2) emissions as well as trends toward small incremental improvements are possible. For example, Si IGBTs are fundamentally limited
more efficient power conversion and electrification, are key. GaN FETs enable the best efficiency with in frequency of operations, speed, sluggish high-temperature performance, and poor low-current
lower system cost while making systems lighter, smaller, and cooler. Electrification in the automotive characteristics. Si SJ technology is used in power conversion at higher frequencies like AC/DC
sector can be the biggest beneficiary of this new power GaN FET technology. conventional power-factor–correction (PFC) and DC/DC power-conversion stages. But as the
voltage goes up, reverse-recovery losses go up significantly for Si-based devices. To achieve higher
AUTOMOTIVE ELECTRIFICATION LEADS THE DRIVE ON EFFICIENCY efficiency, these devices are limited to size and cost due to their inherent material limitation for
The world is changing fast. Technology is making that change possible and helping accelerate the high-frequency operation. These limitations can be summarized by switching crossover losses,
trend. There are many challenges, such as harmful emissions, power losses, heat dissipation, cooling conduction losses, and reverse-recovery losses.
systems, system size and weight, power densities, and high-temperature performance. The industry
is working across multiple facets to address these challenges. Within automotive, there are numerous
application areas where significant improvement is expected to address these issues:
▶ Improved, more efficient power conversion

→ AC/DC on-board charging
→ DC/DC power conversion
→ Auxiliary power
→ Booster power conversion
Table 1: Material properties
→ DC/AC inverter to drive the traction motors
▶ Improved traction motors On the other hand, even with limited maturity, GaN and silicon carbide wide-bandgap (WBG) devices
→ Improved efficiency can offer significant performance improvements (see Table 1). They are free from reverse-recovery
→ Better torque and power losses and can offer exceptionally low switching crossover losses (because of extremely fast
→ Lower losses turn-on and -off characteristics), as well as high-temperature operations and lower conduction
→ Higher dV/dt handling for improved power density losses. Together, higher critical electric fields in WBG materials and greater mobility deliver the
→ Simpler driver and control schemes lowest drain-source on-resistance (RDS(on)) for higher voltages and a significantly faster switching
figure of merit.
▶ Improved batteries and storage systems
▶ Improved battery management systems As GaN FET devices enter the market, they show significant promise and remove the limitations
naturally imposed by Si IGBT and Si SJ devices. In hard-switched application topologies where Si
Efficient power conversion helps significantly in many ways. Nexperia Power GaN FETs offer higher SJ FETs cannot be used, due to the high diode reverse recovery, power GaN FETs can easily be
efficiency but also the scalability to support electric vehicle (xEV) growth ambitions and volumes. used and take full advantage of reduced component counts and higher efficiency with simpler
Si-based infrastructures and fabrication process steps allow the best cost roadmap for commercial control schemes. Faster switching speeds and higher operation frequencies enabled by Nexperia
viability. Currently, Nexperia technology delivers 650-V products for battery voltages up to 500 V and power GaN transistors enable better signal control and higher cutoff frequencies for passive filter
can serve up to 1,000-V battery systems with multilevel inverter topologies. Power range can be high designs and lower ripple currents. This allows for smaller inductors, capacitors, and transformers,
with a multilevel converter. with related cost savings. As a result, system solution size can be significantly reduced without
compromising the performance, instead improving performance.

Power GaN FETs come in two main flavors: E-mode or single-die normally off devices, and D-mode of E-mode devices and makes the whole usage very simple.
or two-die normally off devices. At the moment, stability and leakage current of the E-mode gates Low-voltage Si-based gate structure is a very mature
are of concern, but two-die normally off or cascode configuration gives peace of mind, as driving technology and engineers are well used to using them. Qrr
these FETs is simple and robust. Nexperia uses two-die normally off cascode configuration for for low-voltage Si is very low as shown in Figure 3 below
high-power applications, helping avoid the challenges of gate bounce or unwanted turn-on and and enables the full potential of the power GaN technology.
shoot-through. For operations up to 1-MHz switching-frequency cascode, GaN FETs are best suited, E-mode device channel mobility is much lower compared
although current high-voltage power-conversion frequencies are only about 300 kHz and traction with the normally on GaN HEMT channel that naturally
inverter frequencies are still below 40 kHz. exists. Driving a cascode device is also very simple. Cascode
device operation is shown below in Figure 4 for different
The GaN-on-Si two-die normally off configuration allows significant design flexibility. Nexperia GaN bias situations. Power GaN FETs can be used in bidirectional
FET technology offers ±20-V gate rating with oxide/insulator gate, 4-V gate threshold voltage with form.
0-V turn-off and low gate charge, hence simple Si drivers are suitable for using with these devices.
Figure 2: Cascode schematic
Any 0-8, 10, 12 V gate drive can be used. SiC technology generally requires at least 15 V, very high
current driver with negative gate drive capability to turn off the device adding cost for the driver
and increased driver loss and switching losses. Nexperia GaN also has a very good antiparallel diode Since the introduction
built in helping robust freewheeling conduction path. Cascode offers significant freedom to make of power GaN
the gate structure have the same robustness automotive customers are used to. This is valid for transistors in the
both Si FET and the GaN HEMT with insulated gates. market, a significant
improvement has taken
place on performance,
reliability, cost, and
availability. More
capable GaN power
transistors are Figure 3: Qrr, reverse-recovery charges for GaN and Si
becoming available to
drive higher and higher power to meet xEV requirements while also being well positioned for data
centers, telecom infrastructures, and industrial applications.
Power GaN FETS offer significant switching advantages for both hard and soft switching
Figure 1: Cross-section of the GaN HEMTs (left: D-mode for cascode; right: E-mode) applications.
GaN HEMT works with the formation of two-dimensional electron gas (2DEG) due to the spontaneous
polarization and piezoelectric polarization combined at the interface of GaN and AlxGa1-xN. Epi is
formed on the Si substrate via a seed layer and a graded layer of GaN and AlGaN layers, before the
pure GaN layer is grown and a thin layer of AlGaN then forms the 2DEG. Electron mobility in this
layer is remarkably high hence the name.
Combining a low voltage (30 V) robust Si MOSFET as shown in the schematic (Figure 2) shows
how the cascode configuration can eliminate all the major concerns of the poor gate structures
Figure 4: Cascode device operation

Figure 5 shows excellent hard switching performance with lowest turn off losses as measured using temperatures, GaN FETs offer the highest electron mobility and highest saturation velocity resulting
double pulse tests. in the lowest switching losses. Additionally the carrier transition between on and off state is fastest
when comapred to the Si SJ and SiC. Si IGBT is even slower due to the slow hole carrier transition
which makes it sluggish in high temperature response.
APPLICATIONS AND
PERFORMANCE
Whether it is an AC/DC PFC stage,
DC/DC converter (Fig. 7) or traction inverter
(Fig. 8), the basic building block for most
topologies is a half bridge (Fig. 9). Hence
when GaN FETs are compared with Si
FETs in a simple boost converter, the GaN
FET shows its superior performance due
to the differences in material properties.
Figure 7: AC/DC PFC stage and isolated DC/DC configuration
All these applications can take advantage
of the benefits and hence reduce losses.
Figure 5: Hard-switching double-pulse test in CCPAK GaN FETs When it comes to Si IGBTs, their non-linear operation means light load (low current) losses as well
as high-temperature and higher frequency losses are significantly higher in comparison with the
linear operation of power GaN FETs.
Figure 6 shows lowest Esw even when compared with other higher RDS(on) competitor devices in Si
SJ FETs, SiC FETs and E-mode GaN FETs. No unexpected increase due to dynamic RDS(on) or Coss GaN FET losses are significantly lower due to absence of reverse recovery losses and switching cross
hysteresis makes an excellent choice for soft switching applications. over losses. It is possible to achieve near ideal turn on and off losses with a dV/dt around 200 V/ns.
GaN switches are extremely fast and routinely used in the RF amplifiers at GHz frequencies, though
Implied summary of the reduced losses (conduction, switching, and reverse recovery) together at much lower voltages, but this shows the capability as both use the GaN HEMT structure. As GaN
results in the lowest losses and highest efficiencies. As the applications typically work at high devices are very fast and can be used in applications with high dV/dt and high dI/dt, care must be taken
to optimize PCB layouts. Layout optimization (to minimize parasitic inductances) is fundamental to
power GaN usage. Surface
mount packages and low
inductance high current
high-performance modules
are essential to maximize
the performance, and are
being worked on.
Currently, using GaN devices

in a Traction Inverter
requires them to be slowed
down significantly to save
the motor windings as they
Figure 6: Soft-switching test results using calorimetric method with CCPAK GaN FETs Figure 8: Traction inverter

over stresses are used, like voltage

and temperature, and different
acceleration factors are defined for
end of life and FIT rate estimations
for differing application situations.
And as products are increasingly
used in real applications, this will
provide a better position to estimate
Figure 9: Half-bridge boost converter; VIN = 240 V, VOUT = 400 V, Fsw = 70 kHz (same converter with replacement switches)
field failure rates and PPMs.
are nearly limited to a dV/dt of 10 V/ns. That means there is enormous potential to improve the motors Figure 10: Efficiency of boost converters (1,000 hours)
and take the frequency up to 40 kHz to increase the power density significantly. Development of MARKET READINESS
new electric motor technology with better capability is on the way to make system more efficient. OF POWER GaN
TECHNOLOGY
TECHNOLOGY ROBUSTNESS: QUALITY AND RELIABILITY Power GaN technology is ready to take its place in the market for efficient power conversion. Already
Good levels of quality and reliability are important for any technology adoption. Power GaN FET it is being adopted in non-automotive application segments and is being evaluated and designed
technology currently shows decent quality and reliability even at this early stage of technology into automotive applications, which can take advantage of lower losses and higher power densities.
maturity, with multiple vendors demonstrating JEDEC and AECQ101 quality standards. Beyond While Si technology is well established in the market, it is reaching its limits. As the benefits
these standards there are many GaN specific tests and measurements that need to be carried out. become clear and the volume of installed devices grows, power GaN technology will become the
And even within the normal JEDEC and AECQ101, Nexperia aims to achieve 2x, 3x and even 4x times norm for high-efficiency power-conversion platforms.
the AECQ101 requirements.
Dynamic RDS(on) or current collapse phenomena is well known for power GaN FETs and methods References and further reading:
for testing have been introduced, and devices verified. Material quality, trapping and appropriate
de-trapping responsible for the dynamic RDS(on) can be measured and provide a high level confidence
level for its usage as the values are improving and now around 10%. But we continuously need to ▶ 1AN9005 – Understanding Power GaN FET data sheet parameters
look at the different failure modes and drive devices to failure to understand the physics of failure.
▶ 2
AN9006 – Circuit design and PCB layout recommendations for GaN FET half
Beyond AEC Q101 qualifications, for validating the GaN FETs’ reliability in actual operating condition,
bridges
a number of identical half-bridge circuits (with continuous current conduction mode) were prepared
using one high- and one low-side GaN device. These were operated continuously for 1000 hours as
▶ 3
T. Kikkawa et al., “600 V JEDEC-qualified highly reliable GaN HEMTs on Si
synchronous-boost converters with the following conditions: Vin = 200 V, Vout = 480 V, Pout = 800
W, Tj = 175 °C, Freq = 300 KHz substrates.” 2014 IEEE International Electron Devices Meeting, San Francisco,
CA, 2014, pp. 2.6.1-2.6.4.
The adjacent graph, Figure 10, shows efficiency of all samples for a 1000 hour duration test. There is
no indication of any degradation in the performance of any circuits. Following the high temperature ▶ 4
S. Chowdhury, et al., “650 V Highly Reliable GaN HEMTs on Si substrates
switching tests, all devices were tested for dynamic RDS(on) shifts, leakage current, and threshold
over multiple generations: matching Silicon CMOS manufacturing metrics and
voltage. All parameters were found to be stable, with parametric shifts below allowed levels.
process control.” Compound Semiconductor Integrated Circuit Symposium
Devices were also tested for high temperature transient spikes and over voltages to eliminate (CSICS), IEEE, 2016.
any risk of high voltage transient that is an integral part of the device specification. Many other

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Batteries
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Editorial Contact Although we make every effort to Power saving methods for LTE-M and NB-IoT
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DEC

TAKING THE NOISE

Noise free e-mobility Highlights Yours Sincerely,

DECEMBER 2022 | www.powerelectronicsnews.com 3

COVER STORY — DESIGN

Approaching the Perfect Switch with

A Novel Efficient Step-Down Converter

Gallium Oxide: A Next-Gen

eGaN FETs Enable More Than 4-kW/in.3

4 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 5

MICROMODULE WITH HIGH EFFICIENCY

Free Power Supply with

6 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 7

8 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 9

INPUT PROTECTION CIRCUIT OUTPUT FILTER

10 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 11

▶ 1RedExpert Filter Designer

Timur Uludag, Würth Elektronik

12 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 13

14 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 15

Figure 2: Fast DC charger configuration options

Figure 1: Path of the leakage current in an EV charging system

16 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 17

The corresponding topology is shown in Figure 4.

Figure 6: Topology of the non-isolated three-phase charger

18 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 19

Figure 8: Tested DC/DC stage efficiency

20 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 21

THE NOVEL INDUCTOR DESIGN

A Novel Inductor Design

DC/DC Converters The static magnetization curve of NPA-F,

22 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 23

Two commercial shielded power inductors

The measured inductance versus frequency,

24 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 25

The cascode configuration

Perfect Switch with

Another characteristic of the cascode

26 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 27

THE THIRD-QUADRANT TRADEOFF

THERE ARE MORE GAINS TO BE HAD

28 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 29

30 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 31

THE PROPOSED ARCHITECTURE

32 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 33

The measurement of IC CONCLUSION

▶ 1Amerasekera, A. (2010). “Ultra low power electronics in the next decade.”

34 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 35

Gallium Oxide: A is also relatively

Semiconductor for aluminum, and nickel at

Wafering and lapping of

36 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 37

(Figure 2). interest is driving the impressive

Figure 2: A typical semiconductor wafer (Source: Tip3X)

38 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 39

eGaN FETs Enable More

40 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 41

ML91S,9 the same soft-ferrite

42 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 43

▶ 1de Rooij, M. and Negahdari, A. (2022). “Beyond 4 kW/in3 Power-Density for

44 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 45

46 DECEMBER 2022 | www.powerelectronicsnews.com DECEMBER 2022 | www.powerelectronicsnews.com 47