CSD Lab Manual v1

Computer System Design Laboratory Manual 3rd SEM CSE
BMS INSTITUTE OF TECHNOLOGY AND MANAGEMENT

(Autonomous Institute Affiliated to VTU)
COMPUTER SCIENCE AND ENGINEERING
Avalahalli , Yelahanka , Bengaluru – 560064
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
LAB MANUAL OF
Computer System Design Laboratory
[21CSL38B]
[As per Choice Based Credit System (CBCS) scheme]
(Effective from the academic year 2022 -2023)

SEMESTER – III
VISION AND MISSION OF THE CS&E DEPARTMENT
Vision :To develop technical professionals acquainted with recent trends and
technologies of computer science to serve as valuable resource for the nation/society.
Mission: Facilitating and exposing the students to various learning opportunities

through dedicated academic teaching, guidance and monitoring.
VISION AND MISSION OF THE INSTITUTE
Vision :To emerge as one of the finest technical institutions of higher learning, to
develop engineering professionals who are technically competent, ethical and
environment friendly for betterment of the society.
Mission:Accomplish stimulating learning environment through high quality

academic instruction, innovation and industry-institute interface
B M S Institute of Technology & Management Page 1 of 40

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
Choice Based Credit System (CBCS)

SEMESTER
Computer System Design – III
Laboratory (0:0:2) 1
(Effective from the academic year 2021 -2022)
Course Code 21CSL38B CIE Marks 50
Teaching Hours/Week (L:T:P) 0:0:2 SEE Marks 50
Total Number of Contact Hours 26 Exam Hours 3
Course objectives:
This course will enable students to:
1. Understand the Basics of digital electronics and able to design basic logic circuits
2. Familiarize the concepts of Combinational circuits.
3. Design experiments using the concepts of flip-flops, registers and counters
To design the hardware using verilog/VHDL based design practices and introduce students
to a disciplined use of industry-based practices for writing models to ensure that a
behavioral description can be synthesized into physical hardware, and that the behavior of
the synthesized circuit will match that of the behavioral description.
Lab Experiments
1. Introduction to VHDL.
2. Realize the truth tables of half adder, full adder half subtractor and full subtractor and
simulate the same using VHDL.
3. Given a 4-variable logic expression, simplify it using Entered Variable Map and realize
the simplified logic expression using 8:1 multiplexer IC and simulate the same using
VHDL.
4. Design and realization Two Bit Magnitude Comparator, binary to grey and grey to
binary using Basic Gates
5. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table and
6. Design and implement a mod-n (n<=8) synchronous up counter using J-K Flip-Flop ICs
and demonstrate its working. Simulate the same using VHDL.
7. Design and implement an asynchronous counter using decade counter IC to count up
from 0 to n (n<=9) and demonstrate on a 7-segment display (using IC- 7447).
8. Design an 8-bit ALU. - Design a ripple carry adder.
Course Outcomes: The students will be able to:
CO1: Understand the basics of sequential and combinational circuits.
CO2: Use appropriate realization methods to implement the digital circuits.
CO3: Examine and verify the design of digital circuits using simulators.

Question paper pattern:
CIE (50 marks)

●
SEE(50 marks)
●
Conduct of Practical Examination:
All laboratory experiments are to be included for practical examination.
Experiment distribution
For questions having only one part: Students are allowed to pick one experiment
from the lot and are given equal opportunity.
 For questions having part A: Students are allowed to pick one experiment from part
A.
 Change of experiment is allowed only once and marks allotted for procedure part to
be made zero
Marks Distribution :
For questions having only one part – Procedure + Execution + Viva-Voce: =50 Marks.

DIGITAL COMPONENTS (BASIC GATES)
NOT GATE:


1. Introduction to VHDL-
VHDL stands for very high-speed integrated circuit hardware description language.
Which is one of the programming languages used to model a digital system by
dataflow, behavioral and structural style of modeling?
VHDL: - V -VHSIC, H - Hardware, D - Description, L – Language Sequential language

like C, C++ can design any hardware but not able to synthesis that hardware or may
not able to simulated. Hence like HDL is there. VHDL is a case intensive language but
it is a strongly type.
Strongly type means the input and outputs of the design components ( entity)
should be of the same type i.e. they should be either bit type, real, integer, natural,
boolean, std_logic type etc.
Fundamental section of a basic VHDL code
Library :
Syntax : Library library name;
Eg. library ieee;
Library is the collection of compile VHDL design units i.e. entity, architecture,
configuration package and package. Use statement can access different component
inside the library
Syntax of use statement
Use library_name.package_name.item_name;
Eg. Use ieee.std_logic_1164.all;
Describing a design:
For learning VHDL , we will start with basic element of the language. Any vhdl code
is a combination of design units, objects, type & operators linked together in a
logical manner to produce the desired output.
In VHDL an entity is used to describe a hardware module. An entity can be described using,
1. Entity declaration.
2. Architecture.
3. Configuration
4. Package declaration.
5. Package body.
Entity declaration: It defines the names, input output signals and modes of a hardware
module. Syntax: entity entity name is Port declaration; end entity name; It describe the
interface of the design to its external environment. It can be use as a component in other
entity after being compile into a default library work
Ports are interface through which an entity can communicates with its environments.

Port declaration defines the name, type, direction and possible defaults value for the signal.
Each port has a type i.e. bit_type, std_logic type.  Each port has a direction i.e. IN, OUT,
INOUT,BUFFER
IN — Input: It indicates the input port whose values can read but cannot assign any values
i.e. c <= a ….. Read
a <= ‘1’ ….. Not assigned
OUT — Output : It indicates the output port to which value can only be assign but not read.
i.e. b <= ‘1’……. Assign, d <= ‘b’ ….x
INOUT – It indicate bidirectional port whose value can be read and also
assign BUFFER – It is an output port with read capability. It is not a bidirectional port i.e. port
can be read and write.
It has only one source.
For ex. For AND gate Library ieee;
Use ieee.std_logic_1164.all;
Entity and_2 is Port ( a,b : in std_logic; Z : out std_logic);
End and_2;
Architecture: Architecture body contains the internal description of the entity.
It describes the functioning and the structure of the circuit. Architecture always present with
an entity i.e. without entity architecture is not possible.
Single entity can have multiple architecture. Architecture can be used to described a design
at different level of abstraction like gate level, RTL or behavioral level Architecture contains
only concurrent statement.
Process is only concurrent statement that contains sequential statement inside it.
Architecture can be describe using structural, data flow, behavioral or mixed style
Syntax: Architecture architecture_name of entity_name is
[ declaration ]
Begin
[ statements ]
End architecture_name;
There are 4 different modeling style use in architecture body
1. As a set of interconnection ports ( to represent the structure)
2. As a set of concurrent assignment statements ( to represents data flow)
3. As a set of sequential statements ( to represents behavioral )
4. as the combination of above three ( mixed style)
For ex. Library ieee; Use ieee.std_logic_1164.all;
Entity and_2 is
Port ( a,b : in std_logic; z : out std_logic);
End and_2;
Architecture Df of and_2 is
Begin
Z <= a and b;
End DF;
Configuration: If an entity contains many architectures and any one of the possible
architecture binding with its entity is done using configuration.
It is used to bind the architecture body to its entity and a component with an entity.  Syntax:
Configuration configuration_name of entity_name is
For architecture_name
End for;
End configuration_name;
For example Configuration DEC_CONFIG of DECODER 2x4 is
For DEC_DATA FLOW
End for;
End DEC_CONFIG;
Package:
Package is a collection of commonly used sub-program, data types, constant, function and
procedure
Syntax: Package package_name is
Declaration;
End package_name;
Package Body It contain the implementation details of either function or a sub-program.
Package body cannot be written without a package. It is used to store private declaration that
should not be visible.
Syntax: Package body package_name is Declaration Sub program body;
End package_name;
Different modeling style in VHDL: The internal working of an entity can be defined using
different modeling styles inside architecture body.
They are
1. Behavioral modeling
2. Data flow modeling
3. Structural modeling
2. Realize the truth tables of half adder, full adder half subtractor and full subtractor and
Hal Adder : Half Adder : Half Adder is a combinational logic circuit which is designed by
connecting one EX-OR gate and one AND gate. The half adder circuit has two inputs: A and
B, which add two input digits and generates a carry and a sum.

SUM = A’B + AB’ CARRY = AB
//behavioural model of half adder

entity HA_behavioural is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry_out : out STD_LOGIC);
end HA_behavioural;
architecture Behavioral of HA_behavioural is
begin
process(a,b)
begin
if a = '1' then
sum <=not b;
carry_out <= b;
else
sum <= b;
carry_out <='0';
end if;
end process;
end Behavioral;
Full adder:-
A full adder is a combinational circuit that forms the arithmetic sum of input it consists of
three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder
cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be
taken from OR Gate.
TRUTH TABLE:

Logical Expression for

SUM: = A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN
= C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN XOR (A XOR B) = (1,2,4,7)
Logical Expression for
C-OUT: = A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN
= A B + B C-IN + A C-IN = (3,5,6,7)
Another form in which C-OUT can be implemented:
= A B + A C-IN + B C-IN (A + A’)
= A B C-IN + A B + A C-IN + A’ B C-IN
= A B (1 +C-IN) + A C-IN + A’ B C-IN
= A B + A C-IN + A’ B C-IN
= A B + A C-IN (B + B’) + A’ B C-IN

= A B C-IN + A B + A B’ C-IN + A’ B C-IN

= A B (C-IN + 1) + A B’ C-IN + A’ B C-IN
= A B + A B’ C-IN + A’ B C-IN
= AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fullAdder is
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fullAdder;
architecture Behavioral of fullAdder is

begin
sum<=a xor b xor c;
carry<=(a and b)or(b and c)or(c and a);
end Behavioral;
Output:

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two
input and two outputs. The outputs are difference and borrow. The difference can be applied
using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.

library IEEE;
entity hsub is
b : in STD_LOGIC;
diff : out STD_LOGIC;
borr : out STD_LOGIC);
end hsub;
architecture Behavioral of hsub is

begin
diff<=a xor b;
borr<=(not a and b);
end Behavioral;
Output:
FULL SUBTRACTOR
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together

gives a full subtractor .The first half subtractor will be C and A B. The output will be
difference output of full subtractor. The expression AB assembles the borrow output of the
half subtractor and the second term is the inverted difference output of first X-OR.

library IEEE;
entity fullsub is
b : in STD_LOGIC;
c : in STD_LOGIC;
diff : out STD_LOGIC;
borr : out STD_LOGIC);
end fullsub;
architecture Behavioral of fullsub is

begin
diff<=a xor b xor c;
borr<=(not a and b)or(not a and c)or(b and c);
end Behavioral;
Output:

3. Given a 4-variable logic expression, simplify it using Entered Variable Map and
realize the simplified logic expression using 8:1 multiplexer IC and simulate the
same using VHDL.
E.g., Simplify the function using MEV technique
f(a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)
Decimal LSB f MEV map entry
0}0 0000 0 0------Do
1 0001 0
1}2 0010 1 1------D1
9 0011 1
2}4 0100 1 1-----D2
5 0101 1

3}6 0110 0 0-----D3
7 0111 0
4}8 1000 X X-----D4
9 1001 X
5}10 1010 X X-----D5
11 1011 X
6}12 1100 0 d----D6
13 1101 1
7}14 1110 0 d----D7
15 1111 1
Components Used: IC 74LS151, Patch Chords, Power chords, Trainer kit.
Pin Diagram of Ics Used:
Rules for entering values in a MEV Map:
Rule MEV Function Entry in Comments

No. MEV Map
1 0 0 0 If function equals 0 for both values of MEV, enter 0

1 0 in appropriate cell of MEV Map
2 0 1 1 If function equals 1 for both values of MEV, enter 1

in appropriate cell of MEV Map
1 1
3 0 0 MEV If function equals MEV for both values of MEV,

enter MEV in appropriate cell of MEV Map
1 1
4 0 1 MEV If function is complement of MEV, enter MEV in

appropriate cell of MEV Map
1 0
5 0 x x If function equals x for both values of MEV, enter x

in appropriate cell of MEV Map
1 x
6 0 x 0 If f = x for MEV = 0 and f = 0 for MEV = 1, enter 0 in

1 0
7 0 0 0 If f = 0 for MEV = 0 and f = x for MEV = 1, enter 0 in

1 x
8 0 x 1 If f = x for MEV = 0 and f = 1 for MEV = 1, enter 1 in

1 1
9 0 1 1 If f = 1 for MEV = 0 and f = x for MEV = 1, enter 1 in

1 x

VHDL code:
entity mx is
Port ( sel : in STD_LOGIC_VECTOR (2 downto 0);
a : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC);
end mx;
architecture Behavioral of mx is
begin
process(sel,a)
begin
case sel is
when "000"=>y<=a(0);
when "001"=>y<=a(1);
when "010"=>y<=a(2);
when "011"=>y<=a(3);
when "100"=>y<=a(4);
when "101"=>y<=a(5);
when "110"=>y<=a(6);
when "111"=>y<=a(7);
when others=>y<=a(7);
end case;
end process;
end Behavioral;
4. Design and realization Two Bit Magnitude Comparator, binary to grey and grey to
binary using Basic Gates
Two Bit Magnitude Comparator
A comparator used to compare two binary numbers each of two bits is called a 2-bit
Magnitude comparator. It consists of four inputs and three outputs to generate less
than, equal to, and greater than between two binary numbers.
The truth table for a 2-bit comparator is given below:

From the above truth table K-map for each output can be drawn as follows:

From the above K-maps logical expressions for each output can be expressed as follows:
A>B:A1B1’ + A0B1’B0’ + A1A0B0’

A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A<B:A1’B1 + A0’B1B0 + A1’A0’B0
By using these Boolean expressions, we can implement a logic circuit for this comparator
as given below:

VHDL CODE:
entity comparator_2bit is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : in STD_LOGIC_VECTOR(1 downto 0);
equal : out STD_LOGIC;
greater : out STD_LOGIC;
lower : out STD_LOGIC
);
end comparator_2bit;
architecture comparator_2bit_arc of comparator_2bit is

begin
equal <= '1' when (a=b) else ‘0’;
greater <= '1' when (a<b) else '0';
lower <= '1' when (a>b) else'0';
end comparator_2bit_arc;
BINARY TO GREY :
Steps: The example shows the steps involved in conversion of a binary code to its gray code
Binary code taken for the example is 1011.In the conversion process the most significant bit
(MSB) of the binary code is taken as the MSB of the Gray code. The bit positions G2, G1 and

G0 is obtained by adding (B3, B2),(B2, B1) and (B1, B0) respectively, ignoring the carry
generated. From the K-Map simplification
Binary to Gray Conversion:

Gray to Binary Conversion:
GRAY TO BINARY CODE CONVERSION STEPS:

The example shows the steps involved in conversion of a Gray code to binary code. Gray code
taken for the example is 1110. In the conversion process the most significant bit (MSB) of the
Gray code is taken as the MSB of the binary code. The bit positions B2, B1 and B0 is obtained
by adding (B3, G2), (B2, G1) and (B1, G0) respectively, ignoring the carry generated.
Truth-table:

PROCEDURE:
(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT:
2-bit magnitude comparator ,Binary to Gray and Gray to Binary converters are designed,
constructed using logic Gates and their truth table was verified.
5. Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table
and simulate the same using VHDL.
Components used: IC 74LS00, IC 74LS10, IC 74LS20, Power chords, Patch chords, Trainer
kit.

Pin Details of the ICs: 7400
IC-7410
Theory:
The circuit below shows the solution. To the RS flip-flop we have added two new connections
from the Q and Q' outputs back to the original input gates. Remember that a NAND gate may
have any number of inputs, so this causes no trouble. To show that we have done this, we
change the designations of the logic inputs and of the flip-flop itself. The inputs are now
designated J (instead of S) and K (instead of R). The entire circuit is known as a JK flip-flop.
In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q' outputs will
only change state on the falling edge of the CLK signal, and the J and K inputs will control
the future output state pretty much as before. However, there are some important
differences.
Since one of the two logic inputs is always disabled according to the output state of the
overall flip-flop, the master latch cannot change state back and forth while the CLK input
is at logic 1. Instead, the enabled input can change the state of the master latch once,
after which this latch will not change again. This was not true of the RS flip-flop.
If both the J and K inputs are held at logic 1 and the CLK signal continues to change, the
Q and Q' outputs will simply change state with each falling edge of the CLK signal. (The
master latch circuit will change state with each rising edge of CLK.) We can use this
characteristic to advantage in a number of ways. A flip-flop built specifically to operate
this way is typically designated as a T (for Toggle) flip-flop. The lone T input is in fact the
CLK input for other types of flip-flops.
The JK flip-flop must be edge triggered in this manner. Any level-triggered JK latch
circuit will oscillate rapidly if all three inputs are held at logic 1. This is not very useful.
For the same reason, the T flip-flop must also be edge triggered. For both types, this is
the only way to ensure that the flip-flop will change state only once on any given clock
pulse.
Because the behavior of the JK flip-flop is completely predictable under all conditions,
this is the preferred type of flip-flop for most logic circuit designs. The RS flip-flop is only
used in applications where it can be guaranteed that both R and S cannot be logic 1 at
the same time.
At the same time, there are some additional useful configurations of both latches and
flip-flops. In the next pages, we will look first at the major configurations and note their
properties. Then we will see how multiple flip-flops or latches can be combined to
perform useful functions and operations.
Master Slave Flip Flop:
The control inputs to a clocked flip flop will be making a transition at approximately the
same times as triggering edge of the clock input occurs. This can lead to unpredictable
triggering.
A JK master flip flop is positive edge triggered, where as slave is negative edge triggered.
Therefore master first responds to J and K inputs and then slave. If J=0 and K=1, master
resets on arrival of positive clock edge. High output of the master drives the K input of the
slave. For the trailing edge of the clock pulse the slave is forced to reset. If both the inputs are
high, it changes the state or toggles on the arrival of the positive clock edge and the slave
toggles on the negative clock edge. The slave does exactly what the master does.

Function Table:
Clk J K Q Q bar comment

0 0 Q0 Q0 bar No change
Reset
0 1 0 1
Set
1 0 1 0
toggle
1 1 Q0 Q0
VHDL CODE
entity master_slave_jk is
port(j,k,clk:in std_logic;q1,q1x,z1x:inout std_logic;
q2,q2x,z2x: inout std_logic);
end master_slave_jk;
architecture arc of master_slave_jk is
begin

process(clk)
begin
if clk='1' then
z1x<=(j and (not q2)) or ((not k)and q2);
q1<=z1x after 5 ns;
q1x<=not z1x after 5ns;
else
z2x<=(q1 and (not q2)) or ((not q1x)and q2);
q2<=z2x after 5 ns;
q2x<=not z2x after 5ns;
end if;
end process;
end arc;
RESULT:
JK Master/Slave circuit is designed, constructed using NAND gates and their truth table
was verified.
6. Design and implement a mod-n (n<=8) synchronous up counter using J-K Flip-Flop
ICs and demonstrate its working. Simulate the same using VHDL .
Components used: IC 74LS76, IC 74LS08, Patch chords, power chords, and Trainer kit.
Pin diagram of 7476

Theory:
The ripple counter requires a finite amount of time for each flip flop to change state. This
problem can be solved by using a synchronous parallel counter where every flip flop is
triggered in synchronism with the clock, and all the output which are scheduled to change do
so simultaneously.
The counter progresses counting upwards in a natural binary sequence from count 000 to
count 100 advancing count with every negative clock transition and get back to 000 after this
cycle.
Circuit Diagram:
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Transition Table:
Present State Nert State Jc Kc Jb Kb Ja Ka

Qc Qb Qa Qc+1 Qb+1 Qa+1
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 0 0 x 1 x x 1
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 1 0 0 1 x x 1 x 1
1 0 0 0 0 0 x 1 0 x 0 x
1 0 1 x x x x x x x x x
1 1 0 x x x x x x x x x
1 1 1 x x x x x x x x x

VHDL CODE:
library IEEE;
entity mod8 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (2 downto 0));
end mod8;
architecture Behavioral of mod8 is

begin
process(clk,reset)
begin
if(reset='1') then
q<="000";
elsif(clk'event and clk='1') then

q<=q+1;
end if;
end process;
end Behavioral;
Output:
RESULT:
A mod n (n<8) synchronous up counter using JK FF IC’s are designed, constructed and truth
table was verified.
7. Design and implement an asynchronous counter using decade counter IC to

count up from 0 to n (n<=9) and demonstrate on a 7-segment display (using IC-
7447).
Theory:
Asynchronous counter is a counter in which the clock signal is connected to the clock input of
only first stage flip flop. The clock input of the second stage flip flop is triggered by the output
of the first stage flip flop and so on. This introduces an inherent propagation delay time
through a flip flop. A transition of input clock pulse and a transition of the output of a flip flop
can never occur exactly at the same time. Therefore, the two flip flops are never
simultaneously triggered, which results in asynchronous counter operation.


Result: To verify truth table.

8. Design a ripple carry adder
Components:-
IC 7486,IC 7408,IC 7432
Digital IC Trainer Kit
Patch chords
Logic Circuit:
Result:-

CSD Lab Manual v1

Uploaded by

Copyright:

Available Formats

You might also like

CSD Lab Manual v1

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CSD Lab Manual v1

Uploaded by

Copyright:

Available Formats

Computer System Design Laboratory Manual 3rd SEM CSE

BMS INSTITUTE OF TECHNOLOGY AND MANAGEMENT

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer System Design Laboratory

[As per Choice Based Credit System (CBCS) scheme]

(Effective from the academic year 2022 -2023)

VISION AND MISSION OF THE CS&E DEPARTMENT

Mission: Facilitating and exposing the students to various learning opportunities

VISION AND MISSION OF THE INSTITUTE

Mission:Accomplish stimulating learning environment through high quality

B M S Institute of Technology & Management Page 1 of 40

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

Choice Based Credit System (CBCS)

This course will enable students to:

Course Outcomes: The students will be able to:

CO1: Understand the basics of sequential and combinational circuits.

CO2: Use appropriate realization methods to implement the digital circuits.

B M S Institute of Technology & Management Page 2 of 40

Question paper pattern:

CIE (50 marks)

All laboratory experiments are to be included for practical examination.

B M S Institute of Technology & Management Page 3 of 40

DIGITAL COMPONENTS (BASIC GATES)

B M S Institute of Technology & Management Page 5 of 40

B M S Institute of Technology & Management Page 6 of 40

VHDL: - V -VHSIC, H - Hardware, D - Description, L – Language Sequential language

B M S Institute of Technology & Management Page 8 of 40

B M S Institute of Technology & Management Page 10 of 40

SUM = A’B + AB’ CARRY = AB

//behavioural model of half adder

B M S Institute of Technology & Management Page 12 of 40

Logical Expression for

B M S Institute of Technology & Management Page 13 of 40

= A B C-IN + A B + A B’ C-IN + A’ B C-IN

architecture Behavioral of fullAdder is

B M S Institute of Technology & Management Page 14 of 40

B M S Institute of Technology & Management Page 15 of 40

architecture Behavioral of hsub is

B M S Institute of Technology & Management Page 16 of 40

B M S Institute of Technology & Management Page 17 of 40

architecture Behavioral of fullsub is

B M S Institute of Technology & Management Page 18 of 40

Decimal LSB f MEV map entry

0}0 0000 0 0------Do

1}2 0010 1 1------D1

2}4 0100 1 1-----D2

B M S Institute of Technology & Management Page 19 of 40

3}6 0110 0 0-----D3

4}8 1000 X X-----D4

5}10 1010 X X-----D5

6}12 1100 0 d----D6

7}14 1110 0 d----D7

Components Used: IC 74LS151, Patch Chords, Power chords, Trainer kit.

Pin Diagram of Ics Used:

Rules for entering values in a MEV Map:

Rule MEV Function Entry in Comments

1 0 0 0 If function equals 0 for both values of MEV, enter 0