MT7531 Reference Manual For Development Board

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MT7531 Reference Manual for
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Development Board
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© 2019 MediaTek Inc. a
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This document contains information that is proprietary to MediaTek Inc.
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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Document Revision History
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Revision
1.0
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Date
2019-09-05
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Initial Release
Description
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MediaTek Confidential © 2019 MediaTek Inc.
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Table of Contents
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Document Revision History ................................................................................................................... 2
f a P
C o n n a n
Table of Contents .................................................................................................................................. 3
e k B a
Memory Map................................................................................................................................. 6
T r
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1.1
F o
Top memory map ................................................................................................................ 6
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1.2 GPHY memory map ............................................................................................................ 6
2 Address Resolution Logic (ARL) ............................................................................................... 7
r
2.1 Introduction .......................................................................................................................... 7
2.2
f o
Features ............................................................................................................................... 7
2.3
a se
Frame Classifications ........................................................................................................ 10
l e
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2.3.1 Broadcast Frames ............................................................................................. 10
2.3.2
2.3.3
a R
Multicast Frames ............................................................................................... 10
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Unicast Frames ................................................................................................. 11
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2.4
n t
Switch L2/L3 Address Table .............................................................................................. 12
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2.4.1
n
2.4.2
f i d MAC Address Table .......................................................................................... 12
a P
Destination IP Address Table ............................................................................ 13
n
2.5
k C o
2.4.3
a n a
Source IP Address Table .................................................................................. 15
Virtual LAN......................................................................................................................... 16
i a T e o r
2.5.1
2.5.2B VLAN Table ....................................................................................................... 16
VLAN Security Mechanism ............................................................................... 17
Me d 2.6
F2.5.3
2.5.4
VLAN Membership Resolution .......................................................................... 17
Egress VLAN Tag Process ............................................................................... 18
Access Control Logic (ACL) .............................................................................................. 19
2.6.1 ACL Rule Table ................................................................................................. 19
2.6.2 ACL Rule Control Table .................................................................................... 20
o r
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2.7 Register Definition ............................................................................................................. 22
2.7.1
a s
ARL Register ..................................................................................................... 22
ele
2.7.2 ARL Port-Based Register .................................................................................. 66
l R
Scheduler (SCH) ...................................................................................................................... 176
i a
3.1
e n t
Introduction ...................................................................................................................... 176
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3.2
i d P
Features ........................................................................................................................... 176
n f n a
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3.3 Register Definition ........................................................................................................... 177
k C 3.3.1
a n a SCH Register .................................................................................................. 177
i a T e o r B
MediaTek Confidential © 2019 MediaTek Inc. Page 3 of 830
M e d F This document contains information that is proprietary to MediaTek Inc.

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Buffer Management Unit (BMU) ............................................................................................. 333
4.1
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Introduction ...................................................................................................................... 333
4.2
f i d e P i
Features ........................................................................................................................... 333
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4.3
o n a n
Register Definition ........................................................................................................... 334
C n
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4.3.1 BMU_FC Register ........................................................................................... 334
T e r B
Media Access Controller (MAC) ............................................................................................. 406
i a o
Me d5.1
5.2
F
Introduction ...................................................................................................................... 406
Features ........................................................................................................................... 406

5.2.1 MAC Layer function ......................................................................................... 406
5.2.2 Interface translation ......................................................................................... 406
5.2.3
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Inter-Frame Gap Shrink................................................................................... 406
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5.2.4 Flow Control .................................................................................................... 406
5.2.5 Energy Efficient Ethernet (EEE) ...................................................................... 407
5.2.6
5.2.7
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Priority Flow Control (PFC) ............................................................................. 407
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Loop detection ................................................................................................. 407
5.3
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i a
5.3.1
e n t
MAC Register .................................................................................................. 408
i
6
n f d
Management information base (MIB) .................................................................................... 505
i n a P
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6.1 Introduction ...................................................................................................................... 505
6.2
k C a n a
Features ........................................................................................................................... 505
i a T e6.2.1
o r B Overview of MIB Counters .............................................................................. 505
Me 7 d
6.3
F
Serial Gigabit Media Independent Interface (SGMII) ............................................................ 712
7.1 Introduction ...................................................................................................................... 712
7.2
r
Features ........................................................................................................................... 712
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7.3 SGMII AN/force mode setting guide ................................................................................ 712
7.3.1
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Auto-Negotiation mode.................................................................................... 712
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7.3.2 Force mode ..................................................................................................... 713
7.4
i a l R
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Switch System Control ........................................................................................................... 731
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8.1
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Introduction ...................................................................................................................... 731
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8.2 Features ........................................................................................................................... 731
8.3
k C a n a
Theory of Operations ....................................................................................................... 731
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M e d F This document contains information that is proprietary to MediaTek Inc.

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8.3.1
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EEPROM Programming Format ...................................................................... 731
8.4
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TOP ........................................................................................................................................... 756
f i a P
9.1
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Introduction ...................................................................................................................... 756
C n a
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10
a T e o r B
GPIO Controller (GPIO) ........................................................................................................... 760
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10.1 Introduction ...................................................................................................................... 760
10.2 Features ........................................................................................................................... 760
11
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GPHY ........................................................................................................................................ 805
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1 Memory Map
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1.1
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Top memory map
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The top level memory map is shown as table below. For more memory information, please refer the
o
section “Buffer Management Unit”.
Start Address
T
0x0000
e k r B a
End Address
0x0fff
Size
4096 ARL registers
Registers
d i a
0x1000
F o 0x10ff 256 Scheduler registers
Me
0x1100 0x1fff 3840 BMU registers
0x2000 0x20ff 256 Per-port ARL registers
0x3000 0x30ff 256 MAC registers
0x4000 0x47ff 2048 MIB registers
0x5000
0x6000
0x51ff
0x61ff
512
512
Port 5 SGMII registers
Port 6 SGMII registers
f o r
0x7000
0x7800
0x77ff
0x79ff
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2048
512
Switch system control registers
Top registers
se
0x7c00 0x7eff
l R e 768 I/O registers
1.2 GPHY memory map
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The GPHY related registers are listed in section “GPHY”.
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2
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Address Resolution Logic (ARL)
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2.1
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Introduction
C n a n
T k r B a
Address Resolution Logic (ARL) supports 2K address table shared by MAC address, destination IP address and
e
source IP address. When frame forwarding is performed on the address table, the MAC DA will be used to look
i a o
up the MAC entry to get the destination port map, priority, VLAN ID, etc. At the same time, the MAC SA should
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be learned into the address table. When the incoming frame carries the IP multicast frame, the destination IP
address will be used to look up the DIP entry. For IGMPv3 or MLDv2, SIP is also used to check the Source IP List.
ARL also supports up to 4K IEEE 802.1Q port-based VLAN and 8 priority queues for advanced network
management and QoS solutions. Using the VLAN feature, users can manage the broadcasted traffic efficiently.
Through the priority queue mechanisms, ARL switches different kinds of traffic (e.g., normal data, expedited data,
voice and video) according to the traffic characteristics and user’s requirements and provides end users with a
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multimedia environment.
e l e a
Although Ethernet switch or bridge is well-defined by IEEE Std.802.3, additional requirements are still needed
for it to fit in future standards or to improve security, QoS, or policy control. ARL provides Access Control Logic
entries rule control table.
i a R
(ACL) with the wire-speed control on the incoming frames. ACL Table includes 256 entries rule table and 128
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2.2 Features
n f i d n a P

-
k C o a n a
Built-in address table with 2K MAC addresses which can support up to 8 filtering databases
Accessible by managing interface to keep static addresses
-
i a T e r B
Support IVL/SVL based on FID from VLAN table
o
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- F
Programmable aging timer: no aging out, 10 ~ 1,000,000 seconds; default is 300 seconds
Configurable Address look-up algorithm. Address look-up based on the proprietary hashing
algorithm, CRC16 or CRC32.
- Support Collision Pool with 64 entries
 Up to 4K full VLAN entries with flexible support for IEEE 802.1Q and port-based VLAN
o r
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- Support port-based, Tag-based, and up to 4 port-and-protocol based VLAN
- Support per-port VLAN tag addition, removal, or leave unchanged
a s
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- Provide special tag for CPU port
-
-
i a R
Support Per Egress port stack VLAN (Q in Q)
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Support Per Egress port 1:1 and N:1 VLAN Translation

n t
Leaky VLAN based on port attribute, MAC address and ACL
e i

i d P
ACL Table includes 256 entries rule table and 128 entries rule control table
n f n a
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- ACL Rule support layer 1 to layer 4. Rules include Port No., DA/SA, Ether Type, VLAN ID, IP Protocol,
k C n a
SIP/DIP, TCP/UDP , SP/DP and user-defined content
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Actions support mirror, redirect, dropping, priority adjustment, and traffic rate policing
-
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Optional per-port Enable/Disable of ACL function
f i a P
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- Optional setting of per-port action when ACL is mismatched

C o
IGMP/MLD snooping
n a n
-
-
T k r B a
Support IPv4 IGMP v1/v2/v3 snooping and IPv6 MLD v1/v2 snooping
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Trap all IGMP and MLD packets to the CPU port. CPU writes the correct multicast entry to the
d i a F o
lookup table via management interface
Me
- Support hardware IGMP(v1/v2) join and fast leave
- Support partial hardware IGMPv3 and MLDv2 - IS_EX(), TO_EX(), TO_IN(). User-defined SIP Table for
IGMPv3/MLDv2, SIP Table hardware auto learning is not supported.
 Support Spanning Tree port behavior configuration
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- IEEE 802.1w Rapid Spanning Tree
a
- IEEE 802.1s Multiple Spanning Tree with up to 8 Spanning Tree instances

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Broadcast/Multicast/Unknown DA storm control/alert depending on the number of the frames received
R e
during a period of time to protect the system from being attacked by hackers

i a l
Per port MAC Address learning control to protect the system from being attacked by hackers
t
-
-
i d n
Disable learning or aging for Per-port
e P i
Limit SA Learning number for Per-port

o n f n a
Support IEEE 802.1x access control protocol and advanced security features
a
-
-
e k C B n
Access policy based on Port-based, MAC-based and guest VLAN
a
Access control based on ACL rules
d i
-
a T o r
Drop unknown Source MAC or Destination MAC address for Per-port
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 PPPoE/PPP identifier and header removal for IP multicast packets
 Support Link Aggregation (Port Trunking)
- Support maximum 3 aggregation group. Each aggregation group has 2 ports.
- Configurable port setting for each aggregation group.
o r
ef
- Configurable distribution scenario. Information used to assign conversations to aggregation ports is
s
configurable. Including Source Port, MAC DA, MAC SA, Source IP Address, Destination IP Address,
TCP/UDP Source Port and TCP/UDP Destination Port.
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2.3 Frame Classifications

n t i a
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2.3.1 Broadcast Frames
i d e a P i
C o n n a n Broadcast Frames
T e
FTAG
k r B a DA Type
IPv4/IPv6
Protocol
Description
d i a
BC
F o
FF-FF-FF-FF-FF-FF - - Broadcast Frames
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ARP FF-FF-FF-FF-FF-FF 08-06 - ARP Request Frames
- 08-06 - ARP Reply Frames
RARP FF-FF-FF-FF-FF-FF 80-35 - RARP Request Frames
- 80-35 - RARP Reply Frames
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2.3.2 Multicast Frames
e l e a Multicast Frames
IPv4/IPv6
R
FTAG DA Type Description
Protocol
MC
i a l
The 1st bit of MSB is 1’b1
t
- - Multicast Frames
n
IGMP - 08-00 0x02 IGMP Message
IP_MULT
MLD -
f i d e
01-00-5E-xx-xx-xx
a P i -
86-DD
-
0x00
IP Multicast (UDP)
Hop-by-Hop
C o n n a n
IPV6_MU 33-33-xx-xx-xx-xx -
0x3A
-
ICMPv6 (MLDv2)
IPv6 Multicast (UDP)
LT
T
BPDU
e k r B a
01-80-C2-00-00-00 - - Bridge Group Address (BPDU)
d i a F o
REV_01 01-80-C2-00-00-01 - - Clause 31 (MAC Control) of IEEE Std
Me
802.3
CONTRO - 88-08 - Discarded
L 01-80-C2-00-00-01 88-08 Followed MAC Control -Pause Frame (< 1518
(PAUSE) Or by 00-01 bytes)
(Discarded)
r
Unicast DA
REV_02 01-80-C2-00-00-02 - - Clause 43 (Link Aggregation) and Clause
57 (OAM) of IEEE Std 802.3
ef o
PAE 01-80-C2-00-00-03 88-8E -
a s
ele
Or IEEE Std 802.1X PAE address
Other
REV_03
REV_UN
01-80-C2-00-00-03
i a l
01-80-C2-00-00-04 ~05R --
-
-
- Reserved for future standardization—
e n t i
media access method specific
d
01-80-C2-00-00-06 ~0D - - Reserved for future standardization—
REV_0E
o n f i n
01-80-C2-00-00-0E
a P VLAN-aware Bridge specific
IEEE Std 802.1AB Link Layer Discovery
k C a n a Protocol multicast address
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REV_UN
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01-80-C2-00-00-0F
i a Reserved for future standardization—
REV_10
f i d e
01-80-C2-00-00-10
a P i
VLAN-aware Bridge specific
All LANs Bridge Management Group
REV_20
C o n a n
01-80-C2-00-00-20
n
Address
GMRP Address
REV_21
REV_UN
T e k r B a
01-80-C2-00-00-21
01-80-C2-00-00-22 - -
GVRP Address
d i a F
~
o
01-80-C2-00-00-xx
Reserved for future standardization
Me 2.3.3 Unicast Frames
FTAG DA
Unicast Frames
Type Description
f o r
UC
ARP
The 1st bit of MSB is 1’b0
FF-FF-FF-FF-FF-FF
l e a
-
08-06
Unicast Frames
ARP Request Frames
se
e
- 08-06 ARP Reply Frames
RARP FF-FF-FF-FF-FF-FF
-
i a l R 80-35
80-35
RARP Request Frames
RARP Reply Frames
e n t i
n f i d n a P
k C o a n a
i a T e o r B
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2.4
t i a
Switch L2/L3 Address Table
n
f i d e a P i
The switch has a 2K address table built in for packet look-up forwarding. All the entries can be shared and mixed
by L2 MAC address or L3 IP address according to “TYPE” definition. When the entry is regarded as a MAC address
C o n n a n
table, it is used to forward packets by L2 DA and learn packets by L2 SA. When the entry is regarded as a DIP
a
address table, it is used to process IGMP/MLD snooping. To support IGMPv3/MLDv2, a SIP entry is added to
e k B
search the Source IP list after DIP look-up.
T r
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2.4.1 MAC Address Table
MAC Address Table

Bytes Bits Name
Customer VID [11:0]
Description
f o r
se
11:0 CVID Customer VLAN ID is learned automatically from VLAN tag or port-based
e l a
register PPBV#.PORT_VID.
e
Filter ID[2:0]
7:0
14:12 FID
i a l R Filter ID is learned automatically from VLAN Table. 0 is the default value if

VLAN Table is not applicable.
15 IVL
e n t i
Independent VID Learning
IVL is learned automatically from VLAN Table. 0 is the default value if
n f i d n a P
VLAN Table is not applicable.
MAC Address[47:0]
63:16
k C o ADDRESS
a n a 48-bits MAC Physical Address is searched by Destination MAC Address

and learned from Source MAC Address.
Bytes
i a T eBits
o r B Name
Layer2/Layer3 Address Entry Type
Description
Me d 1:0
F TYPE
2’b00: MAC Address Entry
2’b01: DIP Address Entry.
2’b10: Source IP Address Table
2’b11: Reserved
Address Entry Live Status
2’b00: Entry is empty
o r
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3:2 STATUS 2’b01: Entry is dynamic and valid
s
2’b10: Reserved
a
3:0
2’b11: Entry is static and won’t be aged out or changed by the hardware
ele
Destination Port Map
11:4 PORT / FILTER
i a l R (Note: Frame dropped by DA Address through PORT=6’b0)

Bit4: Port 0
e n t i
~
Bit11: Port 7
12
n f i d
LEAKY_EN
n a P Leaky VLAN Enable

1’b0: This frame address will be blocked by VLAN (default)
k C o a n a 1’b1: This frame address can pass through VLAN
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n t i a (Note: Leaky VLAN can be configured by ARL or Port Control Register
f i d e a P i
based on the indication of MFC.UC_ARL_LKYV or MFC.MC_ARL_LKYV.)
Egress VLAN Tag Attribution
C o n n a n
3’b000: System default (Default)
3’b001: Consistent
T e k
15:13
B
EG_TAG
r a 3’b010,3’b011: Reserved
3’b100: Untagged
d i a F o 3’b101: Swap
3’b110: Tagged
Me
3’b111: Stack
User Priority from Address Table
18:16 USR_PRI
0: Default
Source Address Hit to Mirror port
19 SA_MIR_EN 1’b0: No action (default)
f o r
se
1’b1: Frame is copied to mirror port when SA hits the MAC table
Source Address Hit Frame TO_CPU Forwarding
e l e a
3’b0xx: System Default (Disable)
3’b100: System Default and CPU Port Excluded
22:20 SA_PORT_FW
i a l R 3’b101: System Default and CPU Port Included

3’b110: CPU Port Only (while the ingress port is not CPU port, otherwise
e n t i
system default and CPU excluded)
3’b111: Frame Dropped
23 -
n f i d n a P Reserved
o
Age Timer
31:24
k C TIMER
a n a Programmable age timer. The age duration can be set from 1 to

1,000,000 seconds. The field value will be reset to the register
i a T e o r B AAC.AGE_CNT and counted down by one every AAC.AGE_UNIT seconds.
Me d F
2.4.2 Destination IP Address Table
While receiving IP Multicast frames, the destination IP will be used to search the address table. For this usage,
the address entry has TYPE=2’b01 (IGMPv2). The table is shown below.
o r
ef
DIP Address Table
Bytes Bits Name Description
a s
ele
Response Counter[15:0]
A response counter for each port is used to count the consecutive
15:0 RESP_CNT
i a l R occurrence times of no IGMP Report message received before the

Response Timer counts to zero.
t
7:0 Bit[49:48]: Port 0
i d e n P i
~
f
Bit[63:62]: Port 7
23:16
C o nRESP_FLAG
a n a Response Flag[7:0]
e k B a n
d i a T F o r
M e This document contains information that is proprietary to MediaTek Inc.

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n t i a After receiving the Group Query or Group Specific Query, this flag is used
f i d e a P i
to record any IGMP report message received for the corresponding port
before the response interval counts to zero.
C o n n a n
Bit40: Port 0
~
k a
Bit47: Port 7
i a T e
31:24
o r B
RESP_TIIMER
Response Timer[7:0]
This timer will be set according to the maximum response time field in
Me d 63:32
F ADDRESS
the General Specific Query message and count down every second. The
default timer for the General Query message (=0x0) is 10 seconds.
IP Multicast Destination IP Address[31:0]
The latest 32-bits DIP(GA) for IPv4 or IPv6 packets
f o r
se
1:0 TYPE 2’b01: DIP Address Entry
e l a
e
2’b11: Reserved
i a l R Address Entry Live Status

2’b00: Group entry is empty.
e n t i
2’b01: Group entry is dynamically valid whenever any IGMP report
message received before the response timer counts to zero, and the
3:2
n f i
STATUS
d n a P
response counter is not larger than the robustness variable.
2’b10: Entry is static, and the final port map will result from the SIP table
k C o a n a
search.
2’b11: Entry is static and will not be aged out or changed by the
e B
hardware.
d i a T11:4
F o r
PORT / FILTER
Destination Port Map or Filter Mode for IGMPv3/MLDv2
Bit4: Port 0
Me
3:0 ~
Bit11: Port 7
Leaky VLAN Enable
1’b0: This frame address will be blocked by VLAN (default).
12 LEAKY_EN 1’b1: This frame address can pass through VLAN.
o r
ef
(Note: Leaky VLAN can be configured by ARL or Port Control Register
based on the indication of MFC.UC_ARL_LKYV or MFC.MC_ARL_LKYV.)
a s
ele
3’b000: System default (Default)
R
15:13 EG_TAG
t i a l 3’b010 ~ 3’b011: Reserved

3’b100: Untagged
i d e n P i
3’b101: Swap
3’b110: Tagged
o n f a n a 3’b111: Stack
User Priority from IGMP Table
e k C
18:16 USR_PRI
B a n 0: Default
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31:19 -
n t i a Reserved
f i d e a P i
C o n
2.4.3 Source IP Address Table
n a n
T k r B a
The internal 4K entries address table can also be used for Source IP table for IGMPv3. For this usage, the address
e
entry has TYPE=2’b11. The table is shown below.
d i a F o
Me
Source IP Address Table
IP Multicast Source IP Address [31:0]
31:0 SIP_ADR
r
The latest 32-bits IPv4 or IPv6 Source address
7:0
63:32 DIP_ADR
IP Multicast Destination IP Address [31:0]
f o
se
The latest 32-bits IPv4 or IPv6 Destination or Group address
a
R e l e
1:0 TYPE
t i a l 2’b01: DIP Address Entry

i d e n P i
2'b11: Reserved
Address Entry Live Status
3:0 3:2
o n f
STATUS
a n a 2’b00: Group entry is empty

2’b01 ~ 10: Reserved
e k C B a n 2’b11: Entry is static and won’t be aged out or changed by the hardware
Port Member
d i a T
11:4
F o r
PORT_MAP
Bit.4: Port 0
~
Me
Bit.1: Port 7
31:12 - Reserved
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
2.5 Virtual LAN

n t i a
2.5.1 VLAN Table
f i d e a P i
C o n n a n
Bits
T e kName
r B a VLAN Table
Description
0
d i a VALID
F o VLAN Entry Valid
Me
Filtering Database
3’h0: Default FID for all MAC address
3:1 FID
~
3’h7
(1) Service Tag Identification (VLAN Table PORT_STAG=1’b0)
12-bits Service Tag ID for VLAN translation or Stack VLAN
f o r
se
(2) Service Tag Index (VLAN Table PORT_STAG=1’b1)
15:4 S_TAG1
l e a
bit[5:4]: Port 0 STAG index
e
R
t i l
a
i d e nbit[15:14]: Port 5 STAG index
P i
VLAN Member Control
o n f a n a
(Note: Frame dropped through PORT=6’b0)
Port 0 -
23:16
e k C
PORT_MEM
B a n Bit 0: VID Port Member

~
d i a T F o r Port 7 -
Bit 7: VID Port Member
Me
26:24 USER_PRI Service Tag User Priority Value from VLAN Table
27 COPY_PRI Copy User Priority Value from Customer Priority Tag for Stack VLAN
Per VLAN Egress Tag Control
28 VTAG_EN
Enable per-vlan egress tag attribute by EG_CON and EG_TAG
Egress Tag Consistent
o r
ef
29 EG_CON Keep the original ingress tag attribute.
(Note: When the EG_CON is set, EG_TAG will be invalid for the outgoing frames)
a s
ele
MAC Address Learned by Individual CVID
30 IVL_MAC 1'b0: MAC address will be learned by MAC and FID
i a R
1'b1: MAC address will be learned by MAC and CVID
l
Port-based STAG
31 PORT_STAG
e n t 1'b0: S_TAG1 shows 12-bit VID
i
1'b1: S_TAG1 and S_TAG2 show 2-bit STAG index on per port.
n f i d n P
VLAN Egress Tag Control
a
o
Bit.33~Bit.32 (Port 0) –
47:32 EG_TAG
k C a n a 2’b00: Untagged
2’b01: Swap
i a T e o r B
M e d F
Page 16 of 830
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n t i a
2’b10: Tagged
f i d e ~
a P i
2’b11: Stack
C o n n a n Bit.47 ~ Bit.46 (Port 7)

(2) Service Tag Index
59:48
T e k
S_TAG2
r B a bit[49:48]: Port 6 STAG index

d i a F o bit[59:52]: Reserved
Me 2.5.2 VLAN Security Mechanism

The ingress port can support VLAN security or flexible ingress rule. There are four ingress port attributes
r
described as follows -
2’b11: Security mode
f o
se
Enable 802.1Q VLAN for all the received frames.
l a
Discard received frame due to ingress membership violation (interrupt CPU).
e
Discard received frames once if VID is missed on the VLAN table (interrupt CPU).
e
2’b10: Check mode
a l R
Enable 802.1Q function for all the received frames.
i
e n t
Do not discard received frame due to ingress membership violation.
i
Discard received frames once if VID is missed on the VLAN table (interrupt CPU).
2’b01: Fallback mode
n f i d n a P
o
Enable 802.1Q function for all the received frames.
C n a
Do not discard received frame due to ingress membership violation.
k a
e B
Frames whose VID is missed on the VLAN table will be filtered by the Port Matrix Member.
d i T F o r
2’b00: Port Matrix mode
a 802.1Q function is disabled (VLAN Security and VLAN Filter Table).
Me
Frames filtered by the Port Matrix Member
2.5.3 VLAN Membership Resolution
r
VLAN Membership Resolution
ACL PCR.PORT_VLAN VLAN

VLAN
Member
Action
ef o
Hit - - - Use Port in Rule Control Table
a s
ele
Not Hit Port Matrix - - Use PORT_MATRIX in PCR register
Fallback
i a l R Hit
Not Hit
-
-
Use PORT_MEM in VLAN Table
Use PORT_MATRIX in PCR register
Check
e n t i
Hit
Not Hit
-
-
Use PORT_MEM in VLAN Table
Frame Dropped
f i d
Security
n n a P Hit Yes Use PORT_MEM in VLAN Table
o
- - Frame Dropped
k C a n a
i a T e o r B
M e d F
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2.5.4
t i a
Egress VLAN Tag Process
n
f i d e a P i EG_TAG Attribute Priority Resolution
n
ACL FTAG ARL PVC.EG_TAG VLAN Action
Hit -
C o -
n a n - - Use EG_TAG in Rule Control Table

Not Hit PPPoE
T e k
Discovery
r B a
- - - Use EG_TAG in APC register
d i a
ARP/RARP
F o
Me
IGMP/MLD - - - Use EG_TAG in IMC register
BPDU and - - - Use EG_TAG in BPC register
PAE
REV_01, - - - Use EG_TAG in RGAC1~ RGAC4 registers
REV_02,
REV_03,
f o r
REV_0E
REV_10,
l e a se
REV_20
REV_21,
l R e
REV_UN
n t i a
e
Other Hit - - Use EG_TAG in Address Table
n f i d
Not Hit
a P i Hit - Use EG_TAG in PVC register
n
Not Hit Hit Use EG_CON and EG_TAG in VLAN Table
k C o a n a Not Hit Use EG_TAG in PCR register
i a T e o r B
Me d F
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
2.6
t i a
Access Control Logic (ACL)
n
f i d e a P i
Although Ethernet switch or bridge is well-defined by IEEE Std.802.3, additional requirements are still needed
for it to fit in future standards or to improve security, QoS, or policy control. ARL provides 256 entries ACL rule
C o n n a n
table and 128 entries ACL rule control table with wire-speed on the incoming frames.
2.6.1
T e k B a
ACL Rule Table
r
i a o
ACL rule table is implemented along with packet parser. For the incoming packet, the 2-bytes packet content is
d F
Me
filtered sequentially and compared with 256 patterns in the ACL rule table. When one pattern is hit, the
corresponding rule flag will be set. After the whole packet is done, the final rule flag will be sent to the ACL look-
up engine to get the corresponding rule control.
ACL Rule Table
f o r
se
Byte Bit Name Description
a
Comparison Pattern
1:0 15:0 CMP_PAT
R e l e If CMP_SEL=='b0, this field indicates the 16-bits data pattern.

If CMP_SEL=='b1, this field indicates the low threshold.
3:2 15:0
t i a
BIT_CMP
l Comparison Pattern Mask
If CMP_SEL=='b0, this field indicates the bit-map valid comparison.
i d e n P i
If CMP_SEL=='b1, this field indicates the high threshold.
f
Comparison mode selection
0
C o n n a
CMP_SEL
a
'b0: Pattern hit by data pattern and bit mask
n
'b1: Pattern hit by low and high threshold
a
4
T e k 7:1
r B WORD_OFST
Word Offset
2-bytes offset in the corresponding OFST_TP.
d i a F o (Note: 0x3F is the reserved and invalid offset value.)
Me
Physical Source Port Bit-map
5 7:0 SP
SP[7:0]: port 7 ~ port 0
Format Type for Word Offset Range
3'b000: MAC Header (inc. VLAN tags and Length/Type) (L2 Offset)
3'b001: L2 Payload (L2 Offset)
o r
ef
3'b010: IP Header (L3 Offset)
6
2:0 OFST_TP 3'b011: IP Datagram (L3 Offset)
a s
ele
3'b100: TCP/UDP Header (L4 Offset)
3'b101: TCP/UDP Datagram (L4 Offset)
i a l R 3'b110: IPv6 Header (L3 Offset)
t
3'b111: Reserved
3
i d e n EN
P i
ACL Valid Bit
o n f a n a
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
2.6.2
t i a
ACL Rule Control Table
n
f i e a P i
ACL rule control is a 128 entries table with a linear look-up engine. Each packet can find one or multiple hit
d
entries from the ACL rule control. For the general packet control, the first hit entry will be taken and followed
o n n
during the packet process. As for the ACL rate limit control, multiple entries can be applied on the same packet.
C n a
T e k r B a ACL Rule Mask
d i a
Byte
F o Bit Name Description
Me
Hit Pattern -
When a valid bit is set in this table, it means that the corresponding
15:0 127:0 HIT_PAT pattern in the rule table must be hit and necessary.
If all the valid bits can be found in the rule flag, then the rule control
can be applied on this packet.
f o r
l e a ACL Rule Control Table se
Byte Bit
l R e
Name
Frame TO_CPU Forwarding
Description
n t i a 3’b0xx: System Default (Disable)
e
3’b100: System Default and CPU Port Excluded
2:0
n f i d PORT_FW
a P i 3’b101: System Default and CPU Port Included
n
3’b110: CPU Port Only (When the ingress port is not a CPU port it
k C o a n a will follow, the system default and CPU are excluded)

3’b111: Frame Dropped
i a T e 3
o r B MIR_EN Frame Copy to Mirror Port
F
6:4 PRI_USER User Priority from ACL
Me d 7 PORT_EN
Force Destination Port Selection
1’b0: Destination port is based on ARL or register
1’b1: Destination port is based on PORT.
1 7:0 PORT Destination Port Member / VLAN Port Member
o r
ef
s
3’b000: System Default (Disable)
2:0 EG_TAG
3’b010,3’b011: Reserved
ele a
2
i a l R 3’b100: Untagged
3’b101: Swap
e n t i
3’b110: Tagged
3’b111: Stack
3
n f i d n a P
LKY_VLAN Leaky VLAN
k C
4
5
o a n a
PPP_RM
SA_SWAP
PPPoE Header Removal
Source MAC Address Swap
i a T e o r B
M e d F
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n t i a Multicast MAC Destination Address Swap

6
f i d e DA_SWAP
a P i
IPv4: 01-00-5E-xx-xx-xx (From Destination IP)
IPv6: 33-33-xx-xx-xx-xx (From Destination IP)
7
C o
2:0 n n a n
VLAN_PORT_EN Swap VLAN Port Member with PORT
CNT_IDX Counter Group Index
T e k 3
4
r B a ACL_CNT_EN
INT_EN
Enable ACL Hit Count (Multi/First)
Interrupt Enable (Multi/First)
d i a
(Counter)
F
5
o ACL_MANG Management Frame Attribute
Me
7:6 - Reserved
Select original drop precedence value or ACL control table defined
0 DROP_PCD_SEL
drop precedence value
Select original class_selector value or ACL control table defined
1 CLASS_SLR_SEL
class selector value
f o r
se
4:2 CLASS_SLR User defined class selector
a
7:5 DROP_PCD_R User defined drop precedence value for red color packet
e
6:4
(trTCM)
2:0
5:3
DROP_PCD_Y
DROP_PCD_G
R e l User defined drop precedence value for yellow color packet

User defined drop precedence value for green color packet
7:6
0
--
t i a l
ACL_TCM_SEL
Reserved
Select color remark by Meter Table or use defined color value
2:1
i d e n
ACL_TCM
P i
User defined color remark
o
7:3
n f n a
(00: Default, 01: Green, 10: Yellow, 11: Red)
ACL_CLASS_IDX Class index for the 32-entries Meter Table
a
e k C B a n ACL Rate Control
d i a T
Byte
F o r
Bit Name Description
Me
Per Flow Ingress Rate Limit Control
Per rate limit, multiple rule controls can constraint one packet.
Generally, the minimum ingress rate limits the flow rate.
14’h0: 0 * 64Kbps or 1Mbps (according to CR 0xC[30])
13:0 RATE
1:0
14’h1: 1 * 64Kbps or 1Mbps
o r
ef
14’h2: 2 * 64Kbps or 1Mbps
s
~~
14 MANG_EN
14’h3D09: 15625* 64Kbps or 1Mbps
Per Flow for Management Frame Ingress Rate Control Enable
ele a
15
14:0
RATE_EN
i a l
RATE_ACCU R Per Flow Ingress Rate Limit Enable (Multi/First)
Per Flow Ingress Rate Limit Accumulator
3:2
15
e n
-
t i
Reserved
n f i d n a P
k C o a n a
i a T e o r B
M e d F
Page 21 of 830
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2.7
t
Register Definition
n i a
2.7.1 ARL Register
f i d e a P i
Address
C n n n
Module name: ARL Base address: (+0x0000)
o a Name Width Register Function

00000004
T e
00000008
k CFC
B
AISR
r a 32
32
CPU Forward Control
ACL Interrupt Status
d i a
0000000C
00000010
F o
AGC
MFC
32
32
ARL Global Control
MAC Forward Control
Me
00000014 VTC 32 VLAN TAG Control
00000018 ISC 32 IGMP Snooping Control
0000001C IMC 32 IGMP/MLD Message Control
00000020 APC 32 ARP and PPPoE Control
r
00000024 BPC 32 BPDU and PAE Control
00000028 RGAC1 32 REV_01 and REV_02 Control
f o
se
0000002C RGAC2 32 REV_03 and REV_0E Control
00000030 RGAC3 32 REV_10 and REV_20 Control
00000034
00000038
RGAC4
PMC
e l e a 32
32
REV_21 and REV_UN Control
Protocol Match Control
0000003C
00000040
PBG1
PBG2
i a l R 32
32
Protocol Based Group ID-1
00000058
0000005C
PIM1
PIM2
e n t i
32
32
DSCP Priority Ingress Mapping I
DSCP Priority Ingress Mapping II
00000060
00000064
PIM3
n f
PIM4
i d n a P
32
32
DSCP Priority Ingress Mapping III
DSCP Priority Ingress Mapping IV
00000068
0000006C
00000070
k C o PIM5
PIM6
PIM7
a n a
32
32
32
DSCP Priority Ingress Mapping V
DSCP Priority Ingress Mapping VI
DSCP Priority Ingress Mapping VII
i a T e
00000074
00000078
o r B
ATA1
ATA2
32
32
Address Table Access I
Address Table Access II
Me d0000007C
00000080
00000084
00000088
F ATWD
ATC
TSRA1
TSRA2
32
32
32
32
Address Table Write Data
Address Table Control
Table Search Read Address I
Table Search Read Address II
0000008C ATRD 32 Address Table Read Data
00000090 VTCR 32 VLAN Table Control
o r
ef
00000094 VAWD1 32 VLAN and ACL Write Data I
00000098 VAWD2 32 VLAN and ACL Write Data II
0000009C TRTCM 32 Two Rate Three Color Mark
a s
ele
000000A0 AAC 32 Address Age Control
000000A4 DHCP 32 DHCP Control
000000A8
000000AC
LCP
MHS
i a l R 32
32
PPPoE LCP Control
MAC Table Hash Seed
000000B0
000000B4
CPGC
CPMONC
e n t i
32
32
Collision Pool Global Control
Collision Pool Monitor Control
000000B8
000000BC
n f i d
CPMOND1
CPMOND2
n a P
32
32
Collision Pool Entry Status Monitor 1
Collision Pool Entry Status Monitor 2
000000C0
000000C4
k C o CPSTSC
a n a
AISR_EXT1
32
32
Collision Pool Status Counter
ACL Extension Interrupt Status I
i a T e o r B
M e d F
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000000C8 AISR_EXT2
n t i a 32 ACL Extension Interrupt Status II
e
000000CC AISR_EXT3 32 ACL Extension Interrupt Status III
000000D0
000000D4
MISR
n f i d
MISR_EXT1
a P i 32
32
MLDv2 Interrupt Status
MLDv2 Extension Interrupt Status I
000000E0
000000E4
C o VAWD3
VAWD4
n a n 32
32
ACL Write Data III
ACL Write Data IV
T e
000000E8
000000EC
k r B
VAWD5
VAWD6 a 32
32
ACL Write Data V
ACL Write Data VI
d i a
000000F0
F o VAWD7 32 ACL Write Data VII
Me
000000F4 VAWD8 32 ACL Write Data VIII
00000100 PTC 32 Port Trunking Control
00000104 PTHS 32 Port Trunking Algorithm Seed
00000108 PTGC0 32 Port Trunking Group Control 0
0000010C PTGC1 32 Port Trunking Group Control 1
00000110
00000114
PTGC2
PTGSC0
32
32
Port Trunking Group Control 2
Port Trunking Group Security Control 0
f o r
se
00000118 PTGSC1 32 Port Trunking Group Security Control 1
0000011C
00000120
PTGSC2
SPTC0
e l e a 32
32
Port Trunking Group Security Control 2
Port Trunking Table Control
i a l R
t
00000004 CFC CPU Forward Control 00000000
Bit
Name
31 30
i d e n
29
P
28
i
27 26 25 24 23 22 21 20 19
MIRRO
18 17 16
f
REV0 MIRROR_PORT
a
R_EN
Type
Reset 0
C o0
n n a
0
n 0 0 0
RW
0 0 0 0 0 0
RW
0 0
RW
0 0
Bit
Name
T e k
15 14
r B a 13 12
REV1
11 10 9 8 7 6 5 4
CPU_PMAP
3 2 1 0
a o
Type
i
RW RW
Me d
Reset
Bit(s)
31:20
0
Name
REV0
F 0 0 0 0 0 0
Description
Reserved
0 0 0 0 0 0 0 0 0
19 MIRROR_EN Mirror Port Enable
r
Enable the mirror port specified in MIRROR_PORT.
0: No mirror available
1: Enable mirror
ef o
s
18:16 MIRROR_PORT Mirror Port Number
Set the mirror port number.
3'h0: Port 0
...
ele a
15:8 REV1
i a l R 3'h7: Port 7
Reserved
t
7:0 CPU_PMAP CPU Port Bit Map
i d e n P i
Provide multiple CPU port selection.
[0]: Port 0
f
[1]: Port 1
C o n a n a ...
[7]: Port 7
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
n t i a
00000008
Bit 31
AISR
f
30
i d e 29
a P i 28 27 26
ACL Interrupt Status
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
C o n n a n
ACL_ISR
W1C
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
i a T e15
o r B
14 13 12 11 10 9 8
ACL_ISR
7 6 5 4 3 2 1 0
d
Type
F
W1C
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name Description

31:0 ACL_ISR ACL Interrupt Status for entry 0~31
r
(Refer to ACL Rule Control Table)
f o
0000000C
Bit 31
AGC
30 29 28
l e a 27 26
ARL Global Control
25 24 23 22 21 20 19
se
18
0007181D
17 16
MLDv2
Name _int_e
TICK_S PCP_A SNOP_
EL WARE DROP
l R e REV0
MAC_S
ARLP_ REV1
MAC_HASH_SE
L
REV2
ACL_IN VLAN_I ADDR_
T NT INT
a
n DIS
Type
Reset
RW
0
RW
0
e n t
RW
0
i RW
0 0
RO
0 0
RW
0 0
RO
0 0
RW
0
RO
0
RO
1
RO
1
RO
1
Bit 15
n
14
f i d 13
a P i 12 11 10 9 8 7
ARL_P
6 5 4 3 2 1 0
n
RATE_ LOCAL_ ACL_M L2LEN_ CTRL_D VLAN4 ARL_PR ALR_RS
o
Name COMP_BNUM ADDIN
a
COMP EN ULTI CHK ROP CPU I T_N
C
G
Type
Reset
e k
RW
0
B0
a n 0 1
RW
1 0 0 0
RW
0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
0
RW
1
d i a
Bit(s) T Name
F o r Description
Me
31 MLDv2_int_en MLDv2 interrupt enable
0: Disable
1: Enable
30 TICK_SEL Select 64Kbps or 1Mbps tick in ACL rate control for supporting 2.5G rate
limit
0: 64Kbps tick
o r
ef
1: 1Mbps tick
29 PCP_AWARE Priority-tag aware for dump switch
0: Disable priority-tag
a s
ele
1: Enable priority-tag
28 SNOP_DROP IGMP snooping can learn the dropped frame
i a l R 0: IGMP snoop will ignore the dropped frame

1: IGMP snoop will learn the dropped frame
t
27:25 REV0 Reserved
24 MAC_SARLP_DIS
i d e n P i
Disable oldest address replacement function for mac address learning.
In default, oldest mac address will be replaced by new address when
f
there are no empty entry for mac address learning
C o n a n a Manual update address table won't be affected

0: Replace oldest mac address
23:22
e k
REV1
B a n 1: Not to replace oldest mac address

Reserved
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
21:20 MAC_HASH_SEL Select MAC Table Hash Function
n f i d a P i 2'b00: XOR
2'b01: CRC16
19 REV2
C o n a n 2'b10: CRC32
Reserved
18
T e k
ACL_INT
r B a Access Control List (ACL) Table Initialization Done

0: ACL Table is busy.
a o
1: ACL Table is cleared.
d
17
i F
VLAN_INT VLAN Table Initialization Done
Me
0: VLAN Table is busy.
1: VLAN Table is cleaned.
16 ADDR_INT ADDR Table Initialization Done
0: ADDR Table is busy.
1: ADDR Table is cleaned.
15 RATE_COMP Rate Limit Compensation
Add or subtract the specific byte number while calculating the packet
f o r
se
length.
0: Add
14:8 COMP_BNUM
e l e a 1: Minus
Compensation Byte Number
R
The added/subtracted byte number for the rate limit or the meter table
l
7 LOCAL_EN Local Port Forwarding Enable
n t i a 0: Drop frames at the local port.

1: Allow frame forwarding to the local port.
e
6 ARL_PADDING ARL Data Padding
n f i d a P i Set ARL to add byte padding up to 46 bytes when the length of the data
field of the incoming frame is less than 46 bytes.
C o n a n 0: Disable (default)
1: Enable
5
T e k
ACL_MULTI
r B a Enable Multiple ACL Hit

0: Only the first hit ACL entry
a o
1: Allow multiple ACL hit entries on Rate, Interrupt, and MIB.
d
4
i F
L2LEN_CHK Layer 2 Frame Length Check
Me
Enable a length check on length-encapsulated frame. Drop length error
frames when the value of the ELEN field of this frame is bigger than the
length of the data field.
0: Disable
1: Enable
r
3 CTRL_DROP MAC Control Frame Drop
Drop MAC control frames with ETYPE=0x8808.
0: Disable (default)
ef o
s
1: Enable
2 VLAN4CPU TO_CPU VLAN Member
Set the TO_CPU frame to check VLAN members.
0: Ignore VLAN members.
ele a
1 ARL_PRI
i a l R 1: Check VLAN members.

ARL Resolution Priority
e n t i
0: P0 is the lowest priority.
1: P0 is the highest priority.
0 ALR_RST_N
n f i d n a P
ARL Enable (Soft Reset)
0: Reset the ARL engine.
o
1: Enable ARL engine.
k C a n a
i a T e o r B
M e d F
Page 25 of 830
f o r
l e a se MT7531
l R e Lynx1
00000010 MFC
n t i a MAC Forward Control FFFFFFFF
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
n f i d a P i BC_FFP UNM_FFP
n
RW RW
Reset
Bit
1
15
k C o 1
14
a n a
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Name
e B
UNU_FFP QRY_FFP
Type
d i
Reset
a T 1
F o r 1 1 1
RW
1 1 1 1 1 1 1 1
RW
1 1 1 1
Me Bit(s)
31:24
Name
BC_FFP
Description
Broadcast Frame Flooding Ports
If MAC receives broadcast frames, this field indicates the flooding ports.
[NOTE]
1. The flooding port excludes the received port on the switch.
2. Frame dropped though BC_FFP=7'b0
f o r
se
23:16 UNM_FFP Unknown Multicast Frame Flooding Ports
If MAC receives multicast frames which can not be found on the ARL, this
e l e a field indicates the flooding ports.

[NOTE]
R
1. The flooding port will exclude the received port by HW.
l
2. Frame dropped though UNM_FFP=7'b0.
15:8 UNU_FFP
n t i a Unknown Unicast Frame Flooding Ports

If MAC receives the unicast or multicast frames which can not be found
e
on the ARL. The field indicates the flooding port.
n f i d a P i [NOTE]
1. The flooding port will excludes the received port by HW
n
2. Frame dropped though UNM_FFP=7'b0
7:0
k C o
QRY_FFP
a n a IGMP/MLD Query Frame Flooding Ports

If MAC receives IGMP/MLD query frame, this field indicates the flooding
e B
ports.
T r
[NOTE]
d i a F o 1. The flooding port will exclude the received port by HW.

2. Frame dropped though QRY_FFP=7'b0.
Me 00000014
Bit 31
VTC
30 29 28 27 26
VLAN TAG Control
25 24 23 22 21 20 19 18
000000FF
17 16
Name REV0
o r
ef
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4
le a s
0
3
0
2
0
1
0
0
e
Name REV0 GUEST_MEM
Type
Reset 0 0
i a
0
l R 0
RW
0 0 0 0 1 1 1 1
RW
1 1 1 1
Bit(s) Name
e n t i
Description
19:8
7:0
REV0
n f i
GUEST_MEM
d n a P
Reserved
Guest VLAN Member
o
The assigned VLAN member for the frames which cannot pass 802.1x
k C a n a authentication
i a T e o r B
Med F
Page 26 of 830
f o r
l e a se MT7531
l R e Lynx1
n t i a
00000018
Bit 31
ISC
f
30
i d e 29
a P i28 27 26
IGMP Snooping Control
25 24 23 22 21 20 19 18
7F027DFF
17 16
Name
C o n n a n LRN_RP REV0
DWN_
GRADE
_EN
MLD_R IGMP_
P_EN RP_EN
ROBUST_VAR
Type
Reset
T e0
k r
1
B a 1 1
RO
1 1 1 1 0
RW
0 0
RW
0
RW
0
RW
0 1
RW
0
Bit
d
Name
i a 15
F o 14 13 12
QRY_INTL
11 10 9 8 7 6 5 4
DEF_RP
3 2 1 0
Me
Type RW RW
Reset 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

31:24 LRN_RP Learned Router Ports
Show the router ports for IGMP/MDL messages including the default and
f o r
se
learned ports.
23:21 REV0 Reserved
20 DWN_GRADE_EN
e l e a IGMP v2 to v1 Auto-Downgrade Enable

Enable an automatic downgrade from IGMPv2 to v1 due to a IGMPv1
R
report message.
t i a l 0: Disable
1: Enable
n
19 MLD_RP_EN MLD Router Port Learning Enable
f i d e a P i
Enable automatic router port learning automatically based on MLD
queries.
n
0: Disable
18
C o
IGMP_RP_EN
n a n 1: Enable
IGMP Router Port Learning
T e k r B a Enable automatic router port learning based on IGMP queries.

0: Disable
a o
1: Enable
d i
17:16
F
ROBUST_VAR Robustness Variable
Me
Define the maximum allowable number of IGMP Query messages that
may be lost consecutively.
0: Reserved
1: One time
2: Two times (default)
3: Three times
o r
ef
15:8 QRY_INTL Query Interval
Together with the Robustness Variable, the Query Interval sets the age-
Age-out time = (QRY_INTL * ROBUST_VAR)
a s
out time for router ports automatically learned from IGMP Query frames.
ele
(unit: sec)
7:0 DEF_RP Default Router Port
i a l R Set the default router port which will not be aged out when IGMP/MLD
router port learning is enabled.
e n t i
0000001C
f
IMC
n i d n a P IGMP/MLD Message Control 08100810
o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
k C a n a
i a T e o r B
M e d F
Page 27 of 830
f o r
l e a se MT7531
l R e Lynx1
MDL_R
n t i a MLD_
MLD_P
MLD_B MLD_L MLD_P MLD_Q
e
Name PT_MI MLD_RPT_FW MANG PDU_F MLD_EG_TAG KY_VLA RI_HIG UE_MI MLD_QUE_FW
i
AE_FR
d
R _FR R N H R
Type
Reset
RW
0
o n
0
f i RW
0
n a P 0
RW
1
RW
0
RW
0 0
RW
0 0
RW
0
RW
1
RW
0 0
RW
0 0
Bit 15
k C
IGMP_
14
a n a
13 12 11
IGMP_
10
IGMP_
9 8 7 6 5 4
IGMP_ IGMP_ IGMP_
3 2 1 0
e B
IGMP_
Name RPT_M IGMP_RPT_FW MANG BPDU_ IGMP_EG_TAG LKY_VL PRI_HI QUE_M IGMP_QUE_FW
T r
PAE_FR
a
IR _FR FR AN GH IR
d i
Type RW
F o RW RW RW RW RW RW RW RW RW
Me
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0

31 MDL_RPT_MIR MLD Report/Done Message to Mirror Port
0: Disable
30:28 MLD_RPT_FW
1: Frame copied to Mirror port
MLD Report/Done Message TO_CPU Forwarding
f o r
se
3'b0xx: System default (disable)
e l e a 3'b100: System default and CPU port excluded

3'b101: System default and CPU port included
3'b110: CPU port only (As long as the ingress port is not the CPU port. If
i a l R the ingress port is the CPU port, then the system default and CPU port
are excluded.)
t
3'b111: Frame dropped
27 MLD_MANG_FR
i d e n P i
MLD Message as Management Frame
0: Disable
26
n
MLD_PAE_FR
o f a n a
1: Regarded as management frame
MLD Message as PAE Frame
C
0: Disable
25
e k B
MLD_BPDU_FR
a n 1: Regarded as PAE frame
MLD Message as BPDU Frame
d i a T F o r 0: Non-BPDU Frame
1: Regarded as BPDU frame
Me
24:22 MLD_EG_TAG MLD Message Egress VLAN Tag Attribution
3'b000: System default (disable)
3'b001: Consistent
3'b010, 3'b011: Reserved
3'b100: Untagged
r
3'b101: Swap
3'b110: Tagged
3'b111: Stack
ef o
21 MLD_LKY_VLAN MLD Leaky VLAN Enable
a s
ele
0: Disable
1: Enable
R
20 MLD_PRI_HIGH MLD Force the Highest Priority
t i a l 0: System default
1: Assigned to the highest priority queue.
n
19 MLD_QUE_MIR MLD Query Message to Mirror Port
f i d e a P i
0: Disable
n
18:16 MLD_QUE_FW MLD Query Message TO_CPU Forwarding
C o n a n 3'b0xx: System default (disable)

3'b100: System default and CPU port excluded
T e k r B a 3'b101: System default and CPU port included
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i the ingress port is the CPU port, then the system default and CPU port
are excluded.)
15
C o
IGMP_RPT_MIR
n a n 3'b111: Frame Dropped

IGMP Report/Done Message to Mirror Port
k a
0: Disable
14:12
i a T e r B
IGMP_RPT_FW
o
IGMP Report/Done Message TO_CPU Forwarding
F
Me d 3'b100: System default and CPU port excluded

the ingress port is the CPU port, then the system default and CPU port
are excluded.)
r
11 IGMP_MANG_FR IGMP Message as Management Frame
0: Disable
f o
se
10 IGMP_PAE_FR
e l e a IGMP Message as PAE Frame

0: Disable
1: Regarded as PAE frame
9 IGMP_BPDU_FR
i a l R IGMP Message as BPDU Frame

0: Non-BPDU Frame
8:6 IGMP_EG_TAG
e n t i
IGMP Message Egress VLAN Tag Attribution
n f i d n a P
3'b001: Consistent
k C o a n a
3'b100: Untagged
3'b101: Swap
i a T e o r B 3'b110: Tagged
3'b111: Stack
Me d5
4
F
IGMP_LKY_VLAN
IGMP_PRI_HIGH
IGMP Leaky VLAN Enable
0: Disable
1: Enable
IGMP Force the Highest Priority
0: System default
3 IGMP_QUE_MIR IGMP Query Message to Mirror Port
o r
ef
0: Disable
2:0 IGMP_QUE_FW IGMP Query Message TO_CPU Forwarding
a s
ele
i a l R 3'b101: System default and CPU port included

t
i d e n P i
are excluded.)
3'b111: Frame Dropped
o n f a n a
00000020
e k C APC
B a n ARP and PPPoE Control 08100810
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit 31 30
n t i
29
a 28 27 26 25 24 23 22 21 20 19 18 17 16
e i
PPP_M PPP_LK
d
PPP_P PPP_BP PPP_PR PPP_M
i P
Name REV0 ANG_F PPP_EG_TAG Y_VLA PPP_PORT_FW
f
AE_FR DU_FR I_HIGH IR
a
R N
Type
Reset 0
C o n 0
RO
n a n0 0
RW
1
RW
0
RW
0 0
RW
0 0
RW
0
RW
1
RW
0 0
RW
0 0
Bit
T e k
15 14
r B a 13 12 11
ARP_M
ARP_P
10
ARP_B
9 8 7 6 5
ARP_LK ARP_P
4
ARP_M
3 2 1 0
a o
Name REV1 ANG_F PDU_F ARP_EG_TAG Y_VLA RI_HIG ARP_PORT_FW
i
AE_FR IR
Me d
Type
Reset 0 F 0
RW
0 0
R
RW
1
RW
0
R
RW
0 0
RW
0 0
N
RW
0
H
RW
1
RW
0 0
RW
0 0
r
31:28 REV0 Reserved
27 PPP_MANG_FR PPPoE Discovery as Management Frame
0: Disable
f o
se
26 PPP_PAE_FR
e l e a PPPoE Discovery as PAE Frame

0: Disable
25 PPP_BPDU_FR
i a l R PPPoE Discovery as BPDU Frame

0: Non-BPDU Frame
24:22 PPP_EG_TAG
e n t i
PPPoE Discovery Egress VLAN Tag Attribution
n f i d n a P
3'b001: Consistent
o
k C a n a 3'b100: Untagged
3'b101: Swap
i a T e o r B 3'b110: Tagged
3'b111: Stack
Me d
21
20
F
PPP_LKY_VLAN
PPP_PRI_HIGH
PPPoE Discovery Leaky VLAN Enable
0: Disable
1: Enable
PPPoE Discovery Force the Highest Priority
0: System default
19 PPP_MIR PPPoE Discovery to Mirror Port
o r
ef
0: Disable
18:16 PPP_PORT_FW PPPoE Discovery TO_CPU Forwarding
a s
ele
i a l R 3'b101: System default and CPU port included

t
i d e n P i
are excluded.)
f
15:12 REV1 Reserved
11
C o n
ARP_MANG_FR
a n a ARP/RARP Discovery as Management Frame

0: Disable
10
e k
ARP_PAE_FR
B a n 1: Regarded as management frame

ARP/RARP Discovery as PAE Frame
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Disable
n f
ARP_BPDU_FR
i d a P i 1: Regarded as PAE frame
ARP/RARP Discovery as BPDU Frame
C o n a n 0: Non-BPDU Frame
8:6
T e k
ARP_EG_TAG
r B a ARP/RARP Discovery Egress VLAN Tag Attribution

a o
3'b001: Consistent
d i F 3'b010, 3'b011: Reserved
Me
3'b100: Untagged
3'b101: Swap
3'b110: Tagged
3'b111: Stack
5 ARP_LKY_VLAN ARP/RARP Discovery Leaky VLAN Enable
0: Disable
1: Enable
f o r
se
4 ARP_PRI_HIGH ARP/RARP Discovery Force the Highest Priority
a
0: System default
3 ARP_MIR
R e l e 1: Assigned to the highest priority queue.

ARP/RARP Discovery to Mirror Port
0: Disable
2:0 ARP_PORT_FW
t i a l 1: Frame copied to Mirror port

ARP/RARP Discovery TO_CPU Forwarding
i d e n P i
o n f a n a
C
e k B a n are excluded.)
d i a T F o r
Me
00000024 BPC BPDU and PAE Control 0C100A10
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAE_M PAE_B PAE_LK PAE_P
PAE_P PAE_M
Name REV0 ANG_F PDU_F PAE_EG_TAG Y_VLA RI_HIG PAE_PORT_FW
AE_FR IR
R R N H
Type RO RW RW RW RW RW RW RW RW
o r
ef
Reset 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0
s
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name REV1
BPDU_
MANG
_FR
BPDU_
PAE_FR
BPDU_
BPDU_
FR
BPDU_EG_TAG
BPDU_ BPDU_
ele
LKY_VL PRI_HI
AN GH a
BPDU_
MIR
BPDU_PORT_FW
Type
Reset 0 0
RW
i a l
0
R 0
RW
1
RW
0
RW
1 0
RW
0 0
RW
0
RW
1
RW
0 0
RW
0 0
Bit(s) Name
e n t i
Description
31:28
27
REV0
n f i d
PAE_MANG_FR
n a P Reserved
PAE as Management Frame
k C o a n a
0: Disable
e B
26 PAE_PAE_FR PAE as PAE Frame
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Disable
25
n f
PAE_BPDU_FR
i d a P i 1: Regarded as PAE frame
PAE as BPDU Frame
C o n a n 0: Non-BPDU Frame
24:22
T e k
PAE_EG_TAG
r B a PAE Egress VLAN Tag Attribution

a o
3'b001: Consistent
d i F 3'b010, 3'b011: Reserved
Me
3'b100: Untagged
3'b101: Swap
3'b110: Tagged
3'b111: Stack
21 PAE_LKY_VLAN PAE Leaky VLAN Enable
0: Disable
1: Enable
f o r
se
20 PAE_PRI_HIGH PAE Force the Highest Priority
a
0: System default
19 PAE_MIR
R e l e 1: Assigned to the highest priority queue.

PAE to Mirror Port
0: Disable
18:16 PAE_PORT_FW
t i a l 1: Frame copied to Mirror port

PAE TO_CPU Forwarding
i d e n P i
o n f a n a
C
e k B a n are excluded.)
15:12
11
d i a T REV1
o r
BPDU_MANG_FR
F
Reserved
BPDU as Management Frame
0: Disable
Me
10 BPDU_PAE_FR BPDU as PAE Frame
0: Disable
9 BPDU_BPDU_FR BPDU as BPDU Frame
0: Non-BPDU Frame
o r
ef
s
8:6 BPDU_EG_TAG BPDU Egress VLAN Tag Attribution
a
ele
3'b001: Consistent
i a l R 3'b100: Untagged
3'b101: Swap
e n t i
3'b110: Tagged
3'b111: Stack
5
n f i
BPDU_LKY_VLAN
d n a P
BPDU Leaky VLAN Enable
0: Disable
o
1: Enable
4
C
BPDU_PRI_HIGH
k a n a BPDU Force the Highest Priority

0: System default
i a T e o r B
M e d F
Page 32 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
3 BPDU_MIR
n f i d a P i BPDU to Mirror Port

0: Disable
2:0
C o
BPDU_PORT_FW
n a n 1: Frame copied to Mirror port

BPDU TO_CPU Forwarding
T e k r B a 3'b0xx: System default (disable)

a o
d i F 3'b110: CPU port only (As long as the ingress port is not the CPU port. If
Me
are excluded.)
00000028 RGAC1 REV_01 and REV_02 Control
f o r
08100810
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R02_M R02_LK
a
R02_P R02_BP R02_PR R02_M
e
Name REV0 ANG_F R02_EG_TAG Y_VLA R02_PORT_FW
l
R N
Type
Reset 0 0
RO
0
l R0
e RW
1
RW
0
RW
0 0
RW
0 0
RW
0
RW
1
RW
0 0
RW
0 0
Bit 15 14
n t
13
i a 12 11
R01_M
10 9 8 7 6 5
R01_LK
4 3 2 1 0
e
i
d
i P
R N
Type
Reset 0
o n
0
f RW
a n
0
a 0
RW
1
RW
0
RW
0 0
RW
0 0
RW
0
RW
1
RW
0 0
RW
0 0
Bit(s)
e k
NameC B a n Description
31:28
27
d i a T REV0
F o r
R02_MANG_FR
Reserved
REV_02 as Management Frame
Me
0: Disable
26 R02_PAE_FR REV_02 as PAE Frame
0: Disable
r
25 R02_BPDU_FR REV_02 as BPDU Frame
0: Non-BPDU Frame
ef o
24:22 R02_EG_TAG REV_02 Egress VLAN Tag Attribution
a s
ele
3'b001: Consistent
R
t i a l 3'b100: Untagged
3'b101: Swap
n
3'b110: Tagged
21
f i
R02_LKY_VLAN
d e a P i
3'b111: Stack
REV_02 Leaky VLAN Enable
n
0: Disable
20
C o
R02_PRI_HIGH
n a n 1: Enable
REV_02 Force the Highest Priority
T e k r B a 0: System default
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
19 R02_MIR
n f i d a P i REV_02 to Mirror Port

0: Disable
18:16
C o
R02_PORT_FW
n a n 1: Frame copied to Mirror port

REV_02 TO_CPU Forwarding
T e k r B a 3'b0xx: System default (disable)

a o
d i F 3'b110: CPU port only (As long as the ingress port is not the CPU port. If
Me
are excluded.)
15:12 REV1 Reserved
11 R01_MANG_FR REV_01 as Management Frame
r
0: Disable
f o
se
0: Disable
9 R01_BPDU_FR
e l e a 1: Regarded as PAE frame

REV_01 as BPDU Frame
R
0: Non-BPDU Frame
8:6 R01_EG_TAG
t i a l 1: Regarded as BPDU frame

REV_01 Egress VLAN Tag Attribution
n
f i d e a P i
3'b001: Consistent
n
3'b100: Untagged
C o n a n 3'b101: Swap
3'b110: Tagged
T e k r B
R01_LKY_VLAN
a 3'b111: Stack
d i a F o 0: Disable
1: Enable
Me
4 R01_PRI_HIGH REV_01 Force the Highest Priority
0: System default
3 R01_MIR REV_01 to Mirror Port
0: Disable
o r
ef
2:0 R01_PORT_FW REV_01 TO_CPU Forwarding
s
a
ele
i a l R the ingress port is the CPU port, then the system default and CPU port
are excluded.)
t
i d e n P i
0000002C
o n f
RGAC2
a n a REV_03 and REV_0E Control 08100810
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
n t i a R0E_M
R0E_PA R0E_BP
R0E_LK
R0E_PR R0E_MI
e
Name REV0 ANG_F R0E_EG_TAG Y_VLA R0E_PORT_FW
i
E_FR DU_FR I_HIGH R
d
R N
Type
Reset 0
o n f
0
i RO
n0
a P 0
RW
1
RW
0
RW
0 0
RW
0 0
RW
0
RW
1
RW
0 0
RW
0 0
Bit 15
k C 14
a n a 13 12 11
R03_M
10 9 8 7 6 5
R03_LK
4 3 2 1 0
e B
T r
a
R N
d i
Type
F o RW RW RW RW RW RW RW RW RW
Me
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0

31:28 REV0 Reserved
27 R0E_MANG_FR REV_0E as Management Frame
0: Disable
f o r
se
26 R0E_PAE_FR REV_0E as PAE Frame
a
0: Disable
25 R0E_BPDU_FR
R e l e 1: Regarded as PAE frame

REV_0E as BPDU Frame
0: Non-BPDU Frame
24:22 R0E_EG_TAG
t i a l 1: Regarded as BPDU frame

REV_0E Egress VLAN Tag Attribution
i d e n P i
3'b001: Consistent
o n f a n a
3'b100: Untagged
C n
3'b101: Swap
T e k r B a 3'b110: Tagged
3'b111: Stack
a o
21 R0E_LKY_VLAN REV_0E Leaky VLAN Enable
d i F
0: Disable
Me
1: Enable
20 R0E_PRI_HIGH REV_0E Force the Highest Priority
0: System default
19 R0E_MIR REV_0E to Mirror Port
0: Disable
o r
ef
18:16 R0E_PORT_FW REV_0E TO_CPU Forwarding
a s
ele
R
t i a l the ingress port is the CPU port, then the system default and CPU port
are excluded.)
n
15:12
11
REV1
R03_MANG_FR
f i d e a P i
Reserved
n
0: Disable
10
C o
R03_PAE_FR
n a n 1: Regarded as management frame

REV_03 as PAE Frame
T e k r B a 0: Disable
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
9 R03_BPDU_FR
n f i d a P i REV_03 as BPDU Frame

0: Non-BPDU Frame
8:6
C o
R03_EG_TAG
n a n 1: Regarded as BPDU frame

T e k r B a 3'b000: System default (disable)

3'b001: Consistent
a o
d i F 3'b100: Untagged
Me
3'b101: Swap
3'b110: Tagged
3'b111: Stack
5 R03_LKY_VLAN REV_03 Leaky VLAN Enable
0: Disable
4 R03_PRI_HIGH
1: Enable
f o r
se
0: System default
a
3 R03_MIR
R e l e REV_03 to Mirror Port

0: Disable
2:0 R03_PORT_FW
t i a l REV_03 TO_CPU Forwarding

i d e n P i
o n f a n a
are excluded.)
e k C B a n 3'b111: Frame Dropped
d i a
00000030 T F o r
RGAC3 REV_10 and REV_20 Control 08100810
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R20_M R20_LK
R N
Type RO RW RW RW RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
R10_M R10_LK
a
ele
R N
Type RW RW RW RW RW RW RW RW RW
Reset 0 0
i
0
a l R 0 1 0 0 0 0 0 0 1 0 0 0 0
Bit(s)
31:28
Name
REV0
e n t i
Description
Reserved
27
f i
R20_MANG_FR
n d n a P REV_20 as Management Frame

0: Disable
26
C o
R20_PAE_FR
k a n a
REV_20 as PAE Frame
0: Disable
i a T e o r B
M e d F
Page 36 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
25 R20_BPDU_FR
n f i d a P i REV_20 as BPDU Frame

0: Non-BPDU Frame
24:22
C o
R20_EG_TAG
n a n 1: Regarded as BPDU frame

T e k r B a 3'b000: System default (disable)

3'b001: Consistent
a o
d i F 3'b100: Untagged
Me
3'b101: Swap
3'b110: Tagged
3'b111: Stack
21 R20_LKY_VLAN REV_20 Leaky VLAN Enable
0: Disable
20 R20_PRI_HIGH
1: Enable
f o r
se
0: System default
a
19 R20_MIR
R e l e REV_20 to Mirror Port

0: Disable
18:16 R20_PORT_FW
t i a l REV_20 TO_CPU Forwarding

i d e n P i
o n f a n a
are excluded.)
15:12
e k
REV1
C B a n 3'b111: Frame Dropped
Reserved
T r
11 R10_MANG_FR REV_10 as Management Frame
Me
0: Disable
9 R10_BPDU_FR REV_10 as BPDU Frame
0: Non-BPDU Frame
o r
ef
8:6 R10_EG_TAG REV_10 Egress VLAN Tag Attribution
s
a
3'b001: Consistent
ele
3'b100: Untagged
i a l R 3'b101: Swap
3'b110: Tagged
5 R10_LKY_VLAN
e n t i
3'b111: Stack
n f i d n a P
0: Disable
1: Enable
o
4 R10_PRI_HIGH REV_10 Force the Highest Priority
k C a n a 0: System default
i a T e o r B
M e d F
Page 37 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
3 R10_MIR REV_10 to Mirror Port
n f i d a P i 0: Disable
2:0
C o
R10_PORT_FW
n a n REV_10 TO_CPU Forwarding

T e k r B a 3'b100: System default and CPU port excluded

a o
d i F
Me
are excluded.)
r
00000034 RGAC4 REV_21 and REV_UN Control 08100810
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18
f o
17 16
se
RUN_ RUN_B RUN_L RUN_P
RUN_P RUN_
Name REV0 MANG PDU_F RUN_EG_TAG KY_VLA RI_HIG RUN_PORT_FW
a
AE_FR MIR
_FR R N H
Type
Reset 0 0
RO
0
R
0
RW
1
RW
0
RW
0 0
RW
0 0
RW
0
e l
RW
1
e RW
0 0
RW
0 0
Bit 15 14
t i
13
a l 12 11
R21_M
10
R21_P R21_BP
9 8 7 6 5
R21_LK
4
R21_PR R21_M
3 2 1 0
n
Type
f i d e
RW
a P i
R
RW RW RW RW
N
RW RW RW RW
n
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
C o n a n
k a
31:28
27
i a T e REV0
o r B
RUN_MANG_FR
Reserved
F
0: Disable
M e d 26 RUN_PAE_FR
REV_20 as PAE Frame
0: Disable
25 RUN_BPDU_FR REV_20 as BPDU Frame
r
0: Non-BPDU Frame
24:22 RUN_EG_TAG
ef o
s
3'b001: Consistent
ele a
R
3'b100: Untagged
t i a l 3'b101: Swap
3'b110: Tagged
n
3'b111: Stack
21 RUN_LKY_VLAN
f i d e a P i
0: Disable
n
1: Enable
20
o
RUN_PRI_HIGH
C n a n REV_20 Force the Highest Priority

0: System default
T e k r B a 1: Assigned to the highest priority queue.
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
19 RUN_MIR REV_20 to Mirror Port
18:16
C o
RUN_PORT_FW
n a n REV_20 TO_CPU Forwarding

T e k r B a 3'b100: System default and CPU port excluded

a o
d i F
Me
are excluded.)
15:12 REV1 Reserved
11 R21_MANG_FR REV_UN as Management Frame
0: Disable
r
10 R21_PAE_FR REV_UN as PAE Frame
f o
se
0: Disable
9 R21_BPDU_FR
e l e a REV_UN as BPDU Frame

0: Non-BPDU Frame
R
8:6 R21_EG_TAG
t i a l REV_UN Egress VLAN Tag Attribution

n
3'b001: Consistent
f i d e a P i
3'b100: Untagged
n
3'b101: Swap
C o n a n 3'b110: Tagged
3'b111: Stack
5
T e k B
R21_LKY_VLAN
r a REV_UN Leaky VLAN Enable

0: Disable
d4
i a F o
R21_PRI_HIGH
1: Enable
REV_UN Force the Highest Priority
Me
0: System default
3 R21_MIR REV_UN to Mirror Port
0: Disable
2:0 R21_PORT_FW REV_UN TO_CPU Forwarding
o r
ef
s
a
ele
i a l R are excluded.)
e n t i
00000038
Bit 31
n f i
PMC
d30
n a P
29 28 27 26
Protocol Match Control
25 24 23 22 21 20 19 18
00000000
17 16
Name
k C o REV0
a n a TYPE3_ TYPE3_
EN VLD
TYPE3_ENCAP REV1
TYPE2_ TYPE2_
EN VLD
TYPE2_ENCAP
i a T e o r B
M e d F
Page 39 of 830
f o r
l e a se MT7531
l R e Lynx1
Type RW
n t i a
RW RW RW RW RW RW RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15
n f i d
14 13
a P i
TYPE1_ TYPE1_
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
C o
REV2
RW
n a n EN
RW
VLD
RW
TYPE1_ENCAP
RW
REV3
RW
Reset
T e
0
k r B
0
a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a
Bit(s)
d
Name
F o Description
Me
31:30 REV0 Reserved
29 TYPE3_EN TYPE 3 Match Enable
28 TYPE3_VLD TYPE 3 Value Valid
27:24 TYPE3_ENCAP Encapsulated Frame Type Value
23:22 REV1 Reserved
20
19:16
TYPE2_VLD
TYPE2_ENCAP
TYPE 2 Value Valid
Encapsulated Frame Type Value
f o r
se
15:14 REV2 Reserved
a
12 TYPE1_VLD
R e l e TYPE 1 Value Valid

0: TYPE 1 Value in register PBG.TYPE1 is "don't care", i.e. it has no effect.
1: TYPE 1 Value in register PBG.TYPE1 is valid.
11:8 TYPE1_ENCAP
t i a l Encapsulated Frame Type Value

Bit0: Ethernet II
i d e n P i
Bit1: RFC_1042
Bit2: IPX Raw 802.3
f
Bit3: 802.2/802.3 Length Encapsulated
7:0 REV3
C o n a n a Reserved
e k B a n
T r
0000003C PBG1 Protocol Based Group ID-1 00000000
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Name TYPE1
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name REV0
Type RW
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a s
ele
31:16 TYPE1 TYPE 1 Value
Ethernet II: Matched with EtherType
i a l R RFC_1042: Matched with SNAP Type

IPX Raw 802.3: "Don't care"
15:0 REV0
e n t i
802.2/802.3 Length Encapsulate: Matched with DSAP[15:8] and SSAP[7:0]
Reserved
n f i d n a P
00000040
Bit
k C
31
o PBG2
a n
30
a 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
i a T e o r B
M e d F
Page 40 of 830
f o r
l e a se MT7531
l R e Lynx1
Name
n t i a TYPE3
e
Type RW
Reset
Bit
0
15
n f i
0
d
14
0
a
13
P i 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
C o n a n TYPE2
a
RW
Reset
T e
0
k r B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) Name
F o Description
Me
r
00000058 PIM1 DSCP Priority Ingress Mapping I 09000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18
f o 17 16
se
Name REV0 PRI_DSCP_09 PRI_DSCP_08 PRI_DSCP_07 PRI_DSCP_06 PRI_DSCP_05
a
Type RO RW RW RW RW RW
Reset
Bit
0
15
0
14
0
13
R e l e
0
12
1
11
0
10
0
9
1
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
l
PRI_DS
Name PRI_DSCP_04 PRI_DSCP_03 PRI_DSCP_02 PRI_DSCP_01 PRI_DSCP_00
a
CP_05
Type
Reset
RW
0 0
e n t iRW
0 0 0
RW
0 0 0
RW
0 0 0
RW
0 0 0
RW
0 0
Bit(s) Name
n f i d a P i Description
31:30
29:27
REV0
C o
PRI_DSCP_09
n a n Reserved
User Priority for Differentiated Services Code Point (DSCP) 0b001_001
26:24
23:21
T k
PRI_DSCP_08
e B
PRI_DSCP_07
r a User Priority for DSCP 0b001_000

User Priority for DSCP 0b000_111
a o
20:18 PRI_DSCP_06 User Priority for DSCP 0b000_110
d i
17:15
F
PRI_DSCP_05 User Priority for DSCP 0b000_101
Me
o r
0000005C
Bit 31
PIM2
30 29 28 27 26
DSCP Priority Ingress Mapping II
25 24 23 22 21 20
a s 19 18
ef12489249
17 16
ele
Name REV0 PRI_DSCP_19 PRI_DSCP_18 PRI_DSCP_17 PRI_DSCP_16 PRI_DSCP_15
R
Reset
Bit
0
15
0
14
t i a l
0
13
1
12
0
11
0
10
1
9
0
8
0
7
1
6
0
5
0
4
1
3
0
2
0
1
0
0
Name
PRI_DS
CP_15
i d e n PRI_DSCP_14
P i
PRI_DSCP_13 PRI_DSCP_12 PRI_DSCP_11 PRI_DSCP_10
f
Type RW RW RW RW RW RW
Reset 1
C o n 0
a n a 0 1 0 0 1 0 0 1 0 0 1 0 0 1
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
31:30 REV0 Reserved
29:27
26:24
PRI_DSCP_19
f
PRI_DSCP_18
n i d a P i User Priority for DSCP 0b010_011

23:21
20:18
C o
PRI_DSCP_17
PRI_DSCP_16
n a n User Priority for DSCP 0b010_001

k a
e B
11:9
i
8:6
d
5:3
a T o r
PRI_DSCP_13
PRI_DSCP_12
F
PRI_DSCP_11
Me
00000060 PIM3 DSCP Priority Ingress Mapping III 1B6DB492

Bit
Name
31
REV0
30 29 28
PRI_DSCP_29
27 26 25
PRI_DSCP_28
24 23 22
PRI_DSCP_27
21 20 19
PRI_DSCP_26
18
f o r17
PRI_DSCP_25
16
se
Reset
Bit
0
15
0
14
0
13
1
12
1
11
0
10
1
9
1
8
0
7
1
6
1
5
e l
0
4
e a 1
3
1
2
0
1
1
0
R
PRI_DS
Name PRI_DSCP_24 PRI_DSCP_23 PRI_DSCP_22 PRI_DSCP_21 PRI_DSCP_20
l
CP_25
Type
Reset
RW
1
n
0
t i a RW
1 1 0
RW
1 0 0
RW
1 0 0
RW
1 0 0
RW
1 0
Bit(s) Name
f i d e a P i Description
31:30
29:27
26:24
C n
REV0
o
PRI_DSCP_29
PRI_DSCP_28
n a n
Reserved
T e
23:21
20:18
k r B a
PRI_DSCP_27
PRI_DSCP_26
ed i a
17:15
14:12
11:9
F o
PRI_DSCP_25
PRI_DSCP_24
PRI_DSCP_23
M 8:6
5:3
2:0
PRI_DSCP_22
PRI_DSCP_21
PRI_DSCP_20
o r
ef
00000064 PIM4 DSCP Priority Ingress Mapping IV 2492491B
Bit
Name
31
REV0
30 29 28
PRI_DSCP_39
27 26 25
PRI_DSCP_38
24 23 22
PRI_DSCP_37
21 20
le a s
19
PRI_DSCP_36
18 17
PRI_DSCP_35
16
e
Reset
Bit
0
15
0
14
i a l R1
13
0
12
0
11
1
10
0
9
0
8
1
7
0
6
0
5
1
4
0
3
0
2
1
1
0
0
Name
PRI_DS
CP_35
e n t PRI_DSCP_34
i
PRI_DSCP_33 PRI_DSCP_32 PRI_DSCP_31 PRI_DSCP_30
d
Reset 0
o n f i 1
n a P 0 0 1 0 0 1 0 0 0 1 1 0 1 1
Bit(s)
31:30
k CName
REV0
a n a Description
Reserved
i a T e o r B
Med F
Page 42 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
26:24
23:21
PRI_DSCP_38
f
PRI_DSCP_37

20:18
17:15
C o
PRI_DSCP_36
PRI_DSCP_35

k a
e B
8:6
i
5:3
d
2:0
a T o r
PRI_DSCP_32
PRI_DSCP_31
F
PRI_DSCP_30
Me 00000068
Bit 31
PIM5
30 29 28 27 26
DSCP Priority Ingress Mapping V
25 24 23 22 21 20 19 18
36B6DB6D
17 16
Name
Type
REV0
RO
PRI_DSCP_49
RW
PRI_DSCP_48
RW
PRI_DSCP_47
RW
PRI_DSCP_46
RW
f o r
PRI_DSCP_45
RW
se
Reset 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0
Bit
Name
15
PRI_DS
14 13
PRI_DSCP_44
e l
12
e a 11 10
PRI_DSCP_43
9 8 7
PRI_DSCP_42
6 5 4
PRI_DSCP_41
3 2 1
PRI_DSCP_40
0
R
CP_45
l
Reset 1 1
n t i a
0 1 1 0 1 1 0 1 1 0 1 1 0 1
Bit(s)
31:30
Name
REV0
Reserved
29:27
26:24
23:21 n
PRI_DSCP_49
o
PRI_DSCP_48
C
PRI_DSCP_47
n a n
20:18
17:15
T e k r B
PRI_DSCP_46
PRI_DSCP_45
a User Priority for DSCP 0b101_110
d i
14:12
11:9
a F o
PRI_DSCP_44
PRI_DSCP_43
Me
o r
ef
0000006C PIM6 DSCP Priority Ingress Mapping VI 3FFF6DB6
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
REV0
RO
PRI_DSCP_59
RW
PRI_DSCP_58
RW
PRI_DSCP_57
RW
le a
RW
s
PRI_DSCP_56 PRI_DSCP_55
RW
Reset
e
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit
Name
PRI_DS
15 14
i a l R
13
PRI_DSCP_54
12 11 10
PRI_DSCP_53
9 8 7
PRI_DSCP_52
6 5 4
PRI_DSCP_51
3 2 1
PRI_DSCP_50
0
t
CP_55
Type
Reset
RW
0
i d e n
1
P
RW
i1 0 1
RW
1 0 1
RW
1 0 1
RW
1 0 1
RW
1 0
Bit(s)
o n
Name
f a n a Description
31:30
29:27
e k CREV0
a
PRI_DSCP_59
B n Reserved
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
23:21
20:18
PRI_DSCP_57
f
PRI_DSCP_56

17:15
14:12
C o
PRI_DSCP_55
PRI_DSCP_54

k a
e B
5:3
d i
2:0
a T o r
PRI_DSCP_51
PRI_DSCP_50
F
Me 00000070
Bit 31
PIM7
30 29 28 27 26
DSCP Priority Ingress Mapping VII
25 24 23 22 21 20 19 18
00000FFF
17 16
r
Name REV0
Type
Reset
RO
f o
se
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
REV0
RO
PRI_DSCP_63
RW
PRI_DSCP_62
RW
e l
RW
e a
PRI_DSCP_61 PRI_DSCP_60
RW
Reset 0 0
i
0
a l R 0 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s)
31:12
Name
REV0
e n t i
Description
Reserved
11:9
8:6
f i
PRI_DSCP_63
PRI_DSCP_62
n d n a P
o
2:0
k C
PRI_DSCP_60
a n a User Priority for DSCP 0b111_100
i a T
00000074 e o r B
ATA1 Address Table Access I 00000000
M e d Bit
Name
Type
Reset 0
F
31 30
0
29
0
28
0
BYTE_0
RW
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
BYTE_1
RW
19
0
18
0
17
0
16
0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BYTE_2 BYTE_3
o r
ef
Type RW RW
Reset
s
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ele a
R
31:24 BYTE_0 MAC Address[47:40] / Destination IP(DIP) Address [31:24]
23:16
15:8
7:0
BYTE_1
BYTE_2
BYTE_3
t i a l MAC Address[39:32] / Destination IP(DIP) Address [23:16]

MAC Address[31:24] / Destination IP(DIP) Address [15:8]
i d e n P i
00000078
o n f
ATA2
a n a Address Table Access II 00000000
C n
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
T e k r B a BYTE_0 BYTE_1
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Type
n t i a RW RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15
n
14
f i d 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
n
BYTE_2 BYTE_3
Type
Reset 0
k C o 0
a n a 0 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
a
Bit(s)
i T e
Name
o r B Description
Me d
31:24
23:16
15:8 F
BYTE_0
BYTE_1
BYTE_2
MAC Address[15:8] / Source IP(SIP) Address [31:24]
MAC Address[7:0] / Source IP(SIP) Address [23:16]
SIP Address [15: 8] or
bit[15]: IVL
bit[14:12]: Filter ID[2:0]
bit[11:8]: CVID[11: 8]
r
NOTE: When IVL is reset, MAC[47:0] and FID[2:0] will be used to
read/write the address table. When IVL is set, MAC[47:0] and CVID[11:0]
will be used to read/write the address table.
f o
se
7:0 BYTE_3 SIP Address[7:0] or CVID[7:0]
e l e a
0000007C
Bit 31
ATWD
30 29
i a l R 28 27 26
Address Table Write Data
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
e n t i
WDATA
RW
Reset
Bit
0
15
n
0
f
14
i d 0
13
n a P
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
k C o a n a
WDATA
RW
e B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s)
T Name
F o r Description
Me
31:0 WDATA Table Write Data
00000080 ATC Address Table Control 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name REV0
COL_A
CC
ADDR
ef o
Type
Reset 0
RO
0 0
RO
0 0 0 0 0 0 0
RO
0 0
le a s
0 0 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BUSY
ND
l
HIT NVLD
i a R
SRCH_E SRCH_ ADDR_I
AC_MAT REV1 AC_SAT
AC_CA
E
AC_CMD
t
Type W1S RO RO RO RW RW RW RW RW
Reset 0
i d
0
e n 0
P i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:29
o n
Name
REV0
f a n a Description
Reserved
28
e k CCOL_ACC
B a n
Access Target is Collision Pool
Read/Write command is applied to collision pool
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Address Table
27:16 ADDR
n f i d a P i 1: Collision Pool
Address Table Access Index
C o n a n The actual address table access index which is calculated from a 48-bit
MAC address, a 32-bit DIP, and a SIP address. (for debugging purposes)
k a
15 BUSY Address Table Is Busy
i a T e o r B SW can set this bit to 1 only if this bit is reset. After ATWD registers are
written and this bit is set, this chip will perform the corresponding
F
function according to AC_CMD, AC_SAT, and AC_MAT included in this
Me d
14
13
SRCH_END
SRCH_HIT
register.
Linear Search End
The linear search has reached the index end of the address table.
For Search Command Only (AC_CMD=3'b100 or 3'b101)
Linear Search Hit
The linear search has find the target based on AC_MAT and return the
data on TSRA1,2 and ATRD. If this register is not TRUE(1) after search
command completed, that means nothing found and data on TSRA1,2
f o r
se
and ATRD are invalid.
For Search Command Only (AC_CMD=3'b100 or 3'b101)
12 ADDR_INVLD
e l e a Address Entry is not Valid

Read Operations: The specified entry is not valid for read or removal
R
access. Read Data returned on TSRA1, TSRA2 and ATRD are invalid.
l
Write Operations: The specified entry cannot be modified or added for
n t i a write access.
For Single Entry Read/Write Only (AC_CMD=3'b000 or 3'b001).
e
11:8 AC_MAT Address Table Multiple Access Target
n f i d a P i Whenever MATC register is written and bit.15 is set, this chip will
perform the corresponding function on the Address table based on
n
AC_CMD bits.
k C o a n a 4'b0000: All MAC address entries

4'b0001: All DIP/GA address entries
i a T e o r B
4'b0010: All SIP address entries
4'b0011: All valid address entry
F
4'b0100: All non-static MAC address entries.
Me d 4'b0101: All non-static DIP address entries.

4'b0110: All static MAC address entries
4'b0111: All static DIP address entries
4'b1000: All relative SIP address entries based on the specific DIP from
ATA2 register.
r
4'b1001: All relative SIP address entries based on the specific SIP from
ATA2 register.
4'b1010: All MAC Address entries with the customer VID specified in
ef o
s
ATA2.CVID[11:0]
ATA2.FID[2:0]
ele a
4'b1010: All MAC address entries with the Filter ID specified in
4'b1100: All MAC Address entries with the source ports specified in
i a l R ATA1.PORT[7:0]
4'b1101 to 4'b1111: Reserved
t
7:6 REV1 Reserved
5:4 AC_SAT
i d e n P i
Address Table Single Access Target
Whenever MATC register is written and bit.31 is set, this chip will
f
perform the corresponding function on the Address table based on FUNC
C o n a n a bits.
2'b00: Specified MAC address entry
e k B a n 2'b01: Specified DIP address entry

2'b10: Specified SIP address entry
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
2'b11: Specified address entry(read only)
3 AC_CAE
n f i d a P i Collision Pool Access Enable

For Read and Write command(single entry), read/write collision pool
C o n a n while address table hash collision.

For Clean and Search command, access target is collision pool (not to
k a
access address table)
i a T e o r B
If Collision Pool is disabled, this register is invalid.
0: Disable
F
1: Enable
Me d
2:0 AC_CMD Address Table Access Command
3'b000: Read command (single entry)
3'b001: Write command (single entry)
NOTE: Supports modify, add, and remove
3'b010: Clean command (multiple entries)
r
3'b011: Reserved
3'b100: Start Search command (reset to 1st entry)
f o
se
3'b101: Next Search command (next entry)
3'b110 to 3'b111: Reserved
e l e a
00000084
Bit 31
TSRA1
30 29
i a l R28 27 26
Table Search Read Address I
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
e n t i
BYTE_0 BYTE_1
d
RO RO
Reset
Bit
0
15
o n
0
f
14
i 0
n
13
a P 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
k C a n a BYTE_2
RO
BYTE_3
RO
Reset
i a T e0
o r
0
B 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit(s)
31:24
Name
F
BYTE_0
Description
The data on this register is invalid if the following is true:

Read/Write Operation: ADDR_INVLD=1 after the operation finished
Search Operation: SRCH_HIT=0 after the operation finished
o r
a s
ef
ele
i a l R The data on this register is invalid if the following is true:

7:0 BYTE_3
e n t i
n f i d n a P The data on this register is invalid if the following is true:
k C o a n a
i a T e o r B
M e d F
Page 47 of 830
f o r
l e a se MT7531
l R e Lynx1
n t i a
00000088
Bit 31
TSRA2
f
30
i d e 29
a P i28 27 26
Table Search Read Address II
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
C o n n a n
BYTE_0
RO
BYTE_1
RO
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
i a T e15
o r B
14 13 12
BYTE_2
11 10 9 8 7 6 5 4
BYTE_3
3 2 1 0
d
Type
F
RO RO
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:24 BYTE_0 MAC Address[15:8] / Source IP(SIP) Address [31:24]

f o r
se
a
23:16 BYTE_1 MAC Address[7:0] / Source IP(SIP) Address [23:16]
R e l e The data on this register is invalid if the following is true:

15:8 BYTE_2
t i a l Search Operation: SRCH_HIT=0 after the operation finished

SIP Address [15: 8] or
i d e n P i
bit[15]: IVL
bit[14:12]: Filter ID[2:0]
bit[11:8]: CVID[11: 8]
o n f a n a NOTE: When IVL is reset, MAC[47:0] and FID[2:0] will be used to

read/write the address table. When IVL is set, MAC[47:0] and CVID[11:0]
e k C B a n
will be used to read/write the address table.
d i a T F o r Read/Write Operation: ADDR_INVLD=1 after the operation finished

Me
7:0 BYTE_3 SIP Address[7:0] or CVID[7:0]

o r
0000008C
Bit 31
ATRD
30 29 28 27 26
Address Table Read Data
25 24 23 22 21 20
a s 19 18
ef00000000
17 16
ele
Name RDATA
R
Type RO
Reset
Bit
0
15
0
14
t
0
i
13
a l 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
i d e n P i
RDATA
RO
Reset 0
o n f0
a n
0
a
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
e k C
Name
RDATA
B a n Description
Table Read Data
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i The data on this register is invalid if the following is true:
n
C o n a n Search Operation: SRCH_HIT=0 after the operation finished
00000090
T e k r B
VTCR a VLAN Table Control 00000000
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
IDX_IN
Name BUSY REV0
VLD
Type W1S RO RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
FUNC
RW
VID
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
R
31 BUSY VLAN Table Is Busy
t i a l SW can set this bit to 1 only if this bit is reset. After the VTCR register is
written and this bit is set, this chip will perform the corresponding
n
function on the VLAN table based on FUNC bits.
e
30:17 REV0 Reserved
16 IDX_INVLD
n f i d a P i Entry is not Valid

This index for the access control is out of the valid index.
15:12 FUNC
C o n a n Access Control Function

Whenever VTCR register is written and bit.31 is set, this chip will perform
k a
the corresponding function on the VLAN table based on FUNC bits.
e B
4'b0000: Read the specified VID Entry from VAWD# register based on VID
d i a T F o r bits
4'b0001: Write the specified VID Entry though VAWD# register based on
VID bits.
Me
4'b0010: Make the specified VID entry invalid based on VID bits.
4'b0011: Make the specified VID entry valid based on VID bits.
4'b0100: Read the specified ACL Table entry.
4'b0101: Write the specified ACL Table entry.
r
4'b0110: Read the specified trTCM Meter Table.
4'b0111: Write the specified trTCM Meter Table.
4'b1000: Read the specified ACL Mask entry.
ef o
s
4'b1001: Write the specified ACL Mask entry.
4'b1010: Read the specified ACL Rule Control entry.
ele
4'b1011: Write the specified ACL Rule Control entry.
a
R
4'b1100: Read the specified ACL Rate Control entry.
t i a l 4'b1101: Write the specified ACL Rate Control entry.

4'b1110: Reserved
n
4'b1111: Reserved
11:0 VID
f i d e a P i
1. VLAN ID Number: 0x0 to 0x1F (16)
2. ACL table index: 0x0 to 0xFF (256)
n
3. ACL mask control: 0x0 to 0x7F (128)
C o n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
00000094 VAWD1
n t i a VLAN and ACL Write Data I 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
n f i d a P i WDATA
n
RW
Reset
Bit
0
15
k C o 0
14
a n a
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
e B
WDATA
Type
d i
Reset
a T 0
F o r
0 0 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Me Bit(s)
31:0
Name
WDATA
Description
VLAN Table Write Data I
00000098 VAWD2 VLAN and ACL Write Data II
f o r
00000000
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
a
WDATA
Type
Reset 0 0 0
R
0
e l e 0 0 0 0
RW
0 0 0 0 0 0 0 0
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
n t i a WDATA
RW
Reset 0 0
f i d e 0
a P i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
C
WDATA
o n n a n Description
VLAN Table Write Data II
T e k r B a
d i a
0000009C
F oTRTCM Two Rate Three Color Mark 00000000
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRTCM
Name REV0
_EN
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r 0
ef
Name REV0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0
a s 0 0 0 0
Bit(s)
31
Name
TRTCM_EN
l R
Description
Two Rate Three Color Marker (trTCM) Enable
ele
n t i a When this bit is enabled, the meter table will be updated based on Peak
Information Rate (PIR) and Committed Information Rate (CIR). The color
e
marker will also be enabled when ACL is hit.
1: Enable
30:0 REV0
C o n a n Reserved
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
000000A0 AAC
n t i a Address Age Control 00095001
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
n f i d a P i AGE_DI
S
AGE_CNT
Type
Reset
C o n a n RW
0 1 0
RW
0 1
Bit
Name
T e k
15
r B
14
a
AGE_CNT
13 12 11 10 9 8 7 6
AGE_UNIT
5 4 3 2 1 0
Type
d i a F o RW RW
Me
Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1

20 AGE_DIS Address Table Aging Disable
Disable or pause MAC address aging.
19:12 AGE_CNT Address Table Age Count
f
This age count is recorded in the age timer field of the MAC address table
o r
se
when a new source address is received and the table entry is ready to
refresh the timer. The applied age timer is equal to (AGE_CNT+1)
11:0 AGE_UNIT
e l e a *(AGE_UNIT+1) seconds.
Address Table Age Unit
R
The applied aging unit is equal to (AGE_UNIT+1) seconds.
t i a l
000000A4
Bit 31
DHCP
30
i d e n 29
P i 28 27 26
DHCP Control
25 24 23 22 21 20 19 18
08100810
17 16
Name
o n f a
REV0
n a DHCPv DHCPv DHCPv

6_MAN 6_PAE_ 6_BPD DHCPv6_EG_TAG
DHCPv DHCPv
6_LKY_ 6_PRI_
DHCPv
DHCPv6_PORT_FW
C
6_MIR
n
G_FR FR U_FR VLAN HIGH
Type
Reset
T e0
k r B
0
aRO
0 0
RW
1
RW
0
RW
0 0
RW
0 0
RW
0
RW
1
RW
0 0
RW
0 0
i a o
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me d
Name
Type
Reset 0
F 0
REV1
RW
0 0
DHCPv DHCPv DHCPv
4_MAN 4_PAE_ 4_BPD
G_FR
RW
1
FR U_FR
RW
0
RW
0
DHCPv4_EG_TAG
0
RW
0 0
DHCPv DHCPv
4_LKY_ 4_PRI_
VLAN HIGH
RW
0
RW
1
DHCPv
4_MIR
RW
0
DHCPv4_PORT_FW
0
RW
0 0
o r
ef
31:28 REV0 Reserved
s
27 DHCPv6_MANG_FR DHCPv6 Discovery/Request as Management Frame
26 DHCPv6_PAE_FR
0: Disable
DHCPv6 Discovery/Request as PAE Frame
ele a
i a l R 0: Disable
25 DHCPv6_BPDU_FR
e n t i
DHCPv6 Discovery/Request as BPDU Frame
0: Non-BPDU Frame
24:22
f i d
DHCPv6_EG_TAG
n n a P
DHCPv6 Discovery/Request Egress VLAN Tag Attribution
o
k C a n a 3'b001: Consistent
i a T e o r B
M e d F
Page 51 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
3'b100: Untagged
n f i d a P i 3'b101: Swap
3'b110: Tagged
21
C o
DHCPv6_LKY_VLAN
n a n 3'b111: Stack
DHCPv6 Discovery/Request Leaky VLAN Enable
1: Enable
a o
20 DHCPv6_PRI_HIGH DHCPv6 Discovery/Request Force the Highest Priority
d i F 0: System default
Me
19 DHCPv6_MIR DHCPv6 Discovery/Request to Mirror Port
0: Disable
18:16 DHCPv6_PORT_FW DHCPv6 Discovery/Request TO_CPU Forwarding
f o r
se
a
R e l e the ingress port is the CPU port, then the system default and CPU port
are excluded.)
15:12
11
REV1
DHCPv4_MANG_FR
t i a l Reserved
DHCPv4 Discovery/Request as Management Frame
n
0: Disable
10
f i
DHCPv4_PAE_FR
d e a P i
DHCPv4 Discovery/Request as PAE Frame
n
0: Disable
C o
DHCPv4_BPDU_FR
n a n 1: Regarded as PAE frame

DHCPv4 Discovery/Request as BPDU Frame
T e k r B a 0: Non-BPDU Frame
d i
8:6
a o
DHCPv4_EG_TAG
F
DHCPv4 Discovery/Request Egress VLAN Tag Attribution
Me
3'b001: Consistent
3'b100: Untagged
3'b101: Swap
3'b110: Tagged
3'b111: Stack
o r
ef
5 DHCPv4_LKY_VLAN DHCPv4 Discovery/Request Leaky VLAN Enable
s
0: Disable
4 DHCPv4_PRI_HIGH
1: Enable
DHCPv4 Discovery/Request Force the Highest Priority
0: System default
ele a
3 DHCPv4_MIR
i a l R 1: Assigned to the highest priority queue.

DHCPv4 Discovery/Request to Mirror Port
e n t i
0: Disable
2:0
n f i d
DHCPv4_PORT_FW
n a P
DHCPv4 Discovery/Request TO_CPU Forwarding
o
k C a n a 3'b101: System default and CPU port included
i a T e o r B
M e d F
Page 52 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
are excluded.)
C o n a n 3'b111: Frame Dropped
000000A8
T e k r
LCP
B a PPPoE LCP Control 08100000
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
PPP_LC PPP_LC PPP_LC PPP_LC PPP_LC
PPP_LC
Name REV0 P_MAN P_PAE_ P_BPD PPP_LCP_EG_TAG P_LKY_ P_PRI_ PPP_LCP_PORT_FW
P_MIR
G_FR FR U_FR VLAN HIGH
Type RW RW RW RW RW RW RW RW RW
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
Bit
Name
15 14 13 12 11 10 9 8
REV1
7 6 5 4 3 2
f o
1
r 0
se
Type RW
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
R e l e Description
l
31:28 REV0 Reserved
27 PPP_LCP_MANG_FR
n t i a PPPoE Session LCP as Management Frame

0: Disable
e
26
i
PPP_LCP_PAE_FR
n f d a P i PPPoE Session LCP as PAE Frame

0: Disable
25
C o
PPP_LCP_BPDU_FR
n a n 1: Regarded as PAE frame

PPPoE Session LCP as BPDU Frame
T e k r B a 0: Non-BPDU Frame
a o
24:22 PPP_LCP_EG_TAG PPPoE Session LCP Egress VLAN Tag Attribution
d i F
Me
3'b001: Consistent
3'b100: Untagged
3'b101: Swap
3'b110: Tagged
3'b111: Stack
o r
ef
21 PPP_LCP_LKY_VLAN PPPoE Session LCP Leaky VLAN Enable
0: Disable
1: Enable
a s
ele
20 PPP_LCP_PRI_HIGH PPPoE Session LCP Force the Highest Priority
0: System default
19 PPP_LCP_MIR
i a l R 1: Assigned to the highest priority queue.

PPPoE Session LCP to Mirror Port
t
0: Disable
18:16
d e
PPP_LCP_PORT_FW
i n P i
PPPoE Session LCP TO_CPU Forwarding
f
C o n a n a 3'b100: System default and CPU port excluded

e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
are excluded.)
15:0 REV1
C o n a n 3'b111: Frame Dropped

Reserved
T e k r B a
d i a
000000AC
F oMHS MAC Table Hash Seed FFFFFFFF
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CRC_SEED
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
CRC_SEED
RW
f o r
se
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s) Name
e l e a Description
R
31:0 CRC_SEED MAC Table Hash CRC16/CRC32 Seed
t i a l CRC32 : bit [31:0]

CRC16 : bit [15:0]
i d e n P i
000000B0
Bit 31
o n f
CPGC
30
a n
29
a 28 27 26
Collision Pool Global Control
25 24 23 22 21 20 19 18
00000017
17 16
Name
Type
e k C B a n
Reset
d i
Bit
a T 15
F o r14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
COL_B COL_RS COL_CL COL_E
Name
USY T_N K_EN N
Type RO RW RW RW
Reset 0 1 1 1
o r
ef
3 COL_BUSY Collision Pool is Busy
s
0: IDLE
2 COL_RST_N
1: BUSY
Collision Pool Soft Reset
ele a
Active Low. Before reset collision pool, it must be disabled and is not
i a l R busy
0: Reset activated
1 COL_CLK_EN
e n t i
1: Not activated
Collision Pool Clock Enable
n f i d n a P
Before enable/disable collision pool clock, collision pool must be disabled
and is not busy
o
0: Disable
k C
COL_EN
a n a 1: Enable
Collision Pool Enable
i a T e o r B
M e d F
Page 54 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
Do NOT enable collision pool while collision pool soft reset activated
1: Enable
C o n a n
000000B4
T e k B
CPMONC
r a Collision Pool Monitor Control 00070020
a o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d i F COL_F
Me
COL_C
Name ULL_CN COL_CNT_CTRL
NT_CLR
T_CLR
Type W1S W1S RW
Reset 0 0 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name COL_USED_CNT
COL_E COL_F
COL_F
ULL_CN
COL_C
f o r
COL_MON_SEL
se
MPTY ULL NT_EN
T_EN
a
Type RO RO RO RW RW RW
Reset 0 0
R
0 0 0 0 0 1
e l0
e 0 0 0 0
Bit(s)
20
Name
COL_FULL_CNT_CLR
t i a l Description
Full and Collision Counter Reset
i d e n P i
Return to 0 automatically after reset done
0: Reset Released
f
1: Reset Active
19
C o n
COL_CNT_CLR
a n a Address Table Collision Counter Reset

Return to 0 automatically after reset done
e k B a n 0: Reset Released
1: Reset Active
T r
18:16 COL_CNT_CTRL Collision Type Bit Map for Collision Counters
e d i a F o The type of collision for counters. To enable the specific type, set
corresponding bits to 1.
BIT 0: DIP Table Collision
M 14:8
5
COL_USED_CNT
COL_EMPTY
BIT 1: SA Learning Collision
BIT 2: CSR Path Write Access Collision
Collision Pool used entry counter
Collision Pool is empty
0: Not empty
o r
ef
1: Empty
4 COL_FULL Collision Pool is full
0: Not full
a s
ele
1: Full
3 COL_FULL_CNT_EN Full and Collision Counter Enable
i a l R 0: Disable
1: Enable
t
2 COL_CNT_EN Address Table Collision Counter Enable
i d e n P i
0: Disable
1: Enable
f
1:0 COL_MON_SEL Collision Pool Entry Status Monitor Selection
C o n a n a Select which type of entries are shown in Entry Status Monitor CPMOND1
and CPMOND2
e k B a n 2'b00: Empty entry

2'b01: Dynamic entry
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
2'b10: Reserved entry
n f i d a P i 2'b11: Static entry
C o n a n
k a
000000B8 CPMOND1 Collision Pool Entry Status Monitor 1 FFFFFFFF
Bit
Name
i a T e31
o r B
30 29 28 27 26 25 24
ENTRY
23 22 21 20 19 18 17 16
Me d
Type
Reset
Bit
Name
1
15
F 1
14
1
13
1
12
1
11
1
10
1
9
1
8
RO
ENTRY
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Type RO
r
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
f o
se
a
31:0 ENTRY Collision Pool Entry Status Monitor
R e l e Bit map of entry 31~0

0: Not hit selected status
1: Hit selected status
t i a l
000000BC CPMOND2
i d e n P i
Collision Pool Entry Status Monitor 2 FFFFFFFF
f
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
C o n a n a ENTRY
n
RO
Reset
k a
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit
Name
i a T e15
o r B
14 13 12 11 10 9 8
ENTRY
7 6 5 4 3 2 1 0
Me d
Type
Reset
Bit(s)
1
Name
F 1 1 1 1 1 1
Description
1
RO
1 1 1 1 1 1 1 1
31:0 ENTRY Collision Pool Entry Status Monitor
r
Bit map of entry 63~32
0: Not hit selected status
1: Hit selected status
ef o
a s
000000C0
Bit 31
CPSTSC
30 29
l R 28 27 26
Collision Pool Status Counter
25 24 23 22 21
ele
20 19 18
00000000
17 16
Name
Type
n t i a COL_FULL_CNT
RO
Reset
Bit
0
15
f
0
i
14
d e 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
C o n n a n
COL_CNT
RO
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a T e o r B
M e d F
Page 56 of 830
f o r
l e a se MT7531
l R e Lynx1
n t i a
Bit(s)
31:16
Name
COL_FULL_CNT
f i d e a P i
Description
Full and Collision Counter
n
Address Table Collision when Collision Pool is Full
15:0
C o
COL_CNT
n a n Counter disabled automatically when Collision Pool disabled

Address Table Collision Counter
T e k r B a
i a
000000C4
d F o
AISR_EXT1 ACL Extension Interrupt Status I 00000000
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name ACL_ISR_EXT
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
ACL_ISR_EXT
W1C
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
31:0 ACL_ISR_EXT
i a l R ACL Interrupt Status for entry 32~63
000000C8 AISR_EXT2
e n t i
ACL Extension Interrupt Status II 00000000
Bit
Name
31 30
n f i d 29
n a P 28 27 26 25 24
ACL_ISR_EXT
23 22 21 20 19 18 17 16
Type
Reset 0
k C o 0
a n a 0 0 0 0 0 0
W1C
0 0 0 0 0 0 0 0
Bit
Name
i a T e15
o
14
r B 13 12 11 10 9 8
ACL_ISR_EXT
7 6 5 4 3 2 1 0
Me d
Type
Reset
Bit(s)
0
Name
F 0 0 0 0 0 0
Description
0
W1C
0 0 0 0 0 0 0 0
31:0 ACL_ISR_EXT ACL Interrupt Status for entry 64~95
o r
000000CC
Bit 31
AISR_EXT3
30 29 28 27 26
ACL Extension Interrupt Status III
25 24 23 22 21 20
a s 19 18
ef00000000
17 16
ele
Name ACL_ISR_EXT
R
Type W1C
Reset
Bit
0
15 14
0
t
0
i
13
a l 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
i d e n P i
ACL_ISR_EXT
W1C
Reset 0
o n f 0
a n
0
a
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
e k C
Name
ACL_ISR_EXT
B a n Description
ACL Interrupt Status for entry 96~127
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
000000D0
Bit 31
C o n
MISR
30
n a
29
n 28 27 26
MLDv2 Interrupt Status
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
T e k r B a MLDv2_ISR
W1C
d
Bit
i
Reset
a 0
15
F o
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Me
Name MLDv2_ISR
Type W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
MLDv2_ISR
Description
MLDv2 Interrupt Status for entry 0~31
f o r
se
0: Not hit
a
1: Hit
R e l e
000000D4
Bit 31
MISR_EXT1
30 29
t i a l 28 27 26
MLDv2 Extension Interrupt Status I
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
i d e n P i
MLDv2_ISR
W1C
Reset
Bit
0
15
o
0
n
14
f 0
13
a n a
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
e k C B a n
MLDv2_ISR
W1C
T r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me
31:0 MLDv2_ISR MLDv2 Interrupt Status for entry 32~63
0: Not hit
1: Hit
o r
ef
000000E0 VAWD3 ACL Write Data III 00000000
s
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
WDATA
RW
ele a
Reset
Bit
0
15
0
14
i
0
a
13
l R 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
t
WDATA
Type
Reset 0
i
0
d e n 0
P i 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
o n
Name f a n a Description
31:0
e k CWDATA
B a n ACL Mask Table Write Data III
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
000000E4
Bit 31
C o n
VAWD4
30
n a
29
n 28 27 26
ACL Write Data IV
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
T e k r B a WDATA
RW
d
Bit
i
Reset
a 0
15
F o
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Me
Name WDATA
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
WDATA
Description
ACL Mask Table Write Data IV
f o r
l e a se
e
000000E8 VAWD5 ACL Write Data V 00000000
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
t i a l WDATA
RW
Reset
Bit
0
15
0
14
i d e n 0
13
P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
o n f a n a WDATA
RW
Reset
e k
0
C 0
B a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
31:0
T
Bit(s) Name
F o
WDATA
r Description
ACL Mask Table Write Data V
M e000000EC
Bit 31
VAWD6
30 29 28 27 26
ACL Write Data VI
25 24 23 22 21 20 19 18
00000000
17 16
r
Name WDATA
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
a s 3 2 1 0
ele
Name WDATA
Type RW
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
WDATA
e n t i
Description
ACL Mask Table Write Data VI
n f i d n a P
000000F0
Bit
k C
31 o VAWD7
30
a n a 29 28 27 26
ACL Write Data VII
25 24 23 22 21 20 19 18
00000000
17 16
i a T e o r B
M e d F
Page 59 of 830
f o r
l e a se MT7531
l R e Lynx1
Name
n t i a WDATA
e
Type RW
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
C o n a n WDATA
a
RW
Reset
T e
0
k 0
r B
0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) Name
F o Description
Me
31:0 WDATA ACL Mask Table Write Data VII
000000F4 VAWD8 ACL Write Data VIII 00000000

Bit
Name
31 30 29 28 27 26 25 24
WDATA
23 22 21 20 19 18
f
17
o r 16
se
Type RW
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
R e l e 11 10 9 8
WDATA
7 6 5 4 3 2 1 0
l
Type RW
Reset 0 0
n
0
t i a 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:0
Name
WDATA
ACL Mask Table Write Data VIII
C o n n a n
00000100
Bit
T e k
31
PTC
r
30
B a 29 28 27 26
Port Trunking Control
25 24 23 22 21 20 19 18
0000FE00
17 16
Name
d i a F o
Me
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name INFO_SEL BUSY
r
Type RW RO
Reset 1 1 1 1 1 1 1
ef
0
o
a s
ele
15:9 INFO_SEL Information Control Bit Map
The information used to assign conversations to ports. To apply the
i a l R information, set corresponding bits to 1.

BIT 0: Source Port
t
BIT 1: MAC SA
i d e n P i
BIT 2: MAC DA
BIT 3: IPv4/IPv6 SIP
o n f a n a
BIT 4: IPv4/IPv6 DIP
BIT 5: TCP/UDP SPORT
C n
BIT 6: TCP/UDP DPORT
1
T e k
BUSY
r B a Busy
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: IDLE
n f i d a P i 1: BUSY
C o n a n
k a
00000104 PTHS Port Trunking Algorithm Seed 0000FFFF
Bit
Name
i a T e31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me d
Type
Reset
Bit
Name
15
F 14 13 12 11 10 9 8
SEED
7 6 5 4 3 2 1 0
Type RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1
f o
1
r 1
se
15:0 SEED
e l e a Seed
00000108 PTGC0
i a l R Port Trunking Group Control 0 00001012

Bit
Name
31 30
e n t
29
i
28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
n f i d n a P
Bit
Name
15
k C o 14
a n a13
GRP_PORT1
12 11 10 9
GRP_PORT0
8 7 6
ACL_T
5
SA_LRN_PORT
4 3 2 1
LINK_D
EN
0
e B
NK WN
Type
i
Reset
d a T F o r 0
RW
0 1 0
RW
0 0
RW
0 0
RW
1
RO
1
RW
0
Me Bit(s)
14:12
10:8
Name
GRP_PORT1
GRP_PORT0
Description
Trunking Port 1
Set the trunking port of this group
Trunking Port 0
o r
ef
6 ACL_TNK ACL Destination Port Trunking
Enable Port Trunking for ACL forced destination port if the destination
port is trunking port.
a s
ele
0: Disable
1: Enable
5:4 SA_LRN_PORT
i a l R Port Trunking Source MAC Address Learning Port

Select the source port for MAC SA Learning if ingress port is in this
trunking group.
e n t i
2'b00: Ingress Port
2'b01: GRP_PORT0
n f i d n a P 2'b10: GRP_PORT1
2'b11: Reserved
1
k C o
LINK_DWN
a n a
Port Trunking Group Link Down
Link down when all trunking ports link down
Link up when one or more trunking ports link up
i a T e o r B
M e d F
Page 61 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Link Up
0 EN
n f i d a P i 1: Link Down
Port Trunking Group Enable
C o n a n Enable/Disable this group

0: Disable
T e k r B a 1: Enable
d i a F o
Me
0000010C PTGC1 Port Trunking Group Control 1 00004312
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
r
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o1 0
se
ACL_T LINK_D
Name GRP_PORT1 GRP_PORT0 SA_LRN_PORT EN
NK WN
Type
Reset 1
RW
0 0 0
RW
1 1
RW
0 0
RW
e l1
e a RO
1
RW
0
Bit(s) Name
i a l R Description
14:12 GRP_PORT1
e n t i
Trunking Port 1
d
10:8 GRP_PORT0 Trunking Port 0
n
ACL_TNK
o f i n a P Set the trunking port of this group

ACL Destination Port Trunking
k C a n a Enable Port Trunking for ACL forced destination port if the destination
e B
0: Disable
d i a
5:4
T o r
SA_LRN_PORT
F
1: Enable
Port Trunking Source MAC Address Learning Port
M e trunking group.
2'b00: Ingress Port
2'b01: GRP_PORT0
2'b10: GRP_PORT1
2'b11: Reserved
1 LINK_DWN Port Trunking Group Link Down
o r
ef
Link up when one or more trunking ports link up
0: Link Up
a s
ele
1: Link Down
0 EN Port Trunking Group Enable
i a l R Enable/Disable this group

0: Disable
t
1: Enable
i d e n P i
00000110
o n f
PTGC2
a n a Port Trunking Group Control 2 00006512
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Type
n t i a
Reset
Bit 15 14
f i d e 13
a P i12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
C o n n a n
GRP_PORT1 GRP_PORT0
ACL_T
NK
SA_LRN_PORT
LINK_D
WN
EN
a
RW RW RW RW RO RW
Reset
T e k r B
1 1 0 1 0 1 0 0 1 1 0
d i a
Bit(s) Name
F o Description
Me
6 ACL_TNK ACL Destination Port Trunking
Enable Port Trunking for ACL forced destination port if the destination
f o r
se
0: Disable
1: Enable
5:4 SA_LRN_PORT
e l e a Port Trunking Source MAC Address Learning Port

R
trunking group.
l
2'b00: Ingress Port
n t i a 2'b01: GRP_PORT0
2'b10: GRP_PORT1
1 LINK_DWN
f i d e a P i
2'b11: Reserved
Port Trunking Group Link Down
n
C o n a n Link up when one or more trunking ports link up

0: Link Up
T e
EN
k r B a 1: Link Down
Port Trunking Group Enable
a o
Enable/Disable this group
d i F
0: Disable
Me
1: Enable
00000114 PTGSC0 Port Trunking Group Security Control 0 0000FFF8

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
Name
s
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5
ele
4
a 3 2 1 0
R
SA_CN
Name MAX_SA_CNT
l
T_EN
Type
Reset 1 1
n t i
1
a 1 1 1
RW
1 1 1 1 1 1 1
RW
0
Bit(s) Name
15:3
C o n
MAX_SA_CNT
n a n SA Allowable Learning Number

Maximum number of SA learned addresses for this trunking group when
k a
SA_CNT_EN is set.
i a T e o r B
M e d F
Page 63 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0 SA_CNT_EN Enables the learned source MAC Address counter of this group
1: Enable
C o n a n
00000118
T e k B
PTGSC1
r a Port Trunking Group Security Control 1 0000FFF8
a o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d
Name
i F
Me
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SA_CN
Name MAX_SA_CNT
r
T_EN
Type RW
f o RW
se
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Bit(s)
15:3
Name
MAX_SA_CNT
e l e a Description
SA Allowable Learning Number
i a l R Maximum number of SA learned addresses for this trunking group when

SA_CNT_EN is set.
0 SA_CNT_EN
e n t i
Enables the learned source MAC Address counter of this group
0: Disable
d
1: Enable
o n f i n a P
0000011C
k C PTGSC2
a n a Port Trunking Group Security Control 2 0000FFF8
e B
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
d i
Type
a T F o r
Me
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SA_CN
Name MAX_SA_CNT
T_EN
r
Type RW RW
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1
ef o 0
a s
ele
15:3 MAX_SA_CNT SA Allowable Learning Number
Maximum number of SA learned addresses for this trunking group when
0 SA_CNT_EN
i a l R SA_CNT_EN is set.
Enables the learned source MAC Address counter of this group
t
0: Disable
n
1: Enable
f i d e a P i
00000120
Bit
C
31
o n
SPTC0
30
n a n
29 28 27 26
Port Trunking Table Control
25 24 23 22 21 20 19 18
84F0012C
17 16
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Name TBL1_GRP
n t i a TBL1_E
TBL0_GRP
TBL0_E
INFO_SEL AGE_CNT
e
N N
Type
Reset 1
RW
n f0
i d a P i RW
0 0
RW
1
RW
0 1 1
RW
1 1 0 0
RW
0 0
Bit
Name
15
C o 14
n a n13 12 11 10 9 8
AGE_CNT
7 6 5 4 3 2 1 0
Type
Reset
T e0
k r B0
a 0 0 0 0 0 1
RW
0 0 1 0 1 1 0 0
d i a F o
Me
31:30 TBL1_GRP Trunking Table 1 Group Selection
Select trunking group to be serviced
2'b00: Group 0
2'b01: Group 1
2'b10: Group 2
2'b11: Reserved
f o r
se
28 TBL1_EN Trunking Table 1 Enable
0: Disable
27:26 TBL0_GRP
e l e a 1: Enable
Trunking Table 0 Group Selection
i a l R Select trunking group to be serviced

2'b00: Group 0
t
2'b01: Group 1
i d e n P i
2'b10: Group 2
2'b11: Reserved
f
24 TBL0_EN Trunking Table 0 Enable
C o n a n a 0: Disable
1: Enable
23:20 INFO_SEL
e k B a n Trunking Table Information Control Bit Map

The information used by table to assign conversations to ports. To apply
T r
the information, set corresponding bits in the bit map to 1.
d i a F o BIT 0: IPv4/IPv6 SIP

BIT 1: IPv4/IPv6 DIP
Me
BIT 2: TCP/UDP SPORT
BIT 3: TCP/UDP DPORT
19:0 AGE_CNT Trunking Table Age Count
This age count is recorded in the age timer field of the Trunking table for
a new entry. The applied age timer is equal to AGE_CNT seconds.
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
2.7.2
t i a
ARL Port-Based Register
n
f i d e a P i
Module name: ARL_PORT Base address: (+0x0000)
n
Address Name Width Register Function
00002000
00002004
C o P0_SSC
P0_PCR
n a n 32
32
STP State Control of P0
Port Control of P0
T e
00002008
0000200C
k r B
P0_PIC
P0_PSC
a 32
32
Port IGMP Control of P0
Port Security Control of P0
d i a
00002010
F o P0_PVC 32 Port VLAN Control of P0
Me
00002014 P0_PPBV1 32 Port-and-Protocol Based VLAN I of P0
00002018 P0_PPBV2 32 Port-and-Protocol Based VLAN II of P0
0000201C P0_BSR 32 Broadcast Storm Rate Control of P0
00002020 P0_STAG01 32 STAG Index 0/1 of P0
00002028
0000202C
P0_STAG45
P0_STAG67
32
32
STAG Index 4/5 of P0
f o r
se
00002030 P0_BSR_EXT1 32 Broadcast Storm Rate Control I of P0
a
00002034 P0_BSR_EXT2 32 Broadcast Storm Rate Control II of P0
00002038
00002040
P0_BSR_EXT3
P0_UPW
R e l e 32
32
Broadcast Storm Rate Control III of P0
User Priority Weight of P0
l
00002044 P0_PEM1 32 User Priority Egress Mapping I of P0
00002048
0000204C
P0_PEM2
P0_PEM3
n t i a 32
32
User Priority Egress Mapping II of P0
User Priority Egress Mapping III of P0
00002050
00002100
P0_PEM4
f i
P1_SSC
d e a P i
32
32
User Priority Egress Mapping IV of P0
00002104
00002108
C o n
P1_PCR
P1_PIC
n a n
32
32
Port Control of P1
a
0000210C P1_PSC 32 Port Security Control of P1
T e
00002110
00002114 k r B
P1_PVC
P1_PPBV1
32
32
Port VLAN Control of P1
Port-and-Protocol Based VLAN I of P1
d i a
00002118
F o P1_PPBV2 32 Port-and-Protocol Based VLAN II of P1
Me
0000212C P1_STAG67 32 STAG Index 6/7 of P1
o r
ef
00002134 P1_BSR_EXT2 32 Broadcast Storm Rate Control II of P1
s
00002138 P1_BSR_EXT3 32 Broadcast Storm Rate Control III of P1
00002140
00002144
P1_UPW
P1_PEM1
32
32
ele a
User Priority Egress Mapping I of P1
R
00002148 P1_PEM2 32 User Priority Egress Mapping II of P1
0000214C
00002150
P1_PEM3
P1_PEM4
t i a l 32
32
n
00002200 P2_SSC 32 STP State Control of P2
00002204
00002208
P2_PCR
f i d
P2_PIC
e a P i
32
32
Port Control of P2
0000220C
00002210
C o n P2_PSC
P2_PVC
n a n
32
32
k a
i a T e o r B
M e d F
Page 66 of 830
f o r
l e a se MT7531
l R e Lynx1
00002218 P2_PPBV2
n t i a 32 Port-and-Protocol Based VLAN II of P2
e
00002220
00002224
n f i d
P2_STAG01
P2_STAG23
a P i 32
32
00002228
0000222C
C o P2_STAG45
n
P2_STAG67
a n 32
32
T e
00002230
00002234
k r B a
P2_BSR_EXT1
P2_BSR_EXT2
32
32
Broadcast Storm Rate Control I of P2
Broadcast Storm Rate Control II of P2
d i a
00002238
F o P2_BSR_EXT3 32 Broadcast Storm Rate Control III of P2
Me
00002240 P2_UPW 32 User Priority Weight of P2
0000224C P2_PEM3 32 User Priority Egress Mapping III of P2
00002250 P2_PEM4 32 User Priority Egress Mapping IV of P2
00002300
00002304
P3_SSC
P3_PCR
32
32
Port Control of P3
f o r
se
00002308 P3_PIC 32 Port IGMP Control of P3
0000230C
00002310
00002314
P3_PSC
P3_PVC
P3_PPBV1
e l e a 32
32
32
00002318
0000231C
P3_PPBV2
P3_BSR
i a l R 32
32
Port-and-Protocol Based VLAN II of P3
Broadcast Storm Rate Control of P3
00002320
00002324
P3_STAG01
e
P3_STAG23
n t i
32
32
00002328
0000232C
n f i d
P3_STAG45
P3_STAG67
n a P 32
32
00002330
00002334
k C o a n a
P3_BSR_EXT1
P3_BSR_EXT2
32
32
T e
00002338
00002340
i a o r B
P3_BSR_EXT3
P3_UPW
32
32
F
Me d00002348
0000234C
00002350
00002400
P3_PEM2
P3_PEM3
P3_PEM4
P4_SSC
32
32
32
32
00002404 P4_PCR 32 Port Control of P4
00002408 P4_PIC 32 Port IGMP Control of P4
o r
ef
0000240C P4_PSC 32 Port Security Control of P4
s
00002410 P4_PVC 32 Port VLAN Control of P4
00002414
00002418
P4_PPBV1
P4_PPBV2
32
32
ele a
R
00002420
00002424
P4_STAG01
P4_STAG23
t i a l 32
32
00002428
0000242C
P4_STAG45
e
P4_STAG67
i d n P i
32
32
f
00002434
00002438
C o nP4_BSR_EXT2
a
P4_BSR_EXT3
n a 32
32
00002440
e k a
P4_UPW
B n 32 User Priority Weight of P4
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
00002444 P4_PEM1
n t i a 32 User Priority Egress Mapping I of P4
e
0000244C
00002450
n f i d
P4_PEM3
P4_PEM4
a P i 32
32
00002500
00002504
C o P5_SSC
P5_PCR
n a n 32
32
Port Control of P5
T e
00002508
0000250C
k r B
P5_PIC
P5_PSCa 32
32
d i a
00002510
F o P5_PVC 32 Port VLAN Control of P5
Me
00002518 P5_PPBV2 32 Port-and-Protocol Based VLAN II of P5
00002528
0000252C
P5_STAG45
P5_STAG67
32
32
f o r
se
00002534
00002538
00002540
P5_BSR_EXT2
P5_BSR_EXT3
P5_UPW
e l e a 32
32
32
00002544
00002548
P5_PEM1
P5_PEM2
i a l R 32
32
0000254C
00002550
P5_PEM3
P5_PEM4
e n t i
32
32
00002554
00002558
n f i d
P5_BSR_EXT4
P5_BSR_EXT5
n a P 32
32
Broadcast Storm Rate Control IV of P5
Broadcast Storm Rate Control V of P5
00002600
00002604
k C o P6_SSC
P6_PCR
a n a 32
32
Port Control of P6
T e
00002608
0000260C
i a o r B
P6_PIC
P6_PSC
32
32
F
00002610 P6_PVC 32 Port VLAN Control of P6
Me d00002614
00002618
0000261C
00002620
P6_PPBV1
P6_PPBV2
P6_BSR
P6_STAG01
32
32
32
32
o r
ef
0000262C P6_STAG67 32 STAG Index 6/7 of P6
s
00002634
00002638
P6_BSR_EXT2
P6_BSR_EXT3
32
32
ele a
R
00002640 P6_UPW 32 User Priority Weight of P6
00002644
00002648
P6_PEM1
P6_PEM2
t i a l 32
32
0000264C
00002650
P6_PEM3
P6_PEM4
i d e n P i
32
32
f
00002654 P6_BSR_EXT4 32 Broadcast Storm Rate Control IV of P6
00002658
C o nP6_BSR_EXT5
a n a 32 Broadcast Storm Rate Control V of P6
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
00002000 P0_SSC
n t i a STP State Control of P0 0000FFFF
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
n f i d a P i REV0
n
Type RO
Reset
Bit
0
15
k C o 0
14
a n a 0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
i a T eFID7_PST
RW
o r B
FID6_PST
RW
FID5_PST
RW
FID4_PST
RW
FID3_PST
RW
FID2_PST
RW
FID1_PST
RW
FID0_PST
RW
F
Reset
d
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Me Bit(s)
31:16
15:14
13:12
Name
REV0
FID7_PST
FID6_PST
Description
Reserved
(Rapid) Spanning Tree Protocol Port State
11:10
9:8
FID5_PST
FID4_PST
f o r
se
7:6 FID3_PST (Rapid) Spanning Tree Protocol Port State
3:2
1:0
FID1_PST
FID0_PST
e l e a (Rapid) Spanning Tree Protocol Port State

i a l R
00002004
Bit 31
P0_PCR
30
e n t29
i
28 27 26
Port Control of P0
25 24 23 22 21 20 19 18 17
00FF2000
16
Name REV0
n f
MLDv2
_EN
i d n a P
EG_TAG REV1 PORT_PRI PORT_MATRIX
Type
Reset
RW
0
k C o RW
0
a n a 0
RW
0
RW
0 0
RW
0 0 1 1 1 1
RW
1 1 1 1
e B
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
d i a T F o r
REV2
UP2DS UP2TA ACL_E
CP_EN G_EN N
PORT_ PORT_
TX_MI RX_MI
R R
ACL_MI
R
MIS_PORT_FW REV3
VLAN_
MIS
PORT_VLAN
Me
Type RW RW RW RW RW RW RW RW RW RW RW
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

31 REV0 Reserved
o r
ef
30 MLDv2_EN IPv6 MLDv2 source address multicast forwarding enable
0: Disable
29:28 EG_TAG
1: Enable
Port-Based Egress VLAN Tag Attribution
a s
ele
2'b00: Untagged
2'b01: Swap
i a l R 2'b10: Tagged
2'b11: Stack
27
26:24
REV1
PORT_PRI
e n t i
Reserved
Port-based User Priority
23:16
n f i
PORT_MATRIX
d n a P
User priority for the ingress port
Port Matrix Member
o
The legacy port VLAN function. Each bit indicates the permissible egress
k C a n a ports. This function can work with 802.1Q function to decide the last port
member.
i a T e o r B
M e d F
Page 69 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
NOTE: The final and effective port member should exclude the received
port.
n
15:13 REV2 Reserved
12
C o
UP2DSCP_EN
n a n User Priority to DSCP Enable

Replace DSCP according to user priority.
k a
0: Disable
11
i a T e o r
UP2TAG_EN
B 1: Enable
User Priority to Tag Enable
F
Replace 802.Q priority by user priority.
Me d
10 ACL_EN
0: Disable
1: Enable
Port-based ACL Enable
0: Bypass the ACL Table.
1: Look up the ACL Table and take corresponding actions.
9 PORT_TX_MIR Port Tx Mirror Enable
All frames transmitted from this port are copied to the mirror port.
f o r
se
[NOTE] Multi-port support is possible.
0: Disable
8 PORT_RX_MIR
e l e a 1: Enable
Port Rx Mirror Enable
R
All frames received from this port are copied to the mirror port.
l
n t i a 0: Disable
1: Enable
7 ACL_MIR
f i d e a P i
ACL Mismatch to Mirror Port
Frames are copied to Mirror port when the ACL table is enabled and the
n
frame does not match any ACL rule.
C o n a n 0: Disable
1: Enable
6:4
T e k
MIS_PORT_FW
r B a ACL Mismatch TO_CPU Forward

Frame port forwarding when ACL table is enabled and the frame is
a
mismatched
d i F o 3'b0xx: System default (disabled)
Me
the ingress port is the CPU port, the system default and CPU port are
excluded.)
r
3
2
REV3
VLAN_MIS
Reserved
VLAN Mismatch to Mirror Port
ef o
1'b0: Frame is processed according to PORT_VLAN.
1'b1: VLAN mismatched frame is copied to MIRROR port.
a s
ele
1:0 PORT_VLAN Port-based VLAN Mechanism Select
R
2'b00: Port Matrix Mode. Frames are forwarded by the Port Matrix
l
Member.
n t i a 2'b01: Fallback Mode. Forward received frames with ingress ports that do
not belong to the VLAN member. Each frame whose VID is not listed on
e
the VLAN table is forwarded based on the Port Matrix member.
n f i d a P i 2'b10: Check Mode. Forward received frames whose ingress port do not
belong to the VLAN member. Discard frames if VID is missed on the VLAN
n
table.
k C o a n a 2'b11: Security Mode. Enable VLAN security and discard any frame due to
ingress membership violation or VID missed on the VLAN table.
i a T e o r B
M e d F
Page 70 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
00002008
Bit 31
C o n
P0_PIC
30
n a n29 28 27 26
25 24 23 22 21 20 19 18
00008000
17 16
Name
T e k r B a REV0
IGMP_
MIR
IGMP_MIS
a o
Type RO RW RW
d i
Reset 0
F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLD_H IGMP_ MLD2_ IGMP3 MLD_J IGMP_J MLD_S IGMP_ MLD_G IGMP_
IPM_22
Name ROBUST_VAR W_LEA HW_LE REV1 IPM_33 IPM_01 JOIN_E _JOIN_ OIN_E OIN_E QRY_E SQRY_ QRY_E GQRY_
44
VE AVE N EN N N N EN N EN
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
0 0
Bit(s)
31:20
19
Name
REV0
IGMP_MIR
l e a
Description
Reserved
IP Multicast IGMP Table Mismatch to Mirror Port se
l R e Copy IP multicast frames with an IGMP table mismatch to the mirror
port.
a
[NOTE] This control register is valid only if PSR.IGMP_EN or MLD_EN is set
e n t i on a per-port basis.
0: Disable
18:16 IGMP_MIS
n f i d a P i 1: Frame copied to Mirror port

IP Multicast "TO_CPU" Forwarding
C o n a n Select how to forward IP multicast frames when the IGMP table is

mismatched.
a
T e k r B
on a per-port basis.
3'b0xx: System default (By MFC.UNM_FFP)
d i a F o 3'b100: System default and CPU port excluded

Me
excluded.)
15:14 ROBUST_VAR Robustness Variable
Define the number of times an IGMP report message may be lost
o r
ef
consecutively.
0: Unlimited (No Age out)
1: One time
a s
ele
3: Three times
13 MLD_HW_LEAVE
i a l R MLD HW Leave Enable

Enable HW MLD Done snooping and fast leave. The corresponding
e n t i
incoming port will be removed from the specific group address without a
group-specific query.
d
0: Disable
12
n f i
IGMP_HW_LEAVE
o n a P 1: Enable
IGMP HW Leave Enable
k C a n a Enable HW IGMP Leave snooping and fast leave. The corresponding

incoming port will be removed from the specific group address without a
e B
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Disable
11 REV1
n f i d a P i 1: Enable
Reserved
10
C o
IPM_2244
n a n IP Multicast frame for DIP is Class D:224.x.x.x to 239.x.x.x

0: This frame is regarded as a normal multicast and search ADDR Table.
T e k
IPM_33
r B a 1: This frame is regarded as an IP multicast frame and search IGMP table.

IP Multicast frame for MAC DA is 33-33-xx-xx-xx-xx
a o
0: This frame is regarded as normal multicast and search ADDR table.
d i F 1: This frame is regarded as IP multicast frame and search IGMP table.
Me
8 IPM_01 IP Multicast frame for MAC DA is 01-00-5E-xx-xx-xx
0: This frame is regarded as normal multicast and search ADDR Table.
1: This frame is regarded as IP multicast frame and search IGMP table.
7 MLD2_JOIN_EN MLD v2 HW Join Enable
Enable HW IGMP snooping. Group Address will be learned and added to
the ADDR Table automatically for the specific Record Type -IS_EX(),
TO_EX().
f o r
se
0: Disable
1: Enable
6 IGMP3_JOIN_EN
e l e a IGMP v3 HW Join Enable

R
t i a l TO_EX().
0: Disable
n
1: Enable
5 MLD_JOIN_EN
f i d e a P i
MLD Snooping HW Join Enable
0: MLD message and multicast IPv6 frame is regarded as a general
n
multicast frame.
C o n a n 1: This port is capable of recognizing the MLD message and multicast IPv6
frames (FF00:/8).
4
T e k
IGMP_JOIN_EN
r B a IGMP Snooping HW Join Enable

the ADDR Table automatically.
Me
1: Enable
3 MLD_SQRY_EN MLD HW Specific Query Enable
0: MLD-specific query message does not refresh the IP multicast table.
1: This port is capable of recognizing the MLD-specific query message to
refresh the specific multicast member.
r
2 IGMP_SQRY_EN IGMP HW Specific Query Enable
0: IGMP-specific query message does not refresh the IP multicast table.
1: This port is capable of recognizing the IGMP-specific query message to
ef o
s
1 MLD_GQRY_EN MLD HW General Query Enable
ele a
0: MLD general query message will not refresh the IP multicast table.
1: This port is capable of recognizing the MLD general query message to
0 IGMP_GQRY_EN
i a l R refresh the multicast member.

IGMP HW General Query Enable
t
0: IGMP general Query message will not refresh the IP multicast table.
i d e n P i
1: This port is capable of recognizing the IGMP general query message to
refresh the multicast member.
o n f a n a
0000200C
e k C P0_PSC
B a n Port Security Control of P0 000FFF00
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit 31 30
n t
29
i a 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
f i d e a P i
SA_LRN_CNT
RO
MAC_SA_LRN
RW
Reset
Bit
0
15
C o n 0
14
n a n
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
1
0
a
TX_PO RX_PO
Name
T e k r B
MAC_SA_LRN REV0
SA_CN
T_EN
SA_DIS SA_LOCK RT_LOC RT_LO
K CK
Type
d i
Reset
a 1
F o 1 1 1
RW
1 1 1 1 0
RW
0
RW
0
RW
0 0
RW
0
RW
0
RW
0
Me Bit(s)
31:20
19:8
Name
SA_LRN_CNT
MAC_SA_LRN
Description
Learned Source Address Number
Rx SA Allowable Learning Number
Set the maximum number of SA learned addresses when SA_CNT_EN is
set.
f o r
se
12'h0: Disable SA learning
12'h1:
e l e a 12'hFFE: 1 to 4094 address table

12'hFFF: SA Learning without limitation
R
7:6 REV0 Reserved
5 SA_CNT_EN
t i a l SA Counter Enable
Enable the learned source MAC Address counter.
n
0: Disable
4 SA_DIS
f i d e a P i
1: Enable
SA Disable
n
Disable source MAC address learning.
C o n a n 0: Enable
1: Disable
3:2
T e k
SA_LOCK
r B a SA Lock Select
[NOTE] PAE frames should be passed and is not affected by SA Lock.
a o
2'b00: Receive without SA authorization.
d i F 2'b01: All received frames whose SA look-up is missing or the received
Me
frames that are not port members in the ARL will be dropped.
2'b10: All received frames whose SA look-up is missing or are not port
members in the ARL are forwarded to some Port Matrix Members
(PCR.PORT_MATRIX).
r
members in the ARL are forwarded among the Guest VLAN Member.
1 TX_PORT_LOCK
(VTC.GUEST_MEM)
Tx Port Lock Enable
ef o
s
[NOTE] PAE Frames should be passed and are not affected by Port Lock.
0 RX_PORT_LOCK
0: Transmit authorized.
1: Disable frame transmission.
Rx Port Lock Enable
ele a
i a l R [NOTE] PAE frames should be passed and are not affected by Port Lock.
0: Receive authorized.
e n t i
1: Disable frame receiving.
00002010
n f i
P0_PVCd n a P Port VLAN Control of P0 810000C0
Bit
Name
k C
31
o 30
a n a 29 28 27 26 25 24
STAG_VPID
23 22 21 20 19 18 17 16
i a T e o r B
M e d F
Page 73 of 830
f o r
l e a se MT7531
l R e Lynx1
Type
n t i a RW
e
Reset 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15
n
14
f i d
DIS_PV FORCE BC_LKY
13
a P i
PT_OP
12 11 10 9 8 7 6 5 4 3
PORT_ IPM_LK MC_LK UC_LKY
2 1 0
Name
Type
ID
RW
C o_PVID V_EN
RW
n a n
REV0
RW
TION
RW RW
EG_TAG
RW
VLAN_ATTR
RW
STAG YV_EN YV_EN V_EN
RW RW RW RW
ACC_FRM
RW
Reset
T e k
0
r B
0
a 0 0 0 0 0 0 1 1 0 0 0 0 0 0
i a
Bit(s)
d
Name
F o Description
Me
31:16 STAG_VPID Stack Tag VPID (VLAN Protocol ID) Value
The received frame will be regarded as a legal stack tag frame if the
following conditions are matched:
Outer VPID == STAG_VPID
Inner VPID == 16'h8100
r
The outgoing frame will be added by the outer VLAN tag with the
o
programmable VPID field = STAG_VPID.
15 DIS_PVID PVID Disable
Disable PVID insertion in priority-tagged frames.
se f
a
0: Use PVID for priority-tagged frames.
14 FORCE_PVID
R e l e 1: Keep VID=0 for priority-tagged frames.

Force PVID on VLAN-tagged frames
0: Use VID in VLAN-tagged frame.
13 BC_LKYV_EN
t i a l 1: Force the replacement of VID with PVID.

Broadcast Leaky VLAN Enable
i d e n P i
0: Broadcast frames received by this port will be blocked by VLAN.
1: Broadcast frames received by this port can pass through VLAN.
12
11
REV0
o n
PT_OPTION
f a n a
Reserved
Pass-through capability on TX special tag
C
0: Disable pass-through on TX special tag
10:8
e k
EG_TAG
B a n 1: Enable pass-through on TX special tag

Incoming Port Egress VLAN Tag Attribution
d i a T F o r 3'b000: System default (disabled)

3'b001: Consistent
Me
3'b100: Untagged
3'b101: Swap
3'b110: Tagged
3'b111: Stack
7:6 VLAN_ATTR VLAN Port Attribute
o r
ef
2'b00: User port
2'b01: Stack port
2'b10: Translation port
a s
ele
2'b11: Transparent port
5 PORT_STAG Special Tag Enable
i a l R Enable a proprietary VLAN tag format to carry additional information to

the remote port.
t
0: No special tag format for Tx/Rx
n
1: Enable
4 IPM_LKYV_EN
f i d e a P i
IP Multicast Leaky VLAN Enable
(note*) If MC_LKYV_EN is set, this field will become "don't care" bit. All
n
multicast frames including IP_Multi will be leaky between VLAN groups.
C o n a n 0: IP_Multi frames received by this port will be blocked by VLAN.

1: IP_Multi frames received by this port can pass through VLAN.
3
T e k
MC_LKYV_EN
r B a Multicast Leaky VLAN Enable
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Multicast frames received by this port will be blocked by VLAN.
n
UC_LKYV_EN
f i d a P i 1: Multicast frames received by this port can pass through VLAN.

Unicast Leaky VLAN Enable
C o n a n 0: Unicast frame received by this port will be blocked by VLAN.

1: Unicast frame received by this port can pass through VLAN.
1:0
T e k
ACC_FRM
r B a Acceptable Frame Type

2'b00: Admit All frames
a o
2'b01: Admit Only VLAN-tagged frames
d i F 2'b10: Admit only untagged or priority-tagged frames.
Me
2'b11: Reserved
00002014 P0_PPBV1 Port-and-Protocol Based VLAN I of P0 00010001

Bit
Name
31 30
G1_PORT_PRI
29 28
REV0
27 26 25 24 23 22
G1_PORT_VID
21 20 19 18
f o
17
r 16
se
Type RW RW RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
e l
0
4
e a 0
3
0
2
0
1
1
0
R
Name G0_PORT_PRI REV1 G0_PORT_VID
Type
Reset 0
RW
0
t i0
a l RW
0 0 0 0 0 0 0
RW
0 0 0 0 0 1
Bit(s) Name
i d e n P i Description
31:29
o n f
G1_PORT_PRI
a n a
Group 1 Port Priority (optional)
The Group 1 Priority for each port according to IEEE 802.1Q definition
C
28 REV0 Reserved
27:16
e k
G1_PORT_VID
B a n Group 1 Port VLAN ID (optional)

The Group 1 VID for each port according to IEEE 802.1Q definition
d i a T
15:13
F o r
G0_PORT_PRI Group 0 Port Priority (Default Port Priority)
The Group 0 and default Priority for each port according to IEEE 802.1Q
definition
M e 12
11:0
REV1
G0_PORT_VID
Reserved
Group 0 Port VLAN ID (Default Port VID)
The Group 0 and default VID for each port according to IEEE 802.1Q
definition
o r
ef
00002018 P0_PPBV2 Port-and-Protocol Based VLAN II of P0 00010001
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Type RW RW RW
Reset
Bit
0
15
0
14
i
0
a
13
l R 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
Name
Type RW
e n
G2_PORT_PRI
t i
REV1
RW
G2_PORT_VID
RW
Reset 0
n f i d
0
n
0
a P
0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s)
31:29
k C o
Name
a
G3_PORT_PRI
n a Description
i a T e o r B
M ed F
Page 75 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
28 REV0
f i d e a P i
Reserved
n
27:16 G3_PORT_VID Group 3 Port VLAN ID (optional)
15:13
C o
G2_PORT_PRI
n a n The Group 3 VID for each port according to IEEE 802.1Q definition
k a
12
11:0
i a T e
REV1
o r B
G2_PORT_VID
Reserved
Group 2 Port VLAN ID (optional)
F
Me d
0000201C P0_BSR Broadcast Storm Rate Control of P0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
STRM_
STRM_ STRM_ STRM_ STRM_ STRM_
Name
MODE BC_INC
MC_IN
C
UC_INC DROP PERD
STRM_UNIT STORM_1G
f o
se
Type RW RW RW RW RW RW RW RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
e l
0
4
e a 0
3
0
2
0
1
0
0
R
Name STORM_100M STORM_10M
Type
Reset 0 0
t
0
i a l 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
31
o n f
STRM_MODE
a n a
Broadcast Storm Suppression
0: Packet-based (1 second period)
30
e k C
STRM_BC_INC
B a n
1: Rate-based
Broadcast Storm Included
0: Exclude BC frame
d i
29
a T F o r
STRM_MC_INC
1: Include BC frame
Unknown Multicast Storm Included
e
0: Exclude MC frame
M
1: Include MC frame
28 STRM_UC_INC Unknown Unicast Storm Included
0: Exclude UC frame
1: Include UC frame
27 STRM_DROP Broadcast Storm Suppression enabled
o r
ef
0: BC Storm detection only
1: Enable packet drop when BC storm is detected
26 STRM_PERD Broadcast Strom Detection Signal Period
a s
ele
0: One second
1: 125us
25:24 STRM_UNIT
i a l R Broadcast Storm Suppression

2'b00: 64 packets or 64 Kbps
t
i d e n P i
2'b10: 1 K packets or 1 Mbps
f
23:16 STORM_1G 1000 Mbps Broadcast Storm Rate Limit Control
C o n a n a The broadcast storm rate limit for 1000 Mbps link speed
8'h0: (0* STORM_UNIT) packets or bps
15:8
e k B
STORM_100M
a n 8'h1: (1* STORM_UNIT) packets or bps
100 Mbps Broadcast Storm Rate Limit Control
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
The broadcast storm rate limit for 100 Mbps link speed
n
7:0
o
STORM_10M
C n a n 10 Mbps Broadcast Storm Rate Limit Control

T e k r B a 8'h0: (0* STORM_UNIT) packets or bps

d i a F o
Me
00002020 P0_STAG01 STAG Index 0/1 of P0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name REV0 VID1
Type RO RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
f o
0
1
r 0
0
Name
se
VID1 VID0
Type
Reset 0 0
RW
0 0 0 0 0 0 0 0
RW
0
e l0
e a 0 0 0 0
Bit(s) Name
i a l R Description
31:24
23:12
REV0
VID1
e n t i
Reserved
VLAN Identifier for STAG index 1
d
11:0 VID0 VLAN Identifier for STAG index 0
o n f i n a P
00002024
k C n
P0_STAG23
a a STAG Index 2/3 of P0 00000000
e B
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
i
Type
d a T F o r REV0
RO
VID3
RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M Bit
Name
Type
Reset
15
0
14
0
VID3
RW
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
VID2
RW
5
0
4
0
3
0
2
0
1
0
0
o r
ef
31:24 REV0 Reserved
a s
ele
i a l R
00002028
Bit 31
P0_STAG45
30
e n t 29
i
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
n f i d n a P
REV0
RO
VID5
RW
Reset
Bit
k
0
C
15
o 0
14
a n a
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
i a T e o r B
M e d F
Page 77 of 830
f o r
l e a se MT7531
l R e Lynx1
Name VID5
n t i a VID4
e
Type RW RW
Reset 0 0
n f i d 0
a P i0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
C o n a n Description
k a
31:24 REV0 Reserved
e B
11:0
d i a T VID4
F o r VLAN Identifier for STAG index 4
Me 0000202C
Bit
Name
31
P0_STAG67
30 29 28
REV0
27 26
25 24 23 22 21 20
VID7
19 18
00000000
17 16
r
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Name VID7 VID6
Type
Reset 0 0
RW
0
R
0
e l e 0 0 0 0 0 0
RW
0 0 0 0 0 0
Bit(s) Name
t i a l Description
n
31:24 REV0 Reserved
23:12
11:0
VID7
VID6
f i d e a P i
C o n n a n
k a
00002030 P0_BSR_EXT1 Broadcast Storm Rate Control I of P0 00000000
Bit
i a T e31
o
30
r B
STRM_ STRM_
STRM_
29 28
STRM_ STRM_ STRM_

27 26 25 24 23 22 21 20 19 18 17 16
d
Name
F
MC_IN STRM_UNIT STORM_1G
MODE BC_INC UC_INC DROP PERD
Me
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a s
ele
31 STRM_MODE Broadcast Storm Suppression
R
30 STRM_BC_INC
t i a l 1: Rate-based
n
0: Exclude BC frame
29
f i
STRM_MC_INC
d e a P i
1: Include BC frame
n
0: Exclude MC frame
28
C o
STRM_UC_INC
n a n 1: Include MC frame
Unknown Unicast Storm Included
T e k r B a 0: Exclude UC frame
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
1: Include UC frame
27 STRM_DROP
n f i d a P i Broadcast Storm Suppression enabled

26
C o
STRM_PERD
n a n 1: Enable packet drop when BC storm is detected

Broadcast Strom Detection Signal Period
T e k r B a 0: One second
1: 125us
a o
25:24 STRM_UNIT Broadcast Storm Suppression
d i F 2'b00: 64 packets or 64 Kbps
Me
f o r
se
15:8 STORM_100M 100 Mbps Broadcast Storm Rate Limit Control
a
e
7:0 STORM_10M
R e l 8'h1: (1* STORM_UNIT) packets or bps

t i a l The broadcast storm rate limit for 10 Mbps link speed

i d e n P i
00002034
o n f
P0_BSR_EXT2
a n a Broadcast Storm Rate Control II of P0 00000000

Bit
e
31
k C 30
B
STRM_ STRM_
a n
STRM_
29 28
STRM_ STRM_ STRM_

27 26 25 24 23 22 21 20 19 18 17 16
Name
d
Type
i a T RW
F o r
MODE BC_INC
RW
MC_IN
C
UC_INC DROP PERD
RW RW RW RW
STRM_UNIT
RW
STORM_1G
RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
31
Name
STRM_MODE
Description
a s ef
ele
1: Rate-based
30 STRM_BC_INC
i a l R Broadcast Storm Included

0: Exclude BC frame
29 STRM_MC_INC
e n t i
1: Include BC frame
d
0: Exclude MC frame
28
o n f i
STRM_UC_INC
n a P 1: Include MC frame
k C a n a 0: Exclude UC frame
1: Include UC frame
i a T e o r B
M e d F
Page 79 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 0: BC Storm detection only

26
C o
STRM_PERD
n a n Broadcast Strom Detection Signal Period

0: One second
25:24
T e k
STRM_UNIT
r B a 1: 125us
a o
d i F 2'b01: 256 packets or 256 Kbps
Me
15:8 STORM_100M
f o r
se
7:0 STORM_10M
e l e a 8'h1: (1* STORM_UNIT) packets or bps

i a l R The broadcast storm rate limit for 10 Mbps link speed

t
i d e n P i
00002038
Bit 31
o n
30 f
P0_BSR_EXT3
a
29
n a 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
e k C
STRM_ STRM_
MODE BC_INC
STRM_
B
MC_IN
a n
STRM_ STRM_ STRM_
UC_INC DROP PERD
STRM_UNIT STORM_1G
T r
C
Type
d i
Reset
a RW
0
F oRW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
s
a
ele
1: Rate-based
30 STRM_BC_INC Broadcast Storm Included
i a l R 0: Exclude BC frame
1: Include BC frame
29 STRM_MC_INC
e n t i
0: Exclude MC frame
d
1: Include MC frame
28
f i
STRM_UC_INC
o n n a P Unknown Unicast Storm Included

0: Exclude UC frame
27
k C
STRM_DROP
a n a 1: Include UC frame
Broadcast Storm Suppression enabled
i a T e o r B
M e d F
Page 80 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
26
n
STRM_PERD
f i d a P i 1: Enable packet drop when BC storm is detected

C o n a n 0: One second
1: 125us
25:24
T e k
STRM_UNIT
r B a Broadcast Storm Suppression

a o
d i F 2'b10: 1 K packets or 1 Mbps
Me
f o r
se
a
7:0 STORM_10M
R e l e 10 Mbps Broadcast Storm Rate Limit Control

t i a l 8'h1: (1* STORM_UNIT) packets or bps
i d e n P i
f
00002040 P0_UPW User Priority Weight of P0 00234567
Bit
Name
31
C o n
30 29
a n a 28 27 26 25 24 23
REV0
22 21
ARL_UPW
20 19
REV1
18 17
PORT_UPW
16
Type
e k B a n RW RW RW RW
T
Reset 0 0 1 0 0 0 1 1
Bit
d
Name
i a 15
REV2
F o r
14 13
DSCP_UPW
12 11
REV3
10 9
TAG_UPW
8 7
REV4
6 5
STAG_UPW
4 3
REV5
2 1
ACL_UPW
0
Me
Reset 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1

23 REV0 Reserved
o r
ef
22:20 ARL_UPW ARL User Priority Weight (MAC/DIP Hit)
19 REV1 Reserved
18:16 PORT_UPW Port-Based User Priority Weight Value
a s
ele
Weights range from 0x0 to 0x7.
15 REV2 Reserved
R
14:12 DSCP_UPW DSCP Priority Weight (IPv4)
l
11 REV3 Reserved
10:8
7
TAG_UPW
REV4
n t i a Priority Tag User Priority Weight

Reserved
e
6:4 STAG_UPW Special Tag User Priority Weight
3
2:0
REV5
ACL_UPW
n f i d a P i Reserved
ACL User Priority Weight (ACL Hit)
C o n a n
00002044
T e k r B a
P0_PEM1 User Priority Egress Mapping I of P0 10080480
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit 31 30 29
n t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
REV0
RW
f i e
TAG_PRI_1
d RW
a P i
QUE_PFCR_1
RW
QUE_PFCT_1
RW
DSCP_PRI_1
RW
Reset
Bit
0
15
C o n
0
14
n a
0
13
n
1
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
0
2
0
1
0
0
a
Name
k
REV1 TAG_PRI_0 QUE_PFCR_0 QUE_PFCT_0 DSCP_PRI_0
Type
e B
RW RW RW RW RW
Reset
d i a T 0
F o r
0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Me
31 REV0 Reserved
30:28 TAG_PRI_1 User Priority 1 Priority Tag Value
27:25 QUE_PFCR_1 User Priority 1 Egress Queue Selection or PFC RX Mapping
24:22 QUE_PFCT_1 User Priority 1 PFC TX Mapping
21:16
15
DSCP_PRI_1
REV1
User Priority 1 DSCP Value
Reserved
f o r
se
8:6
5:0
QUE_PFCT_0
DSCP_PRI_0
e l e a User Priority 0 PFC TX Mapping

i a l R
00002048
Bit 31
P0_PEM2
30
e n
29
t 28
i
27 26
25 24 23 22 21 20 19 18
36D82250
17 16
Name
Type
REV0
RW
n f i d
TAG_PRI_3
RW
n a P
QUE_PFCR_3
RW
QUE_PFCT_3
RW
DSCP_PRI_3
RW
Reset
Bit
0
15
k C o 0
14
a n a
1
13
1
12
0
11
1
10
1
9
0
8
1
7
1
6
0
5
1
4
1
3
0
2
0
1
0
0
e B
Name REV1 TAG_PRI_2 QUE_PFCR_2 QUE_PFCT_2 DSCP_PRI_2
Type
d i
Reset
a T RW
0
F o r
0
RW
1 0 0
RW
0 1 0
RW
0 1 0 1 0
RW
0 0 0
Me Bit(s)
31
30:28
27:25
Name
REV0
TAG_PRI_3
QUE_PFCR_3
Description
Reserved
User Priority 3 Priority Tag Value
User Priority 3 Egress Queue Selection or PFC RX Mapping
o r
ef
21:16 DSCP_PRI_3 User Priority 3 DSCP Value
15 REV1 Reserved
a s
ele
R
t i a l
0000204C
Bit 31
P0_PEM3
30
i d e n 29
P i 28 27 26
25 24 23 22 21 20 19 18
5B684920
17 16
Name
Type
REV0
RW
o n f TAG_PRI_5
a n
RW
a QUE_PFCR_5
RW
QUE_PFCT_5
RW
DSCP_PRI_5
RW
Reset
e k
0
C 1
B a n 0 1 1 0 1 1 0 1 1 0 1 0 0 0
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit 15 14
n t i
13
a 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type
Reset
RW
0
n f1
i d RW
0
a P i 0 1
RW
0 0 1
RW
0 0 1 0 0
RW
0 0 0
C o n a n
k a
31
30:28
i a T e
REV0
o r
TAG_PRI_5
B Reserved
F
Me d
24:22
21:16
15
14:12
11:9
QUE_PFCT_5
DSCP_PRI_5
REV1
TAG_PRI_4
QUE_PFCR_4
User Priority 5 PFC TX Mapping
Reserved
f o r
00002050 P0_PEM4
l e a User Priority Egress Mapping IV of P0

se 7FF86DB0
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
REV0
RW
TAG_PRI_7
RW
i a l R QUE_PFCR_7
RW
QUE_PFCT_7
RW
DSCP_PRI_7
RW
Reset
Bit
0
15
1
14
e n t 1
13
i
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
0
2
0
1
0
0
Name
Type
REV1
RW
n f i d TAG_PRI_6
n
RW
a P
QUE_PFCR_6
RW
QUE_PFCT_6
RW
DSCP_PRI_6
RW
Reset 0
k C o 1
a n a
1 0 1 1 0 1 1 0 1 1 0 0 0 0
Bit(s)
31
i a T e
Name
REV0
o r B Description
Reserved
F
Me d
27:25
24:22
21:16
15
QUE_PFCR_7
QUE_PFCT_7
DSCP_PRI_7
REV1
Reserved
o r
ef
a s
ele
00002100 P1_SSC STP State Control of P1 0000FFFF
Bit
Name
31 30
i
29
a l R 28 27 26 25 24
REV0
23 22 21 20 19 18 17 16
Type
Reset 0 0
e n t 0
i
0 0 0 0 0
RO
0 0 0 0 0 0 0 0
Bit
Name
15
n f
FID7_PST
i d
14
n
13
a P
FID6_PST
12 11
FID5_PST
10 9
FID4_PST
8 7
FID3_PST
6 5
FID2_PST
4 3
FID1_PST
2 1
FID0_PST
0
Type
Reset
k
1
C o RW
1
a n a 1
RW
1 1
RW
1 1
RW
1 1
RW
1 1
RW
1 1
RW
1 1
RW
1
i a T e o r B
M e d F
Page 83 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
31:16 REV0 Reserved
15:14
13:12
FID7_PST
FID6_PST
n f i d a P i (Rapid) Spanning Tree Protocol Port State

11:10
9:8
C o
FID5_PST
FID4_PST
n a n (Rapid) Spanning Tree Protocol Port State

k a
e B
3:2
d i
1:0
a T FID1_PST
o
FID0_PST
F r (Rapid) Spanning Tree Protocol Port State

Me 00002104
Bit 31
P1_PCR
30 29 28 27 26
Port Control of P1
25 24 23 22 21 20 19 18
00FF2000
17 16
r
MLDv2
Name REV0 EG_TAG REV1 PORT_PRI PORT_MATRIX
o
_EN
Type
Reset
RW
0
RW
0 0
RW
0
RW
0 0
RW
0 0 1 1 1 1
RW
1
se
1
f 1 1
Bit
Name
15 14
REV2
13 12
e l e a 11
UP2DS UP2TA ACL_E

10
PORT_ PORT_
TX_MI RX_MI
9
ACL_MI
8 7 6 5
MIS_PORT_FW
4 3
REV3
2
VLAN_
1
PORT_VLAN
0
Type RW
i a l R
CP_EN G_EN
RW RW
N
R
RW
R
R
RW RW RW RW RW
MIS
RW RW
Reset 0 0
e n t1
i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
REV0
n f i d n a P Description
Reserved
30
k C o
MLDv2_EN
a n a IPv6 MLDv2 source address multicast forwarding enable

0: Disable
e B
1: Enable
T r
29:28 EG_TAG Port-Based Egress VLAN Tag Attribution
d i a F o
2'b00: Untagged
2'b01: Swap
Me
2'b10: Tagged
2'b11: Stack
27 REV1 Reserved
26:24 PORT_PRI Port-based User Priority
23:16 PORT_MATRIX Port Matrix Member
o r
ef
ports. This function can work with 802.1Q function to decide the last port
member.
a s
ele
port.
R
15:13 REV2 Reserved
12 UP2DSCP_EN
t i a l User Priority to DSCP Enable

n
0: Disable
11 UP2TAG_EN
f i d e a P i
1: Enable
n
1: Enable
10
T e k
ACL_EN
r B a Port-based ACL Enable
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f
PORT_TX_MIR
i d a P i 1: Lookup the ACL Table and take the corresponding actions.
Port Tx Mirror Enable
C o n a n All frames transmitted from this port are copied to the mirror port.
1: Enable
a o
8 PORT_RX_MIR Port Rx Mirror Enable
d i F
Me
0: Disable
1: Enable
7 ACL_MIR ACL Mismatch to Mirror Port
r
0: Disable
f o
se
1: Enable
6:4 MIS_PORT_FW ACL Mismatch TO_CPU Forward
e l e a Frame port forwarding when ACL table is enabled and the frame is
mismatched
3'b0xx: System default (disabled)
i a l R 3'b100: System default and CPU port excluded

e n t i
n f i d n a P
excluded.)
o
3 REV3 Reserved
2
C
VLAN_MIS
k a n a VLAN Mismatch to Mirror Port

1'b0: Frame is processed according to PORT_VLAN.
1:0
i a T e o r
PORT_VLAN
B 1'b1: VLAN mismatched frame is copied to MIRROR port.
Port-based VLAN Mechanism Select
d F
Me
Member.
2'b01: Fallback Mode. Forward received frames with ingress ports that do
2'b10: Check Mode. Forward received frames whose ingress port does
r
not belong to the VLAN member. Discard frames if VID is missed on the
o
VLAN table.
ef
2'b11: Security Mode. Enable VLAN security and discard any frame due to
a s
00002108 P1_PIC
l R Port IGMP Control of P1

ele 00008000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e n t i REV0
IGMP_
MIR
IGMP_MIS
Type
Reset 0
n f i d0
a
0
P i 0 0 0
RO
0 0 0 0 0 0
RW
0 0
RW
0 0
Bit
C o
15 14
n a n 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Lynx1
t
MLD_H IGMP_
n i a IPM_22
MLD2_ IGMP3 MLD_J IGMP_J MLD_S IGMP_ MLD_G IGMP_
e
i
44
d
Type
Reset 1
RW
o n f
0
i RW
n
0
a P RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
k C a n a
e B
T r
31:20 REV0 Reserved
19
d i a o
IGMP_MIR
F
IP Multicast IGMP Table Mismatch to Mirror Port
Copy IP multicast frames with an IGMP table mismatch to the mirror
Me
port.
0: Disable
18:16 IGMP_MIS IP Multicast "TO_CPU" Forwarding
Select how to forward IP multicast frames when the IGMP table is
f o r
se
mismatched.
e l e a on a per-port basis.
R
t i a l 3'b101: System default and CPU port included

n
f i d e a P i
excluded.)
n
C o n a n Define the number of times an IGMP report message may be lost

consecutively.
T e k r B a 0: Unlimited (No Age out)

1: One time
a o
d i F 3: Three times
Me
13 MLD_HW_LEAVE MLD HW Leave Enable
incoming port will be removed on the specific group address without a
0: Disable
1: Enable
o r
ef
12 IGMP_HW_LEAVE IGMP HW Leave Enable
Enable HW IGMP Leave snooping and fast leave. The corresponding
s
a
ele
0: Disable
R
1: Enable
11
10
REV1
IPM_2244
t i a l Reserved
IP Multicast frame for DIP is Class D:224.x.x.x to 239.x.x.x
n
9 IPM_33
f i d e a P i
1: This frame is regarded as an IP multicast frame and search IGMP table.
n
C o
IPM_01
n a n 1: This frame is regarded as IP multicast frame and search IGMP table.

IP Multicast frame for MAC DA is 01-00-5E-xx-xx-xx
T e k r B a 0: This frame is regarded as normal multicast and search ADDR Table.
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
7 MLD2_JOIN_EN
n f i d a P i MLD v2 HW Join Enable

C o n a n the ADDR Table automatically for the specific Record Type -IS_EX(),
TO_EX().
k a
0: Disable
i a T e r B
IGMP3_JOIN_EN
o
1: Enable
IGMP v3 HW Join Enable
F
Me d the ADDR Table automatically for the specific Record Type -IS_EX(),
TO_EX().
0: Disable
1: Enable
5 MLD_JOIN_EN MLD Snooping HW Join Enable
r
multicast frame.
1: This port is capable of recognizing the MLD message and multicast IPv6
f o
se
frames (FF00:/8).
4 IGMP_JOIN_EN
e l e a IGMP Snooping HW Join Enable

i a l R 0: Disable
1: Enable
3 MLD_SQRY_EN
e n t i
MLD HW Specific Query Enable
0: MLD specific query message will not refresh the IP multicast table.
d
1: This port is capable of recognizing the MLD specific query message to
n f
IGMP_SQRY_EN
o i n a P refresh the specific multicast member.

IGMP HW Specific Query Enable
k C a n a 0: IGMP specific query message will not refresh the IP multicast table.
1: This port is capable of recognizing the IGMP specific query message to
e B
T r
d i a F o 0: MLD general query message will not refresh the IP multicast table.
Me
0 IGMP_GQRY_EN IGMP HW General Query Enable
o r
0000210C P1_PSC Port Security Control of P1
a s ef 000FFF00
le
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
l R e SA_LRN_CNT
RO
MAC_SA_LRN
RW
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit 15 14
e n t i13 12 11 10 9 8 7 6 5 4 3 2 1
TX_PO RX_PO
0
d i
SA_CN
i
Name
P
MAC_SA_LRN REV0 SA_DIS SA_LOCK RT_LOC RT_LO
f
T_EN
a
K CK
Type
Reset
C o
1
n 1
n a n 1 1
RW
1 1 1 1 0
RW
0
RW
0
RW
0 0
RW
0
RW
0
RW
0
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
31:20 SA_LRN_CNT Learned Source Address Number
19:8 MAC_SA_LRN
n f i d a P i Rx SA Allowable Learning Number

Sets the maximum number of SA learned addresses when SA_CNT_EN is
C o n a n set.
k a
12'h1:
i a T e o r B 12'hFFE: 1 to 4094 address table

d F
7:6 REV0 Reserved
Me
5 SA_CNT_EN SA Counter Enable
0: Disable
1: Enable
4 SA_DIS SA Disable
r
0: Enable
f o
se
1: Disable
3:2 SA_LOCK SA Lock Select
e l e a [NOTE] PAE frames should be passed and are not affected by SA Lock.
R
l
members in the ARL will be dropped.
n t i a 2'b10: All received frames whose SA look-up is missing or are not port
e
(PCR.PORT_MATRIX).
n f i d a P i 2'b11: All received frames whose SA look-up is missing or are not port
n
(VTC.GUEST_MEM)
1
k C o
TX_PORT_LOCK
a n a Tx Port Lock Enable

e B
d
0
i a T o r
RX_PORT_LOCK
F
Rx Port Lock Enable
[NOTE] PAE frames should be passed and are not affected by Port Lock.
Me
00002110 P1_PVC Port VLAN Control of P1
o r
810000C0
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
s
STAG_VPID
Type
Reset 1 0 0 0 0 0 0 1
RW
0 0 0
ele
0
a 0 0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
DIS_PV FORCE BC_LKY
ID _PVID V_EN
t i
REV0
a l
PT_OP
TION
EG_TAG VLAN_ATTR
ACC_FRM
n
Type RW RW RW RW RW RW RW RW RW RW RW RW
Reset 0
f i d
0
e a
0
P i
0 0 0 0 0 1 1 0 0 0 0 0 0
Bit(s)
31:16
C o n
Name
STAG_VPID
n a n Description
Stack Tag VPID (VLAN Protocol ID) Value
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
C o n a n Inner VPID == 16'h8100

k a
15
i a T e
DIS_PVID
o r B PVID Disable
F
Me d
14 FORCE_PVID
1: Keep VID=0 for priority-tagged frames.
1: Force the replacement of VID with PVID.
13 BC_LKYV_EN Broadcast Leaky VLAN Enable
r
f o
se
12 REV0 Reserved
11 PT_OPTION Pass-through capability on TX special tag
e l e a 0: Disable pass-through on TX special tag

1: Enable pass-through on TX special tag
R
10:8 EG_TAG Incoming Port Egress VLAN Tag Attribution
l
3'b000: System default (disabled)
n t i a 3'b001: Consistent
f i d e a P i
3'b100: Untagged
3'b101: Swap
n
3'b110: Tagged
7:6
C o
VLAN_ATTR
n a n 3'b111: Stack
VLAN Port Attribute
T e k r B a 2'b00: User port

2'b01: Stack port
d i a F o 2'b10: Translation port

Me
Enable a proprietary VLAN tag format to carry additional information to
the remote port.
1: Enable
4 IPM_LKYV_EN IP Multicast Leaky VLAN Enable
o r
ef
a s
0: IP_Multi frames received by this port will be blocked by VLAN.
ele
3 MC_LKYV_EN Multicast Leaky VLAN Enable
i a l R 0: Multicast frames received by this port will be blocked by VLAN.

1: Multicast frames received by this port can pass through VLAN.
2 UC_LKYV_EN
e n t i
0: Unicast frame received by this port will be blocked by VLAN.
d
1:0 ACC_FRM
o n f i n a P Acceptable Frame Type

k C a n a 2'b01: Admit Only VLAN-tagged frames

2'b10: Admit only untagged or priority-tagged frames.
i a T e o r B
M e d F
Page 89 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
2'b11: Reserved
n f i d a P i
00002114
C oP1_PPBV1
n a n Port-and-Protocol Based VLAN I of P1 00010001

Bit
Name
T e k
31
r
30
B a
G1_PORT_PRI
29 28
REV0
27 26 25 24 23 22
G1_PORT_VID
21 20 19 18 17 16
Type
d i
Reset
a 0
F o
RW
0 0
RW
0 0 0 0 0 0 0
RW
0 0 0 0 0 1
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
f o r
se
31:29 G1_PORT_PRI Group 1 Port Priority (optional)
a
28
27:16
REV0
G1_PORT_VID
R e l e Reserved
15:13 G0_PORT_PRI
t i a l Group 0 Port Priority (Default Port Priority)

n
definition
12
11:0
REV1
G0_PORT_VID
f i d e a P i
Reserved
n
C o n a n definition
00002118
T e k r B a
P1_PPBV2 Port-and-Protocol Based VLAN II of P1 00010001
d i
Bit
a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0
RW
0 0
RW
0 0 0 0 0 0 0
RW
0 0 0 0
ef
0
o 1
a s
ele
28 REV0
i a l R The Group 3 Priority for each port according to IEEE 802.1Q definition
Reserved
t
n
15:13 G2_PORT_PRI
f i d e a P i
n
12 REV1 Reserved
11:0
o
G2_PORT_VID
C n a n Group 2 Port VLAN ID (optional)

T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
n t i a
0000211C
Bit 31
P1_BSR
30
f i d e29
a P i
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
STRM_ STRM_
C
MODE BC_INC
o n
STRM_
MC_IN
C
n n
STRM_ STRM_ STRM_
a
UC_INC DROP PERD
STRM_UNIT STORM_1G
Type
Reset
T
RW
e0
k RW
0
r B a RW
0
RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
d
Name
i a 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
STORM_100M STORM_10M
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

f o r
se
1: Rate-based
a
29 STRM_MC_INC
R e l e 0: Exclude BC frame
1: Include BC frame
t i a l 0: Exclude MC frame
1: Include MC frame
28 STRM_UC_INC
i d e n P i
0: Exclude UC frame
27
o n
STRM_DROP
f a n a
1: Include UC frame
C
26
e k
STRM_PERD
B a n 1: Enable packet drop when BC storm is detected

d i a T F o r 0: One second
1: 125us
Me
o r
ef
a s
ele
R
7:0 STORM_10M

n
f i d e a P i
C o n n a n
00002120
T e k r B a
P1_STAG01 STAG Index 0/1 of P1 00000000
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit 31 30
n t
29
i a 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
f i d e a P i
REV0
RO
VID1
RW
Reset
Bit
0
15
C o n
0
14
n a n
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
a
Name
k
VID1 VID0
Type
e B
RW RW
Reset
d i a T 0
F o r
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
31:24 REV0 Reserved
f o r
se
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
R e l e
REV0
RO
VID3
RW
l
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14
VID3
n
13
t i a 12 11 10 9 8 7 6
VID2
5 4 3 2 1 0
Type
Reset 0 0
f i
RW
d e 0
a P i0 0 0 0 0 0 0
RW
0 0 0 0 0 0
Bit(s) Name
C o n n a n Description
k a
31:24 REV0 Reserved
23:12
11:0
i a T e
VID3
VID2
o r B VLAN Identifier for STAG index 3

Me d
00002128
Bit 31
F P1_STAG45
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name REV0 VID5
r
Type RO RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
ef
0
1
o 0
0
Name VID5 VID4
a s
ele
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
i a l R Description
31:24
23:12
REV0
VID5
e n t i
Reserved
11:0 VID4
n f i d n a P
0000212C
k C o a n
P1_STAG67
a STAG Index 6/7 of P1 00000000
i a T e o r B
M e d F
Page 92 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit 31 30
n t
29
i a 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
f i d e a P i
REV0
RO
VID7
RW
Reset
Bit
0
15
C o n
0
14
n a n
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
a
Name
k
VID7 VID6
Type
e B
RW RW
Reset
d i a T 0
F o r
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
31:24 REV0 Reserved
f o r
se
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
STRM_ STRM_
MODE BC_INC
STRM_
MC_IN
C
l
UC_INC DROP PERD
R e
STRM_ STRM_ STRM_
e
STRM_UNIT STORM_1G
Type
Reset
RW
0
RW
0
RW
t
0
i a lRW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
15 14
i d e n 13 12
i
STORM_100M
P
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Type
Reset 0
o n
0
f a n
0
a 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Bit(s)
e k
Name
C B a n Description
T r
d i a F o 0: Packet-based (1 second period)

1: Rate-based
Me
0: Exclude BC frame
1: Include BC frame
29 STRM_MC_INC Unknown Multicast Storm Included
0: Exclude MC frame
1: Include MC frame
o r
ef
s
0: Exclude UC frame
27 STRM_DROP
1: Include UC frame
ele a
26 STRM_PERD
i a l R 1: Enable packet drop when BC storm is detected

e n t i
0: One second
1: 125us
25:24 STRM_UNIT
n f i d n a P
o
k C a n a 2'b10: 1 K packets or 1 Mbps

i a T e o r B
M e d F
Page 93 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i The broadcast storm rate limit for 1000 Mbps link speed
15:8
C o
STORM_100M
n a n 8'h1: (1* STORM_UNIT) packets or bps

T e k r B a The broadcast storm rate limit for 100 Mbps link speed
a
d i
7:0
F o
STORM_10M 10 Mbps Broadcast Storm Rate Limit Control
Me
00002134 P1_BSR_EXT2 Broadcast Storm Rate Control II of P1
f o r
00000000
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STRM_
Name
STRM_ STRM_
MODE BC_INC
MC_IN
C
STRM_ STRM_ STRM_
UC_INC DROP PERD
e l e a STRM_UNIT STORM_1G
R
Reset
Bit
0
15
0
14
0
13
t i a l 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
i d e n STORM_100M
P i RW
STORM_10M
RW
Reset 0
o
0
n f 0
a n a
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
e k C
STRM_MODE
B a n Description
T
d
30
i a F o r
STRM_BC_INC
1: Rate-based
Me
0: Exclude BC frame
1: Include BC frame
0: Exclude MC frame
1: Include MC frame
o r
ef
0: Exclude UC frame
1: Include UC frame
a s
ele
26 STRM_PERD
i a l R Broadcast Strom Detection Signal Period

0: One second
25:24 STRM_UNIT
e n t i
1: 125us
d
o n f i n a P 2'b01: 256 packets or 256 Kbps

23:16
k C
STORM_1G
a n a 2'b11: 4 K packets or 4 Mbps

i a T e o r B
M e d F
Page 94 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
15:8
o
STORM_100M


a o
d i F The broadcast storm rate limit for 10 Mbps link speed
Me
00002138
Bit 31
P1_BSR_EXT3
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17
r
00000000
16
se
STRM_
a
Name MC_IN STRM_UNIT STORM_1G
e
C
Type
Reset
RW
0
RW
0
RW
0
RW
R0
e l RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
15 14 13
t i a l 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Type
Reset 0 0
i d e n0
P i0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
o n f a n a Description
31
e k C
STRM_MODE
B a n Broadcast Storm Suppression

T r
1: Rate-based
30
d i a o
STRM_BC_INC
F
0: Exclude BC frame
Me
1: Include BC frame
0: Exclude MC frame
1: Include MC frame
r
o
0: Exclude UC frame
ef
1: Include UC frame
s
26 STRM_PERD
ele a
i a l R 0: One second
1: 125us
25:24 STRM_UNIT
e n t i
n f i d n a P
o
23:16
C
STORM_1G
k a n a 1000 Mbps Broadcast Storm Rate Limit Control

i a T e o r B
M e d F
Page 95 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
15:8
n
STORM_100M
f i d a P i 8'h1: (1* STORM_UNIT) packets or bps

C o n a n The broadcast storm rate limit for 100 Mbps link speed
7:0
T e k
STORM_10M
r B a 8'h1: (1* STORM_UNIT) packets or bps

a o
d i F
Me

Bit
Name
31 30 29 28 27 26 25 24 23
REV0
22 21
ARL_UPW
20 19
REV1
18
f o r
17
PORT_UPW
16
se
Type RW RW RW RW
Reset
Bit 15 14 13 12 11 10 9 8
0
7
0
6
1
5
e l
0
4
e a 0
3
0
2
1
1
1
0
R
Name REV2 DSCP_UPW REV3 TAG_UPW REV4 STAG_UPW REV5 ACL_UPW
Type
Reset
RW
0 1
t
RW
i
0
a l 0
RW
0 1
RW
0 1
RW
0 1
RW
1 0
RW
0 1
RW
1 1
Bit(s) Name
23
22:20
REV0
o n
ARL_UPW
f a n a Reserved
ARL User Priority Weight (MAC/DIP Hit)
19
18:16
e k C
REV1
PORT_UPW
B a n
Reserved
Port-Based User Priority Weight Value
d i
15
a T
14:12
11
REV2
F o r
DSCP_UPW
REV3
Reserved
DSCP Priority Weight (IPv4)
Reserved
M e 10:8
7
6:4
3
TAG_UPW
REV4
STAG_UPW
REV5
Priority Tag User Priority Weight
Reserved
Special Tag User Priority Weight
Reserved
2:0 ACL_UPW ACL User Priority Weight (ACL Hit)
o r
00002144 P1_PEM1 User Priority Egress Mapping I of P1
a s ef
10080480
le
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
REV0
RW
TAG_PRI_1
RW
l R e QUE_PFCR_1
RW
QUE_PFCT_1
RW
DSCP_PRI_1
RW
Reset
Bit
0
15
0
14
n t i
0
13
a 1
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
0
2
0
1
0
0
Name
Type
REV1
RW
f i d eTAG_PRI_0
RW
a P i
QUE_PFCR_0
RW
QUE_PFCT_0
RW
DSCP_PRI_0
RW
Reset
n n
0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
M ed F
Page 96 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
31 REV0 Reserved
30:28
27:25
TAG_PRI_1
QUE_PFCR_1
n f i d a P i User Priority 1 Priority Tag Value

24:22
21:16
C o
QUE_PFCT_1
DSCP_PRI_1
n a n User Priority 1 PFC TX Mapping

k a
15 REV1 Reserved
e B
11:9
i
8:6
d
5:0
a T o r
QUE_PFCR_0
QUE_PFCT_0
F
DSCP_PRI_0
Me 00002148
Bit 31
P1_PEM2
30 29 28 27 26
25 24 23 22 21 20 19 18
36D82250
17 16
Name
Type
REV0
RW
TAG_PRI_3
RW
QUE_PFCR_3
RW
QUE_PFCT_3
RW
DSCP_PRI_3
RW
f o r
Reset
Bit
0
15
0
14
1
13
1
12
l e a
0
11
1
10
1
9
0
8
1
7
1
6
0
5
1
4
1
3
0
2
se 0
1
0
0
e
Type
Reset
RW
0 0
RW
1
i a l R0 0
RW
0 1 0
RW
0 1 0 1 0
RW
0 0 0
Bit(s) Name
e n t i
Description
31
30:28
REV0
n
TAG_PRI_3
f i d n a P
Reserved
o
24:22
21:16
k C
QUE_PFCT_3
DSCP_PRI_3
a n a User Priority 3 PFC TX Mapping

15
14:12
i a T e
REV1
o r
TAG_PRI_2
B Reserved
F
Me d
8:6
5:0
QUE_PFCT_2
DSCP_PRI_2
0000214C P1_PEM3 User Priority Egress Mapping III of P1 5B684920

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
Type
s
RW RW RW RW RW
Reset
Bit
0
15
1
14
0
13
e
1
12
1
11
0
10
1
9
1
8
0
7
1
6
1
5
0
4
le a 1
3
0
2
0
1
0
0
R
Type
Reset
RW
0 1
t i a
RW
0
l 0 1
RW
0 0 1
RW
0 0 1 0 0
RW
0 0 0
Bit(s) Name
31
30:28
o n
REV0
f
TAG_PRI_5
a n a Reserved
27:25
24:22
e k CQUE_PFCR_5
a
QUE_PFCT_5
B n
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
15
14:12
REV1
TAG_PRI_4
11:9
8:6
C o
QUE_PFCR_4
QUE_PFCT_4
n a n User Priority 4 Egress Queue Selection or PFC RX Mapping

k a
i a T e o r B
Me d
00002150
Bit
Name
Type
31
REV0
RW
F P1_PEM4
30 29
TAG_PRI_7
RW
28 27 26
QUE_PFCR_7
RW
25 24 23
QUE_PFCT_7
RW
22 21 20 19
DSCP_PRI_7
RW
18
7FF86DB0
17 16
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
Bit
Name
15
REV1
14 13
TAG_PRI_6
12 11 10
QUE_PFCR_6
9 8 7
QUE_PFCT_6
6 5 4 3
DSCP_PRI_6
2
f o
1
r 0
se
Type RW RW RW RW RW
a
Reset 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0
Bit(s) Name
R e l e Description
31
30:28
REV0
TAG_PRI_7
t i a l Reserved
n
e
21:16
15
DSCP_PRI_7
REV1
n f i d a P i User Priority 7 DSCP Value

Reserved
14:12
11:9
C o
TAG_PRI_6
QUE_PFCR_6
n a n User Priority 6 Priority Tag Value

k a
5:0
i a T e
DSCP_PRI_6
o r B User Priority 6 DSCP Value
Me d
00002200
Bit
Name
31
F P2_SSC
30 29 28 27 26
25 24
REV0
23 22 21 20 19 18 17
0000FFFF
16
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FID7_PST FID6_PST FID5_PST FID4_PST FID3_PST FID2_PST FID1_PST FID0_PST
a s RW RW
ele
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s)
31:16
Name
REV0
i a l R Description
Reserved
15:14
13:12
FID7_PST
FID6_PST
e n t i
11:10
9:8
FID5_PST
n
FID4_PST
f i d n a P
o
5:4
3:2
k C
FID2_PST
FID1_PST
a n a (Rapid) Spanning Tree Protocol Port State

i a T e o r B
M e d F
Page 98 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i
00002204
C oP2_PCR
n a n Port Control of P2 00FF2000
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
i a T e
REV0
o r B
MLDv2
_EN
d F
Me
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_ PORT_
UP2DS UP2TA ACL_E ACL_MI VLAN_
Name REV2 TX_MI RX_MI MIS_PORT_FW REV3 PORT_VLAN
CP_EN G_EN N R MIS
R R
Type
Reset 0
RW
0 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0
RW
0
RW
0
f o r
0
RW
0
Bit(s)
31
Name
REV0
l e a Description
Reserved se
30 MLDv2_EN
l R e IPv6 MLDv2 source address multicast forwarding enable

0: Disable
a
1: Enable
29:28 EG_TAG
e n t i Port-Based Egress VLAN Tag Attribution

2'b00: Untagged
n f i d a P i 2'b01: Swap
2'b10: Tagged
27 REV1
C o n a n 2'b11: Stack
Reserved
k a
26:24 PORT_PRI Port-based User Priority
23:16
i a T e r B
PORT_MATRIX
o
Port Matrix Member
F
Me d
15:13 REV2
member.
port.
Reserved
12 UP2DSCP_EN User Priority to DSCP Enable
o r
ef
0: Disable
1: Enable
11 UP2TAG_EN User Priority to Tag Enable
a s
ele
Replace 802.Q priority by user priority
0: Disable
10 ACL_EN
i a l R 1: Enable
t
9 PORT_TX_MIR
i d e n P i
1: Lookup the ACL Table and take the corresponding actions.
Port Tx Mirror Enable
f
C o n a n a [NOTE] Multi-port support is possible.

0: Disable
e k B
PORT_RX_MIR
a n 1: Enable
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
0: Disable
C o
ACL_MIR
n a n 1: Enable
T e k r B a Frames are copied to Mirror port when the ACL table is enabled and the
a o
0: Disable
d i F
1: Enable
Me
mismatched
f
o r
se
excluded.)
3 REV3
e l e a 3'b111: Frame dropped

Reserved
R
2 VLAN_MIS VLAN Mismatch to Mirror Port
l
1'b0: Frame processed according to PORT_VLAN.
1:0 PORT_VLAN
n t i a 1'b1: VLAN mismatched frame copied to MIRROR port.

e
n f i d a P i Member.
C o n a n not belong to the VLAN member. Each frame whose VID is not listed on
k a
i a T e o r B not belong to the VLAN member. But, discard frames if VID is missed on
the VLAN table.
Me d F ingress membership violation or VID missed on the VLAN table.
00002208 P2_PIC Port IGMP Control of P2 00008000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGMP_
o r
ef
Name REV0 IGMP_MIS
MIR
s
Type RO RW RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
ele
0
4
a 0
3
0
2
0
1
0
0
R
IPM_22
l
44
Type RW
VE
n t i
AVE
a
RW RW RW
N
RW
EN
RW
N
RW
N N
RW
EN N
RW
EN
RW RW RW RW RW RW
e
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31:20
19
REV0
C o
IGMP_MIR
k a n a Reserved
i a T e o r B
M e d F
Page 100 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
port.
n
C o n a n on a per-port basis.
0: Disable
18:16
T e k
IGMP_MIS
r B a 1: Frame copied to Mirror port

a
d i F o mismatched.
Me
r
excluded.)
f o
se
15:14 ROBUST_VAR
e l e a Robustness Variable
consecutively.
i a l R 0: Unlimited (No Age out)

1: One time
e n t i
3: Three times
13 MLD_HW_LEAVE
n f i d n a P
MLD HW Leave Enable
o
k C a n a group-specific query.
0: Disable
12
i a T e r B
IGMP_HW_LEAVE
o
1: Enable
IGMP HW Leave Enable
F
Me d incoming port will be removed on the specific group address without a

0: Disable
1: Enable
11 REV1 Reserved
r
10 IPM_2244 IP Multicast frame for DIP is Class D:224.x.x.x to 239.x.x.x
ef o
s
9 IPM_33 IP Multicast frame for MAC DA is 33-33-xx-xx-xx-xx
8 IPM_01 a
ele
IP Multicast frame for MAC DA is 01-00-5E-xx-xx-xx
i a l R 0: This frame is regarded as normal multicast and search ADDR Table.

7 MLD2_JOIN_EN
e n t i
MLD v2 HW Join Enable
n f i d n a P
TO_EX().
o
0: Disable
k C
IGMP3_JOIN_EN
a n a 1: Enable
IGMP v3 HW Join Enable
i a T e o r B
M e d F
Page 101 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
TO_EX().
1: Enable
5
T e k
MLD_JOIN_EN
r B a MLD Snooping HW Join Enable

a
multicast frame.
d i F o 1: This port is capable of recognizing the MLD message and multicast IPv6
Me
frames (FF00:/8).
4 IGMP_JOIN_EN IGMP Snooping HW Join Enable
0: Disable
r
1: Enable
3 MLD_SQRY_EN MLD HW Specific Query Enable
f o
se
2 IGMP_SQRY_EN
e l e a refresh the specific multicast member.

0: IGMP specific query message will not refresh the IP multicast table.
i a l R 1: This port is capable of recognizing the IGMP specific query message to

1 MLD_GQRY_EN
e n t i
MLD HW General Query Enable
d
n f
IGMP_GQRY_EN
o i n a P refresh the multicast member.

k C a n a 0: IGMP general Query message will not refresh the IP multicast table.
e B
d i a T F o r
Me
0000220C P2_PSC Port Security Control of P2 000FFF00
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SA_LRN_CNT MAC_SA_LRN
Type RO RW
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
ef o1
TX_PO RX_PO
0
s
SA_CN
Name MAC_SA_LRN REV0 SA_DIS SA_LOCK RT_LOC RT_LO
a
T_EN
K CK
ele
Type RW RW RW RW RW RW RW
R
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bit(s) Name
t i a l Description
31:20
19:8
SA_LRN_CNT
MAC_SA_LRN
i d e n P i
Learned Source Address Number
o n f a n a
set.
e k C B a n 12'h1:
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
12'hFFE: 1 to 4094 address table
7:6 REV0
n f i d a P i 12'hFFF: SA Learning without limitation

Reserved
5
C o
SA_CNT_EN
n a n SA Counter Enable
1: Enable
a o
4 SA_DIS SA Disable
d i F
Me
0: Enable
1: Disable
[NOTE] PAE frames should be passed and are not affected by SA Lock.
f o r
se
e l e a (PCR.PORT_MATRIX).
1 TX_PORT_LOCK
i a l R (VTC.GUEST_MEM)
Tx Port Lock Enable
e n t i
d
0
f
RX_PORT_LOCK
o n i n a P Rx Port Lock Enable

k C a n a 0: Receive authorized.
i a T e o r B
Me d
00002210
Bit
Name
Type
31
F P2_PVC
30 29 28 27 26
25 24
STAG_VPID
RW
23 22 21 20 19 18
810000C0
17 16
Reset 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r 0
ef
DIS_PV FORCE BC_LKY PT_OP PORT_ IPM_LK MC_LK UC_LKY
Name REV0 EG_TAG VLAN_ATTR ACC_FRM
ID _PVID V_EN TION STAG YV_EN YV_EN V_EN
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0 1
RW
1
RW
0
RW
0
le a s
RW
0
RW
0 0
RW
0
Bit(s) Name
l R e Description
31:16 STAG_VPID
n t i a Stack Tag VPID (VLAN Protocol ID) Value

e
n f i d a P i Outer VPID == STAG_VPID

C o n a n The outgoing frame will be added by the outer VLAN tag with the
k a
i a T e o r B
Med F
Page 103 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
14
o
FORCE_PVID
C n a n Force PVID on VLAN-tagged frames

13
T e k
BC_LKYV_EN
r B a 1: Force the replacement of VID with PVID.

a o
d i F 1: Broadcast frames received by this port can pass through VLAN.
Me
12 REV0 Reserved
3'b001: Consistent
f o r
se
a
3'b100: Untagged
R e l e 3'b101: Swap
3'b110: Tagged
3'b111: Stack
7:6 VLAN_ATTR
t i a l VLAN Port Attribute

2'b00: User port
i d e n P i
2'b01: Stack port
o n
PORT_STAG
f a n a
Special Tag Enable
e k C B a n
the remote port.
d
4
i a T F o r
IPM_LKYV_EN
1: Enable
Me
r
2 UC_LKYV_EN
ef o
a s
ele
1:0 ACC_FRM Acceptable Frame Type
R
t i a l 2'b01: Admit Only VLAN-tagged frames

n
2'b11: Reserved
f i d e a P i
00002214
Bit
C
31
o nP2_PPBV1
30
n a n29 28 27 26
25 24 23 22 21 20 19 18
00010001
17 16
Name
T e k B a
G1_PORT_PRI
r
REV0 G1_PORT_VID
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Type RW
n t i a RW RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit
Name
15
n
14
f i d 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
n
G0_PORT_PRI REV1 G0_PORT_VID
Type
Reset 0
k C o RW
0
a n a 0
RW
0 0 0 0 0 0 0
RW
0 0 0 0 0 1
a
Bit(s)
i T e
Name
o r B Description
Me d
31:29
28
27:16
REV0F
G1_PORT_PRI
G1_PORT_VID
Reserved
15:13 G0_PORT_PRI Group 0 Port Priority (Default Port Priority)
r
12 REV1
definition
Reserved
f o
se
11:0 G0_PORT_VID Group 0 Port VLAN ID (Default Port VID)
e l e a The Group 0 and default VID for each port according to IEEE 802.1Q
definition
i a l R
t
Bit
Name
31 30
i d e
G3_PORT_PRI
n 29
P i
28
REV0
27 26 25 24 23 22
G3_PORT_VID
21 20 19 18 17 16
Type
Reset 0
o n f
RW
0
a n0
a
RW
0 0 0 0 0 0 0
RW
0 0 0 0 0 1
Bit
Name
e
15
k C 14
a n
G2_PORT_PRI
B
13 12
REV1
11 10 9 8 7 6
G2_PORT_VID
5 4 3 2 1 0
T r
Type RW RW RW
d i
Reset
a 0
F o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Me
28 REV0 Reserved
r
15:13 G2_PORT_PRI
ef o
s
12
11:0
REV1
G2_PORT_VID
Reserved
ele a
i a l R
0000221C P2_BSR
e n t i
Broadcast Storm Rate Control of P2 00000000
d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
o n f i
STRM_ STRM_
STRM_
MC_IN
a P
STRM_ STRM_ STRM_
n
STRM_UNIT STORM_1G
a
C
C
Type
e k
RW
B
RW
a n RW RW RW RW RW RW
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Reset 0 0
n
0
t i a 0 0 0 0 0 0 0 0 0 0 0 0 0
e i
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
n f i d n a P
STORM_100M
RW
STORM_10M
RW
Reset 0
k C o0
a n a
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
i a T e
Name
o r
STRM_MODE
B Description
d F
Me
1: Rate-based
0: Exclude BC frame
1: Include BC frame
0: Exclude MC frame
1: Include MC frame
f o r
se
0: Exclude UC frame
27 STRM_DROP
e l e a 1: Include UC frame
R
26 STRM_PERD
t i a l 1: Enable packet drop when BC storm is detected

i d e n P i
0: One second
1: 125us
f
C o n a n a 2'b00: 64 packets or 64 Kbps

e k B a n 2'b10: 1 K packets or 1 Mbps

23:16
d i a T STORM_1G
F o r 1000 Mbps Broadcast Storm Rate Limit Control

Me
r
ef o
s
ele a
00002220 P2_STAG01
i a l R STAG Index 0/1 of P2 00000000

Bit
Name
31 30
e n t 29
i
28
REV0
27 26 25 24 23 22 21 20
VID1
19 18 17 16
Type
Reset 0
n f i
0
d n a
0
P 0
RO
0 0 0 0 0 0 0 0
RW
0 0 0 0
Bit
Name
k C o
15 14
a n a
VID1
13 12 11 10 9 8 7 6
VID0
5 4 3 2 1 0
i a T e o r B
Med F
Page 106 of 830
f o r
l e a se MT7531
l R e Lynx1
Type RW
n t i a RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31:24
23:12
REV0
VID1
k C o a n a Reserved
e B
d i a T F o r
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name REV0 VID3
Type RO RW
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o1 0
se
Name VID3 VID2
a
Type RW RW
Reset 0 0 0
R
0
e l e 0 0 0 0 0 0 0 0 0 0 0 0
l
31:24
23:12
REV0
VID3
n t i a Reserved
e
n f i d a P i
00002228
C oP2_STAG45
n a n STAG Index 4/5 of P2 00000000
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
i a T e o r B REV0
RO
VID5
RW
Me d
Reset
Bit
Name
Type
0
15
F 0
14
VID5
RW
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
VID4
RW
0
5
0
4
0
3
0
2
0
1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
31:24 REV0 Reserved
a s
ele
0000222C P2_STAG67
i a l R STAG Index 6/7 of P2 00000000

Bit 31 30
e n t 29
i
28 27 26 25 24 23 22 21 20 19 18 17 16
d
Name REV0 VID7
Type
Reset 0
o n f
0
i n
0
a P 0
RO
0 0 0 0 0 0 0 0
RW
0 0 0 0
Bit
Name
k C
15 14
a n a
VID7
13 12 11 10 9 8 7 6
VID6
5 4 3 2 1 0
i a T e o r B
M e d F
Page 107 of 830
f o r
l e a se MT7531
l R e Lynx1
Type RW
n t i a RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31:24
23:12
REV0
VID7
k C o a n a Reserved
e B
d i a T F o r
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STRM_
C
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0
f o0
r 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
STORM_100M
e l e
RW
a STORM_10M
RW
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
t i a l Description
31 STRM_MODE
i d e n P i
30
o n f
STRM_BC_INC
a n a
1: Rate-based
C
0: Exclude BC frame
29
e k B
STRM_MC_INC
a n 1: Include BC frame
d i a T F o r 0: Exclude MC frame
1: Include MC frame
Me
0: Exclude UC frame
1: Include UC frame
o r
ef
0: One second
1: 125us
a s
ele
R
t i a l 2'b10: 1 K packets or 1 Mbps

23:16 STORM_1G
i d e n P i
f
15:8
o n
STORM_100M
C a n a 8'h1: (1* STORM_UNIT) packets or bps

e k B a n The broadcast storm rate limit for 100 Mbps link speed
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
7:0 STORM_10M
n f i d a P i 10 Mbps Broadcast Storm Rate Limit Control

C o n a n 8'h0: (0* STORM_UNIT) packets or bps

T e k r B a
i a
00002234
d F oP2_BSR_EXT2 Broadcast Storm Rate Control II of P2 00000000
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STRM_
C
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
f o
0
1
r 0
0
se
a
Type RW RW
Reset 0 0 0
R
0
e l e 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
STRM_MODE
t i a l Description
n
30
f
STRM_BC_INC
i d e a P i
1: Rate-based
n
0: Exclude BC frame
29
C o
STRM_MC_INC
n a n 1: Include BC frame
T e k r B a 0: Exclude MC frame
1: Include MC frame
28
d i a o
STRM_UC_INC
F
0: Exclude UC frame
Me
1: Include UC frame
0: One second
o r
ef
1: 125us
s
ele a
23:16 STORM_1G
i a l R 2'b11: 4 K packets or 4 Mbps

e n t i
15:8
f
STORM_100M
n i d n a P
o
k C a n a 8'h0: (0* STORM_UNIT) packets or bps

i a T e o r B
M e d F
Page 109 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i The broadcast storm rate limit for 10 Mbps link speed

C o n a n 8'h1: (1* STORM_UNIT) packets or bps
00002238
T e k r B a
P2_BSR_EXT3 Broadcast Storm Rate Control III of P2 00000000
d i
Bit
a 31
F o30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
STRM_
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2
f o
1
r 0
se
Type RW RW
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
R e l e Description
31 STRM_MODE
t i a l Broadcast Storm Suppression

n
1: Rate-based
30 STRM_BC_INC
f i d e a P i
0: Exclude BC frame
n
1: Include BC frame
29
o
STRM_MC_INC
C n a n Unknown Multicast Storm Included

0: Exclude MC frame
28
T e k r B
STRM_UC_INC
a 1: Include MC frame
d i a F o 0: Exclude UC frame
1: Include UC frame
Me
0: One second
1: 125us
o r
ef
s
ele a
23:16 STORM_1G
i a l R 1000 Mbps Broadcast Storm Rate Limit Control

e n t i
15:8 STORM_100M
n f i d n a P
o
7:0
k C
STORM_10M
a n a 8'h1: (1* STORM_UNIT) packets or bps

i a T e o r B
M e d F
Page 110 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
C o n a n
00002240
T e k B
P2_UPW
r a User Priority Weight of P2 00234567
a o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d
Name
i F REV0 ARL_UPW REV1 PORT_UPW
Me
Type RW RW RW RW
Reset 0 0 1 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset
RW
0 1
RW
0 0
RW
0 1
RW
0 1
RW
0 1
RW
1 0
RW
0 1
f o r
RW
1 1
Bit(s)
23
Name
REV0
l e a Description
Reserved se
22:20
19
ARL_UPW
REV1
l R e ARL User Priority Weight (MAC/DIP Hit)

Reserved
18:16 PORT_UPW
n t i a Port-Based User Priority Weight Value

e
15 REV2 Reserved
14:12
11
DSCP_UPW
REV3
n f i d a P i DSCP Priority Weight (IPv4)

Reserved
n
10:8 TAG_UPW Priority Tag User Priority Weight
7
6:4
REV4
C o
STAG_UPW
k a n a Reserved
e B
3 REV5 Reserved
T r
d i a F o
Me 00002244
Bit
Name
31
REV0
P2_PEM1
30 29
TAG_PRI_1
28 27 26
QUE_PFCR_1
25 24 23
QUE_PFCT_1
22 21 20 19
DSCP_PRI_1
18
10080480
17 16
r
Type RW RW RW RW RW
Reset
Bit
0
15
0
14
0
13
1
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
0
2
ef
0
1
o 0
0
Name REV1 TAG_PRI_0 QUE_PFCR_0 QUE_PFCT_0
a s DSCP_PRI_0
ele
Type RW RW RW RW RW
Reset 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Bit(s) Name
i a l R Description
31
30:28
REV0
TAG_PRI_1
e n t i
Reserved
27:25
24:22
QUE_PFCR_1
f
QUE_PFCT_1
n i d n a P
o
15
14:12
k C
REV1
TAG_PRI_0
a n a Reserved
i a T e o r B
M e d F
Page 111 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
8:6
5:0
QUE_PFCT_0
DSCP_PRI_0
n f i d a P i User Priority 0 PFC TX Mapping

C o n a n
00002248
Bit
T e k
31
r
30
B
P2_PEM2
a 29 28 27 26
25 24 23 22 21 20 19 18
36D82250
17 16
d
Name
i a REV0
F o TAG_PRI_3 QUE_PFCR_3 QUE_PFCT_3 DSCP_PRI_3
Me
Type RW RW RW RW RW
Reset 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
r
RW RW RW RW RW
Reset
o
0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0
se f
a
e
31 REV0 Reserved
30:28
27:25
TAG_PRI_3
QUE_PFCR_3
R e l User Priority 3 Priority Tag Value

24:22
21:16
QUE_PFCT_3
DSCP_PRI_3
t i a l User Priority 3 PFC TX Mapping

n
15 REV1 Reserved
e
11:9
8:6
QUE_PFCR_2
QUE_PFCT_2
n f i d a P i User Priority 2 Egress Queue Selection or PFC RX Mapping

5:0
C o
DSCP_PRI_2
n a n User Priority 2 DSCP Value
0000224C
T e k r B
P2_PEM3a User Priority Egress Mapping III of P2 5B684920
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW RW RW RW RW
Reset 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW RW RW RW RW
o r
ef
Reset 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0
a s
ele
31 REV0 Reserved
30:28
27:25
24:22
TAG_PRI_5
QUE_PFCR_5
QUE_PFCT_5
i a l R User Priority 5 Priority Tag Value

21:16
15
DSCP_PRI_5
REV1
e n t i
Reserved
14:12
11:9
TAG_PRI_4
n f
QUE_PFCR_4
i d n a P
o
5:0
C
DSCP_PRI_4
k a n a User Priority 4 DSCP Value
i a T e o r B
M e d F
Page 112 of 830
f o r
l e a se MT7531
l R e Lynx1
n t i a
00002250
Bit 31
P2_PEM4
f i
30
d e 29
a P i 28 27 26
25 24 23 22 21 20 19 18
7FF86DB0
17 16
Name
Type
REV0
RW
C o n n a n
TAG_PRI_7
RW
QUE_PFCR_7
RW
QUE_PFCT_7
RW
DSCP_PRI_7
RW
k a
Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0
Bit
Name
i a T e15
REV1
o r B14 13
TAG_PRI_6
12 11 10
QUE_PFCR_6
9 8 7
QUE_PFCT_6
6 5 4 3
DSCP_PRI_6
2 1 0
Me d
Type
Reset
Bit(s)
RW
0
Name
F 1
RW
1 0 1
RW
1 0
Description
1
RW
1 0 1 1 0
RW
0 0 0
31 REV0 Reserved
r
o
24:22
21:16
QUE_PFCT_7
DSCP_PRI_7
se f
a
15 REV1 Reserved
14:12
11:9
8:6
TAG_PRI_6
QUE_PFCR_6
QUE_PFCT_6
R e l e User Priority 6 Priority Tag Value

5:0 DSCP_PRI_6
t i a l User Priority 6 DSCP Value
00002300
i
P3_SSC
d e n P i STP State Control of P3 0000FFFF

Bit 31
o n f30
a n
29
a 28 27 26 25 24 23 22 21 20 19 18 17 16
C
Name REV0
Type
Reset
e0
k B0
a n 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
Bit
d
Name
i a T 15
F o r
FID7_PST
14 13
FID6_PST
12 11
FID5_PST
10 9
FID4_PST
8 7
FID3_PST
6 5
FID2_PST
4 3
FID1_PST
2 1
FID0_PST
0
Me
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
r
31:16 REV0 Reserved
15:14
13:12
FID7_PST
FID6_PST
ef o
s
9:8
7:6
5:4
FID4_PST
FID3_PST
FID2_PST
ele a
3:2
1:0
FID1_PST
FID0_PST
i a l R (Rapid) Spanning Tree Protocol Port State

e n t i
00002304
Bit 31
n f i d
P3_PCR
30
n a
29
P 28 27 26
Port Control of P3
25 24 23 22 21 20 19 18
00FF2000
17 16
Name
k C
REV0
o MLDv2
_EN
a n a EG_TAG REV1 PORT_PRI PORT_MATRIX
e B
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Reset 0 0
n t
0
i a 0 0 0 0 0 1 1 1 1 1 1 1 1
e i
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
n
REV2
f i d n a P
UP2DS UP2TA ACL_E
CP_EN G_EN N
PORT_ PORT_
TX_MI RX_MI
ACL_MI
R
MIS_PORT_FW REV3
VLAN_
MIS
PORT_VLAN
o
R R
Type
Reset 0
k C RW
0
a n a 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0
RW
0
RW
0 0
RW
0
i a
Bit(s)
T e
Name
o r B Description
Me d
31
30
REV0
F
MLDv2_EN
Reserved
IPv6 MLDv2 source address multicast forwarding Enable
0: Disable
1: Enable
29:28 EG_TAG Port-Based Egress VLAN Tag Attribution
2'b00: Untagged
2'b01: Swap
2'b10: Tagged
f o r
se
2'b11: Stack
27
26:24
REV1
PORT_PRI
e l e a Reserved
23:16 PORT_MATRIX
i a l R Port Matrix Member

t
i d e n P i
member.
f
port.
15:13
12
REV2
o n
UP2DSCP_EN
C a n a Reserved
User Priority to DSCP Enable
e k B a n Replace DSCP according to user priority.

0: Disable
T r
1: Enable
11
d i a o
UP2TAG_EN
F
Me
0: Disable
1: Enable
10 ACL_EN Port-based ACL Enable
o r
ef
0: Disable
a s
ele
1: Enable
i a l R All frames received from this port are copied to the mirror port.
t
0: Disable
7 ACL_MIR
i d e n P i
1: Enable
f
C o n a n a frame does not match any ACL rule.

0: Disable
6:4
e k
MIS_PORT_FW
B a n 1: Enable
ACL Mismatch TO_CPU Forward
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
mismatched
n
C o n a n 3'b100: System default and CPU port excluded

T e k r B a 3'b110: CPU port only (As long as the ingress port is not the CPU port. If
a o
excluded.)
d i F
Me
3 REV3 Reserved
1'b1: VLAN mismatched frame copied to MIRROR port.
1:0 PORT_VLAN Port-based VLAN Mechanism Select
Member.
f o r
se
e l e a the VLAN table is forwarded based on the Port Matrix member.

not belong to the VLAN member. But, discard frames if VID is missed on
i a l R the VLAN table.

e n t i
00002308
n f i
P3_PIC
d n a P Port IGMP Control of P3 00008000
Bit
Name
31
k C o 30
a n a 29 28 27 26
REV0
25 24 23 22 21 20 19
IGMP_
18 17
IGMP_MIS
16
e B
MIR
Type
d i
Reset
a T 0
F o r 0 0 0 0 0
RO
0 0 0 0 0 0
RW
0 0
RW
0 0
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPM_22
44
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
r
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ef o
31:20 REV0 Reserved
a s
ele
19 IGMP_MIR IP Multicast IGMP Table Mismatch to Mirror Port
i a l R port.
t
n
0: Disable
18:16 IGMP_MIS
f i d e a P i
C o n n a n
mismatched.
T e k r B a on a per-port basis.
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 3'b100: System default and CPU port excluded

C o n a n 3'b110: CPU port only (As long as the ingress port is not the CPU port. If
T e k r B a excluded.)
a o
d i F
Me
consecutively.
1: One time
3: Three times
13 MLD_HW_LEAVE MLD HW Leave Enable
f o r
se
e l e a 0: Disable
1: Enable
R
t i a l Enable HW IGMP Leave snooping and fast leave. The corresponding

i d e n P i
0: Disable
1: Enable
11
10
REV1
o
IPM_2244
n f a n a IP Multicast frame for DIP is Class D:224.x.x.x to 239.x.x.x
e k C
IPM_33
B a n
d i a T F o r 0: This frame is regarded as normal multicast and search ADDR table.

Me
o r
ef
TO_EX().
0: Disable
1: Enable
a s
ele
6 IGMP3_JOIN_EN IGMP v3 HW Join Enable
R
l
TO_EX().
n t i a 0: Disable
1: Enable
5 MLD_JOIN_EN
f i d e a P i
MLD Snooping HW Join Enable
multicast frame.
C o n n a n 1: This port is capable of recognizing the MLD message and multicast IPv6
frames (FF00:/8).
k a
i a T e o r B
M e d F
Page 116 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
0: Disable
C o
MLD_SQRY_EN
n a n 1: Enable
T e k r B a 0: MLD specific query message will not refresh the IP multicast table.
a o
d
2
i F
IGMP_SQRY_EN IGMP HW Specific Query Enable
Me
r
0 IGMP_GQRY_EN
f o
se
e l e a 1: This port is capable of recognizing the IGMP general query message to

i a l R
0000230C
Bit 31
P3_PSC
30
e n t
29
i
28 27 26
25 24 23 22 21 20 19 18
000FFF00
17 16
Name
Type
n f i d n a P
SA_LRN_CNT
RO
MAC_SA_LRN
RW
Reset
Bit
0
15
k C o 0
14
a n a
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
1
3
1
2
1
1
1
0
e B
TX_PO RX_PO
SA_CN
T r
T_EN
d
Type
i a F o RW RW RW RW RW
K
RW
CK
RW
Me
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

31:20 SA_LRN_CNT Learned Source Address Number
r
19:8 MAC_SA_LRN Rx SA Allowable Learning Number
set.
ef o
s
12'h1:
ele a
R
7:6
5
REV0
SA_CNT_EN
t i a l Reserved
SA Counter Enable
i d e n P i
0: Disable
1: Enable
4 SA_DIS
o n f a n a SA Disable
e k C B a n
0: Enable
1: Disable
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i [NOTE] PAE frames should be passed and are not affected by SA Lock.
C o n a n 2'b01: All received frames whose SA look-up is missing or are not port
k a
i a T e o r B members in the ARL are forwarded to some Port Matrix Members

(PCR.PORT_MATRIX).
Me d1 F
TX_PORT_LOCK
(VTC.GUEST_MEM)
Tx Port Lock Enable
0 RX_PORT_LOCK Rx Port Lock Enable
f o r
se
a
R e l e
00002310
Bit 31
P3_PVC
30
t
29
i a l 28 27 26
25 24 23 22 21 20 19 18
810000C0
17 16
Name
Type
i d e n P i
STAG_VPID
RW
Reset
Bit
1
15
o n
14
f0
a n
0
13
a 0
12
0
11
0
10
0
9
1
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
ID
e k C
DIS_PV FORCE BC_LKY
_PVID V_EN
B a n
REV0
PT_OP
TION
EG_TAG VLAN_ATTR
ACC_FRM
T
Type RW RW RW RW RW
r
RW RW RW RW RW RW RW
d i
Reset
a 0
F o
0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Me
31:16 STAG_VPID Stack Tag VPID (VLAN Protocol ID) Value
r
o
ef
s
a
ele
14 FORCE_PVID
i a l R 1: Keep VID=0 for priority-tagged frames.

t
13 BC_LKYV_EN
i d e n P i
o n f a n a
C
12 REV0 Reserved
11
e k
PT_OPTION
B a n Pass-through capability on TX special tag
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
10:8 EG_TAG
n f i d a P i 1: Enable pass-through on TX special tag

C o n a n 3'b000: System default (disabled)

3'b001: Consistent
T e k r B a 3'b010, 3'b011: Reserved

3'b100: Untagged
d i a F o
3'b101: Swap
3'b110: Tagged
Me
3'b111: Stack
2'b00: User port
2'b01: Stack port
5 PORT_STAG
Special Tag Enable
f o r
se
a
the remote port.
4 IPM_LKYV_EN
R e l e 0: No special tag format for Tx/Rx

1: Enable
t i a l (note*) If MC_LKYV_EN is set, this field will become "don't care" bit. All
i d e n P i
3 MC_LKYV_EN
o n f a n a
Multicast Leaky VLAN Enable
C
2
k
UC_LKYV_EN
e B a n Unicast Leaky VLAN Enable

d i
1:0
a T F o
ACC_FRM
r 1: Unicast frame received by this port can pass through VLAN.
Acceptable Frame Type
Me
2'b11: Reserved
o r
ef
00002314 P3_PPBV1 Port-and-Protocol Based VLAN I of P3 00010001
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Type RW RW RW
Reset
Bit
0
15
0
14
i a
0
13
l R 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
Name
Type RW
e n t
G0_PORT_PRI
i
REV1
RW
G0_PORT_VID
RW
Reset 0
n f i d0
n a
0
P
0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s)
31:29
k C o
Name
G1_PORT_PRI
a n a Description
e B
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
28 REV0 Reserved
27:16 G1_PORT_VID
n f i d a P i Group 1 Port VLAN ID (optional)

15:13
C o
G0_PORT_PRI
n a n Group 0 Port Priority (Default Port Priority)

k a
definition
e B
12 REV1 Reserved
11:0
d i a T F o r
G0_PORT_VID Group 0 Port VLAN ID (Default Port VID)
definition
Me 00002318
Bit 31
P3_PPBV2
30 29 28 27 26
25 24 23 22 21 20 19 18
00010001
17 16
Name
Type
G3_PORT_PRI
RW
REV0
RW
G3_PORT_VID
RW
f o r
Reset
Bit
0
15
0
14
0
13
0
12
l e a
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
se 0
1
1
0
e
Type
R
RW RW RW
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit(s)
31:29
Name
G3_PORT_PRI
i d e n P i
Description
28 REV0
o n f a n a
Reserved
C n
k a
15:13
12
i a T e
REV1
o B
G2_PORT_PRI
r
Reserved
Me d
11:0
F
G2_PORT_VID Group 2 Port VLAN ID (optional)
0000231C P3_BSR Broadcast Storm Rate Control of P3 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
STRM_
s
a
C
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
i a l R 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Type
Reset 0 0
e n t 0
i
0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
n f i d n a P
o
31
k C
STRM_MODE
a n a Broadcast Storm Suppression

i a T e o r B
M e d F
Page 120 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
1: Rate-based
30 STRM_BC_INC
n f i d a P i Broadcast Storm Included

0: Exclude BC frame
29
C o
STRM_MC_INC
n a n 1: Include BC frame
T e k r B a 0: Exclude MC frame
1: Include MC frame
a o
d i F 0: Exclude UC frame
Me
1: Include UC frame
0: One second
1: 125us
f o r
se
a
R e l e 2'b01: 256 packets or 256 Kbps

23:16 STORM_1G
t i a l 1000 Mbps Broadcast Storm Rate Limit Control

i d e n P i
15:8 STORM_100M
o n f a n a
C
7:0
e k
STORM_10M
B a n 8'h1: (1* STORM_UNIT) packets or bps

d i a T F o r The broadcast storm rate limit for 10 Mbps link speed

Me 00002320 P3_STAG01 STAG Index 0/1 of P3 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
REV0
RO
VID1
RW
ef o
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
le a s 0
3
0
2
0
1
0
0
e
Name VID1 VID0
Type
Reset 0 0
RW
i a
0
l R 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:24
23:12
REV0
n
VID1
f i d n a P
Reserved
11:0
k C o
VID0
a n a
i a T e o r B
Med F
Page 121 of 830
f o r
l e a se MT7531
l R e Lynx1
00002324 P3_STAG23
n t i a STAG Index 2/3 of P3 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
n f i d a P i REV0 VID3
n
Type RO RW
Reset
Bit
0
15
k C o 0
14
a n a 0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
i a T e o r B
VID3
RW
VID2
RW
F
Reset
d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me Bit(s)
31:24
23:12
11:0
Name
REV0
VID3
VID2
Description
Reserved
f o r
00002328
Bit 31
P3_STAG45
30 29 28
l e a 27 26
25 24 23 22 21 20 19
se
18
00000000
17 16
Name
Type
l R e REV0
RO
VID5
RW
Reset
Bit
0
15
0
14
n
0
t
13
i a 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
f iRW
e
VID5
d a P i
VID4
RW
Reset
n n
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
k
Name
C o a n a Description
31:24
23:12
i a T e
REV0
VID5
o r B Reserved
F
Me d
0000232C P3_STAG67 STAG Index 6/7 of P3 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name REV0 VID7
o r
ef
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
a s 3 2 1 0
ele
Name VID7 VID6
Type RW RW
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:24
Name
REV0
e n t i
Description
Reserved
23:12
11:0
VID7
VID6
n f i d n a P
k C o a n a
i a T e o r B
M e d F
Page 122 of 830
f o r
l e a se MT7531
l R e Lynx1
00002330 P3_BSR_EXT1
n t i a Broadcast Storm Rate Control I of P3 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
STRM_ STRM_
n f
STRM_
MC_IN
i d a P i
STRM_ STRM_ STRM_
STRM_UNIT STORM_1G
n
o
C
Type
Reset
RW
0
k C RW
0
a n a
RW
0
RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
i a T e15
o r
14
B 13 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Me d
Type
Reset
Bit(s)
0
Name
F 0 0 0
RW
0 0 0
Description
0 0 0 0 0
RW
0 0 0 0

1: Rate-based
f o r
se
0: Exclude BC frame
29 STRM_MC_INC
e l e a 1: Include BC frame
i a l R 0: Exclude MC frame
1: Include MC frame
t
i d e n P i
0: Exclude UC frame
1: Include UC frame
f
C o n a n a 0: BC Storm detection only

26 STRM_PERD
e k B a n Broadcast Strom Detection Signal Period

0: One second
i
25:24
d a T F o r
STRM_UNIT
1: 125us
Me
r
ef o
a s
ele
7:0 STORM_10M
i a l R 10 Mbps Broadcast Storm Rate Limit Control

e n t i
n f i d n a P
00002334
Bit
k C
31 o 30
a n a
P3_BSR_EXT2
29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
i a T e o r B
M e d F
Page 123 of 830
f o r
l e a se MT7531
l R e Lynx1
STRM_ STRM_
STRM_
n t i a
STRM_ STRM_ STRM_
e
i
d
C
Type
Reset
RW
0
o
RW
n
0
f i RW
0
n a P
RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
15
k C 14
a n a
13 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Type
i
Reset
a T e 0
o r
0
B 0 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Me d
Bit(s)
31
NameF
STRM_MODE
Description
1: Rate-based
0: Exclude BC frame
f o r
se
1: Include BC frame
e l e a 0: Exclude MC frame
1: Include MC frame
R
t i a l 0: Exclude UC frame
1: Include UC frame
n
f i d e a P i
26
C o n
STRM_PERD
n a n
0: One second
1: 125us
25:24
T e k
STRM_UNIT

d i a F o 2'b01: 256 packets or 256 Kbps

Me
o r
ef
a s
ele
i a l R 8'h0: (0* STORM_UNIT) packets or bps

e n t i
00002338
f i d
P3_BSR_EXT3
n n a P Broadcast Storm Rate Control III of P3 00000000
o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
k C a n a
i a T e o r B
M e d F
Page 124 of 830
f o r
l e a se MT7531
l R e Lynx1
STRM_ STRM_
STRM_
n t i a
STRM_ STRM_ STRM_
e
i
d
C
Type
Reset
RW
0
o
RW
n
0
f i RW
0
n a P
RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
15
k C 14
a n a
13 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Type
i
Reset
a T e 0
o r
0
B 0 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Me d
Bit(s)
31
NameF
STRM_MODE
Description
1: Rate-based
0: Exclude BC frame
f o r
se
1: Include BC frame
e l e a 0: Exclude MC frame
1: Include MC frame
R
1: Include UC frame
n
f i d e a P i
26
C o n
STRM_PERD
n a n
0: One second
1: 125us
25:24
T e k
STRM_UNIT

d i a F o 2'b01: 256 packets or 256 Kbps

Me
o r
ef
a s
ele
i a l R 8'h0: (0* STORM_UNIT) packets or bps

e n t i
00002340
f i
P3_UPW
n d n a P User Priority Weight of P3 00234567
o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
k C a n a REV0
RW
ARL_UPW
RW
REV1
RW
PORT_UPW
RW
i a T e o r B
M e d F
Page 125 of 830
f o r
l e a se MT7531
l R e Lynx1
Reset
n t i a 0 0 1 0 0 0 1 1
Bit
Name
15
REV2
14
f i d e 13
DSCP_UPW
a P i
12 11
REV3
10 9
TAG_UPW
8 7
REV4
6 5
STAG_UPW
4 3
REV5
2 1
ACL_UPW
0
Type
Reset
RW
0
C o n
1
n
RW
a0
n 0
RW
0 1
RW
0 1
RW
0 1
RW
1 0
RW
0 1
RW
1 1
Bit(s)
T e k
Name
r B a Description
a o
23 REV0 Reserved
d i
22:20
F
ARL_UPW ARL User Priority Weight (MAC/DIP Hit)
Me
19 REV1 Reserved
15 REV2 Reserved
r
11 REV3 Reserved
10:8
7
TAG_UPW
REV4
Priority Tag User Priority Weight
Reserved
f o
se
6:4 STAG_UPW Special Tag User Priority Weight
3
2:0
REV5
ACL_UPW
e l e a Reserved
i a l R
t
00002344 P3_PEM1 User Priority Egress Mapping I of P3 10080480
Bit
Name
31
REV0
30
i d e n
29
TAG_PRI_1
P
28
i
27 26
QUE_PFCR_1
25 24 23
QUE_PFCT_1
22 21 20 19
DSCP_PRI_1
18 17 16
Type
Reset
RW
0
o n
0
f RW
a
0
n a 1 0
RW
0 0 0
RW
0 0 0 0 1
RW
0 0 0
Bit
Name
15
k
REV1
e C 14
B a n
13
TAG_PRI_0
12 11 10
QUE_PFCR_0
9 8 7
QUE_PFCT_0
6 5 4 3
DSCP_PRI_0
2 1 0
T r
Type RW RW RW RW RW
d i
Reset
a 0
F o 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Me
31 REV0 Reserved
r
21:16
15
DSCP_PRI_1
REV1
Reserved
ef o
s
11:9
8:6
5:0
QUE_PFCR_0
QUE_PFCT_0
DSCP_PRI_0
User Priority 0 DSCP Value a
ele
i a l R
00002348 P3_PEM2
e n t i
User Priority Egress Mapping II of P3 36D82250
d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
REV0
RW
o n f i TAG_PRI_3
n
RW
a P QUE_PFCR_3
RW
QUE_PFCT_3
RW
DSCP_PRI_3
RW
Reset
Bit
k
0
C
15
0
14
a n a 1
13
1
12
0
11
1
10
1
9
0
8
1
7
1
6
0
5
1
4
1
3
0
2
0
1
0
0
i a T e o r B
M e d F
Page 126 of 830
f o r
l e a se MT7531
l R e Lynx1
Name REV1
n t
TAG_PRI_2
i a QUE_PFCR_2 QUE_PFCT_2 DSCP_PRI_2
e
Type RW RW RW RW RW
Reset 0 0
n f i d 1
a P i0 0 0 1 0 0 1 0 1 0 0 0 0
Bit(s) Name
k a
31 REV0 Reserved
e B
27:25
i
24:22
d
21:16
a T o r
QUE_PFCR_3
QUE_PFCT_3
F
DSCP_PRI_3
Me
15 REV1 Reserved
f o r
0000234C
Bit 31
P3_PEM3
30 29 28
l e a 27 26
25 24 23 22 21 20 19
se
18
5B684920
17 16
Name
Type
REV0
RW
TAG_PRI_5
RW
l R e QUE_PFCR_5
RW
QUE_PFCT_5
RW
DSCP_PRI_5
RW
a
Reset 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0
Bit
Name
15
REV1
14
e
13
n t
TAG_PRI_4i 12 11 10
QUE_PFCR_4
9 8 7
QUE_PFCT_4
6 5 4 3
DSCP_PRI_4
2 1 0
Type
Reset
RW
0
n
1
f i d RW
0
a P i0 1
RW
0 0 1
RW
0 0 1 0 0
RW
0 0 0
C o n a n
k a
31
30:28
i a T e
REV0
o r
TAG_PRI_5
B Reserved
F
Me d
24:22
21:16
15
14:12
11:9
QUE_PFCT_5
DSCP_PRI_5
REV1
TAG_PRI_4
QUE_PFCR_4
Reserved
o r
a s ef
le
00002350 P3_PEM4 User Priority Egress Mapping IV of P3 7FF86DB0
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
REV0
RW
TAG_PRI_7
i a
RW
l R QUE_PFCR_7
RW
QUE_PFCT_7
RW
DSCP_PRI_7
RW
Reset
Bit
0
15
1
14
e n t 1
13
i
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
0
2
0
1
0
0
Name
Type
REV1
RW
n f i d n a
RW
P
TAG_PRI_6 QUE_PFCR_6
RW
QUE_PFCT_6
RW
DSCP_PRI_6
RW
Reset
k C o
0 1
a n a
1 0 1 1 0 1 1 0 1 1 0 0 0 0
i a T e o r B
Med F
Page 127 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
31 REV0 Reserved
30:28
27:25
TAG_PRI_7
QUE_PFCR_7
n f i d a P i User Priority 7 Priority Tag Value

24:22
21:16
C o
QUE_PFCT_7
DSCP_PRI_7
n a n User Priority 7 PFC TX Mapping

k a
15 REV1 Reserved
e B
11:9
i
8:6
d
5:0
a T o r
QUE_PFCR_6
QUE_PFCT_6
F
DSCP_PRI_6
Me 00002400
Bit 31
P4_SSC
30 29 28 27 26
25 24 23 22 21 20 19 18
0000FFFF
17 16
Name
Type
REV0
RO
f o r
Reset
Bit
0
15
0
14
0
13
0
12
l e a
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
se 0
1
0
0
e
Type
Reset 1
RW
1 1
i a
RW
l R 1 1
RW
1 1
RW
1 1
RW
1 1
RW
1 1
RW
1 1
RW
1
Bit(s) Name
e n t i
Description
31:16
15:14
REV0
FID7_PST
n f i d n a P
Reserved
o
11:10
9:8
k C
FID5_PST
FID4_PST
a n a (Rapid) Spanning Tree Protocol Port State

7:6
5:4
i a T e
FID3_PST
FID2_PST
o r B (Rapid) Spanning Tree Protocol Port State

F
Me d
1:0
00002404
FID0_PST
P4_PCR
Port Control of P4 00FF2000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name REV0
MLDv2
_EN
ef o
s
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
1
7
1
6
1
5
ele
1
4
a 1
3
1
2
1
1
1
0
R
PORT_ PORT_
l
a
CP_EN G_EN N R MIS
i
R R
Type
Reset 0
RW
0
e n t 1
i
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0
RW
0
RW
0 0
RW
0
Bit(s) Name
31
30
C
REV0
o
MLDv2_EN
k a n a Reserved
IPv6 MLDv2 source address multicast forwarding enable
i a T e o r B
M e d F
Page 128 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Disable
29:28 EG_TAG
n f i d a P i 1: Enable
C o n a n 2'b00: Untagged
2'b01: Swap
2'b11: Stack
a o
27 REV1 Reserved
d i
26:24
F
PORT_PRI Port-based User Priority
Me
23:16 PORT_MATRIX Port Matrix Member
member.
r
o
port.
15:13
12
REV2
UP2DSCP_EN
Reserved
se f
a
11 UP2TAG_EN
R e l e 0: Disable
1: Enable
t i a l Replace 802.Q priority by user priority.

0: Disable
10 ACL_EN
i d e n P i
1: Enable
o n f a n a
C
e k B a n All frames transmitted from this port are copied to the mirror port.
d i a T F o r 0: Disable
1: Enable
Me
0: Disable
1: Enable
r
7 ACL_MIR ACL Mismatch to Mirror Port
o
ef
s
0: Disable
6:4 MIS_PORT_FW
1: Enable
ACL Mismatch TO_CPU Forward
ele a
i a l R mismatched
e n t i
d
o n f i n a P the ingress port is the CPU port, the system default and CPU port are
excluded.)
k C
REV3
a n a 3'b111: Frame dropped

Reserved
i a T e o r B
M e d F
Page 129 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 1'b0: Frame processed according to PORT_VLAN.

1'b1: VLAN mismatched frame copied to MIRROR port.
1:0
C o
PORT_VLAN
n a n Port-based VLAN Mechanism Select

T e k r B a Member.
d i a F o the VLAN table is forwarded based on the Port Matrix member.
Me
the VLAN table.
f o r
se
00002408 P4_PIC Port IGMP Control of P4 00008000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
R
REV0
RO
e l e IGMP_
MIR
RW
IGMP_MIS
RW
Reset
Bit
0
15
0
14
t i a l
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
i d e n
MLD_H IGMP_
i
ROBUST_VAR W_LEA HW_LE REV1
P
IPM_22
MLD2_ IGMP3 MLD_J IGMP_J MLD_S IGMP_ MLD_G IGMP_
IPM_33 IPM_01 JOIN_E _JOIN_ OIN_E OIN_E QRY_E SQRY_ QRY_E GQRY_
f
44
a
Type
Reset
C
1
o n RW
0
n a n RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
T e
Bit(s)
k Name
r B a Description
ed i a
31:20
19
F o
REV0
IGMP_MIR
Reserved
M port.
0: Disable
o r
ef
18:16 IGMP_MIS IP Multicast "TO_CPU" Forwarding
mismatched.
a s
ele
R
t i a l 3'b100: System default and CPU port excluded

n
f i d e a P i
excluded.)
n
15:14
o
ROBUST_VAR
C n a n Robustness Variable
T e k r B a consecutively.
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 1: One time
13
C o
MLD_HW_LEAVE
n a n 3: Three times
MLD HW Leave Enable
T e k r B a Enable HW MLD Done snooping and fast leave. The corresponding

a o
d i F
0: Disable
Me
1: Enable
r
0: Disable
1: Enable
f o
se
11 REV1
e l e a 0: This frame is regarded as a normal multicast and search ADDR Table.

R
t i a l 0: This frame is regarded as normal multicast and search ADDR table.

n
f i d e a P i
n
C o n a n Enable HW IGMP snooping. Group Address will be learned and added to

T e k r B a TO_EX().
0: Disable
a o
1: Enable
d
6
i F
IGMP3_JOIN_EN IGMP v3 HW Join Enable
Me
TO_EX().
0: Disable
1: Enable
o r
ef
multicast frame.
frames (FF00:/8).
a s
ele
i a l R the ADDR Table automatically.

0: Disable
3 MLD_SQRY_EN
e n t i
1: Enable
n f i d n a P
o
2
k C
IGMP_SQRY_EN
a n a IGMP HW Specific Query Enable

i a T e o r B
M e d F
Page 131 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
f
MLD_GQRY_EN
n i d a P i refresh the specific multicast member.

C o n a n 0: MLD general query message will not refresh the IP multicast table.
k a
0
i a T e o r B
IGMP_GQRY_EN IGMP HW General Query Enable
F
Me d
0000240C P4_PSC
Port Security Control of P4 000FFF00
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name SA_LRN_CNT
f o
MAC_SA_LRN
se
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5
SA_CN
4 3 2 1
TX_PO RX_PO
0
R
l
T_EN
K CK
Type
Reset 1 1
n t
1
i a 1
RW
1 1 1 1 0
RW
0
RW
0
RW
0 0
RW
0
RW
0
RW
0
Bit(s) Name
31:20
19:8
C o n
SA_LRN_CNT
MAC_SA_LRN
n a n Learned Source Address Number

k a
i a T e o r B set.
F
12'h1:
Me d
7:6
5
REV0
SA_CNT_EN
Reserved
SA Counter Enable
r
0: Disable
4 SA_DIS
1: Enable
SA Disable
ef o
s
0: Enable
1: Disable
ele a
R
l
n t i a 2'b00: Receive without SA authorization.

e
n f i d a P i 2'b10: All received frames whose SA look-up is missing or are not port
C o n a n (PCR.PORT_MATRIX).
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i members in the ARL are forwarded among the Guest VLAN Member.
(VTC.GUEST_MEM)
1
C o
TX_PORT_LOCK
n a n Tx Port Lock Enable

k a
i a T e r B
RX_PORT_LOCK
o
Rx Port Lock Enable
F
Me d 0: Receive authorized.
r
00002410 P4_PVC Port VLAN Control of P4 810000C0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18
f o
17 16
se
Name STAG_VPID
Type RW
Reset
Bit
1
15 14
0 0
13
e
0
12
l e a 0
11
0
10
0
9
1
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
DIS_PV FORCE BC_LKY
ID _PVID V_EN
REV0
PT_OP
a
TION
i l R EG_TAG VLAN_ATTR
ACC_FRM
t
Reset 0 0
i d e n 0
P i
0 0 0 0 0 1 1 0 0 0 0 0 0
Bit(s)
31:16
Name
o n
STAG_VPID
f a n a Description
e k C B a n
d i a T F o r Inner VPID == 16'h8100

Me
r
14 FORCE_PVID Force PVID on VLAN-tagged frames
ef o
a s
ele
R
12 REV0 Reserved
l
n t i a 0: Disable pass-through on TX special tag

10:8 EG_TAG
f i d e a P i
n
3'b001: Consistent
C o n a n 3'b010, 3'b011: Reserved

3'b100: Untagged
T e k r B a 3'b101: Swap
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
3'b110: Tagged
7:6
n
VLAN_ATTR
f i d a P i 3'b111: Stack
VLAN Port Attribute
C o n a n 2'b00: User port

2'b01: Stack port
T e k r B a 2'b10: Translation port

d
5
i a o
PORT_STAG
F
Special Tag Enable
Me
the remote port.
1: Enable
4 IPM_LKYV_EN IP Multicast Leaky VLAN Enable
f o r
se
e l e a 0: Multicast frames received by this port will be blocked by VLAN.

2 UC_LKYV_EN
i a l R Unicast Leaky VLAN Enable

t
1:0 ACC_FRM
i d e n P i
Acceptable Frame Type
f
C o n a n a 2'b10: Admit only untagged or priority-tagged frames.

2'b11: Reserved
e k B a n
d i
Bit
a
00002414
T 31
F o r
P4_PPBV1
30 29 28 27 26
25 24 23 22 21 20 19 18
00010001
17 16
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o r
ef
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
a s
ele
R
28
27:16
REV0
G1_PORT_VID
t i a l The Group 1 Priority for each port according to IEEE 802.1Q definition
Reserved
15:13
i
G0_PORT_PRI
d e n P i
Group 0 Port Priority (Default Port Priority)
o n f a n a
definition
C
12 REV1 Reserved
11:0
e k
G0_PORT_VID
B a n Group 0 Port VLAN ID (Default Port VID)
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
definition
C o n n a n
k a
Bit
Name
i a T e31
o r B
30
G3_PORT_PRI
29 28
REV0
27 26 25 24 23 22
G3_PORT_VID
21 20 19 18 17 16
Me d
Type
Reset
Bit
Name
0
15 F RW
0
14
G2_PORT_PRI
0
13
RW
0
12
REV1
0
11
0
10
0
9
0
8
0
7
0
6
RW
G2_PORT_VID
0
5
0
4
0
3
0
2
0
1
1
0
Type RW RW RW
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
f o
se
a
28
27:16
REV0
G3_PORT_VID
R e l e The Group 3 Priority for each port according to IEEE 802.1Q definition
Reserved
15:13 G2_PORT_PRI
t i a l The Group 3 VID for each port according to IEEE 802.1Q definition
n
12
11:0
REV1
G2_PORT_VID
f i d e a P i
Reserved
n
C o n a n
0000241C
T e k B
P4_BSR
r a Broadcast Storm Rate Control of P4 00000000
a o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d i F STRM_
Me
C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o r
ef
Type RW RW
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ele a
R
t i a l 0: Packet-based (1 second period)

1: Rate-based
n
f i d e a P i
0: Exclude BC frame
1: Include BC frame
29
C o n
STRM_MC_INC
n a n
0: Exclude MC frame
1: Include MC frame
28
T e k B
STRM_UC_INC
r a Unknown Unicast Storm Included
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Exclude UC frame
27
n
STRM_DROP
f i d a P i 1: Include UC frame
C o n a n 0: BC Storm detection only

26
T e k
STRM_PERD
r B a Broadcast Strom Detection Signal Period

0: One second
a o
1: 125us
d i
25:24
F
STRM_UNIT Broadcast Storm Suppression
Me
f o r
se
a
R e l e The broadcast storm rate limit for 100 Mbps link speed
7:0 STORM_10M

i d e n P i
o n f a n a
00002420
Bit
e k
31
C P4_STAG01
30
B a n 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
d i a T F o r REV0
RO
VID1
RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name VID1 VID0
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
31:24
23:12
REV0
VID1
Reserved
a s
ele
i a l R
00002424
Bit 31
P4_STAG23
30
e n t 29
i
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
n f i d n a P
REV0
RO
VID3
RW
Reset
Bit
k
0
C
15
o 0
14
a n a
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
i a T e o r B
M e d F
Page 136 of 830
f o r
l e a se MT7531
l R e Lynx1
Name VID3
n t i a VID2
e
Type RW RW
Reset 0 0
n f i d 0
a P i0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
k a
31:24 REV0 Reserved
e B
11:0
d i a T VID2
F o r VLAN Identifier for STAG index 2
Me 00002428
Bit
Name
31
P4_STAG45
30 29 28
REV0
27 26
25 24 23 22 21 20
VID5
19 18
00000000
17 16
r
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Name VID5 VID4
Type
Reset 0 0
RW
0
R
0
e l e 0 0 0 0 0 0
RW
0 0 0 0 0 0
Bit(s) Name
t i a l Description
n
31:24 REV0 Reserved
23:12
11:0
VID5
VID4
f i d e a P i
C o n n a n
k a
0000242C P4_STAG67 STAG Index 6/7 of P4 00000000
Bit
Name
i a T e31
o
30
r B 29 28
REV0
27 26 25 24 23 22 21 20
VID7
19 18 17 16
Me d
Type
Reset
Bit
Name
0
15 F 0
14
VID7
0
13
0
12
RO
0
11
0
10
0
9
0
8
0
7
0
6
VID6
0
5
0
4
RW
0
3
0
2
0
1
0
0
Type RW RW
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ef o
31:24 REV0 Reserved
a s
ele
i a l R
00002430
Bit 31 30
e n
P4_BSR_EXT1
t 29
i
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
n f i
STRM_ STRM_
d
STRM_
MC_IN
a P
STRM_ STRM_ STRM_
n
STRM_UNIT STORM_1G
o
a
C
Type
Reset
e k C
RW
0
RW
B
0
a n RW
0
RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit 15 14 13
n t i a 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Type
Reset 0
n
0
f i d 0
a P i
0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
C o n a n
k a
31
i a T e
STRM_MODE
o r B Broadcast Storm Suppression

F
1: Rate-based
Me d
30
29
STRM_BC_INC
STRM_MC_INC
0: Exclude BC frame
1: Include BC frame
0: Exclude MC frame
28 STRM_UC_INC
1: Include MC frame
f o r
se
0: Exclude UC frame
1: Include UC frame
27 STRM_DROP
e l e a Broadcast Storm Suppression enabled

R
26 STRM_PERD
t i a l Broadcast Strom Detection Signal Period

0: One second
n
1: 125us
25:24 STRM_UNIT
f i d e a P i
C o n n a n
23:16
T e k
STORM_1G
r B a 1000 Mbps Broadcast Storm Rate Limit Control

d i a F o 8'h0: (0* STORM_UNIT) packets or bps

Me
o r
ef
s
ele a
00002434
Bit 31
P4_BSR_EXT2
30 29
i a l R 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
STRM_ STRM_
MODE BC_INC
e t
STRM_
n
MC_IN
STRM_ STRM_ STRM_
i
UC_INC DROP PERD
STRM_UNIT STORM_1G
d
C
Type
Reset
RW
o
0
n f i
RW
0
n
RW
0
a P RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
k C
15 14
a n a 13 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
i a T e o r B
Med F
Page 138 of 830
f o r
l e a se MT7531
l R e Lynx1
Type
n t i a RW RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31
k C o
STRM_MODE
a n a Broadcast Storm Suppression

e B
1: Rate-based
30
d i a T F o r
STRM_BC_INC Broadcast Storm Included
0: Exclude BC frame
Me
1: Include BC frame
0: Exclude MC frame
1: Include MC frame
r
0: Exclude UC frame
1: Include UC frame
f o
se
26 STRM_PERD
e l e a 1: Enable packet drop when BC storm is detected

R
0: One second
25:24 STRM_UNIT
t i a l 1: 125us
n
f i d e a P i
n
23:16
o
STORM_1G


d i
15:8
a o
STORM_100M
F
Me
o r
a s ef
le
00002438 P4_BSR_EXT3 Broadcast Storm Rate Control III of P4 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
STRM_ STRM_
MODE BC_INC
STRM_
MC_IN
i l R
STRM_ STRM_ STRM_
a
UC_INC DROP PERD
STRM_UNIT STORM_1G
t
C
Type
Reset
RW
0
RW
0
i d e n RW
0
P i
RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
15
o n f 14
a n
13
a
12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Type
Reset
e k C 0
B
0
a n 0 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
n t i a
Bit(s)
31
Name
STRM_MODE
f i d e a P i
Description
n
30
C o
STRM_BC_INC
n a n 1: Rate-based
T e k r B a 0: Exclude BC frame
1: Include BC frame
29
d i a o
STRM_MC_INC
F
0: Exclude MC frame
Me
1: Include MC frame
0: Exclude UC frame
1: Include UC frame
f o r
se
a
0: One second
25:24 STRM_UNIT
R e l e 1: 125us
t i a l 2'b01: 256 packets or 256 Kbps

23:16 STORM_1G
i d e n P i
o n f a n a
C n
15:8
T e k
STORM_100M
r B a 100 Mbps Broadcast Storm Rate Limit Control

d i a F o 8'h1: (1* STORM_UNIT) packets or bps
Me
o r
ef
Bit
Name
31 30 29 28 27 26 25 24 23
REV0
22 21
ARL_UPW
20
le a s
19
REV1
18 17
PORT_UPW
16
Type
e
RW RW RW RW
Reset
Bit 15 14
i a
13
l R 12 11 10 9 8
0
7
0
6
1
5
0
4
0
3
0
2
1
1
1
0
Name
Type
REV2
RW
e n t
DSCP_UPW
RW
i
REV3
RW
TAG_UPW
RW
REV4
RW
STAG_UPW
RW
REV5
RW
ACL_UPW
RW
Reset 0
n f i1
d n
0
a P
0 0 1 0 1 0 1 1 0 0 1 1 1
Bit(s)
23
k C o
Name
REV0
a n a Description
Reserved
i a T e o r B
Med F
Page 140 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
22:20 ARL_UPW ARL User Priority Weight (MAC/DIP Hit)
19
18:16
REV1
PORT_UPW
Port-Based User Priority Weight Value
15 REV2
C o n a n Weights range from 0x0 to 0x7.

Reserved
k a
e B
11 REV3 Reserved
10:8
d i
7
6:4
a T TAG_UPW
REV4
F o
STAG_UPWr Priority Tag User Priority Weight
Reserved
Me
3 REV5 Reserved
00002444
Bit 31
P4_PEM1
30 29 28 27 26
25 24 23 22 21 20 19 18
f17
r
10080480
o 16
se
Type
Reset
RW
0 0
RW
0 1 0
RW
0 0 0
RW
0 0 0
e l0
e a 1
RW
0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
REV1
RW
TAG_PRI_0
t
RW
i a l QUE_PFCR_0
RW
QUE_PFCT_0
RW
DSCP_PRI_0
RW
Reset
n
0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Bit(s) Name
31
30:28
REV0
C o n
TAG_PRI_1
n a n Reserved
k a
27:25 QUE_PFCR_1 User Priority 1 Egress Queue Selection or PFC TX Mapping
24:22
21:16
i a T e o r B
QUE_PFCT_1
DSCP_PRI_1
User Priority 1 PFC RX Mapping
F
15 REV1 Reserved
M e d14:12
11:9
8:6
5:0
TAG_PRI_0
QUE_PFCR_0
QUE_PFCT_0
DSCP_PRI_0
o r
ef
00002448 P4_PEM2 User Priority Egress Mapping II of P4 36D82250
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name REV0 TAG_PRI_3 QUE_PFCR_3 QUE_PFCT_3
a s DSCP_PRI_3
ele
Type RW RW RW RW RW
Reset 0 0 1 1 0 1 1 0 1 1
R
0 1 1 0 0 0
l
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
REV1
RW
n t
RW
i
TAG_PRI_2
a QUE_PFCR_2
RW
QUE_PFCT_2
RW
DSCP_PRI_2
RW
Reset 0 0
f i d e 1
a P i
0 0 0 1 0 0 1 0 1 0 0 0 0
Bit(s)
31
Name
C
REV0
o n n a n Description
Reserved
30:28
T e k
TAG_PRI_3
r B a User Priority 3 Priority Tag Value
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
24:22
21:16
QUE_PFCT_3
DSCP_PRI_3
n f i d a P i User Priority 3 PFC TX Mapping

15
14:12
REV1
C o
TAG_PRI_2
n a n Reserved
k a
e B
5:0
d i a T F o r
DSCP_PRI_2 User Priority 2 DSCP Value
Me 0000244C
Bit
Name
31
REV0
P4_PEM3
30 29
TAG_PRI_5
28 27 26
QUE_PFCR_5
25 24 23
QUE_PFCT_5
22 21 20 19
DSCP_PRI_5
18
5B684920
17 16
r
Type RW RW RW RW RW
Reset 0 1 0 1 1 0 1 1 0 1 1 0 1 0
f
0
o 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Type
Reset
RW
0 1
RW
0
R
0
e l e 1
RW
0 0 1
RW
0 0 1 0 0
RW
0 0 0
Bit(s) Name
t i a l Description
n
31 REV0 Reserved
e
27:25
24:22
QUE_PFCR_5
QUE_PFCT_5

21:16
15 REV1
C o
DSCP_PRI_5

Reserved
k a
11:9
8:6
i a T e
QUE_PFCR_4
o r
QUE_PFCT_4
B User Priority 4 Egress Queue Selection or PFC RX Mapping
F
Me d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Type
Reset
RW
0 1
RW
1 1 1
RW
1 1 1
RW
1 1 1 1 1
RW
0
ef
0
o 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
a s 3 2 1 0
ele
Type RW RW RW RW RW
Reset 0 1 1
i a l R 0 1 1 0 1 1 0 1 1 0 0 0 0
Bit(s)
31
Name
REV0
e n t i
Description
Reserved
30:28
27:25
TAG_PRI_7
n f
QUE_PFCR_7
i d n a P
o
21:16
15
k C
DSCP_PRI_7
REV1
a n a User Priority 7 DSCP Value

Reserved
i a T e o r B
M e d F
Page 142 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
11:9
8:6
QUE_PFCR_6
QUE_PFCT_6

5:0
C o
DSCP_PRI_6
00002500
T e k r B
P5_SSC a STP State Control of P5 0000FFFF
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Name REV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 1
RW
1 1
RW
1 1
RW
1 1
RW
1 1
RW
1 1
RW
1 1
RW
1
f o
1
r RW
1
Bit(s) Name
l e a Description
se
e
31:16 REV0 Reserved
R
13:12
11:10
FID6_PST
FID5_PST
t i a l (Rapid) Spanning Tree Protocol Port State

n
e
5:4
3:2
FID2_PST
FID1_PST
n f i d a P i (Rapid) Spanning Tree Protocol Port State

1:0
C o
FID0_PST
n a n (Rapid) Spanning Tree Protocol Port State
00002504
T e k r B
P5_PCR a Port Control of P5 00FF2000
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MLDv2
_EN
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_ PORT_
o r
ef
CP_EN G_EN N R MIS
R R
Type
Reset 0
RW
0 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0
le a s
RW
0
RW
0 0
RW
0
Bit(s) Name
l R e Description
31
30
REV0
MLDv2_EN
n t i a Reserved
e
0: Disable
29:28
f
EG_TAG
n i d a P i 1: Enable
n
2'b00: Untagged
k C o a n a 2'b01: Swap
2'b10: Tagged
i a T e o r B
Med F
Page 143 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
2'b11: Stack
27
26:24
REV1
PORT_PRI
23:16
C o
PORT_MATRIX
n a n User priority for the ingress port

Port Matrix Member
k a
i a T e o r B ports. This function can work with 802.1Q function to decide the last port
member.
Me d
15:13
12
REV2
F
UP2DSCP_EN
port.
Reserved
0: Disable
1: Enable
f o r
se
0: Disable
a
1: Enable
10 ACL_EN
R e l e Port-based ACL Enable

9 PORT_TX_MIR
t i a l Port Tx Mirror Enable

i d e n P i
0: Disable
n f
PORT_RX_MIR
o a n a
1: Enable
C
e k B a n [NOTE] Multi-port support is possible.

0: Disable
d
7
i a T o
ACL_MIR
F r 1: Enable
Me
0: Disable
1: Enable
mismatched
o r
ef
s
ele a
i a l R excluded.)
3
2
REV3
VLAN_MIS
e n t i
Reserved
d
1:0
n
PORT_VLAN
o f i n a P 1'b1: VLAN mismatched frame copied to MIRROR port.

k C a n a 2'b00: Port Matrix Mode. Frames are forwarded by the Port Matrix
Member.
i a T e o r B
M e d F
Page 144 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i not belong to the VLAN member. Each frame whose VID is not listed on
C o n a n 2'b10: Check Mode. Forward received frames whose ingress port does
not belong to the VLAN member. But, discard frames once if VID is
k a
missed on the VLAN table.
e B
d i a T F o r ingress membership violation or VID missed on the VLAN table.
Me 00002508
Bit
Name
31
P5_PIC
30 29 28 27 26
REV0
25 24 23 22 21 20 19
IGMP_
18
00008000
17
IGMP_MIS
16
r
MIR
o
Type RO RW RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
se f 0
1
0
0
Name
MLD_H IGMP_
VE AVE
44
l
IPM_22
e e a MLD2_ IGMP3 MLD_J IGMP_J MLD_S IGMP_ MLD_G IGMP_

N EN N N N EN N EN
Type
Reset 1
RW
0
RW
i
0
a l R RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
e n t i
d
31:20
19
REV0
IGMP_MIR
o n f i n a P Reserved
k C a n a Copy IP multicast frames with an IGMP table mismatch to the mirror

port.
i a T e o r B on a per-port basis.
0: Disable
Me d
18:16
F
IGMP_MIS
mismatched.
o r
ef
a s
ele
excluded.)
R
15:14 ROBUST_VAR
t i a l Robustness Variable
n
consecutively.
f i d e a P i
1: One time
n
13
C o
MLD_HW_LEAVE
MLD HW Leave Enable
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
1: Enable
12
T e k
IGMP_HW_LEAVE
r B a IGMP HW Leave Enable

a
d i F o group-specific query.
Me
0: Disable
1: Enable
11 REV1
r
f o
se
8 IPM_01
e l e a IP Multicast frame for MAC DA is 01-00-5E-xx-xx-xx

R
7 MLD2_JOIN_EN
t i a l MLD v2 HW Join Enable

n
e
TO_EX().
1: Enable
6
o
IGMP3_JOIN_EN
C n a n IGMP v3 HW Join Enable

T e k r B a the ADDR Table automatically for the specific Record Type -IS_EX(),
TO_EX().
a
0: Disable
d i F o 1: Enable
Me
multicast frame.
frames (FF00:/8).
r
ef o
s
0: Disable
3 MLD_SQRY_EN
1: Enable
ele a
i a l R 1: This port is capable of recognizing the MLD specific query message to

2 IGMP_SQRY_EN
e n t i
d
n f
MLD_GQRY_EN

k C a n a 0: MLD general query message will not refresh the IP multicast table.
e B
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 0: IGMP general Query message will not refresh the IP multicast table.
C o n a n refresh the multicast member.
0000250C
T e k r B
P5_PSC a Port Security Control of P5 000FFF00
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_PO RX_PO
r
SA_CN
o
f
T_EN
K CK
se
a
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bit(s) Name
R e l e Description
31:20
19:8
SA_LRN_CNT
MAC_SA_LRN
t i a l Learned Source Address Number

i d e n P i
set.
o n f a n a
12'h1:
7:6
5
k
REV0
e C
SA_CNT_EN
B a n
Reserved
SA Counter Enable
d i a T F o r Enable the learned source MAC Address counter.

0: Disable
Me
1: Enable
4 SA_DIS SA Disable
0: Enable
1: Disable
o r
ef
s
a
ele
R
l
(PCR.PORT_MATRIX).
e
(VTC.GUEST_MEM)
1 TX_PORT_LOCK
n f i d a P i Tx Port Lock Enable

n
k C o
RX_PORT_LOCK
a n a 1: Disable frame transmission.

Rx Port Lock Enable
i a T e o r B
M e d F
Page 147 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
C o n a n
00002510
T e k B
P5_PVC
r a Port VLAN Control of P5 810000C0
a o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d
Name
i F STAG_VPID
Me
Type RW
Reset 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset
RW RW RW RW RW RW RW RW RW RW RW
f o RW
se
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bit(s)
31:16
Name
STAG_VPID
e l e a Description
i a l R The received frame will be regarded as a legal stack tag frame if the
t
n
f i d e a P i
n
C o n a n Disable PVID insertion in priority-tagged frames.

14
T e k
FORCE_PVID
r B a 1: Keep VID=0 for priority-tagged frames.

a o
d i F 1: Force the replacement of VID with PVID.
Me
12 REV0 Reserved
o r
ef
a s
ele
3'b001: Consistent
3'b101: Swap
e n t i
3'b110: Tagged
3'b111: Stack
d
o n f i n a P 2'b00: User port

2'b01: Stack port
k C a n a 2'b10: Translation port

i a T e o r B
M e d F
Page 148 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i Enable a proprietary VLAN tag format to carry additional information to

the remote port.
C o n a n 0: No special tag format for Tx/Rx

1: Enable
4
T e k
IPM_LKYV_EN
r B a IP Multicast Leaky VLAN Enable

d i a F o 0: IP_Multi frames received by this port will be blocked by VLAN.
Me
2 UC_LKYV_EN Unicast Leaky VLAN Enable
r
f o
se
e l e a 2'b01: Admit Only VLAN-tagged frames

R
2'b11: Reserved
t i a l
00002514 P5_PPBV1
i d e n P i
Port-and-Protocol Based VLAN I of P5 00010001
f
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
C o n
G1_PORT_PRI
RW
a n a REV0
RW
G1_PORT_VID
RW
Reset
Bit
e
0
k
15
0
B
14
a n 0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
Name
d
Type
i a T F o r
G0_PORT_PRI
RW
REV1
RW
G0_PORT_VID
RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

r
o
28 REV0 Reserved
ef
s
a
ele
definition
12
11:0
REV1
G0_PORT_VID
i a l R Reserved
t
n
definition
f i d e a P i
00002518
Bit
C
31
o nP5_PPBV2
30
n a n29 28 27 26
25 24 23 22 21 20 19 18
00010001
17 16
Name
T e k B a
G3_PORT_PRI
r
REV0 G3_PORT_VID
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Type RW
n t i a RW RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit
Name
15
n
14
f i d 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
n
Type
Reset 0
k C o RW
0
a n a 0
RW
0 0 0 0 0 0 0
RW
0 0 0 0 0 1
a
Bit(s)
i T e
Name
o r B Description
Me d
31:29
28
27:16
REV0F
G3_PORT_PRI
G3_PORT_VID
Reserved
r
12
11:0
REV1
G2_PORT_VID
Reserved
f o
se
e l e a
0000251C
Bit 31
P5_BSR
30 29
i a l R 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
STRM_ STRM_
MODE BC_INC
STRM_
e
MC_IN
n t
STRM_ STRM_ STRM_
i
UC_INC DROP PERD
STRM_UNIT STORM_1G
d
C
Type
Reset
RW
0
o n f
RW
0
i RW
n0
a P RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
15
k C 14
a n a 13 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Type
i
Reset
a T e 0
o r B0 0 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Me d
Bit(s)
31
NameF
STRM_MODE
Description
1: Rate-based
r
0: Exclude BC frame
1: Include BC frame
ef o
0: Exclude MC frame
a s
ele
1: Include MC frame
R
1: Include UC frame
n
f i d e a P i
n
1: 125us
25:24
T e k
STRM_UNIT
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 2'b01: 256 packets or 256 Kbps

23:16
C o
STORM_1G
n a n 2'b11: 4 K packets or 4 Mbps

a o
d i
15:8
F
Me
f o r
l e a se
e
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
t i a l REV0
RO
VID1
RW
Reset
Bit
0
15
i
0
d
14
e n 0
13
P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
o n f VID1
a
RW
n a VID0
RW
Reset
e k C 0
B
0
a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a T
Bit(s)
31:24
F o r
Name
REV0
Description
Reserved
ed
M 00002524 P5_STAG23 STAG Index 2/3 of P5 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
Name REV0 VID3
Type
Reset 0 0 0 0
RO
0 0 0 0 0 0 0 0
RW
le a s 0 0 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
VID3
RW
i a l R VID2
RW
t
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:24
23:12
o n
REV0
VID3
f a n a Reserved
11:0
e k CVID2
B a n
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
n t i a
00002528
Bit 31
P5_STAG45
30
f i d e 29
a P i
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
C o n n a n
REV0
RO
VID5
RW
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
i a T e15
o
14
r B VID5
13 12 11 10 9 8 7 6
VID4
5 4 3 2 1 0
Me d
Type
Reset
Bit(s)
0
Name
F 0
RW
0 0 0 0 0
Description
0 0 0
RW
0 0 0 0 0 0
31:24 REV0 Reserved
r
o
se f
0000252C
Bit 31
P5_STAG67
30 29 28
e l e a 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
i a l R REV0
RO
VID7
RW
Reset
Bit
0
15
0
14
e n t
0
13
i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
n f i d
VID7
RW
n a P VID6
RW
Reset 0
k C o 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:24
i a T e
Name
REV0
o r B Description
Reserved
Me d
23:12
11:0
VID7
VID6
F VLAN Identifier for STAG index 7
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
STRM_ STRM_
STRM_
MC_IN
STRM_ STRM_ STRM_
STRM_UNIT STORM_1G
ef o
s
C
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0 0 0
ele
0
a RW
0 0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
t i a l STORM_100M
RW
STORM_10M
RW
Reset 0
i
0
d e n 0
P i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
o n
Name
f
STRM_MODE
a n a Description
e k C B a n
1: Rate-based
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 0: Exclude BC frame
1: Include BC frame
29
C o
STRM_MC_INC
n a n Unknown Multicast Storm Included

0: Exclude MC frame
28
T e k B
STRM_UC_INC
r a 1: Include MC frame
a o
0: Exclude UC frame
d i F 1: Include UC frame
Me
0: One second
25:24 STRM_UNIT
1: 125us
f o r
se
a
23:16 STORM_1G
R e l e 2'b10: 1 K packets or 1 Mbps

15:8 STORM_100M
i d e n P i
f
C o n a n a 8'h0: (0* STORM_UNIT) packets or bps

7:0 STORM_10M
e k B a n 10 Mbps Broadcast Storm Rate Limit Control

d i a T F o r
Me 00002534
Bit 31
P5_BSR_EXT2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
r
STRM_
Name
o
ef
C
s
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
ele
0
4
a 0
3
0
2
0
1
0
0
R
Type
Reset 0 0
t
0
i a l 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
31
o n f
STRM_MODE
a n a
C n
1: Rate-based
30
T e k
STRM_BC_INC
r B a Broadcast Storm Included
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Exclude BC frame
29
n f
STRM_MC_INC
i d a P i 1: Include BC frame
C o n a n 0: Exclude MC frame
1: Include MC frame
28
T e k
STRM_UC_INC
r B a Unknown Unicast Storm Included

0: Exclude UC frame
a o
1: Include UC frame
d
27
i F
STRM_DROP Broadcast Storm Suppression enabled
Me
0: One second
1: 125us
f o r
se
a
23:16 STORM_1G


15:8 STORM_100M
i d e n P i
f
7:0
C o n
STORM_10M


d i a T F o r 8'h1: (1* STORM_UNIT) packets or bps
Me 00002538
Bit 31
P5_BSR_EXT3
30
STRM_ STRM_
STRM_
29 28
STRM_ STRM_ STRM_

27 26
25 24 23 22 21 20 19 18
00000000
17 16
r
o
C
ef
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
STORM_100M
11 10 9 8 7 6 5
ele
4
a
STORM_10M
3 2 1 0
R
Type RW RW
Reset 0 0
t
0
i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
STRM_MODE
i d e n P i
Description
o n f a n a
1: Rate-based
30
e k C
STRM_BC_INC
B a n
0: Exclude BC frame
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
1: Include BC frame
29 STRM_MC_INC
n f i d a P i Unknown Multicast Storm Included

0: Exclude MC frame
28
C o
STRM_UC_INC
1: Include UC frame
a o
d i F 0: BC Storm detection only
Me
0: One second
1: 125us
f o r
se
a
23:16 STORM_1G

15:8 STORM_100M

i d e n P i
f
7:0
C o n
STORM_10M
a n a 10 Mbps Broadcast Storm Rate Limit Control

e k B a n 8'h0: (0* STORM_UNIT) packets or bps

d i a T F o r
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name REV0 ARL_UPW REV1 PORT_UPW
Type RW RW RW RW
Reset 0 0 1 0 0 0 1
o r 1
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Type
Reset
RW
0 1
RW
0 0
RW
0 1
RW
0 1
RW
0 1
RW
1
ele
0
a RW
0 1
RW
1 1
Bit(s) Name
i a l R Description
t
23 REV0 Reserved
22:20
19
ARL_UPW
REV1
i d e n P i
Reserved
f
15 REV2
C o n a n a Weights range from 0x0 to 0x7.

Reserved
14:12
11
e
DSCP_UPW
k
REV3
B a n DSCP Priority Weight (IPv4)

Reserved
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
7
6:4
REV4
STAG_UPW
3
2:0
REV5
C o
ACL_UPW
n a n Reserved
T e k r B a
d i a
00002544
F oP5_PEM1 User Priority Egress Mapping I of P5 10080480
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW RW RW RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
REV1
RW
TAG_PRI_0
RW
QUE_PFCR_0
RW
QUE_PFCT_0
RW
DSCP_PRI_0
RW
f o r
se
Reset 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
R
31 REV0 Reserved
30:28
27:25
TAG_PRI_1
QUE_PFCR_1
t i a l User Priority 1 Priority Tag Value

n
e
15
14:12
REV1
TAG_PRI_0
11:9
8:6
C o
QUE_PFCR_0
QUE_PFCT_0

k a
i a T e o r B
Me d
00002548
Bit
Name
Type
31
REV0
RW
F P5_PEM2
30 29
TAG_PRI_3
RW
28 27 26
QUE_PFCR_3
RW
25 24 23
QUE_PFCT_3
RW
22 21 20 19
DSCP_PRI_3
RW
18
36D82250
17 16
Reset 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r 0
ef
s
Type RW RW RW RW RW
Reset 0 0 1 0 0 0 1 0 0 1 0
ele
1
a 0 0 0 0
R
31
30:28
REV0
TAG_PRI_3
t i a l Reserved
n
24:22
21:16
QUE_PFCT_3
DSCP_PRI_3
f i d e a P i
n
15 REV1 Reserved
14:12
11:9
C o
TAG_PRI_2
QUE_PFCR_2

8:6
T e k
QUE_PFCT_2
r B a User Priority 2 PFC TX Mapping
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i
0000254C
C oP5_PEM3
n a n User Priority Egress Mapping III of P5 5B684920
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
i a T e
REV0
RW
o r B TAG_PRI_5
RW
QUE_PFCR_5
RW
QUE_PFCT_5
RW
DSCP_PRI_5
RW
Me d
Reset
Bit
Name
Type
0
15
REV1
RW
F 1
14
0
13
TAG_PRI_4
RW
1
12
1
11
0
10
QUE_PFCR_4
RW
1
9
1
8
0
7
QUE_PFCT_4
RW
1
6
1
5
0
4
1
3
DSCP_PRI_4
RW
0
2
0
1
0
0
Reset 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0
f o r
se
31 REV0 Reserved
a
e
24:22
21:16
QUE_PFCT_5
DSCP_PRI_5
R e l User Priority 5 PFC TX Mapping

15
14:12
REV1
TAG_PRI_4
t i a l Reserved
n
e
5:0 DSCP_PRI_4
C o n a n
k a
Bit
Name
i a T e31
REV0
o
30
r B 29
TAG_PRI_7
28 27 26
QUE_PFCR_7
25 24 23
QUE_PFCT_7
22 21 20 19
DSCP_PRI_7
18 17 16
Me d
Type
Reset
Bit
Name
RW
0
15
REV1
F 1
14
RW
1
13
TAG_PRI_6
1
12
1
11
RW
1
10
QUE_PFCR_6
1
9
1
8
RW
1
7
QUE_PFCT_6
1
6
1
5
1
4
1
3
RW
DSCP_PRI_6
0
2
0
1
0
0
Type RW RW RW RW RW
r
Reset 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0
ef o
31 REV0 Reserved
a s
ele
24:22
21:16
15
QUE_PFCT_7
DSCP_PRI_7
REV1
i a l R User Priority 7 PFC TX Mapping

Reserved
14:12
11:9
TAG_PRI_6
QUE_PFCR_6
e n t i
8:6
5:0
QUE_PFCT_6
n f
DSCP_PRI_6
i d n a P
k C o a n a
i a T e o r B
M e d F
Page 157 of 830
f o r
l e a se MT7531
l R e Lynx1
00002554 P5_BSR_EXT4
n t i a Broadcast Storm Rate Control IV of P5 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
n f i d P i
STORM_2P5G_EXT3
a
STORM_2P5G_EXT2
n
Type RW RW
Reset
Bit
0
15
k C o0
14
a n a
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
i a T e o r B
STORM_2P5G_EXT1
RW
STORM_2P5G
RW
F
Reset
d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me Bit(s)
31:24
Name
STORM_2P5G_EXT3
Description
Limitation: Max. rate limit is 1000 Mbps
f o r
se
23:16 STORM_2P5G_EXT2 2500 Mbps Broadcast Storm Rate Limit Control
a
R e l e Limitation: Max. rate limit is 1000 Mbps

15:8 STORM_2P5G_EXT1

i d e n P i
f
7:0
C o n
STORM_2P5G

e k B a n Limitation: Max. rate limit is 1000 Mbps

T r
d i a F o
Me 00002558
Bit
Name
31
P5_BSR_EXT5
30 29 28 27 26
25 24
REV0
23 22 21 20 19 18
00000000
17 16
r
Type RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
ef
0
1
o 0
0
a s STRM_ STRM_ STRM_

STRM_
ele
Name REV0 UNIT_1 UNIT_1 UNIT_1
UNIT_1
_EXT3 _EXT2 _EXT1
R
Type RW RW RW RW RW
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:4
Name
REV0
i d e n P i
Description
Reserved
3
o n f
STRM_UNIT_1_EXT3
a n a
C
2 STRM_UNIT_1_EXT2 Broadcast Storm Suppression
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f
STRM_UNIT_1
i d a P i 1'b1: 16 K packets or 16 Mbps
C o n a n 1'b1: 16 K packets or 16 Mbps
00002600
T e k r B
P6_SSC a STP State Control of P6 0000FFFF
d i
Bit
a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Name REV0
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
f o RW
se
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit(s)
31:16
Name
REV0
e l e a Description
Reserved
15:14
13:12
FID7_PST
FID6_PST
i a l R (Rapid) Spanning Tree Protocol Port State

t
n
7:6
5:4
FID3_PST
FID2_PST
f i d e a P i
n
1:0
o
FID0_PST
C n a n (Rapid) Spanning Tree Protocol Port State
T e k r B a
a
00002604 P6_PCR Port Control of P6 00FF2000
d i
Bit 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MLDv2
_EN
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_ PORT_
o r
ef
CP_EN G_EN N R MIS
R R
Type
Reset 0
RW
0 1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0
le a s
RW
0
RW
0 0
RW
0
Bit(s) Name
l R e Description
31
30
REV0
MLDv2_EN
n t i a Reserved
e
0: Disable
29:28
f
EG_TAG
n i d a P i 1: Enable
C o n a n 2'b00: Untagged
2'b01: Swap
ed i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
2'b11: Stack
27
26:24
REV1
PORT_PRI
23:16
C o
PORT_MATRIX
n a n User priority for the ingress port

Port Matrix Member
k a
i a T e o r B ports. This function can work with 802.1Q function to decide the last port
member.
Me d
15:13
12
REV2
F
UP2DSCP_EN
port.
Reserved
0: Disable
1: Enable
f o r
se
0: Disable
a
1: Enable
10 ACL_EN
R e l e Port-based ACL Enable

9 PORT_TX_MIR
t i a l Port Tx Mirror Enable

i d e n P i
0: Disable
n f
PORT_RX_MIR
o a n a
1: Enable
C
e k B a n [NOTE] Multi-port support is possible.

0: Disable
d
7
i a T o
ACL_MIR
F r 1: Enable
Me
0: Disable
1: Enable
mismatched
o r
ef
s
ele a
i a l R excluded.)
3
2
REV3
VLAN_MIS
e n t i
Reserved
d
1:0
n
PORT_VLAN
o f i n a P 1'b1: VLAN mismatched frame copied to MIRROR port.

k C a n a 2'b00: Port Matrix Mode. Frames are forwarded by the Port Matrix
Member.
i a T e o r B
M e d F
Page 160 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i not belong to the VLAN member. Each frame whose VID is not listed on
C o n a n 2'b10: Check Mode. Forward received frames whose ingress port does
k a
the VLAN table.
e B
d i a T F o r ingress membership violation or VID missed on the VLAN table.
Me 00002608
Bit
Name
31
P6_PIC
30 29 28 27 26
REV0
25 24 23 22 21 20 19
IGMP_
18
00008000
17
IGMP_MIS
16
r
MIR
o
Type RO RW RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
se f 0
1
0
0
Name
MLD_H IGMP_
VE AVE
44
l
IPM_22
e e a MLD2_ IGMP3 MLD_J IGMP_J MLD_S IGMP_ MLD_G IGMP_

N EN N N N EN N EN
Type
Reset 1
RW
0
RW
i
0
a l R RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
e n t i
d
31:20
19
REV0
IGMP_MIR
o n f i n a P Reserved
k C a n a Copy IP multicast frames with an IGMP table mismatch to the mirror

port.
i a T e o r B on a per-port basis.
0: Disable
Me d
18:16
F
IGMP_MIS
mismatched.
o r
ef
a s
ele
excluded.)
R
15:14 ROBUST_VAR
t i a l Robustness Variable
n
consecutively.
f i d e a P i
1: One time
n
13
C o
MLD_HW_LEAVE
MLD HW Leave Enable
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
1: Enable
12
T e k
IGMP_HW_LEAVE
r B a IGMP HW Leave Enable

a
d i F o group-specific query.
Me
0: Disable
1: Enable
11 REV1
r
f o
se
8 IPM_01
e l e a IP Multicast frame for MAC DA is 01-00-5E-xx-xx-xx

R
7 MLD2_JOIN_EN
t i a l MLD v2 HW Join Enable

n
e
TO_EX().
1: Enable
6
o
IGMP3_JOIN_EN
C n a n IGMP v3 HW Join Enable

T e k r B a the ADDR Table automatically for the specific Record Type -IS_EX(),
TO_EX().
a
0: Disable
d i F o 1: Enable
Me
multicast frame.
frames (FF00:/8).
r
ef o
s
0: Disable
3 MLD_SQRY_EN
1: Enable
ele a
i a l R 1: This port is capable of recognizing the MLD specific query message to

2 IGMP_SQRY_EN
e n t i
d
n f
MLD_GQRY_EN

k C a n a 0: MLD general query message will not refresh the IP multicast table.
e B
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 0: IGMP general Query message will not refresh the IP multicast table.
C o n a n refresh the multicast member.
0000260C
T e k r B
P6_PSC a Port Security Control of P6 000FFF00
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RO RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_PO RX_PO
r
SA_CN
o
f
T_EN
K CK
se
a
Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Bit(s) Name
R e l e Description
31:20
19:8
SA_LRN_CNT
MAC_SA_LRN
t i a l Learned Source Address Number

i d e n P i
set.
o n f a n a
12'h1:
7:6
5
k
REV0
e C
SA_CNT_EN
B a n
Reserved
SA Counter Enable
d i a T F o r Enable the learned source MAC Address counter.

0: Disable
Me
1: Enable
4 SA_DIS SA Disable
0: Enable
1: Disable
o r
ef
s
2'b01: All received frame whose SA look-up is missing or are not port
a
ele
R
l
(PCR.PORT_MATRIX).
e
(VTC.GUEST_MEM)
1 TX_PORT_LOCK
n f i d a P i Tx Port Lock Enable

n
k C o
RX_PORT_LOCK
a n a 1: Disable frame transmission.

Rx Port Lock Enable
i a T e o r B
M e d F
Page 163 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
f i d e a P i
n
C o n a n
00002610
T e k B
P6_PVC
r a Port VLAN Control of P6 810000C0
a o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d
Name
i F STAG_VPID
Me
Type RW
Reset 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset
RW RW RW RW RW RW RW RW RW RW RW
f o RW
se
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bit(s)
31:16
Name
STAG_VPID
e l e a Description
i a l R The received frame will be regarded as a legal stack tag frame if the
t
n
f i d e a P i
n
C o n a n Disable PVID insertion in priority-tagged frames.

14
T e k
FORCE_PVID
r B a 1: Keep VID=0 for priority-tagged frames.

a o
d i F 1: Force the replacement of VID with PVID.
Me
12 REV0 Reserved
o r
ef
a s
ele
3'b001: Consistent
3'b101: Swap
e n t i
3'b110: Tagged
3'b111: Stack
d
o n f i n a P 2'b00: User port

2'b01: Stack port
k C a n a 2'b10: Translation port

i a T e o r B
M e d F
Page 164 of 830
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i Enable a proprietary VLAN tag format to carry additional information to

the remote port.
C o n a n 0: No special tag format for Tx/Rx

1: Enable
4
T e k
IPM_LKYV_EN
r B a IP Multicast Leaky VLAN Enable

d i a F o 0: IP_Multi frames received by this port will be blocked by VLAN.
Me
2 UC_LKYV_EN Unicast Leaky VLAN Enable
r
f o
se
e l e a 2'b01: Admit Only VLAN-tagged frames

R
2'b11: Reserved
t i a l
00002614 P6_PPBV1
i d e n P i
Port-and-Protocol Based VLAN I of P6 00010001
f
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
C o n
G1_PORT_PRI
RW
a n a REV0
RW
G1_PORT_VID
RW
Reset
Bit
e
0
k
15
0
B
14
a n 0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
Name
d
Type
i a T F o r
G0_PORT_PRI
RW
REV1
RW
G0_PORT_VID
RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

r
o
28 REV0 Reserved
ef
s
a
ele
definition
12
11:0
REV1
G0_PORT_VID
i a l R Reserved
t
n
definition
f i d e a P i
00002618
Bit
C
31
o nP6_PPBV2
30
n a n29 28 27 26
25 24 23 22 21 20 19 18
00010001
17 16
Name
T e k B a
G3_PORT_PRI
r
REV0 G3_PORT_VID
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Type RW
n t i a RW RW
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit
Name
15
n
14
f i d 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
n
Type
Reset 0
k C o RW
0
a n a 0
RW
0 0 0 0 0 0 0
RW
0 0 0 0 0 1
a
Bit(s)
i T e
Name
o r B Description
Me d
31:29
28
27:16
REV0F
G3_PORT_PRI
G3_PORT_VID
Reserved
r
12
11:0
REV1
G2_PORT_VID
Reserved
f o
se
e l e a
0000261C
Bit 31
P6_BSR
30 29
i a l R 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
STRM_ STRM_
MODE BC_INC
STRM_
e
MC_IN
n t
STRM_ STRM_ STRM_
i
UC_INC DROP PERD
STRM_UNIT STORM_1G
d
C
Type
Reset
RW
0
o n f
RW
0
i RW
n0
a P RW
0
RW
0
RW
0 0
RW
0 0 0 0 0
RW
0 0 0 0
Bit
Name
15
k C 14
a n a 13 12
STORM_100M
11 10 9 8 7 6 5 4
STORM_10M
3 2 1 0
Type
i
Reset
a T e 0
o r B0 0 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Me d
Bit(s)
31
NameF
STRM_MODE
Description
1: Rate-based
r
0: Exclude BC frame
1: Include BC frame
ef o
0: Exclude MC frame
a s
ele
1: Include MC frame
R
1: Include UC frame
n
f i d e a P i
n
1: 125us
25:24
T e k
STRM_UNIT
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 2'b01: 256 packets or 256 Kbps

23:16
C o
STORM_1G
n a n 2'b11: 4 K packets or 4 Mbps

a o
d i
15:8
F
Me
f o r
l e a se
e
R
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
t i a l REV0
RO
VID1
RW
Reset
Bit
0
15
i
0
d
14
e n 0
13
P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
o n f VID1
a
RW
n a VID0
RW
Reset
e k C 0
B
0
a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a T
Bit(s)
31:24
F o r
Name
REV0
Description
Reserved
ed
M 00002624 P6_STAG23 STAG Index 2/3 of P6 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
Name REV0 VID3
Type
Reset 0 0 0 0
RO
0 0 0 0 0 0 0 0
RW
le a s 0 0 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
VID3
RW
i a l R VID2
RW
t
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:24
23:12
o n
REV0
VID3
f a n a Reserved
11:0
e k CVID2
B a n
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
n t i a
00002628
Bit 31
P6_STAG45
30
f i d e 29
a P i
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
C o n n a n
REV0
RO
VID5
RW
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
i a T e15
o
14
r B VID5
13 12 11 10 9 8 7 6
VID4
5 4 3 2 1 0
Me d
Type
Reset
Bit(s)
0
Name
F 0
RW
0 0 0 0 0
Description
0 0 0
RW
0 0 0 0 0 0
31:24 REV0 Reserved
r
o
se f
0000262C
Bit 31
P6_STAG67
30 29 28
e l e a 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
i a l R REV0
RO
VID7
RW
Reset
Bit
0
15
0
14
e n t
0
13
i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
n f i d
VID7
RW
n a P VID6
RW
Reset 0
k C o 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:24
i a T e
Name
REV0
o r B Description
Reserved
Me d
23:12
11:0
VID7
VID6
F VLAN Identifier for STAG index 7
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
STRM_ STRM_
STRM_
MC_IN
STRM_ STRM_ STRM_
STRM_UNIT STORM_1G
ef o
s
C
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
0 0 0 0
ele
0
a RW
0 0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
t i a l STORM_100M
RW
STORM_10M
RW
Reset 0
i
0
d e n 0
P i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
o n
Name
f
STRM_MODE
a n a Description
e k C B a n
1: Rate-based
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i 0: Exclude BC frame
1: Include BC frame
29
C o
STRM_MC_INC
n a n Unknown Multicast Storm Included

0: Exclude MC frame
28
T e k B
STRM_UC_INC
r a 1: Include MC frame
a o
0: Exclude UC frame
d i F 1: Include UC frame
Me
0: One second
25:24 STRM_UNIT
1: 125us
f o r
se
a
23:16 STORM_1G

15:8 STORM_100M
i d e n P i
f
C o n a n a 8'h0: (0* STORM_UNIT) packets or bps

7:0 STORM_10M
e k B a n 10 Mbps Broadcast Storm Rate Limit Control

d i a T F o r
Me 00002634
Bit 31
P6_BSR_EXT2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
r
STRM_
Name
o
ef
C
s
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
ele
0
4
a 0
3
0
2
0
1
0
0
R
Type
Reset 0 0
t
0
i a l 0
RW
0 0 0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
31
o n f
STRM_MODE
a n a
C n
1: Rate-based
30
T e k
STRM_BC_INC
r B a Broadcast Storm Included
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
0: Exclude BC frame
29
n f
STRM_MC_INC
i d a P i 1: Include BC frame
C o n a n 0: Exclude MC frame
1: Include MC frame
28
T e k
STRM_UC_INC
r B a Unknown Unicast Storm Included

0: Exclude UC frame
a o
1: Include UC frame
d
27
i F
STRM_DROP Broadcast Storm Suppression enabled
Me
0: One second
1: 125us
f o r
se
a
23:16 STORM_1G


15:8 STORM_100M
i d e n P i
f
7:0
C o n
STORM_10M


d i a T F o r 8'h1: (1* STORM_UNIT) packets or bps
Me 00002638
Bit 31
P6_BSR_EXT3
30
STRM_ STRM_
STRM_
29 28
STRM_ STRM_ STRM_

27 26
25 24 23 22 21 20 19 18
00000000
17 16
r
o
C
ef
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
STORM_100M
11 10 9 8 7 6 5
ele
4
a
STORM_10M
3 2 1 0
R
Type RW RW
Reset 0 0
t
0
i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
STRM_MODE
i d e n P i
Description
o n f a n a
1: Rate-based
30
e k C
STRM_BC_INC
B a n
0: Exclude BC frame
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
1: Include BC frame
29 STRM_MC_INC
n f i d a P i Unknown Multicast Storm Included

0: Exclude MC frame
28
C o
STRM_UC_INC
1: Include UC frame
a o
d i F 0: BC Storm detection only
Me
0: One second
1: 125us
f o r
se
a
23:16 STORM_1G

15:8 STORM_100M

i d e n P i
f
7:0
C o n
STORM_10M

e k B a n 8'h0: (0* STORM_UNIT) packets or bps

d i a T F o r
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name REV0 ARL_UPW REV1 PORT_UPW
Type RW RW RW RW
Reset 0 0 1 0 0 0 1
o r 1
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Type
Reset
RW
0 1
RW
0 0
RW
0 1
RW
0 1
RW
0 1
RW
1
ele
0
a RW
0 1
RW
1 1
Bit(s) Name
i a l R Description
t
23 REV0 Reserved
22:20
19
ARL_UPW
REV1
i d e n P i
Reserved
f
15 REV2
C o n a n a Weights range from 0x0 to 0x7.

Reserved
14:12
11
e
DSCP_UPW
k
REV3
B a n DSCP Priority Weight (IPv4)

Reserved
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
7
6:4
REV4
STAG_UPW
3
2:0
REV5
C o
ACL_UPW
n a n Reserved
T e k r B a
d i a
00002644
F oP6_PEM1 User Priority Egress Mapping I of P6 10080480
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW RW RW RW
Reset 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
REV1
RW
TAG_PRI_0
RW
QUE_PFCR_0
RW
QUE_PFCT_0
RW
DSCP_PRI_0
RW
f o r
se
Reset 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
R
31 REV0 Reserved
30:28
27:25
TAG_PRI_1
QUE_PFCR_1
t i a l User Priority 1 Priority Tag Value

n
e
15
14:12
REV1
TAG_PRI_0
11:9
8:6
C o
QUE_PFCR_0
QUE_PFCT_0

k a
i a T e o r B
Me d
00002648
Bit
Name
Type
31
REV0
RW
F P6_PEM2
30 29
TAG_PRI_3
RW
28 27 26
QUE_PFCR_3
RW
25 24 23
QUE_PFCT_3
RW
22 21 20 19
DSCP_PRI_3
RW
18
36D82250
17 16
Reset 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r 0
ef
s
Type RW RW RW RW RW
Reset 0 0 1 0 0 0 1 0 0 1 0
ele
1
a 0 0 0 0
R
31
30:28
REV0
TAG_PRI_3
t i a l Reserved
n
24:22
21:16
QUE_PFCT_3
DSCP_PRI_3
f i d e a P i
n
15 REV1 Reserved
14:12
11:9
C o
TAG_PRI_2
QUE_PFCR_2

8:6
T e k
QUE_PFCT_2
r B a User Priority 2 PFC TX Mapping
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f i d a P i
0000264C
C oP6_PEM3
n a n User Priority Egress Mapping III of P6 5B684920
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
i a T e
REV0
RW
o r B TAG_PRI_5
RW
QUE_PFCR_5
RW
QUE_PFCT_5
RW
DSCP_PRI_5
RW
Me d
Reset
Bit
Name
Type
0
15
REV1
RW
F 1
14
0
13
TAG_PRI_4
RW
1
12
1
11
0
10
QUE_PFCR_4
RW
1
9
1
8
0
7
QUE_PFCT_4
RW
1
6
1
5
0
4
1
3
DSCP_PRI_4
RW
0
2
0
1
0
0
Reset 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0
f o r
se
31 REV0 Reserved
a
e
24:22
21:16
QUE_PFCT_5
DSCP_PRI_5
R e l User Priority 5 PFC TX Mapping

15
14:12
REV1
TAG_PRI_4
t i a l Reserved
n
e
5:0 DSCP_PRI_4
C o n a n
k a
Bit
Name
i a T e31
REV0
o
30
r B 29
TAG_PRI_7
28 27 26
QUE_PFCR_7
25 24 23
QUE_PFCT_7
22 21 20 19
DSCP_PRI_7
18 17 16
Me d
Type
Reset
Bit
Name
RW
0
15
REV1
F 1
14
RW
1
13
TAG_PRI_6
1
12
1
11
RW
1
10
QUE_PFCR_6
1
9
1
8
RW
1
7
QUE_PFCT_6
1
6
1
5
1
4
1
3
RW
DSCP_PRI_6
0
2
0
1
0
0
Type RW RW RW RW RW
r
Reset 0 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0
ef o
31 REV0 Reserved
a s
ele
24:22
21:16
15
QUE_PFCT_7
DSCP_PRI_7
REV1
i a l R User Priority 7 PFC TX Mapping

Reserved
14:12
11:9
TAG_PRI_6
QUE_PFCR_6
e n t i
8:6
5:0
QUE_PFCT_6
n f
DSCP_PRI_6
i d n a P
k C o a n a
i a T e o r B
M e d F
Page 173 of 830
f o r
l e a se MT7531
l R e Lynx1
00002654 P6_BSR_EXT4
n t i a Broadcast Storm Rate Control IV of P6 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
n f i d P i
STORM_2P5G_EXT3
a
STORM_2P5G_EXT2
n
Type RW RW
Reset
Bit
0
15
k C o0
14
a n a
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
i a T e o r B
STORM_2P5G_EXT1
RW
STORM_2P5G
RW
F
Reset
d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me Bit(s)
31:24
Name
STORM_2P5G_EXT3
Description
f o r
se
23:16 STORM_2P5G_EXT2 2500 Mbps Broadcast Storm Rate Limit Control
a
R e l e Limitation: Max. rate limit is 1000 Mbps

15:8 STORM_2P5G_EXT1

i d e n P i
f
7:0
C o n
STORM_2P5G

e k B a n Limitation: Max. rate limit is 1000 Mbps

T r
d i a F o
Me 00002658
Bit
Name
31
P6_BSR_EXT5
30 29 28 27 26
25 24
REV0
23 22 21 20 19 18
00000000
17 16
r
Type RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
ef
0
1
o 0
0
a s STRM_ STRM_ STRM_

STRM_
ele
Name REV0 UNIT_1 UNIT_1 UNIT_1
UNIT_1
_EXT3 _EXT2 _EXT1
R
Type RW RW RW RW RW
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:4
Name
REV0
i d e n P i
Description
Reserved
3
o n f
STRM_UNIT_1_EXT3
a n a
C
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Bit(s) Name
n t i a Description
e
n f
STRM_UNIT_1
i d a P i 1'b1: 16 K packets or 16 Mbps
C o n a n 1'b1: 16 K packets or 16 Mbps
T e k r B a
d i a F o
Me
f o r
l e a se
l R e
n t i a
f i d e a P i
C o n n a n
T e k r B a
d i a F o
Me
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
3 Scheduler (SCH)
f i d e a P i
C o n
Introduction
n a n
a
3.1
T e k r B
a o
Since there are eight egress queues for each egress port in MT7531, a scheduler should be used to select a frame
d i F
to be transmitted. In this design, three schedulers are implemented, which are Strict Priority (SP), Weight Fair
Me Queue (WFQ), and Round-Robin (RR). However, these schedulers should co-work with the per-port maximum
and minimum shapers. These functions are the main parts of the SCH (scheduler) module. Besides, the egress
rate control is also implemented in this module, which supports both the leaky and token bucket algorithms.
f o r
3.2 Features
l e a se

Round-Robin (RR) and mixed ones
l R e
Per queue MAX-MIN shapers with different schedulers – Strict Priority (SP), Weight Fair Queue (WFQ),


n t i a
The minmum shapers can use either SP or RR
The maximum shapers can use either SP or WRQ


f i d e
Per shaper is enabled/disabled
a P i
n
Per shaper threshold setting


o a n
Per shaper with both the leaky bucket and token bucket algorithms
C n
a
Per port egress rate control with both the leaky bucket and token bucket approaches
T e k r B
d i a F o
Me
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
3.3
n t i
Register Definitiona
f i d e a P i
3.3.1
C o n
SCH Register
n a n
Module name: SCH Base address: (+0x0000)
T e
Address
k r B a Name Width Register Function
a
32 Max-Min Scheduler Control Register 0 of Queue
d i
00001000
F o MMSCR0_Q0P0
0/Port 0
Me
00001004 MMSCR1_Q0P0
0/Port 0
00001008 MMSCR0_Q1P0
1/Port 0
r
0000100C MMSCR1_Q1P0
1/Port 0
00001010 MMSCR0_Q2P0
f o
se
2/Port 0
a
00001014 MMSCR1_Q2P0
00001018 MMSCR0_Q3P0
R e l e 32
2/Port 0
Max-Min Scheduler Control Register 0 of Queue
3/Port 0
t i a l 32 Max-Min Scheduler Control Register 1 of Queue

3/Port 0
00001020
e n
MMSCR0_Q4P0
i d P i
4/Port 0
00001024
o n f
MMSCR1_Q4P0
a n a
4/Port 0
00001028
e k C a n
MMSCR0_Q5P0
B
5/Port 0
T
d
0000102C
i a F o rMMSCR1_Q5P0
32
5/Port 0
Me
00001030 MMSCR0_Q6P0
6/Port 0
00001034 MMSCR1_Q6P0
6/Port 0
00001038 MMSCR0_Q7P0
7/Port 0
o r
ef
7/Port 0
s
00001040 ERLCR_P0 32 Egress Rate Limit Control Register of Port 0
00001050 MMSCR2_Q0P0
32
32
0/Port 0
a
ele
00001054 MMSCR3_Q0P0
i a l R 32
0/Port 0
t
00001058 MMSCR2_Q1P0
n
1/Port 0
0000105C
f d e
MMSCR3_Q1P0
i a P i
1/Port 0
n
00001060
C o n n
MMSCR2_Q2P0
a 32
2/Port 0
T e k
00001064
r B a
MMSCR3_Q2P0
2/Port 0
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
i
00001068 MMSCR2_Q3P0
d
3/Port 0
0000106C
o n f i
MMSCR3_Q3P0
n a P 32 Max-Min Scheduler Control Register 3 of Queue

3/Port 0
00001070
k C n a
MMSCR2_Q4P0
a
4/Port 0
T e
00001074
i a o r B
MMSCR3_Q4P0
4/Port 0
Me d00001078
0000107C
F MMSCR2_Q5P0
MMSCR3_Q5P0
32
32
5/Port 0
5/Port 0
00001080 MMSCR2_Q6P0
6/Port 0
00001084 MMSCR3_Q6P0
6/Port 0
f o r
se
00001088 MMSCR2_Q7P0
e l e a 32
7/Port 0
7/Port 0
00001090
000010E0
MMSCR_P0
GERLCR
i a l R 32
32
Max-Min Scheduler Control Register of Port 0
Global Egress Rate Limit Control Register
00001100
n
MMSCR0_Q0P1
e t i
0/Port 1
00001104
f i d
MMSCR1_Q0P1
n n a P
0/Port 1
00001108
k C o a
MMSCR0_Q1P1
a n
1/Port 1
e B
T r
1/Port 1
d i a
00001110
F o MMSCR0_Q2P1
2/Port 1
Me
00001114 MMSCR1_Q2P1
2/Port 1
00001118 MMSCR0_Q3P1
3/Port 1
r
o
ef
3/Port 1
00001120 MMSCR0_Q4P1
4/Port 1
a s
ele
00001124 MMSCR1_Q4P1
4/Port 1
R
l
00001128 MMSCR0_Q5P1
5/Port 1
n t i a 32 Max-Min Scheduler Control Register 1 of Queue

5/Port 1
00001130
i d e
MMSCR0_Q6P1
f a P i
6/Port 1
00001134
C o nMMSCR1_Q6P1
n a n
6/Port 1
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
i
00001138 MMSCR0_Q7P1
d
7/Port 1
0000113C
o n f i
MMSCR1_Q7P1

7/Port 1
00001140
k C ERLCR_P1
a n a 32
32
Egress Rate Limit Control Register of Port 1
e B
00001150 MMSCR2_Q0P1
0/Port 1
d i a T
00001154
F o r
MMSCR3_Q0P1
0/Port 1
Me
00001158 MMSCR2_Q1P1
1/Port 1
1/Port 1
00001160 MMSCR2_Q2P1
32
2/Port 1
f o r
se
00001164 MMSCR3_Q2P1
2/Port 1
00001168 MMSCR2_Q3P1
e l e a 32
32
3/Port 1
i a l R 32
3/Port 1
t
00001170 MMSCR2_Q4P1
4/Port 1
00001174
i d e n
MMSCR3_Q4P1
P i
4/Port 1
00001178
o n f
MMSCR2_Q5P1
a n a 32 Max-Min Scheduler Control Register 2 of Queue

5/Port 1
0000117C
e k C a n
MMSCR3_Q5P1
B
5/Port 1
T r
a
00001180 MMSCR2_Q6P1
d i F o 32
6/Port 1
Me
00001184 MMSCR3_Q6P1
6/Port 1
00001188 MMSCR2_Q7P1
7/Port 1
r
7/Port 1
00001190
00001200
MMSCR_P1
MMSCR0_Q0P2
32
32
ef o
0/Port 2
a s
ele
00001204 MMSCR1_Q0P2
0/Port 2
R
l
00001208 MMSCR0_Q1P2
1/Port 2

1/Port 2
00001210
i d e
MMSCR0_Q2P2
f a P i
2/Port 2
00001214
C o nMMSCR1_Q2P2
n a n
2/Port 2
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
i
00001218 MMSCR0_Q3P2
d
3/Port 2
0000121C
o n f i
MMSCR1_Q3P2

3/Port 2
00001220
k C n a
MMSCR0_Q4P2
a
4/Port 2
T e
00001224
i a o r B
MMSCR1_Q4P2
4/Port 2
Me d00001228
0000122C
F MMSCR0_Q5P2
MMSCR1_Q5P2
32
32
5/Port 2
5/Port 2
00001230 MMSCR0_Q6P2
6/Port 2
00001234 MMSCR1_Q6P2
6/Port 2
f o r
se
00001238 MMSCR0_Q7P2
e l e a 32
7/Port 2
7/Port 2
00001240 ERLCR_P2
i a l R 32
32
t
00001250 MMSCR2_Q0P2
0/Port 2
00001254
i d e n
MMSCR3_Q0P2
P i
0/Port 2
00001258
o n f
MMSCR2_Q1P2

1/Port 2
0000125C
e k C a n
MMSCR3_Q1P2
B
1/Port 2
T r
a
00001260 MMSCR2_Q2P2
d i F o 32
2/Port 2
Me
00001264 MMSCR3_Q2P2
2/Port 2
00001268 MMSCR2_Q3P2
3/Port 2
r
3/Port 2
00001270 MMSCR2_Q4P2
4/Port 2
ef o
00001274 MMSCR3_Q4P2
32
4/Port 2
a s
ele
00001278 MMSCR2_Q5P2
R
5/Port 2

5/Port 2
00001280
e n
MMSCR2_Q6P2
i d P i
6/Port 2
f
a
00001284 MMSCR3_Q6P2
00001288
C o n n a
MMSCR2_Q7P2
n 32
6/Port 2
a
7/Port 2
T e k r B
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
i
d
7/Port 2
00001290
o n f i
MMSCR_P2
n a P 32
32
00001300
k C a a
MMSCR0_Q0P3
n 32
0/Port 3
e B
00001304 MMSCR1_Q0P3
0/Port 3
d i a T
00001308
F o r
MMSCR0_Q1P3
1/Port 3
Me
1/Port 3
00001310 MMSCR0_Q2P3
2/Port 3
00001314 MMSCR1_Q2P3
32
2/Port 3
f o r
se
00001318 MMSCR0_Q3P3
3/Port 3
e l e a 32
32
3/Port 3
00001320 MMSCR0_Q4P3
i a l R 32
4/Port 3
t
00001324 MMSCR1_Q4P3
4/Port 3
00001328
i d e n
MMSCR0_Q5P3
P i
5/Port 3
0000132C
o n f
MMSCR1_Q5P3

5/Port 3
00001330
e k C a n
MMSCR0_Q6P3
B
6/Port 3
T r
a
00001334 MMSCR1_Q6P3
d i F o 32
6/Port 3
Me
00001338 MMSCR0_Q7P3
7/Port 3
7/Port 3
r
o
00001350 MMSCR2_Q0P3
ef
0/Port 3
00001354 MMSCR3_Q0P3
0/Port 3
a s
ele
00001358 MMSCR2_Q1P3
1/Port 3
R
l
1/Port 3
00001360 MMSCR2_Q2P3

2/Port 3
00001364
i d e
MMSCR3_Q2P3
f a P i
2/Port 3
00001368
C o nMMSCR2_Q3P3
n a n
3/Port 3
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
i
d
3/Port 3
00001370
o n f i
MMSCR2_Q4P3

4/Port 3
00001374
k C n a
MMSCR3_Q4P3
a
4/Port 3
T e
00001378
i a o r B
MMSCR2_Q5P3
5/Port 3
Me d0000137C
00001380
F MMSCR3_Q5P3
MMSCR2_Q6P3
32
32
5/Port 3
6/Port 3
00001384 MMSCR3_Q6P3
6/Port 3
00001388 MMSCR2_Q7P3
7/Port 3
f o r
se
00001390 MMSCR_P3
e l e a 32
32
7/Port 3
00001400 MMSCR0_Q0P4
i a l R 32
0/Port 4
t
00001404 MMSCR1_Q0P4
0/Port 4
00001408
i d e n
MMSCR0_Q1P4
P i
1/Port 4
0000140C
o n f
MMSCR1_Q1P4

1/Port 4
00001410
e k C a n
MMSCR0_Q2P4
B
2/Port 4
T r
a
00001414 MMSCR1_Q2P4
d i F o 32
2/Port 4
Me
00001418 MMSCR0_Q3P4
3/Port 4
3/Port 4
00001420 MMSCR0_Q4P4
r
4/Port 4
00001424 MMSCR1_Q4P4
4/Port 4
ef o
00001428 MMSCR0_Q5P4
32
5/Port 4
a s
ele
R
5/Port 4
00001430 MMSCR0_Q6P4

6/Port 4
00001434
e n
MMSCR1_Q6P4
i d P i
6/Port 4
f
a
00001438 MMSCR0_Q7P4
0000143C
C o n n a
MMSCR1_Q7P4
n 32
7/Port 4
a
7/Port 4
T e k r B
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
00001450
n f i d
MMSCR2_Q0P4
a P i 32 Max-Min Scheduler Control Register 2 of Queue

0/Port 4
00001454
C o a
MMSCR3_Q0P4
n n 32 Max-Min Scheduler Control Register 3 of Queue

0/Port 4
e
00001458
T k r B a
MMSCR2_Q1P4
1/Port 4
a o
d i
0000145C
F
MMSCR3_Q1P4
1/Port 4
Me
00001460 MMSCR2_Q2P4
2/Port 4
00001464 MMSCR3_Q2P4
2/Port 4
00001468 MMSCR2_Q3P4
32
3/Port 4
f o r
se
3/Port 4
00001470 MMSCR2_Q4P4
e l e a 32
32
4/Port 4
00001474 MMSCR3_Q4P4
i a l R 32
4/Port 4
t
00001478 MMSCR2_Q5P4
5/Port 4
0000147C
i d e n
MMSCR3_Q5P4
P i
5/Port 4
00001480
o n f
MMSCR2_Q6P4

6/Port 4
00001484
e k C a n
MMSCR3_Q6P4
B
6/Port 4
T r
a
00001488 MMSCR2_Q7P4
d i F o 32
7/Port 4
Me
7/Port 4
00001490 MMSCR_P4 32 Max-Min Scheduler Control Register of Port 4
00001500 MMSCR0_Q0P5
0/Port 5
r
o
00001504 MMSCR1_Q0P5
ef
0/Port 5
00001508 MMSCR0_Q1P5
1/Port 5
a s
ele
1/Port 5
R
l
00001510 MMSCR0_Q2P5
2/Port 5
00001514 MMSCR1_Q2P5

2/Port 5
00001518
i d e
MMSCR0_Q3P5
f a P i
3/Port 5
0000151C
C o nMMSCR1_Q3P5
n a n
3/Port 5
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
i
00001520 MMSCR0_Q4P5
d
4/Port 5
00001524
o n f i
MMSCR1_Q4P5

4/Port 5
00001528
k C n a
MMSCR0_Q5P5
a
5/Port 5
T e
0000152C
i a o r B
MMSCR1_Q5P5
5/Port 5
Me d00001530
00001534
F MMSCR0_Q6P5
MMSCR1_Q6P5
32
32
6/Port 5
6/Port 5
00001538 MMSCR0_Q7P5
7/Port 5
7/Port 5
f o r
se
00001550 MMSCR2_Q0P5
e l e a 32
32
0/Port 5
00001554 MMSCR3_Q0P5
i a l R 32
0/Port 5
t
00001558 MMSCR2_Q1P5
1/Port 5
0000155C
i d e n
MMSCR3_Q1P5
P i
1/Port 5
00001560
o n f
MMSCR2_Q2P5

2/Port 5
00001564
e k C a n
MMSCR3_Q2P5
B
2/Port 5
T r
a
00001568 MMSCR2_Q3P5
d i F o 32
3/Port 5
Me
3/Port 5
00001570 MMSCR2_Q4P5
4/Port 5
00001574 MMSCR3_Q4P5
r
4/Port 5
00001578 MMSCR2_Q5P5
5/Port 5
ef o
32
5/Port 5
a s
ele
00001580 MMSCR2_Q6P5
R
6/Port 5
00001584 MMSCR3_Q6P5

6/Port 5
00001588
e n
MMSCR2_Q7P5
i d P i
7/Port 5
f
a
00001590
C o nMMSCR_P5
n a n 32
7/Port 5
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
i
00001600 MMSCR0_Q0P6
d
0/Port 6
00001604
o n f i
MMSCR1_Q0P6

0/Port 6
00001608
k C n a
MMSCR0_Q1P6
a
1/Port 6
T e
0000160C
i a o r B
MMSCR1_Q1P6
1/Port 6
Me d00001610
00001614
F MMSCR0_Q2P6
MMSCR1_Q2P6
32
32
2/Port 6
2/Port 6
00001618 MMSCR0_Q3P6
3/Port 6
3/Port 6
f o r
se
00001620 MMSCR0_Q4P6
00001624 MMSCR1_Q4P6
e l e a 32
4/Port 6
4/Port 6
00001628 MMSCR0_Q5P6
i a l R 32 Max-Min Scheduler Control Register 0 of Queue

5/Port 6
0000162C
n
MMSCR1_Q5P6
e t i
5/Port 6
00001630
f i d
MMSCR0_Q6P6
n n a P
6/Port 6
00001634
k C o a
MMSCR1_Q6P6
a n
32
32
6/Port 6
i a T e
00001638
o B
MMSCR0_Q7P6
r 32
7/Port 6
F
Me d00001640
00001650
ERLCR_P6
MMSCR2_Q0P6
32
32
7/Port 6
0/Port 6
00001654 MMSCR3_Q0P6
r
0/Port 6
00001658 MMSCR2_Q1P6
1/Port 6
ef o
32
1/Port 6
a s
ele
00001660 MMSCR2_Q2P6
R
2/Port 6
00001664 MMSCR3_Q2P6

2/Port 6
00001668
e n
MMSCR2_Q3P6
i d P i
3/Port 6
f
a
00001670
C o n n a
MMSCR2_Q4P6
n 32
3/Port 6
a
4/Port 6
T e k r B
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
i
00001674 MMSCR3_Q4P6
d
4/Port 6
00001678
o n f i
MMSCR2_Q5P6

5/Port 6
0000167C
k C n a
MMSCR3_Q5P6
a
5/Port 6
T e
00001680
i a o r B
MMSCR2_Q6P6
6/Port 6
Me d00001684
00001688
F MMSCR3_Q6P6
MMSCR2_Q7P6
32
32
6/Port 6
7/Port 6
7/Port 6
00001690 MMSCR_P6 32 Max-Min Scheduler Control Register of Port 6
f o r
00001000 MMSCR0_Q0P0
l e a Max-Min Scheduler Control Register 0 of Queue

se 00000000
Bit 31 30 29
l R
28
e 27 26
0/Port 0
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
_Q0_P
n t i a
Type
0
RW
f i d e a P i
Reset
Bit
0
15
C o n
14
n a
13
n 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
ATE_E
T e k r B a MIN_RATE_CTRL_EXP_TB_T_Q
MIN_RATE_CTRL_MAN_TB_CBS_Q0_P0
a o
N_Q0_ 0_P0
d i P0
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
31 MIN_SP_WRR_Q0_P0 Port 0 Queue 0 min. traffic arbitration scheme
0: Round-Robin (RR)
1: Strict Priority (SP)
ef o
15 MIN_RATE_EN_Q0_P0 Port 0 Queue 0 min. shaper rate limit control is enabled
a s
0: Queue 0 min. shaper rate limit control is disabled, the shaper will
ele
always let the pkt pass (infinite rate)
1: Queue 0 min. shaper rate limit control is enabled
11:8
i a l R
MIN_RATE_CTRL_EXP_TB_T_Q0_P0 Depend on MIN_MAX_TB_EN, it can be exponent part for leaky bucket
or TB_T period for token bucket
e n t i
When MIN_MAX_TB_EN = 0, exponent part of Port 0 Queue 0 min.
shaper rate limit control, value range: 0..5
d
0: 1Kbps
o n f i n a P 1: 10Kbps
2: 100Kbps
k C a n a 3: 1Mbps
4: 10Mbps
e B
5: 100Mbps
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When MIN_MAX_TB_EN = 1, support TB_T period for rate measurement,

value range: 0..14
C o n n a n 0: 1/128ms
1: 1/64ms
k a
2: 1/32ms
e B
3: 1/16ms
d i a T F o r
4: 1/8ms
5: 1/4ms
6: 1/2ms
Me
7: 1ms
8: 2ms
9: 4ms
10: 8ms
11: 16ms
12: 32ms
13: 64ms
f o r
se
14: 128ms
7:0 MIN_RATE_CTRL_MAN_TB_CBS_Q0_P0 Depend on MIN_MAX_TB_EN, it can be mantissa part for leaky bucket
e l e a
or TB_CBS stepping for token bucket
When MIN_MAX_TB_EN = 0, mantissa part of Port 0 Queue 0 min. shaper
rate limit control, value range: 1..255
i a l R In MT7531AE/BE, Final Rate Limit = MAN*10^(EXP)*1Kbps

In MT7531DE, Final Rate Limit = (MAN/2)*10^(EXP)*1Kbps
e n t i
When MIN_MAX_TB_EN = 1, support max. bucket size TB_CBS 512 Bytes
stepping, and
d
Token Bucket = Max ( MIN_RATE_CIR*TB_T, TB_CBS*512 )
o n f i n a P
00001004
k C a n
MMSCR1_Q0P0
a Max-Min Scheduler Control Register 1 of Queue 00000000
Bit
i a T e31
o r
30
B 29 28 27 26
0/Port 0
25 24 23 22 21 20 19 18 17 16
Me d
Name
Type
MAX_S
P_WFQ
_Q0_P
0
RW
F MAX_WEIGHT_Q0_P0
RW
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r 0
ef
MAX_R
ATE_E MAX_RATE_CTRL_EXP_TB_T_Q
s
Name MAX_RATE_CTRL_MAN_TB_CBS_Q0_P0
N_Q0_ 0_P0
Type
P0
RW RW
ele a RW
Reset 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
e
MAX_SP_WFQ_Q0_P0
n t i
Description
Port 0 Queue 0 max. traffic arbitration scheme
n f i d n a P
0: Weighted Fair Queuing (WFQ)
27:24
15
k o
MAX_WEIGHT_Q0_P0
C a n a
MAX_RATE_EN_Q0_P0
Port 0 Queue 0 weighted value for max. WFQ weighted value is
(q0_max_weight+1'b1)
Port 0 Queue 0 max. shaper rate limit control is enabled
i a T e o r B
M e d F
Page 187 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: Queue 0 max. shaper rate limit control is disabled, the shaper will
11:8
C o n a n
MAX_RATE_CTRL_EXP_TB_T_Q0_P0
n
1: Queue 0 max. shaper rate limit control is enabled
Depend on MIN_MAX_TB_EN, it can be exponent part for leaky bucket
a
T e k r B
When MIN_MAX_TB_EN = 0, exponent part of Port 0 Queue 0 max.
d i a F o 0: 1Kbps
1: 10Kbps
Me
2: 100Kbps
3: 1Mbps
4: 10Mbps
5: 100Mbps
When MIN_MAX_TB_EN = 1, TB_T period for rate measurement, value
range: 0..14
0: 1/128ms
f o r
se
1: 1/64ms
2: 1/32ms
e l a
3: 1/16ms
e
4: 1/8ms
5: 1/4ms
i a l R 6: 1/2ms
7: 1ms
e n t i
8: 2ms
9: 4ms
d
10: 8ms
o n f i n a P 11: 16ms
12: 32ms
k C a n a 13: 64ms
14: 128ms
e B
7:0 MAX_RATE_CTRL_MAN_TB_CBS_Q0_P0 Depend on MIN_MAX_TB_EN, it can be mantissa part for leaky bucket
T r
d i a F o When MIN_MAX_TB_EN = 0, mantissa part of Port 0 Queue 0 max.

Me
In MT7531AE/BE, Final Rate Limit = MAN*10^(EXP)*1Kbps
In MT7531DE, Final Rate Limit = (MAN/2)*10^(EXP)*1Kbps
stepping, and
Token Bucket = Max ( MAX_RATE_CIR*TB_T, TB_CBS*512 )
o r
00001008 MMSCR0_Q1P0 Max-Min Scheduler Control Register 0 of Queue
a s ef00000000
ele
1/Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
i a l R
t
_Q1_P
n
0
Type
Reset
RW
0
f i d e a P i
Bit
Name
MIN_R
15
C o n 14
n a n
13 12 11 10 9
MIN_RATE_CTRL_EXP_TB_T_Q
8 7 6 5 4 3
2 1 0
k a
ATE_E 1_P0
i a T e o r B
M e d F
Page 188 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
N_Q1_
n t i a
Type
P0
RW
f i d e a P i RW RW
Reset 0
C o n n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
T e k
Name
r B a
MIN_SP_WRR_Q1_P0
Description
Port 0 Queue 1 min. traffic arbitration scheme
d i a F o 0: Round-Robin (RR)
Me
11:8 MIN_RATE_CTRL_EXP_TB_T_Q1_P0 Depend on MIN_MAX_TB_EN, it can be exponent part for leaky bucket
f o r
se
a
When MIN_MAX_TB_EN = 1, support TB_T period for rate measurement,
7:0
e l e
value range: 0..14
MIN_RATE_CTRL_MAN_TB_CBS_Q1_P0 Depend on MIN_MAX_TB_EN, it can be mantissa part for leaky bucket
R
t i a l When MIN_MAX_TB_EN = 0, mantissa part of Port 0 Queue 1 min. shaper

n
f i d e a P i
stepping
0000100C
C o n n a
MMSCR1_Q1P0
n Max-Min Scheduler Control Register 1 of Queue 00000000
Bit
T e k
31
r
30
B a 29 28 27 26
1/Port 0
25 24 23 22 21 20 19 18 17 16
d i a
MAX_S
P_WFQ
F o
Me
Name MAX_WEIGHT_Q1_P0
_Q1_P
0
Type RW RW
Reset 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MAX_R
MAX_RATE_CTRL_MAN_TB_CBS_Q1_P0
ef o
s
N_Q1_ 1_P0
a
P0
ele
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31 MAX_SP_WFQ_Q1_P0
i d e n P i
f
27:24
C o n
MAX_WEIGHT_Q1_P0
a n a Port 0 Queue 1 weighted value for max. WFQ weighted value is

15
e k B a n
MAX_RATE_EN_Q1_P0 Port 0 Queue 1 max. shaper rate limit control is enabled
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
11:8
C o n a n
n
a
T e k r B
d i a F o When MIN_MAX_TB_EN = 1, support TB_T period for rate measurement,

value range: 0..14
Me
When MIN_MAX_TB_EN = 0, mantissa part of Port 0 Queue 1 max.
stepping
f o r
00001010 MMSCR0_Q2P0

se 00000000
e
2/Port 0
Bit
MIN_S
31 30 29
i a
28
l R 27 26 25 24 23 22 21 20 19 18 17 16
t
P_WRR
Name
n
_Q2_P
Type
0
RW
f i d e a P i
Reset
Bit
0
15
C o n
14 13
n a n 12 11 10 9 8 7 6 5 4 3 2 1 0
k a
MIN_R
e B
ATE_E MIN_RATE_CTRL_EXP_TB_T_Q
T
Name MIN_RATE_CTRL_MAN_TB_CBS_Q2_P0
d
Type
i
N_Q2_
aP0
RW
F o r 2_P0
RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Round-Robin (RR)
o r
ef
s
a
ele
11:8
i a l R
t
i d e n P i
f
value range: 0..14
7:0
C o n a n a
e k B a n When MIN_MAX_TB_EN = 0, mantissa part of Port 0 Queue 2 min. shaper

d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When MIN_MAX_TB_EN = 1, support max. bucket size TB_CBS 512 Bytes

stepping
C o n n a n
00001014
T e k B a
MMSCR1_Q2P0
r
2/Port 0
00000000
d
Bit
i a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_S
P_WFQ
_Q2_P
0
Type RW RW
Reset
Bit
0
15 14 13 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2
f1
o r 0
se
MAX_R
a
e
N_Q2_ 2_P0
Type
P0
RW
R e l RW RW
Reset 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
i d
MAX_SP_WFQ_Q2_P0
e n P i
Description
o n f a n a 0: Weighted Fair Queuing (WFQ)

27:24
e k C
MAX_WEIGHT_Q2_P0
B a n Port 0 Queue 2 weighted value for max. WFQ weighted value is

T
15 MAX_RATE_EN_Q2_P0 Port 0 Queue 2 max. shaper rate limit control is enabled
d i a F o r 0: Queue 2 max. shaper rate limit control is disabled, the shaper will
Me
11:8 MAX_RATE_CTRL_EXP_TB_T_Q2_P0 Depend on MIN_MAX_TB_EN, it can be exponent part for leaky bucket
r
7:0
value range: 0..14
MAX_RATE_CTRL_MAN_TB_CBS_Q2_P0 Depend on MIN_MAX_TB_EN, it can be mantissa part for leaky bucket
ef o
s
ele a
i a l R stepping
e n t i
d
00001018 MMSCR0_Q3P0 Max-Min Scheduler Control Register 0 of Queue 00000000
Bit 31
o n f
30
i n
29
a P 28 27 26
3/Port 0
25 24 23 22 21 20 19 18 17 16
Name
k C
MIN_S
P_WRR
a n a
i a T e o r B
M e d F
Page 191 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
_Q3_P
n t i a
Type
0
RW
f i d e a P i
Reset
Bit
0
15
C o n
14
n a
13
n 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
ATE_E
a o
N_Q3_ 3_P0
d i P0
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
0: Round-Robin (RR)
f o
se
e l a
e
11:8
i a l
MIN_RATE_CTRL_EXP_TB_T_Q3_P0
R Depend on MIN_MAX_TB_EN, it can be exponent part for leaky bucket
e n t i
d
7:0
n f i n a P value range: 0..14

o
k C a n a or TB_CBS stepping for token bucket
e B
T r
d i a F o stepping
Me 0000101C
Bit 31
MMSCR1_Q3P0
30 29 28 27 26
3/Port 0
25 24 23 22 21 20 19 18
00000000
17 16
MAX_S
o r
ef
P_WFQ
s
_Q3_P
a
0
ele
Type RW RW
Reset 0 0 0 0 0
Bit
MAX_R
15 14 13
i a l R12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q3_
e n t i
MAX_RATE_CTRL_EXP_TB_T_Q
3_P0
d
P0
Type
Reset
RW
o n f i n a P RW RW
a
0 0 0 0 0 0 0 0 0 0 0 0 0
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
31
f i d
MAX_SP_WFQ_Q3_P0
e a P i Port 0 Queue 3 max. traffic arbitration scheme
27:24
C o n
MAX_WEIGHT_Q3_P0
n a n 1: Strict Priority (SP)

k a
15
i a T e o r B
0: Queue 3 max. shaper rate limit control is disabled, the shaper will
Me d
11:8
F
7:0
value range: 0..14
f o r
se
e l e a
R
stepping
t i a l
00001020
i d e
MMSCR0_Q4P0
n P i
4/Port 0
00000000
Bit
MIN_S
31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
P_WRR
_Q4_P
e k C B a n
T
0
Type
d i
Reset
a RW
0
F o r
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_R
N_Q4_ 4_P0
P0
Type RW RW RW
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
a s
ele
i a l R 0: Round-Robin (RR)
t
i d e n P i
f
11:8
C o n a n a
e k B a n When MIN_MAX_TB_EN = 0, exponent part of Port 0 Queue 4 min.

d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description

value range: 0..14
7:0
o n n
C n a or TB_CBS stepping for token bucket
k a
e B
d i a T F o r
stepping
Me 00001024 MMSCR1_Q4P0 Max-Min Scheduler Control Register 1 of Queue

4/Port 0
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_S
P_WFQ
f o
se
_Q4_P
a
0
Type
Reset
RW
0
R e l e 0 0
RW
0 0
Bit
MAX_R
15 14 13
t i a l
12 11 10 9 8 7 6 5 4 3 2 1 0
n
e
N_Q4_ 4_P0
Type
P0
RW
n f i d a P i RW RW
Reset 0
C o n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
T e k
Name
r B a Description
a
31 MAX_SP_WFQ_Q4_P0 Port 0 Queue 4 max. traffic arbitration scheme
d i F o 0: Weighted Fair Queuing (WFQ)
Me
27:24 MAX_WEIGHT_Q4_P0 Port 0 Queue 4 weighted value for max. WFQ weighted value is
r
11:8 MAX_RATE_CTRL_EXP_TB_T_Q4_P0
ef o
s
ele a
7:0
a l R value range: 0..14

i
t
i d e n P i
f
C o n a n a stepping
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
00001028
n
MMSCR0_Q5P0
t i a Max-Min Scheduler Control Register 0 of Queue 00000000
Bit 31 30
f i d e29
a P i
28 27 26
5/Port 0
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
C o n n a n
k a
_Q5_P
Type
i a
0
T eRW
o r B
Me d
Reset
Bit
Name
MIN_R
ATE_E
N_Q5_
0
15
F 14 13 12 11 10 9
5_P0
8 7 6 5 4 3
2 1 0
P0
Type
Reset
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0
f0
o r 0
Bit(s) Name
e a
Description
l se
e
R
0: Round-Robin (RR)
15 MIN_RATE_EN_Q5_P0
t i a l 1: Strict Priority (SP)

Port 0 Queue 5 min. shaper rate limit control is enabled
n
f i d e a P i
n
C o n a n or TB_T period for token bucket

T e k r B a shaper rate limit control, value range: 0..5

value range: 0..14
i
7:0
d a F o
Me
stepping
o r
0000102C MMSCR1_Q5P0 Max-Min Scheduler Control Register 1 of Queue
5/Port 0
a s ef
00000000
ele
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MAX_S
l
P_WFQ
i a
_Q5_P
Type
0
RW
e n t i
RW
Reset
Bit
0
15
n f
14
i d 13
n a P 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
C o
MAX_R
ATE_E
k a n a
5_P0
i a T e o r B
M e d F
Page 195 of 830
f o r
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l R e Scheduler
Confidential A
N_Q5_
n t i a
Type
P0
RW
f i d e a P i RW RW
Reset 0
C o n n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
T e k
Name
r B a
MAX_SP_WFQ_Q5_P0
Description
d i a F o 0: Weighted Fair Queuing (WFQ)

Me
f o r
se
a
R e e
l
value range: 0..14
7:0
t i a l
n
f i d e a P i
n
stepping
C o n a n
00001030
T e k B a
MMSCR0_Q6P0
r
Max-Min Scheduler Control Register 0 of Queue 00000000
a o
6/Port 0
d
Bit
i 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_S
P_WRR
Name
_Q6_P
0
Type RW
Reset 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
MIN_R
a
Name
ele
N_Q6_ 6_P0
P0
Type
Reset
RW
0
i a l R 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
e n t i
Description
31
f i d
MIN_SP_WRR_Q6_P0
n n a P Port 0 Queue 6 min. traffic arbitration scheme

0: Round-Robin (RR)
15
k C o n a
MIN_RATE_EN_Q6_P0
a
i a T e o r B
Med F
Page 196 of 830
f o r
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l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: Queue 6 min. shaper rate limit control is disabled, the shaper will
11:8
C o n a n
n
a
T e k r B

value range: 0..14
Me
stepping
f o r
00001034 MMSCR1_Q6P0

se 00000000
e
6/Port 0
Bit
MAX_S
31 30 29
i a
28
l R 27 26 25 24 23 22 21 20 19 18 17 16
t
P_WFQ
n
_Q6_P
Type
0
RW
f i d e a P i RW
Reset
Bit
0
15
C o n
14 13
n a n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
k a
MAX_R
e B
T
d
Type
i
N_Q6_
aP0
RW
F o r 6_P0
RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
s
a
ele
i a l R always let the pkt pass (infinite rate)

t
i d e n P i
f
C o n a n a When MIN_MAX_TB_EN = 1, support TB_T period for rate measurement,

value range: 0..14
7:0
e k B n
a or TB_CBS stepping for token bucket
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When MIN_MAX_TB_EN = 0, mantissa part of Port 0 Queue 6 max.

C o n n a n When MIN_MAX_TB_EN = 1, support max. bucket size TB_CBS 512 Bytes

stepping
T e k r B a
d i a
00001038
F o MMSCR0_Q7P0 Max-Min Scheduler Control Register 0 of Queue 00000000
Me
7/Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_S
P_WRR
Name
_Q7_P
r
0
Type RW
f o
se
Reset 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l e
MIN_R
e
R
N_Q7_ 7_P0
Type
P0
RW
t i a l RW RW
Reset 0
i d e n P i
0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
o n f
MIN_SP_WRR_Q7_P0
a n a Description
e k C B a n
0: Round-Robin (RR)
T
d i a F o r 0: Queue 7 min. shaper rate limit control is disabled, the shaper will
Me
r
When MIN_MAX_TB_EN = 1, TB_T period for rate measurement, value
7:0
range: 0..14
ef o
s
ele a
i a l R stepping
e n t i
d
0000103C MMSCR1_Q7P0 Max-Min Scheduler Control Register 1 of Queue 00000000
Bit 31
o n f
30
i n
29
a P 28 27 26
7/Port 0
25 24 23 22 21 20 19 18 17 16
Name
k C
MAX_S
P_WFQ
a n a MAX_WEIGHT_Q7_P0
i a T e o r B
M e d F
Page 198 of 830
f o r
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l R e Scheduler
Confidential A
_Q7_P
n t i a
Type
0
RW
f i d e a P i RW
Reset
Bit
0
15
C o n14
n a
13
n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
MAX_R
ATE_E
T e k r B a MAX_RATE_CTRL_EXP_TB_T_Q
a o
N_Q7_ 7_P0
d i P0
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
f o
se
15 MAX_RATE_EN_Q7_P0
e l e a

11:8
e n t
i
d
o n f i n a P shaper rate limit control, value range: 0..5

7:0
C n a value range: 0..14
k a
e B
T r
d i a F o shaper rate limit control, value range: 1..255

Me
stepping
00001040 ERLCR_P0 Egress Rate Limit Control Register of Port 0 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r16
ef
Name EGC_RATE_CIR_15_0_P0
s
Type RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
ele
4
a 0
3
0
2
0
1
0
0
R
EG_RA EGC_R
EGC_T
l
TE_LIM ATE_CI EG_RATE_LIMIT_EXP_P0_EGC_
Name
a
B_EN_ EG_RATE_LIMIT_MAN_P0_EGC_TB_CBS_P0
i
IT_EN_ R_16_P TB_T_P0
t
P0
P0 0
Type
Reset
RW
0
RW
0
i d e n P i
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
o n f a n a
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
31:16
f i d e
EGC_RATE_CIR_15_0_P0
a P i When EGC_TB_EN = 1, total 17 bits EGC_RATE_CIR include

EGC_RATE_CIR_16 in bit 12 location, support 32Kbps stepping CIR cover
C o n n a n
up to 2.5Gbps
In MT7531AE/BE, EGC_RATE_CIR = [ Egress Port Rate Limitation(bps) / 8 *
(1/EGC_TB_T) (bps) ]
T e k r B a In MT7531DE, EGC_RATE_CIR = [ 2 * Egress Port Rate Limitation(bps) / 8

* (1/EGC_TB_T) (bps) ]
15
d i a o
EG_RATE_LIMIT_EN_P0
F
Port 0 Egress rate limit control is enabled
0: Egress rate limit control disable
Me
1: Enable
14 EGC_TB_EN_P0 When this bit is disabled, the Egress rate control acts like a leaky bucket
principle.
Otherwise, the Egress rate control uses the token bucket method, and
this approach guarantees some burst level for TCP transaction.
0: CIR/CBS mode token bucket Disable
1: Token bucket mode Enable
f o r
se
12 EGC_RATE_CIR_16_P0 Combined with EGC_RATE_CIR_15_0 to form a 17 bits CIR value
a
11:8 EG_RATE_LIMIT_EXP_P0_EGC_TB_T_P0 Depend on EGC_TB_EN, it can be exponent part for leaky bucket or
e
TB_T period for token bucket
R e lWhen EGC_TB_EN = 0, exponent part of Port 0 Egress rate limit control,

value range: 0..5
t i a l 0: 1Kbps
1: 10Kbps
n
2: 100Kbps
e
3: 1Mbps
n f i d a P i 4: 10Mbps
5: 100Mbps
C o n a n When EGC_TB_EN = 1, support EGC_TB_T period for rate measurement,

value range: 0..14
k a
0: 1/128ms
i a T e o r B 1: 1/64ms
2: 1/32ms
3: 1/16ms
Me d F 4: 1/8ms
5: 1/4ms
6: 1/2ms
7: 1ms
8: 2ms
9: 4ms
10: 8ms
o r
ef
11: 16ms
12: 32ms
13: 64ms
a s
ele
14: 128ms
7:0 EG_RATE_LIMIT_MAN_P0_EGC_TB_CBS Depend on EGC_TB_EN, it can be mantissa part for leaky bucket or
R
_P0 TB_CBS stepping for token bucket
t i a l When EGC_TB_EN = 0, mantissa part of Port 0 Egress rate limit control,

value range: 1..255
In MT7531AE/BE, Egress Port Rate Limitation = MAN*10^(EXP)*1Kbps
i d e n P i
In MT7531DE, Egress Port Rate Limitation = (MAN/2)*10^(EXP)*1Kbps
When EGC_TB_EN = 1, support max. bucket size CBS 512 Bytes stepping,
o n f a n a
and
Token Bucket = Max ( EGC_RATE_CIR*EGC_TB_T, EGC_TB_CBS*512 )
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
00001050 MMSCR2_Q0P0
n t i a Max-Min Scheduler Control Register 2 of Queue 00000000
Bit 31 30
f i d e
29
a P
28
i 27 26
0/Port 0
25 24 23 22 21 20 19 18 17 16
Name
C o n n a n MIN_R
ATE_CI
k a
R_Q0_
Type
i a T e o r B P0
RW
Me d
Reset
Bit
Name
Type
15
F 14 13 12 11 10 9 8
MIN_RATE_CIR_Q0_P0
RW
7 6 5 4 3 2 1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
16:0 MIN_RATE_CIR_Q0_P0 When MIN_MAX_TB_EN = 1, total 17 bits MIN_RATE_CIR, support
32Kbps stepping CIR cover up to 2.5Gbps
e l e a In MT7531AE/BE, MIN_RATE_CIR = [ MIN Shaper Rate Limitation / 8 *

(1/TB_T) ] bps
R
In MT7531DE, MIN_RATE_CIR = [ 2 * MIN Shaper Rate Limitation / 8 *
t i a l (1/TB_T) ] bps
00001054
i d
MMSCR3_Q0P0
e n P i Max-Min Scheduler Control Register 3 of Queue 00000000
Bit 31
o
30
n f 29
a n a28 27 26
0/Port 0
25 24 23 22 21 20 19 18 17 16
Name
e k C B a n MAX_R
ATE_CI
T r
R_Q0_
a o
P0
d
Type
i F RW
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MAX_RATE_CIR_Q0_P0
Type RW
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ef o
s
16:0 MAX_RATE_CIR_Q0_P0
a
When MIN_MAX_TB_EN = 1, total 17 bits MAX_RATE_CIR, support
32Kbps stepping CIR cover up to 2.5Gbps
ele
In MT7531AE/BE, MAX_RATE_CIR = [ MAX Shaper Rate Limitation / 8 *
i a l R (1/TB_T) ] bps
In MT7531DE, MAX_RATE_CIR = [ 2 * MAX Shaper Rate Limitation / 8 *
t
(1/TB_T) ] bps
i d e n P i
00001058
o n f
MMSCR2_Q1P0
a n a Max-Min Scheduler Control Register 2 of Queue

1/Port 0
00000000
Bit
e
31
k C 30
B a n29 28 27 26 25 24 23 22 21 20 19 18 17 16
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a MIN_R
Name
f i d e a P i ATE_CI
R_Q1_
Type
C o n n a n
P0
RW
k a
Reset 0
Bit
Name
i a T e
15 14
o r B 13 12 11 10 9 8
MIN_RATE_CIR_Q1_P0
7 6 5 4 3 2 1 0
Me d
Type
Reset
Bit(s)
0
Name
F 0 0 0 0 0 0
Description
0
RW
0 0 0 0 0 0 0 0
16:0 MIN_RATE_CIR_Q1_P0 Total 17 bits MIN_RATE_CIR, support 32Kbps stepping CIR cover up to
r
2.5Gbps
f o

1/Port 0 se 00000000
Bit 31 30 29 28
l R e 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
n t i a ATE_CI
R_Q1_
e
P0
Type
Reset
n f i d a P i RW
0
Bit 15
C o
14 13
n a n 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Type
Reset
T e0
k 0
r B 0 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
d i a F o
Me
16:0 MAX_RATE_CIR_Q1_P0 Total 17 bits MAX_RATE_CIR, support 32Kbps stepping CIR cover up to
2.5Gbps
o r
ef
2/Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
MIN_R
ATE_CI
R
Name
R_Q2_
Type
t i a l P0
RW
Reset
Bit 15 14
i d e n
13
P i
12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
o n f a n a MIN_RATE_CIR_Q2_P0
RW
Reset
e k
0
C 0
B a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MIN_RATE_CIR_Q2_P0
a P i Total 17 bits MIN_RATE_CIR, support 32Kbps stepping CIR cover up to

2.5Gbps
C o n n a n
00001064
T e k B a
MMSCR3_Q2P0
r
2/Port 0
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q2_
P0
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q2_P0
t i a l Description
Total 17 bits MAX_RATE_CIR, support 32Kbps stepping CIR cover up to
n
2.5Gbps
f i d e a P i
00001068
C o n
MMSCR2_Q3P0
n a n Max-Min Scheduler Control Register 2 of Queue

3/Port 0
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
d i a F o ATE_CI
R_Q3_
Me
P0
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Name MIN_RATE_CIR_Q3_P0
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
3/Port 0
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MAX_R
ATE_CI
i a T e o r B
M e d F
Page 203 of 830
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l R e Scheduler
Confidential A
n t i a R_Q3_
Type
f i d e a P i P0
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
T e k r B a MAX_RATE_CIR_Q3_P0
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
4/Port 0
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
R
ATE_CI
l
Name
R_Q4_
Type
n t i a P0
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
C o n n a n MIN_RATE_CIR_Q4_P0
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MIN_RATE_CIR_Q4_P0
Description
Total 17 bits MIN_RATE_CIR, support 32Kbps stepping CIR cover up to
Me
2.5Gbps

4/Port 0
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MAX_R
ATE_CI
ele
Name
R_Q4_
P0
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MAX_RATE_CIR_Q4_P0
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 204 of 830
f o r
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l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MAX_RATE_CIR_Q4_P0
a P i Total 17 bits MAX_RATE_CIR, support 32Kbps stepping CIR cover up to

2.5Gbps
C o n n a n
00001078
T e k B a
MMSCR2_Q5P0
r
5/Port 0
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_R
ATE_CI
Name
R_Q5_
P0
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MIN_RATE_CIR_Q5_P0
t i a l Description
n
2.5Gbps
f i d e a P i
0000107C
C o n
MMSCR3_Q5P0

5/Port 0
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
d i a F o ATE_CI
R_Q5_
Me
P0
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
6/Port 0
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MIN_R
ATE_CI
i a T e o r B
M e d F
Page 205 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a R_Q6_
Type
f i d e a P i P0
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
T e k r B a MIN_RATE_CIR_Q6_P0
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
6/Port 0
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
R
ATE_CI
l
Name
R_Q6_
Type
n t i a P0
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
C o n n a n MAX_RATE_CIR_Q6_P0
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MAX_RATE_CIR_Q6_P0
Description
Me
2.5Gbps

7/Port 0
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MIN_R
ATE_CI
ele
Name
R_Q7_
P0
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MIN_RATE_CIR_Q7_P0
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 206 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MIN_RATE_CIR_Q7_P0

2.5Gbps
C o n n a n
0000108C
T e k B a
MMSCR3_Q7P0
r
7/Port 0
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q7_
P0
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q7_P0
t i a l Description
n
2.5Gbps
f i d e a P i
00001090
Bit 31
C o
30n
MMSCR_P0
n
29
a n 28 27 26
25 24 23 22 21 20 19 18
00000001
17 16
Name
Type
T e k r B a
d i
Reset
a F o
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_
MAX_T
Name
B_EN_
P0
Type
o rRW
ef
Reset 1
a s
ele
0 MIN_MAX_TB_EN_P0 When this bit is disabled, the rate limit acts like a leaky bucket principle.
R
Otherwise, the rate limit uses the token bucket method, and this
l
approach guarantees some burst level for TCP transaction.
n t i a 0: CIR/CBS mode token bucket Disable

f i d e a P i
000010E0
Bit 31
C o n
GERLCR
30
n a
29
n 28 27 26
Global Egress Rate Limit Control Register
25 24 23 22 21 20 19 18
00000118
17 16
Name
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Type
Reset
Bit 15 14
n f i d13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1 0
Name
C o n a n EGC_M
FRM_E
EGC_IP
EGC_IPG_BYTE
k a
G_OP
X
Type
i
Reset
a T e o r B RW
0
RW
1 0 0 0 1
RW
1 0 0 0
Me d
Bit(s)
9
NameF
EGC_MFRM_EX
Description
When this bit is enabled, management frames are excluded in the
egress rate limit control mechanism; otherwise, management frames
are included.
r
(Management frame type is set by ARL registers)
0: Include management frames
f o
se
1: Exclude management frames
8 EGC_IPG_OP Egress Rate IPG Byte Addition or Subtraction Byte count should be
e l e a added or subtracted for the rate calculation.

0: IPG byte is excluded
R
1: IPG byte is included
7:0 EGC_IPG_BYTE
t i a l Egress Rate IPG Byte Count

Byte count should be added while calculating the rate limit.
0x04: 4 byte CRC
i d e n P i
0x18: 4 byte CRC + 12 byte IPG + 8 byte Preamble (default)
o n f a n a
00001100
e k CMMSCR0_Q0P1
B a n
0/Port 1
00000000
T
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d
Name
i a
MIN_S
P_WRR
F o r
Me
_Q0_P
1
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_R
o r
ef
N_Q0_ 0_P1
P1
a s
ele
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31 MIN_SP_WRR_Q0_P1
i d e n P i
0: Round-Robin (RR)
f
15
C o n
MIN_RATE_EN_Q0_P1
a n a Port 1 Queue 0 min. shaper rate limit control is enabled

e k B a n always let the pkt pass (infinite rate)

d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
11:8
f i d e
a P i Depend on MIN_MAX_TB_EN, it can be exponent part for leaky bucket

C o n n a n
7:0
T e k r B a value range: 0..14

d i a F o or TB_CBS stepping for token bucket

Me
stepping
f o r
00000000
se
0/Port 1
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
MAX_S
P_WFQ
_Q0_P
R e l e MAX_WEIGHT_Q0_P1
Type
1
RW
t i a l RW
Reset
Bit
0
15 14
i d e
13
n 12
P i
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
MAX_R
ATE_E
o n f a n a MAX_RATE_CTRL_EXP_TB_T_Q
C
N_Q0_ 0_P1
Type
P1
e
RW
k B a n RW RW
Reset
d i a T 0
F o r 0 0 0 0 0 0 0 0 0 0 0 0
Me
r
o
ef
a s
ele
i a l R or TB_T period for token bucket

t
n
7:0
i d e P i
value range: 0..14
f a
n
C o n a n When MIN_MAX_TB_EN = 0, mantissa part of Port 1 Queue 0 max.

T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description

stepping
C o n n a n
00001108
T e k B a
MMSCR0_Q1P1
r
1/Port 1
00000000
d
Bit
i a 31
F o30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_S
P_WRR
Name
_Q1_P
1
Type RW
Reset
Bit
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
se
MIN_R
a
e
N_Q1_ 1_P1
Type
P1
RW
R e l RW RW
Reset 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
i d
MIN_SP_WRR_Q1_P1
e n P i
Description
o n f a n a 0: Round-Robin (RR)
15
e k C B a n
MIN_RATE_EN_Q1_P1 Port 1 Queue 1 min. shaper rate limit control is enabled
T
d i
11:8
a F o r
Me
value range: 0..14
r
ef o
s
stepping
ele a
i a l R
e n t i
1/Port 1
00000000
Bit
MAX_S
31
n
30
f i d 29
n a P
28 27 26 25 24 23 22 21 20 19 18 17 16
o
P_WFQ
a
C n
_Q1_P
k a
1
i a T e o r B
M e d F
Page 210 of 830
f o r
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l R e Scheduler
Confidential A
n t i a
e
Type RW RW
Reset
Bit
0
15
n
14
f i d 13
a P
12
i 0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
MAX_R
ATE_E
C o n a n MAX_RATE_CTRL_EXP_TB_T_Q
a
Name
k
N_Q1_ 1_P1
Type
i a
P1
T e
RW
o r B RW RW
Me d
Reset
Bit(s)
31
0
Name
F
MAX_SP_WFQ_Q1_P1
0
Description
0 0 0 0

0 0 0 0 0 0 0
27:24 MAX_WEIGHT_Q1_P1
f o r
se
e l a
e
11:8
i a l
e n t i
d
7:0

o
e B
T r
d i a F o stepping
Me 00001110
Bit 31
MMSCR0_Q2P1
30 29 28 27 26
2/Port 1
25 24 23 22 21 20 19 18
00000000
17 16
MIN_S
o r
ef
P_WRR
Name
s
_Q2_P
a
1
ele
Type RW
Reset 0
Bit
MIN_R
15 14 13
i a l R
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q2_
e n t i
2_P1
d
P1
Type
Reset
RW
o n f i n a P RW RW
a
0 0 0 0 0 0 0 0 0 0 0 0 0
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
31
f i d
MIN_SP_WRR_Q2_P1
e a P i Port 1 Queue 2 min. traffic arbitration scheme
0: Round-Robin (RR)
15
C o n
MIN_RATE_EN_Q2_P1

k a
i a T e o r B
F
Me d or TB_T period for token bucket

value range: 0..14
f o r
se
e e a
stepping
l
00001114 MMSCR1_Q2P1
i a l R Max-Min Scheduler Control Register 1 of Queue 00000000
Bit 31 30
e
29
n t 28
i
27 26
2/Port 1
25 24 23 22 21 20 19 18 17 16
MAX_S
P_WFQ
n f i d n a P
o
a
_Q2_P
Type
1
e
RW
k C B a n RW
Reset
Bit
d i a T 0
15
F o r
14 13 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Me
MAX_R
N_Q2_ 2_P1
P1
Type RW RW RW
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ef o
s
a
ele
i a l R Port 1 Queue 2 weighted value for max. WFQ weighted value is

t
i d e n P i
f
11:8
C o n a n a
MAX_RATE_CTRL_EXP_TB_T_Q2_P1 Depend on MIN_MAX_TB_EN, it can be exponent part for leaky bucket
e k B a n When MIN_MAX_TB_EN = 0, exponent part of Port 1 Queue 2 max.

d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description

value range: 0..14
7:0
o n n
k a
e B
d i a T F o r
stepping

3/Port 1
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_S
P_WRR
f o
se
Name
_Q3_P
a
1
Type
Reset
RW
0
R e l e
Bit
MIN_R
15 14 13
t i a l
12 11 10 9 8 7 6 5 4 3 2 1 0
n
e
N_Q3_ 3_P1
Type
P1
RW
n f i d a P i RW RW
Reset 0
C o n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
T e k
Name
r B a Description
a
d i F o 0: Round-Robin (RR)
Me
r
ef o
s
7:0
value range: 0..14
ele a
i a l R or TB_CBS stepping for token bucket
t
i d e n P i
stepping
o n f a n a
0000111C
e k C B a n
MMSCR1_Q3P1 Max-Min Scheduler Control Register 1 of Queue
3/Port 1
00000000
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
31 30 29
n t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
MAX_S
P_WFQ
n f i d a P i MAX_WEIGHT_Q3_P1
o n
_Q3_P
Type
1
RW
k C a n a RW
Reset
Bit
i a T e0
15
o r
14
B 13 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Me d
Name
Type
MAX_R
ATE_E
N_Q3_
P1
RW
F MAX_RATE_CTRL_EXP_TB_T_Q
3_P1
RW
RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

f o r
l e a
1: Strict Priority (SP) se
l R ePort 1 Queue 3 weighted value for max. WFQ weighted value is

n t i a Port 1 Queue 3 max. shaper rate limit control is enabled

e
11:8
f i d a P
n i 1: Queue 3 max. shaper rate limit control is enabled


k a
e B
d i
7:0
a T o r
value range: 0..14
F or TB_CBS stepping for token bucket
Me
stepping
o r
4/Port 1
a s ef
00000000
le
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
l R e
a
_Q4_P
Type
1
RW
e n t i
Reset
Bit
0
15
n f i
14
d 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
C
ATE_E
o n a n MIN_RATE_CTRL_EXP_TB_T_Q
4_P1
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
N_Q4_
n t i a
Type
P1
RW
f i d e a P i RW RW
Reset 0
C o n n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
T e k
Name
r B a
MIN_SP_WRR_Q4_P1
Description
d i a F o 0: Round-Robin (RR)
Me
f o r
se
a
7:0
e l e
value range: 0..14
R
t i a l When MIN_MAX_TB_EN = 0, mantissa part of Port 1 Queue 4 min. shaper

n
f i d e a P i
stepping
00001124
C o n n a
MMSCR1_Q4P1
Bit
T e k
31
r
30
B a 29 28 27 26
4/Port 1
25 24 23 22 21 20 19 18 17 16
d i a
MAX_S
P_WFQ
F o
Me
_Q4_P
1
Type RW RW
Reset 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MAX_R
ef o
s
N_Q4_ 4_P1
a
P1
ele
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31 MAX_SP_WFQ_Q4_P1
i d e n P i
f
27:24
C o n
MAX_WEIGHT_Q4_P1
a n a Port 1 Queue 4 weighted value for max. WFQ weighted value is

15
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
11:8
C o n a n
n
a
T e k r B

value range: 0..14
Me
stepping
f o r
00001128 MMSCR0_Q5P1

se 00000000
e
5/Port 1
Bit
MIN_S
31 30 29
i a
28
l R 27 26 25 24 23 22 21 20 19 18 17 16
t
P_WRR
Name
n
_Q5_P
Type
1
RW
f i d e a P i
Reset
Bit
0
15
C o n
14 13
n a n 12 11 10 9 8 7 6 5 4 3 2 1 0
k a
MIN_R
e B
T
d
Type
i
N_Q5_
aP1
RW
F o r 5_P1
RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

0: Round-Robin (RR)
o r
ef
s
a
ele
11:8
i a l R
t
i d e n P i
f
value range: 0..14
7:0
C o n a n a
e k B a n When MIN_MAX_TB_EN = 0, mantissa part of Port 1 Queue 5 min. shaper

d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description

stepping
C o n n a n
0000112C
T e k B a
MMSCR1_Q5P1
r
5/Port 1
00000000
d
Bit
i a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_S
P_WFQ
_Q5_P
1
Type RW RW
Reset
Bit
0
15 14 13 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2
f1
o r 0
se
MAX_R
a
e
N_Q5_ 5_P1
Type
P1
RW
R e l RW RW
Reset 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
i d
MAX_SP_WFQ_Q5_P1
e n P i
Description
o n f a n a 0: Weighted Fair Queuing (WFQ)

27:24
e k C
MAX_WEIGHT_Q5_P1
B a n Port 1 Queue 5 weighted value for max. WFQ weighted value is

T
d i a F o r 0: Queue 5 max. shaper rate limit control is disabled, the shaper will
Me
r
7:0
value range: 0..14
ef o
s
ele a
i a l R stepping
e n t i
d
Bit 31
o n f
30
i n
29
a P 28 27 26
6/Port 1
25 24 23 22 21 20 19 18 17 16
Name
k C
MIN_S
P_WRR
a n a
i a T e o r B
M e d F
Page 217 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
_Q6_P
n t i a
Type
1
RW
f i d e a P i
Reset
Bit
0
15
C o n
14
n a
13
n 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
ATE_E
a o
N_Q6_ 6_P1
d i P1
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
0: Round-Robin (RR)
f o
se
e l a
e
11:8
i a l
e n t i
d
7:0

o
e B
T r
d i a F o stepping
Me 00001134
Bit 31
MMSCR1_Q6P1
30 29 28 27 26
6/Port 1
25 24 23 22 21 20 19 18
00000000
17 16
MAX_S
o r
ef
P_WFQ
s
_Q6_P
a
1
ele
Type RW RW
Reset 0 0 0 0 0
Bit
MAX_R
15 14 13
i a l R12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q6_
e n t i
6_P1
d
P1
Type
Reset
RW
o n f i n a P RW RW
a
0 0 0 0 0 0 0 0 0 0 0 0 0
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
31
f i d
MAX_SP_WFQ_Q6_P1
27:24
C o n
MAX_WEIGHT_Q6_P1

k a
15
i a T e o r B
Me d
11:8
F
7:0
value range: 0..14
f o r
se
e l e a
R
stepping
t i a l
00001138
i d e
MMSCR0_Q7P1
n P i
7/Port 1
00000000
Bit
MIN_S
31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
P_WRR
_Q7_P
e k C B a n
T
1
Type
d i
Reset
a RW
0
F o r
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_R
N_Q7_ 7_P1
P1
Type RW RW RW
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
a s
ele
t
i d e n P i
f
11:8
C o n a n a

d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description

value range: 0..14
7:0
o n n
k a
e B
d i a T F o r
stepping
Me 0000113C MMSCR1_Q7P1 Max-Min Scheduler Control Register 1 of Queue

7/Port 1
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_S
P_WFQ
f o
se
_Q7_P
a
1
Type
Reset
RW
0
R e l e 0 0
RW
0 0
Bit
MAX_R
15 14 13
t i a l
12 11 10 9 8 7 6 5 4 3 2 1 0
n
e
N_Q7_ 7_P1
Type
P1
RW
n f i d a P i RW RW
Reset 0
C o n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
T e k
Name
r B a Description
a
Me
r
ef o
s
ele a
7:0

i
t
i d e n P i
f
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
00001140 ERLCR_P1
n t i a Egress Rate Limit Control Register of Port 1 00000000

Bit 31 30
f i d e
29
a
28
P i 27 26 25 24 23 22 21 20 19 18 17 16
n
Type
Reset 0
C o 0
n0
a n 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit
T
EG_RA
e
15
k 14
r B a 13 12
EGC_R
11 10 9 8 7 6 5 4 3 2 1 0
a
EGC_T
Name
d i
TE_LIM
IT_EN_
F o
B_EN_
ATE_CI EG_RATE_LIMIT_EXP_P1_EGC_
R_16_P TB_T_P1
EG_RATE_LIMIT_MAN_P1_EGC_TB_CBS_P1
Me
P1
P1 1
Type RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:16
Name
Description
When EGC_TB_EN = 1, total 17 bits EGC_RATE_CIR include
f o r
se
up to 2.5Gbps
e l e a
R
In MT7531DE, EGC_RATE_CIR = [ 2 * Egress Port Rate Limitation(bps) / 8
l
15 EG_RATE_LIMIT_EN_P1
n t i a Port 1 Egress rate limit control is enabled

e
1: Enable
14 EGC_TB_EN_P1
n f i d a P i When this bit is disabled, the Egress rate control acts like a leaky bucket
principle.
C o n a n Otherwise, the Egress rate control uses the token bucket method, and
k a
12
i a T e r B
EGC_RATE_CIR_16_P1
o
Combined with EGC_RATE_CIR_15_0 to form a 17 bits CIR value
F
Me d TB_T period for token bucket

When EGC_TB_EN = 0, exponent part of Port 1 Egress rate limit control,
value range: 0..5
0: 1Kbps
1: 10Kbps
2: 100Kbps
3: 1Mbps
o r
ef
4: 10Mbps
5: 100Mbps
When EGC_TB_EN = 1, support EGC_TB_T period for rate measurement,
a s
ele
value range: 0..14
0: 1/128ms
R
1: 1/64ms
t i a l 2: 1/32ms
3: 1/16ms
n
4: 1/8ms
f i d e a P i
5: 1/4ms
6: 1/2ms
n
7: 1ms
C o n a n 8: 2ms
9: 4ms
k a
10: 8ms
i a T e o r B
M e d F
Page 221 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 11: 16ms
12: 32ms
C o n n a n 13: 64ms
14: 128ms
k a
e B
d i a T F o r
When EGC_TB_EN = 0, mantissa part of Port 1 Egress rate limit control,
value range: 1..255
Me
and
f o r
se
a
0/Port 1
Bit 31 30 29 28
R e l e 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
ATE_CI
l
Name
a
R_Q0_
Type
e n t i P1
RW
Reset
Bit 15 14
n f i d 13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
C o n a n MIN_RATE_CIR_Q0_P1
RW
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a
Bit(s)
d
Name
F o Description
Me
2.5Gbps
r
Bit 31 30 29 28 27 26
0/Port 1
25 24 23 22 21 20 19 18
ef
17
o 16
a s MAX_R
ele
ATE_CI
Name
R_Q0_
P1
Type
Reset
i a l R RW
t
0
Bit
Name
15 14
i d e n
13
P
12
i
11 10 9 8
MAX_RATE_CIR_Q0_P1
7 6 5 4 3 2 1 0
Type
Reset 0
o n f
0
a
0
n a 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MAX_RATE_CIR_Q0_P1

2.5Gbps
C o n n a n
00001158
T e k B a
MMSCR2_Q1P1
r
1/Port 1
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_R
ATE_CI
Name
R_Q1_
P1
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MIN_RATE_CIR_Q1_P1
t i a l Description
n
2.5Gbps
f i d e a P i
0000115C
C o n
MMSCR3_Q1P1

1/Port 1
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
d i a F o ATE_CI
R_Q1_
Me
P1
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
2/Port 1
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MIN_R
ATE_CI
i a T e o r B
M e d F
Page 223 of 830
f o r
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l R e Scheduler
Confidential A
n t i a R_Q2_
Type
f i d e a P i P1
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
2/Port 1
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
R
ATE_CI
l
Name
R_Q2_
Type
n t i a P1
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MAX_RATE_CIR_Q2_P1
Description
Me
2.5Gbps

3/Port 1
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MIN_R
ATE_CI
ele
Name
R_Q3_
P1
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MIN_RATE_CIR_Q3_P1
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 224 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MIN_RATE_CIR_Q3_P1

2.5Gbps
C o n n a n
0000116C
T e k B a
MMSCR3_Q3P1
r
3/Port 1
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q3_
P1
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q3_P1
t i a l Description
n
2.5Gbps
f i d e a P i
00001170
C o n
MMSCR2_Q4P1

4/Port 1
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
d i a F o ATE_CI
R_Q4_
Me
P1
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
4/Port 1
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MAX_R
ATE_CI
i a T e o r B
M e d F
Page 225 of 830
f o r
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l R e Scheduler
Confidential A
n t i a R_Q4_
Type
f i d e a P i P1
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
5/Port 1
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
R
ATE_CI
l
Name
R_Q5_
Type
n t i a P1
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MIN_RATE_CIR_Q5_P1
Description
Me
2.5Gbps

5/Port 1
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MAX_R
ATE_CI
ele
Name
R_Q5_
P1
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MAX_RATE_CIR_Q5_P1
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 226 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MAX_RATE_CIR_Q5_P1

2.5Gbps
C o n n a n
00001180
T e k B a
MMSCR2_Q6P1
r
6/Port 1
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_R
ATE_CI
Name
R_Q6_
P1
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MIN_RATE_CIR_Q6_P1
t i a l Description
n
2.5Gbps
f i d e a P i
00001184
C o n
MMSCR3_Q6P1

6/Port 1
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
d i a F o ATE_CI
R_Q6_
Me
P1
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
7/Port 1
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MIN_R
ATE_CI
i a T e o r B
M e d F
Page 227 of 830
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l R e Scheduler
Confidential A
n t i a R_Q7_
Type
f i d e a P i P1
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
7/Port 1
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
R
ATE_CI
l
Name
R_Q7_
Type
n t i a P1
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MAX_RATE_CIR_Q7_P1
Description
Me
2.5Gbps
00001190 MMSCR_P1 Max-Min Scheduler Control Register of Port 1 00000001

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
Name
Type
a s
ele
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a l R MIN_
MAX_T
t
B_EN_
Type
i d e n P i
P1
RW
Reset
o n f a n a
1
Bit(s)
0
e k C
Name
B a n
MIN_MAX_TB_EN_P1
Description
When this bit is disabled, the rate limit acts like a leaky bucket principle.
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i Otherwise, the rate limit uses the token bucket method, and this
C o n n a n 0: CIR/CBS mode token bucket Disable

T e k r B a
i a
00001200
d F oMMSCR0_Q0P2 Max-Min Scheduler Control Register 0 of Queue 00000000
Me
0/Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_S
P_WRR
Name
_Q0_P
r
2
Type RW
f o
se
Reset 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
ATE_E
N_Q0_
R e l e
0_P2
Type
P2
RW
t i a l RW RW
Reset 0
i d e n P i
0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
o n f
MIN_SP_WRR_Q0_P2
a n a Description
e k C B a n 0: Round-Robin (RR)
T r
d i a F o 0: Queue 0 min. shaper rate limit control is disabled, the shaper will
Me
o r
ef
value range: 0..14
a s
ele
i a l R stepping
e n t i
d
Bit 31
o n f
30 i 29
n a P 28 27 26
0/Port 2
25 24 23 22 21 20 19 18 17 16
Name
MAX_S
P_WFQ
k C a n a MAX_WEIGHT_Q0_P2
i a T e o r B
M e d F
Page 229 of 830
f o r
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l R e Scheduler
Confidential A
_Q0_P
n t i a
Type
2
RW
f i d e a P i RW
Reset
Bit
0
15
C o n
14
n a
13
n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
MAX_R
ATE_E
a o
N_Q0_ 0_P2
d i P2
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
f o
se
e l e a

11:8
e n t
i
d

7:0
k a
e B
T r

Me
stepping

1/Port 2
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
MIN_S
a
P_WRR
Name
ele
_Q1_P
2
Type
Reset
RW
0
i a l R
Bit
MIN_R
15 14
e n t
13
i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q1_
P2
n f i d n a P
1_P2
Type
Reset
k C
RW
0 o a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
M e d F
Page 230 of 830
f o r
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l R e Scheduler
Confidential A
n t i a
Bit(s) Name
n
C o n a n 0: Round-Robin (RR)
15
T e k r B a
a o
d i F
Me
r
value range: 0..14
f o
se
a
R e l e
stepping
t i a l
i d e n P i
1/Port 2
00000000
Bit
MAX_S
31
o
30
n f 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
C
P_WFQ
Name
_Q1_P
2
e k B a n MAX_WEIGHT_Q1_P2
Type
i
Reset
d a T RW
0
F o r 0 0
RW
0 0
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_R
N_Q1_ 1_P2
P2
r
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 1: Strict Priority (SP)

15
e n
MAX_RATE_EN_Q1_P2
t i
n f i d n a P
o
11:8
k C a n a
i a T e o r B
M e d F
Page 231 of 830
f o r
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l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When MIN_MAX_TB_EN = 0, exponent part of Port 2 Queue 1 max.

C o n n a n When MIN_MAX_TB_EN = 1, support TB_T period for rate measurement,

value range: 0..14
k a
e B
d i a T F o r
Me
stepping
Bit 31 30 29 28 27 26
2/Port 2
25 24 23 22 21 20 19 18
f
17
o r 16
se
MIN_S
Name
P_WRR
_Q2_P
2
e l e a
Type
Reset
RW
0
i a l R
Bit
MIN_R
15 14 13
e n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q2_
n f i d n a P
2_P2
o
P2
Type
Reset
RW
0
k C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
F
Me d
31
15
MIN_SP_WRR_Q2_P2
MIN_RATE_EN_Q2_P2
0: Round-Robin (RR)
r
11:8 MIN_RATE_CTRL_EXP_TB_T_Q2_P2
ef o
s
ele a
7:0

i
t
i d e n P i
f
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
00001214 MMSCR1_Q2P2
Bit 31 30
f i d e
29
a P
28
i 27 26
2/Port 2
25 24 23 22 21 20 19 18 17 16
Name
MAX_S
P_WFQ
C o n n a n MAX_WEIGHT_Q2_P2
k a
_Q2_P
Type
i a
2
T e
RW
o r B RW
Me d
Reset
Bit
Name
MAX_R
ATE_E
N_Q2_
0
15
F 14 13 12
0
11
0
10
0
9
2_P2
0
8 7 6 5 4 3
2 1 0
P2
Type
Reset
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0
f0
o r 0
Bit(s) Name
e a
Description
l se
e
R

n
15
f i d e
MAX_RATE_EN_Q2_P2
a P i
n
11:8
C o n a n
T e k r B a or TB_T period for token bucket

Me
value range: 0..14
stepping
o r
a s ef
le
Bit 31 30 29
l R e28 27 26
3/Port 2
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
_Q3_P
n t i a
Type
2
RW
f i d e a P i
Reset
Bit
C o
0
15
n 14
n a n13 12 11 10 9 8 7 6 5 4 3 2 1 0
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
MIN_R
n t i a
Name
ATE_E
N_Q3_
f i d e a P i MIN_RATE_CTRL_EXP_TB_T_Q
3_P2
Type
P2
RW
C o n n a n RW RW
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a
Bit(s)
T e
Name
o r B Description
Me d
31
15
F
MIN_SP_WRR_Q3_P2
MIN_RATE_EN_Q3_P2
0: Round-Robin (RR)
f o r
se
a
e
R e l
value range: 0..14
7:0
t i a l
n
e
n f i d a P i When MIN_MAX_TB_EN = 1, support max. bucket size TB_CBS 512 Bytes

stepping
C o n a n
0000121C
T e k B a
MMSCR1_Q3P2
r
3/Port 2
00000000
d
Bit
i a 31
F o30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_S
P_WFQ
_Q3_P
2
Type RW RW
Reset 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
MAX_R
a
ele
N_Q3_ 3_P2
P2
Type
Reset
RW
0
i a l R 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
e n t i
Description
31
f i d
MAX_SP_WFQ_Q3_P2
n n a P Port 2 Queue 3 max. traffic arbitration scheme

27:24
k C o n a
MAX_WEIGHT_Q3_P2
a
i a T e o r B
Med F
Page 234 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
15
f i d e
MAX_RATE_EN_Q3_P2
a P i Port 2 Queue 3 max. shaper rate limit control is enabled

C o n n a n
k a
e B
d i a T F o r
Me
value range: 0..14
stepping
f o r
l e a se 00000000
Bit 31 30 29
l R
28 27 26
4/Port 2
25 24 23 22 21 e20 19 18 17 16
MIN_S
P_WRR
n t i a
e
Name
i
_Q4_P
Type
2
RW
n f i d n a P
Reset
Bit
k
0
15
C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a T e
MIN_R
ATE_E
N_Q4_
o r B MIN_RATE_CTRL_EXP_TB_T_Q
4_P2
M e d
Type
Reset
P2
RW
0
F 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0

o r
ef
0: Round-Robin (RR)
a s
ele
11:8
a l R
i
t
i d e n P i
f
7:0
o n a n a value range: 0..14

C
e k B a n or TB_CBS stepping for token bucket
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When MIN_MAX_TB_EN = 0, mantissa part of Port 2 Queue 4 min. shaper


stepping
T e k r B a
d i a
00001224
F oMMSCR1_Q4P2 Max-Min Scheduler Control Register 1 of Queue 00000000
Me
4/Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_S
P_WFQ
_Q4_P
r
2
Type RW RW
f o
se
Reset 0 0 0 0 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l e
MAX_R
e
R
N_Q4_ 4_P2
Type
P2
RW
t i a l RW RW
Reset 0
i d e n P i
0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
o n f
MAX_SP_WFQ_Q4_P2
a n a Description
e k C B a n
T
d
15
i a F o r
MAX_RATE_EN_Q4_P2
Me
r
ef o
s
value range: 0..14
ele a
i a l R shaper rate limit control, value range: 1..255
t
stepping
i d e n P i
00001228
o n f
MMSCR0_Q5P2

5/Port 2
00000000
Bit
e k
31
C 30
B a n 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
MIN_S
n t i a
Name
P_WRR
_Q5_P
f i d e a P i
Type
2
RW
C o n n a n
k a
Reset 0
Bit
i a T
MIN_R
e
15
o
14
r B 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F
d
Me
N_Q5_ 5_P2
P2
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
MIN_SP_WRR_Q5_P2
Description
f o r
se
0: Round-Robin (RR)
e l e a

11:8
e n t
i
d

7:0

k a
e
i a T o r B When MIN_MAX_TB_EN = 0, mantissa part of Port 2 Queue 5 min. shaper

Me d F When MIN_MAX_TB_EN = 1, support max. bucket size TB_CBS 512 Bytes

stepping

5/Port 2
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
MAX_S
a
P_WFQ
ele
_Q5_P
2
Type
Reset
RW
0
i a l R 0 0
RW
0 0
Bit
MAX_R
15 14
e
13
n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
d
Name
N_Q5_
P2
o n f i n a P 5_P2
Type
Reset
RW
k
0
C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
M e d F
Page 237 of 830
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l R e Scheduler
Confidential A
n t i a
Bit(s) Name
n
C o n a n 0: Weighted Fair Queuing (WFQ)

27:24
T e k r B a
MAX_WEIGHT_Q5_P2 Port 2 Queue 5 weighted value for max. WFQ weighted value is
a o
d i F
Me
r
value range: 0..14
f o
se
a
R e l e
t i a l stepping
i d e n P i
f
Bit 31
C o n
30 29
a n a 28 27 26
6/Port 2
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
e k B a n
d
Type
i
2
T
_Q6_P
a RW
F o r
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_R
r
N_Q6_ 6_P2
Type
P2
RW RW RW
ef o
Reset 0 0 0 0 0 0 0 0 0
a s 0 0 0 0
Bit(s)
31
Name
MIN_SP_WRR_Q6_P2
l R
Description
ele
n t i a 0: Round-Robin (RR)
e
n f i d a P i 0: Queue 6 min. shaper rate limit control is disabled, the shaper will
11:8
C o a n
n
k a
i a T e o r B
M e d F
Page 238 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When MIN_MAX_TB_EN = 0, exponent part of Port 2 Queue 6 min.


value range: 0..14
k a
e B
d i a T F o r
Me
stepping
Bit 31 30 29 28 27 26
6/Port 2
25 24 23 22 21 20 19 18
f
17
o r 16
se
MAX_S
Name
P_WFQ
_Q6_P
2
e l e a MAX_WEIGHT_Q6_P2
Type
Reset
RW
0
i a l R 0 0
RW
0 0
Bit
MAX_R
15 14 13
e n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q6_
n f i d n a P
6_P2
o
P2
Type
Reset
RW
0
k C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
F
Me d
31
27:24
MAX_SP_WFQ_Q6_P2
MAX_WEIGHT_Q6_P2
r
ef o
s
ele a
t
value range: 0..14
7:0
i d n
e P i
f
C o n a n a shaper rate limit control, value range: 1..255

e k B a n stepping
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001238
C o n
MMSCR0_Q7P2
n a n Max-Min Scheduler Control Register 0 of Queue 00000000
k a
7/Port 2
Bit
i a T
MIN_S
e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d F
P_WRR
Name
Me
_Q7_P
2
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
f o r
se
N_Q7_ 7_P2
P2
Type
Reset
RW
0
e l e a
0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
i a l R Description
31 MIN_SP_WRR_Q7_P2
e n t i
0: Round-Robin (RR)
15
n f i d
MIN_RATE_EN_Q7_P2
n a P
k C o a n a
11:8
i a T e o r B
Me d
7:0
F When MIN_MAX_TB_EN = 0, exponent part of Port 2 Queue 7 min.
value range: 0..14
r
ef o
s
stepping
ele a
i a l R Max-Min Scheduler Control Register 1 of Queue

7/Port 2
00000000
Bit
MAX_S
31 30
e
29
n t 28
i
27 26 25 24 23 22 21 20 19 18 17 16
Name
P_WFQ
_Q7_P
n f i d n a P MAX_WEIGHT_Q7_P2
o
2
Type
Reset
RW
k0
C a n a 0 0
RW
0 0
i a T e o r B
M e d F
Page 240 of 830
f o r
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l R e Scheduler
Confidential A
15 14 13
n t i a 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Bit
Name
MAX_R
ATE_E
n f i d a P i MAX_RATE_CTRL_EXP_TB_T_Q
n
N_Q7_ 7_P2
Type
P2
RW
k C o a n a RW RW
Reset
i a T e0
o r B 0 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit(s)
31
Name
F
MAX_SP_WFQ_Q7_P2
Description
f o r
se
a
R e l e
t i a l shaper rate limit control, value range: 0..5

n
value range: 0..14
7:0
f i e a P i
d or TB_CBS stepping for token bucket
n
C o n a n shaper rate limit control, value range: 1..255

k a
stepping
i a T e o r B
Me d
00001240
Bit
Name
31 F ERLCR_P2
30 29 28 27 26
25 24 23
22 21 20 19 18
00000000
17 16
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r0
ef
EG_RA EGC_R
EGC_T
s
Name B_EN_ EG_RATE_LIMIT_MAN_P2_EGC_TB_CBS_P2
a
P2
ele
P2 2
Type RW RW RW RW RW
Reset 0 0
i a l R0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:16
Name
e n t
i
Description
When EGC_TB_EN = 1, total 17 bits EGC_RATE_CIR include
n f i d n a P EGC_RATE_CIR_16 in bit 12 location, support 32Kbps stepping CIR cover

up to 2.5Gbps
k C o a n a
i a T e o r B
M e d F
Page 241 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i In MT7531DE, EGC_RATE_CIR = [ 2 * Egress Port Rate Limitation(bps) / 8

15
C o n
EG_RATE_LIMIT_EN_P2
n a n Port 2 Egress rate limit control is enabled

k a
1: Enable
14
i a T e o r B
EGC_TB_EN_P2 When this bit is disabled, the Egress rate control acts like a leaky bucket
principle.
F
Me d
12 EGC_RATE_CIR_16_P2
r
o
value range: 0..5
0: 1Kbps
se f
a
1: 10Kbps
R e l e
2: 100Kbps
3: 1Mbps
4: 10Mbps
t i a l 5: 100Mbps
n
value range: 0..14
f i d e a P i
0: 1/128ms
1: 1/64ms
n
2: 1/32ms
C o n a n 3: 1/16ms
4: 1/8ms
T e k r B a 5: 1/4ms
6: 1/2ms
7: 1ms
d i a F o 8: 2ms
Me
9: 4ms
10: 8ms
11: 16ms
12: 32ms
13: 64ms
14: 128ms
o r
ef
value range: 1..255
a s
ele
R
t i a l and
i d e n P i
00001250
o n f
MMSCR2_Q0P2

0/Port 2
00000000
Bit
e
31
k C 30
B a n 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a MIN_R
Name
f i d e a P i ATE_CI
R_Q0_
Type
C o n n a n
P2
RW
k a
Reset 0
Bit
Name
i a T e
15 14
o r B 13 12 11 10 9 8
MIN_RATE_CIR_Q0_P2
7 6 5 4 3 2 1 0
Me d
Type
Reset
Bit(s)
0
Name
F 0 0 0 0 0 0
Description
0
RW
0 0 0 0 0 0 0 0
r
2.5Gbps
f o
00001254 MMSCR3_Q0P2

0/Port 2 se 00000000
Bit 31 30 29 28
l R e 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
n t i a ATE_CI
R_Q0_
e
P2
Type
Reset
n f i d a P i RW
0
Bit 15
C o
14 13
n a n 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Type
Reset
T e0
k 0
r B 0 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
d i a F o
Me
2.5Gbps
o r
ef
1/Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
MIN_R
ATE_CI
R
Name
R_Q1_
Type
t i a l P2
RW
Reset
Bit 15 14
i d e n
13
P i
12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
o n f a n a MIN_RATE_CIR_Q1_P2
RW
Reset
e k
0
C 0
B a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MIN_RATE_CIR_Q1_P2

2.5Gbps
C o n n a n
0000125C
T e k B a
MMSCR3_Q1P2
r
1/Port 2
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q1_
P2
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q1_P2
t i a l Description
n
2.5Gbps
f i d e a P i
00001260
C o n
MMSCR2_Q2P2

2/Port 2
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
d i a F o ATE_CI
R_Q2_
Me
P2
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
2/Port 2
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MAX_R
ATE_CI
i a T e o r B
M e d F
Page 244 of 830
f o r
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l R e Scheduler
Confidential A
n t i a R_Q2_
Type
f i d e a P i P2
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
3/Port 2
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
R
ATE_CI
l
Name
R_Q3_
Type
n t i a P2
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MIN_RATE_CIR_Q3_P2
Description
Me
2.5Gbps

3/Port 2
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MAX_R
ATE_CI
ele
Name
R_Q3_
P2
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MAX_RATE_CIR_Q3_P2
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 245 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MAX_RATE_CIR_Q3_P2

2.5Gbps
C o n n a n
00001270
T e k B a
MMSCR2_Q4P2
r
4/Port 2
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_R
ATE_CI
Name
R_Q4_
P2
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MIN_RATE_CIR_Q4_P2
t i a l Description
n
2.5Gbps
f i d e a P i
00001274
C o n
MMSCR3_Q4P2

4/Port 2
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
d i a F o ATE_CI
R_Q4_
Me
P2
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
5/Port 2
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MIN_R
ATE_CI
i a T e o r B
M e d F
Page 246 of 830
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l R e Scheduler
Confidential A
n t i a R_Q5_
Type
f i d e a P i P2
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
5/Port 2
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
R
ATE_CI
l
Name
R_Q5_
Type
n t i a P2
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MAX_RATE_CIR_Q5_P2
Description
Me
2.5Gbps

6/Port 2
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MIN_R
ATE_CI
ele
Name
R_Q6_
P2
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MIN_RATE_CIR_Q6_P2
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 247 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MIN_RATE_CIR_Q6_P2

2.5Gbps
C o n n a n
00001284
T e k B a
MMSCR3_Q6P2
r
6/Port 2
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q6_
P2
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q6_P2
t i a l Description
n
2.5Gbps
f i d e a P i
00001288
C o n
MMSCR2_Q7P2

7/Port 2
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
d i a F o ATE_CI
R_Q7_
Me
P2
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
7/Port 2
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MAX_R
ATE_CI
i a T e o r B
M e d F
Page 248 of 830
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l R e Scheduler
Confidential A
n t i a R_Q7_
Type
f i d e a P i P2
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
00001290 MMSCR_P2 Max-Min Scheduler Control Register of Port 2 00000001
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e l e a
Reset
Bit 15 14 13
i a l
12
R 11 10 9 8 7 6 5 4 3 2 1 0
e n t i
MIN_
MAX_T
d
Name
i P
B_EN_
Type
o n f a n a
P2
RW
Reset
e k C B a n
1
Bit(s)
d
0
i a T Name
F o r
MIN_MAX_TB_EN_P2
Description
Me
o r
ef
Bit 31 30 29 28 27 26
0/Port 3
25 24 23 22 21 20
le a s
19 18 17 16
e
MIN_S
R
P_WRR
Name
_Q0_P
3
t i a l
n
Type RW
Reset
Bit
0
15
f i
14
d e 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
ATE_E
C
N_Q0_
o n n a n MIN_RATE_CTRL_EXP_TB_T_Q
0_P3
T e k
P3
r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Type RW RW RW
Reset 0
n f i d a P i 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
k a
e B
0: Round-Robin (RR)
15
d i a T F o r
MIN_RATE_EN_Q0_P3
Me
f o r
se
value range: 0..14
a
R e l e
t i a l When MIN_MAX_TB_EN = 1, support max. bucket size TB_CBS 512 Bytes

stepping
i d e n P i
00001304
o n f
MMSCR1_Q0P3

0/Port 3
00000000
Bit
MAX_S
31
e k C 30
B a n
29 28 27 26 25 24 23 22 21 20 19 18 17 16
T r
P_WFQ
a
d i
_Q0_P
3
F o
Me
Type RW RW
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_R
r
o
N_Q0_ 0_P3
ef
P3
s
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0
ele a 0 0 0 0
Bit(s)
31
Name
MAX_SP_WFQ_Q0_P3
i a l R Description
t
27:24
d e
MAX_WEIGHT_Q0_P3
i n P i
15
n f
MAX_RATE_EN_Q0_P3
o a n a
e k C B a n always let the pkt pass (infinite rate)

d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
11:8
f i d e
a P i Depend on MIN_MAX_TB_EN, it can be exponent part for leaky bucket

C o n n a n
7:0
T e k r B a value range: 0..14

d i a F o or TB_CBS stepping for token bucket

Me
stepping
f o r
00000000
se
1/Port 3
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
_Q1_P
R e l e
Type
3
RW
t i a l
Reset
Bit
0
15 14
i d e
13
n 12
P i 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
ATE_E
o n f a n a MIN_RATE_CTRL_EXP_TB_T_Q
C
N_Q1_ 1_P3
Type
P3
e
RW
k B a n RW RW
Reset
d i a T 0
F o r 0 0 0 0 0 0 0 0 0 0 0 0
Me
0: Round-Robin (RR)
r
o
ef
a s
ele

t
value range: 0..14
n
f i d e a P i
n
C o n a n When MIN_MAX_TB_EN = 1, support max. bucket size TB_CBS 512 Bytes

stepping
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
0000130C
i d e
MMSCR1_Q1P3
f a P i Max-Min Scheduler Control Register 1 of Queue 00000000
n
1/Port 3
Bit
MAX_S
31
C o30 29
n a n 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
P_WFQ
T
_Q1_P
e k r B a MAX_WEIGHT_Q1_P3
a o
3
d
Type
i RW
F RW
Me
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_R
N_Q1_ 1_P3
Type
P3
RW RW RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a
Description
31 MAX_SP_WFQ_Q1_P3
i a l R Port 3 Queue 1 max. traffic arbitration scheme

t
i d e n P i
f
C o n a n a 0: Queue 1 max. shaper rate limit control is disabled, the shaper will
11:8
k a n
e B
T r
d i a F o
Me
value range: 0..14
r
stepping
ef o
a s
00001310 MMSCR0_Q2P3
l R
2/Port 3
ele 00000000
Bit
MIN_S
31 30
n t i
29
a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
P_WRR
Name
_Q2_P
3
n f i d a P i
Type
Reset
C o
RW
0
n a n
Bit
T e k 15
r B
14
a 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ed i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
MIN_R
n t i a
Name
ATE_E
N_Q2_
2_P3
Type
P3
RW
C o n n a n RW RW
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a
Bit(s)
T e
Name
o r B Description
Me d
31
15
F
MIN_SP_WRR_Q2_P3
MIN_RATE_EN_Q2_P3
0: Round-Robin (RR)
f o r
se
a
e
R e l
value range: 0..14
7:0
t i a l
n
e

stepping
C o n a n
00001314
T e k B a
MMSCR1_Q2P3
r
2/Port 3
00000000
d
Bit
i a 31
F o30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_S
P_WFQ
_Q2_P
3
Type RW RW
Reset 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
MAX_R
a
ele
N_Q2_ 2_P3
P3
Type
Reset
RW
0
i a l R 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
e n t i
Description
31
f i d
MAX_SP_WFQ_Q2_P3

27:24
k C o n a
MAX_WEIGHT_Q2_P3
a
i a T e o r B
Med F
Page 253 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
15
f i d e
MAX_RATE_EN_Q2_P3

C o n n a n
k a
e B
d i a T F o r
Me
value range: 0..14
stepping
f o r
l e a se 00000000
Bit 31 30 29
l R
28 27 26
3/Port 3
25 24 23 22 21 e20 19 18 17 16
MIN_S
P_WRR
n t i a
e
Name
i
_Q3_P
Type
3
RW
n f i d n a P
Reset
Bit
k
0
15
C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a T e
MIN_R
ATE_E
N_Q3_
3_P3
M e d
Type
Reset
P3
RW
0
F 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0

o r
ef
0: Round-Robin (RR)
a s
ele
11:8
a l R
i
t
i d e n P i
f
7:0

C
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


stepping
T e k r B a
d i a
0000131C
Me
3/Port 3
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_S
P_WFQ
_Q3_P
r
3
Type RW RW
f o
se
Reset 0 0 0 0 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l e
MAX_R
e
R
N_Q3_ 3_P3
Type
P3
RW
t i a l RW RW
Reset 0
i d e n P i
0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
o n f
MAX_SP_WFQ_Q3_P3
a n a Description
e k C B a n
T
d
15
i a F o r
MAX_RATE_EN_Q3_P3
Me
r
ef o
s
value range: 0..14
ele a
t
stepping
i d e n P i
00001320
o n f
MMSCR0_Q4P3

4/Port 3
00000000
Bit
e k
31
C 30
B a n 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
MIN_S
n t i a
Name
P_WRR
_Q4_P
f i d e a P i
Type
3
RW
C o n n a n
k a
Reset 0
Bit
i a T
MIN_R
e
15
o
14
r B 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F
d
Me
N_Q4_ 4_P3
P3
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
MIN_SP_WRR_Q4_P3
Description
f o r
se
0: Round-Robin (RR)
e l e a

11:8
e n t
i
d

7:0

k a
e


stepping

4/Port 3
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
MAX_S
a
P_WFQ
ele
_Q4_P
3
Type
Reset
RW
0
i a l R 0 0
RW
0 0
Bit
MAX_R
15 14
e
13
n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
d
Name
N_Q4_
P3
o n f i n a P 4_P3
Type
Reset
RW
k
0
C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
M e d F
Page 256 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
Bit(s) Name
n

27:24
T e k r B a
a o
d i F
Me
r
value range: 0..14
f o
se
a
R e l e
t i a l stepping
i d e n P i
f
Bit 31
C o n
30 29
a n a 28 27 26
5/Port 3
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
e k B a n
d
Type
i
3
T
_Q5_P
a RW
F o r
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_R
r
N_Q5_ 5_P3
Type
P3
RW RW RW
ef o
Reset 0 0 0 0 0 0 0 0 0
a s 0 0 0 0
Bit(s)
31
Name
MIN_SP_WRR_Q5_P3
l R
Description
ele
e
11:8
C o a n
n
k a
i a T e o r B
M e d F
Page 257 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


value range: 0..14
k a
e B
d i a T F o r
Me
stepping
Bit 31 30 29 28 27 26
5/Port 3
25 24 23 22 21 20 19 18
f
17
o r 16
se
MAX_S
Name
P_WFQ
_Q5_P
3
Type
Reset
RW
0
i a l R 0 0
RW
0 0
Bit
MAX_R
15 14 13
e n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q5_
n f i d n a P
5_P3
o
P3
Type
Reset
RW
0
k C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
F
Me d
31
27:24
MAX_SP_WFQ_Q5_P3
MAX_WEIGHT_Q5_P3
r
ef o
s
ele a
t
value range: 0..14
7:0
i d n
e P i
f

e k B a n stepping
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001330
C o n
MMSCR0_Q6P3
k a
6/Port 3
Bit
i a T
MIN_S
e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d F
P_WRR
Name
Me
_Q6_P
3
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
f o r
se
N_Q6_ 6_P3
P3
Type
Reset
RW
0
e l e a
0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
i a l R Description
31 MIN_SP_WRR_Q6_P3
e n t i
0: Round-Robin (RR)
15
n f i d
MIN_RATE_EN_Q6_P3
n a P
k C o a n a
11:8
i a T e o r B
Me d
7:0
F When MIN_MAX_TB_EN = 0, exponent part of Port 3 Queue 6 min.
value range: 0..14
r
ef o
s
stepping
ele a
00001334 MMSCR1_Q6P3
i a l R Max-Min Scheduler Control Register 1 of Queue

6/Port 3
00000000
Bit
MAX_S
31 30
e
29
n t 28
i
27 26 25 24 23 22 21 20 19 18 17 16
Name
P_WFQ
_Q6_P
n f i d n a P MAX_WEIGHT_Q6_P3
o
3
Type
Reset
RW
k0
C a n a 0 0
RW
0 0
i a T e o r B
M e d F
Page 259 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
15 14 13
n t i a 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Bit
Name
MAX_R
ATE_E
n f i d a P i MAX_RATE_CTRL_EXP_TB_T_Q
n
N_Q6_ 6_P3
Type
P3
RW
k C o a n a RW RW
Reset
i a T e0
o r B 0 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit(s)
31
Name
F
MAX_SP_WFQ_Q6_P3
Description
f o r
se
a
R e l e
t i a l shaper rate limit control, value range: 0..5

n
value range: 0..14
7:0
f i e a P i
d or TB_CBS stepping for token bucket
n
C o n a n shaper rate limit control, value range: 1..255

k a
stepping
i a T e o r B
Me d
00001338
Bit
MIN_S
31
F MMSCR0_Q7P3
30 29 28 27 26
7/Port 3
25 24 23 22 21 20 19 18
00000000
17 16
P_WRR
Name
_Q7_P
o r
ef
3
Type RW
Reset
Bit
0
15 14 13 12 11 10 9 8 7 6 5 4
le a s
3 2 1 0
Name
MIN_R
ATE_E
N_Q7_
l R e MIN_RATE_CTRL_EXP_TB_T_Q
7_P3
Type
P3
RW
n t i a RW RW
Reset 0
f i d e a P i 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
C o n
Name
n a n
MIN_SP_WRR_Q7_P3
Description
T e k r B a 0: Round-Robin (RR)
ed i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
15
f i d e
MIN_RATE_EN_Q7_P3
a P i 1: Strict Priority (SP)

C o n n a n 0: Queue 7 min. shaper rate limit control is disabled, the shaper will
k a
e B
d i a T F o r or TB_T period for token bucket

Me
value range: 0..14
f o r
se
stepping
e l e a
R
Bit 31 30 29
t i a l
28 27 26
7/Port 3
25 24 23 22 21 20 19 18 17 16
Name
MAX_S
P_WFQ
i d e n P i MAX_WEIGHT_Q7_P3
f
_Q7_P
Type
3
RW
C o n a n a RW
Reset
Bit
e
0
15
k 14
B a n
13 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
d
Name
i a T
MAX_R
ATE_E
N_Q7_
F o r MAX_RATE_CTRL_EXP_TB_T_Q
7_P3
Me
P3
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
a s
ele
i a l R Port 3 Queue 7 max. shaper rate limit control is enabled

t
11:8
d e n i
i P
f
C o n a n a When MIN_MAX_TB_EN = 0, exponent part of Port 3 Queue 7 max.

e k B a n When MIN_MAX_TB_EN = 1, support TB_T period for rate measurement,

value range: 0..14
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
7:0
f i d e a P i
C o n n a n
T e k r B a stepping
d i a F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
f
0
1
o r 0
0
se
EG_RA EGC_R
EGC_T
a
e
l
P3
P3 3
Type
Reset
RW
0
RW
0
RW
l0
R e 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
n t i a
e
31:16
i d
n f a P i When EGC_TB_EN = 1, total 17 bits EGC_RATE_CIR include

C o n a n up to 2.5Gbps
k a
15
i a T e o r B
EG_RATE_LIMIT_EN_P3
Me d
14
F
EGC_TB_EN_P3
1: Enable
When this bit is disabled, the Egress rate control acts like a leaky bucket
principle.
o r
ef
s
a
ele
i a l R value range: 0..5

0: 1Kbps
t
1: 10Kbps
n
2: 100Kbps
f i d e a P i
3: 1Mbps
4: 10Mbps
n
5: 100Mbps
C o n a n When EGC_TB_EN = 1, support EGC_TB_T period for rate measurement,

value range: 0..14
T e k r B a 0: 1/128ms
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 1: 1/64ms
2: 1/32ms
C o n n a n 3: 1/16ms
4: 1/8ms
k a
5: 1/4ms
e B
6: 1/2ms
d i a T F o r
7: 1ms
8: 2ms
9: 4ms
Me
10: 8ms
11: 16ms
12: 32ms
13: 64ms
14: 128ms
f o r
se
value range: 1..255
e l e a
R
l
and
n t i a Token Bucket = Max ( EGC_RATE_CIR*EGC_TB_T, EGC_TB_CBS*512 )
00001350
f i d e
MMSCR2_Q0P3
a P i Max-Min Scheduler Control Register 2 of Queue 00000000
Bit 31
C o n
30
n
29
a n 28 27 26
0/Port 3
25 24 23 22 21 20 19 18 17 16
Name
T e k r B a MIN_R
ATE_CI
a o
R_Q0_
d i F
P3
Me
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele
2.5Gbps
i a l R
00001354
e n
MMSCR3_Q0P3
t i
0/Port 3
00000000
Bit 31
n f
30
i d 29
n a P 28 27 26 25 24 23 22 21 20 19 18 17 16
o
MAX_R
Name
k C a n a ATE_CI
R_Q0_
e B
P3
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Type RW
Reset
Bit 15 14
n f i d13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
C o n a n MAX_RATE_CIR_Q0_P3
RW
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) Name
F o Description
Me
2.5Gbps

1/Port 3
f r
00000000
o
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a
MIN_R
Name
R e l e ATE_CI
R_Q1_
P3
Type
Reset
t i a l RW
0
Bit
Name
15 14
i d e
13
n 12
P i
11 10 9 8
MIN_RATE_CIR_Q1_P3
7 6 5 4 3 2 1 0
Type
Reset 0
o0
n f 0
a n a 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
e k
16:0
d i a T F o r
MIN_RATE_CIR_Q1_P3 Total 17 bits MIN_RATE_CIR, support 32Kbps stepping CIR cover up to
2.5Gbps

1/Port 3
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ef o MAX_R
ATE_CI
s
R_Q1_
Type
ele a P3
RW
R
Reset 0
Bit
Name
15 14 13
t i a l12 11 10 9 8
MAX_RATE_CIR_Q1_P3
7 6 5 4 3 2 1 0
Type
Reset 0 0
i d e n
0
P i
0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
16:0
e k C B a n
MAX_RATE_CIR_Q1_P3 Total 17 bits MAX_RATE_CIR, support 32Kbps stepping CIR cover up to
2.5Gbps
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001360
C o n
MMSCR2_Q2P3
k a
2/Port 3
Bit
i a T e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
d F
ATE_CI
Name
Me
R_Q2_
P3
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
MIN_RATE_CIR_Q2_P3
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
16:0 MIN_RATE_CIR_Q2_P3
i a l R Total 17 bits MIN_RATE_CIR, support 32Kbps stepping CIR cover up to

2.5Gbps
e n t i
00001364
n f i d
MMSCR3_Q2P3
n a P Max-Min Scheduler Control Register 3 of Queue

2/Port 3
00000000
Bit 31
k C o30
a
29
n a 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
e B
ATE_CI
Name
T r
R_Q2_
d
Type
i a F o P3
RW
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q2_P3
Description
a s
ef
ele
2.5Gbps
i a l R
00001368 MMSCR2_Q3P3
e n t i
3/Port 3
00000000
Bit 31
n
30
f i d 29
n a P
28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
k C o a n a
ATE_CI
R_Q3_
P3
i a T e o r B
M e d F
Page 265 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Type RW
Reset
Bit 15 14
n f i d13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) Name
F o Description
Me
2.5Gbps

3/Port 3
f r
00000000
o
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a
MAX_R
Name
R e l e ATE_CI
R_Q3_
P3
Type
Reset
t i a l RW
0
Bit
Name
15 14
i d e
13
n 12
P i
11 10 9 8
MAX_RATE_CIR_Q3_P3
7 6 5 4 3 2 1 0
Type
Reset 0
o0
n f 0
a n a 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
e k
16:0
d i a T F o r
2.5Gbps

4/Port 3
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ef o MIN_R
ATE_CI
s
R_Q4_
Type
ele a P3
RW
R
Reset 0
Bit
Name
15 14 13
t i a l12 11 10 9 8
MIN_RATE_CIR_Q4_P3
7 6 5 4 3 2 1 0
Type
Reset 0 0
i d e n
0
P i
0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
16:0
e k C B a n
2.5Gbps
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001374
C o n
MMSCR3_Q4P3
k a
4/Port 3
Bit
i a T e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
d F
ATE_CI
Name
Me
R_Q4_
P3
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
MAX_RATE_CIR_Q4_P3
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
i a l R Total 17 bits MAX_RATE_CIR, support 32Kbps stepping CIR cover up to

2.5Gbps
e n t i
00001378
n f i d
MMSCR2_Q5P3

5/Port 3
00000000
Bit 31
k C o30
a
29
n a 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
e B
ATE_CI
Name
T r
R_Q5_
d
Type
i a F o P3
RW
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
16:0
Name
MIN_RATE_CIR_Q5_P3
Description
a s
ef
ele
2.5Gbps
i a l R
e n t i
5/Port 3
00000000
Bit 31
n
30
f i d 29
n a P
28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
k C o a n a
ATE_CI
R_Q5_
P3
i a T e o r B
M e d F
Page 267 of 830
f o r
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l R e Scheduler
Confidential A
n t i a
e
Type RW
Reset
Bit 15 14
n f i d13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) Name
F o Description
Me
2.5Gbps

6/Port 3
f r
00000000
o
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a
MIN_R
Name
R e l e ATE_CI
R_Q6_
P3
Type
Reset
t i a l RW
0
Bit
Name
15 14
i d e
13
n 12
P i
11 10 9 8
MIN_RATE_CIR_Q6_P3
7 6 5 4 3 2 1 0
Type
Reset 0
o0
n f 0
a n a 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
e k
16:0
d i a T F o r
2.5Gbps

6/Port 3
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ef o MAX_R
ATE_CI
s
R_Q6_
Type
ele a P3
RW
R
Reset 0
Bit
Name
15 14 13
t i a l12 11 10 9 8
MAX_RATE_CIR_Q6_P3
7 6 5 4 3 2 1 0
Type
Reset 0 0
i d e n
0
P i
0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
16:0
e k C B a n
2.5Gbps
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001388
C o n
MMSCR2_Q7P3
k a
7/Port 3
Bit
i a T e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
d F
ATE_CI
Name
Me
R_Q7_
P3
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
MIN_RATE_CIR_Q7_P3
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description

2.5Gbps
e n t i
0000138C
n f i d
MMSCR3_Q7P3

7/Port 3
00000000
Bit 31
k C o30
a
29
n a 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
e B
ATE_CI
Name
T r
R_Q7_
d
Type
i a F o P3
RW
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q7_P3
Description
a s
ef
ele
2.5Gbps
i a l R
00001390
Bit 31
MMSCR_P3
30
e n
29
t 28
i
27 26
25 24 23 22 21 20 19 18
00000001
17 16
Name
Type
n f i d n a P
Reset
Bit
k
15
C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1 0
i a T e o r B
M e d F
Page 269 of 830
f o r
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l R e Scheduler
Confidential A
n t i a MIN_
Name
f i d e a P i MAX_T
B_EN_
Type
C o n n a n
P3
RW
k a
Reset 1
i a
Bit(s)
T e
Name
o r B Description
Me d0
F
MIN_MAX_TB_EN_P3 When this bit is disabled, the rate limit acts like a leaky bucket principle.
f o r
se
a
0/Port 4
Bit
MIN_S
31 30 29 28
R e l e 27 26 25 24 23 22 21 20 19 18 17 16
l
P_WRR
Name
a
_Q0_P
Type
4
RW
e n t i
Reset
Bit
0
15
n
14
f i d 13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
ATE_E
C o n a n MIN_RATE_CTRL_EXP_TB_T_Q
N_Q0_
P4
T e k r B a 0_P4
a
Type RW RW RW
d i
Reset 0
F o 0 0 0 0 0 0 0 0 0 0 0 0
Me Bit(s)
31
Name
MIN_SP_WRR_Q0_P4
Description
0: Round-Robin (RR)
r
ef o
s
ele a
i a l R When MIN_MAX_TB_EN = 0, exponent part of Port 4 Queue 0 min.
e n t i
value range: 0..14
d
o n f i n a P or TB_CBS stepping for token bucket

a
e k C B a n When MIN_MAX_TB_EN = 1, support max. bucket size TB_CBS 512 Bytes

stepping
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001404
C o n
MMSCR1_Q0P4
k a
0/Port 4
Bit
i a T
MAX_S
e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d F
P_WFQ
Me
_Q0_P
4
Type RW RW
Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MAX_R
f o r
se
N_Q0_ 0_P4
P4
Type
Reset
RW
0
e l e a
0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
i a l R Description
31 MAX_SP_WFQ_Q0_P4
e n t i
27:24
n f i d
MAX_WEIGHT_Q0_P4
n a P
15
C o n
MAX_RATE_EN_Q0_P4
k a a
i a T e o r B always let the pkt pass (infinite rate)

Me d
11:8
F
value range: 0..14
r
ef o
s
a
ele
stepping
i a l R
t
Bit 31 30
i d e n
29
P i
28 27 26
1/Port 4
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
o n f a n a
C
_Q1_P
4
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Type RW
Reset
Bit
0
15
n
14
f i d 13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1 0
MIN_R
ATE_E
C o n a n MIN_RATE_CTRL_EXP_TB_T_Q
a
Name
k
N_Q1_ 1_P4
Type
i a
P4
T e
RW
o r B RW RW
Me d
Reset
Bit(s)
31
0
Name
F
MIN_SP_WRR_Q1_P4
0
Description
0 0 0 0

0 0 0 0 0 0 0
0: Round-Robin (RR)
f o r
se
e l e a
R
l
n t i a shaper rate limit control, value range: 0..5

e
value range: 0..14
7:0
n f d a P i
i or TB_CBS stepping for token bucket
n
k C o a n a rate limit control, value range: 1..255

e B
stepping
d i a T F o r
Me
1/Port 4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_S
r
P_WFQ
o
_Q1_P
ef
4
s
Type RW RW
Reset
Bit
0
15 14 13 12
0
11
0
10
0
9
0
8 7 6 5
ele
4
a 3 2 1 0
R
MAX_R
Name
ATE_E
N_Q1_
P4
t i a l MAX_RATE_CTRL_EXP_TB_T_Q
1_P4
Type
Reset
RW
0
i d e n P i 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
o n f a n a
C n
31
T e k r B a
MAX_SP_WFQ_Q1_P4 Port 4 Queue 1 max. traffic arbitration scheme
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: Weighted Fair Queuing (WFQ)

27:24
C o n
MAX_WEIGHT_Q1_P4
n a n Port 4 Queue 1 weighted value for max. WFQ weighted value is

k a
e B
d i
11:8
a T F o r
Me
value range: 0..14
f o r
se
e l e a
stepping
i a l R
00001410 MMSCR0_Q2P4
e n t i
2/Port 4
00000000
Bit
MIN_S
31 30
n f i d 29
n a P
28 27 26 25 24 23 22 21 20 19 18 17 16
Name
P_WRR
_Q2_P
4
k C o a n a
Type
i
Reset
a T e
RW
0
o r B
Me d
Bit
Name
MIN_R
ATE_E
N_Q2_
15
F 14 13 12 11 10 9
2_P4
8 7 6 5 4 3
2 1 0
P4
Type
r
RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele
0: Round-Robin (RR)

t
i d e n P i
f
C o n a n a or TB_T period for token bucket

e k B a n shaper rate limit control, value range: 0..5
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description

value range: 0..14
7:0
o n n
k a
e B
d i a T F o r
stepping

2/Port 4
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_S
P_WFQ
f o
se
_Q2_P
a
4
Type
Reset
RW
0
R e l e 0 0
RW
0 0
Bit
MAX_R
15 14 13
t i a l
12 11 10 9 8 7 6 5 4 3 2 1 0
n
e
N_Q2_ 2_P4
Type
P4
RW
n f i d a P i RW RW
Reset 0
C o n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
T e k
Name
r B a Description
a
Me
r
ef o
s
ele a
7:0

i
t
i d e n P i
f
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
00001418
n
MMSCR0_Q3P4
Bit 31 30
f i d e29
a P i
28 27 26
3/Port 4
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
C o n n a n
k a
_Q3_P
Type
i a
4
T eRW
o r B
Me d
Reset
Bit
Name
MIN_R
ATE_E
N_Q3_
0
15
F 14 13 12 11 10 9
3_P4
8 7 6 5 4 3
2 1 0
P4
Type
Reset
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0
f0
o r 0
Bit(s) Name
e a
Description
l se
e
R
0: Round-Robin (RR)

n
f i d e a P i
n


value range: 0..14
i
7:0
d a F o
Me
stepping
o r
3/Port 4
a s ef
00000000
ele
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MAX_S
l
P_WFQ
i a
_Q3_P
Type
4
RW
e n t i
RW
Reset
Bit
0
15
n f
14
i d 13
n a P 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
C o
MAX_R
ATE_E
k a n a
3_P4
i a T e o r B
M e d F
Page 275 of 830
f o r
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l R e Scheduler
Confidential A
N_Q3_
n t i a
Type
P4
RW
f i d e a P i RW RW
Reset 0
C o n n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
T e k
Name
r B a
MAX_SP_WFQ_Q3_P4
Description

Me
f o r
se
a
R e e
l
value range: 0..14
7:0
t i a l
n
f i d e a P i
n
stepping
C o n a n
00001420
T e k B a
MMSCR0_Q4P4
r
a o
4/Port 4
d
Bit
i 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_S
P_WRR
Name
_Q4_P
4
Type RW
Reset 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
MIN_R
a
Name
ele
N_Q4_ 4_P4
P4
Type
Reset
RW
0
i a l R 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
e n t i
Description
31
f i d
MIN_SP_WRR_Q4_P4

0: Round-Robin (RR)
15
k C o n a
MIN_RATE_EN_Q4_P4
a
i a T e o r B
Med F
Page 276 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
11:8
C o n a n
n
a
T e k r B

value range: 0..14
Me
stepping
f o r
00001424 MMSCR1_Q4P4

se 00000000
e
4/Port 4
Bit
MAX_S
31 30 29
i a
28
l R 27 26 25 24 23 22 21 20 19 18 17 16
t
P_WFQ
n
_Q4_P
Type
4
RW
f i d e a P i RW
Reset
Bit
0
15
C o n
14 13
n a n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
k a
MAX_R
e B
T
d
Type
i
N_Q4_
aP4
RW
F o r 4_P4
RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
s
a
ele

t
i d e n P i
f

value range: 0..14
7:0
e k B n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


stepping
T e k r B a
d i a
00001428
Me
5/Port 4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_S
P_WRR
Name
_Q5_P
r
4
Type RW
f o
se
Reset 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l e
MIN_R
e
R
N_Q5_ 5_P4
Type
P4
RW
t i a l RW RW
Reset 0
i d e n P i
0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
o n f
MIN_SP_WRR_Q5_P4
a n a Description
e k C B a n
0: Round-Robin (RR)
T
Me
r
7:0
value range: 0..14
ef o
s
ele a
i a l R stepping
e n t i
d
Bit 31
o n f
30
i n
29
a P 28 27 26
5/Port 4
25 24 23 22 21 20 19 18 17 16
Name
k C
MAX_S
P_WFQ
i a T e o r B
M e d F
Page 278 of 830
f o r
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l R e Scheduler
Confidential A
_Q5_P
n t i a
Type
4
RW
f i d e a P i RW
Reset
Bit
0
15
C o n
14
n a
13
n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
MAX_R
ATE_E
a o
N_Q5_ 5_P4
d i P4
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
f o
se
e l e a

11:8
e n t
i
d

7:0
k a
e B
T r

Me
stepping

6/Port 4
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
MIN_S
a
P_WRR
Name
ele
_Q6_P
4
Type
Reset
RW
0
i a l R
Bit
MIN_R
15 14
e n t
13
i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q6_
P4
n f i d n a P
6_P4
Type
Reset
k C
RW
0 o a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
M e d F
Page 279 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
Bit(s) Name
n
15
T e k r B a
a o
d i F
Me
r
value range: 0..14
f o
se
a
R e l e
stepping
t i a l
00001434 MMSCR1_Q6P4
i d e n P i
6/Port 4
00000000
Bit
MAX_S
31
o
30
n f 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
C
P_WFQ
Name
_Q6_P
4
Type
i
Reset
d a T RW
0
F o r 0 0
RW
0 0
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_R
N_Q6_ 6_P4
P4
r
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele

15
e n
MAX_RATE_EN_Q6_P4
t i
n f i d n a P
o
11:8
k C a n a
i a T e o r B
M e d F
Page 280 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


value range: 0..14
k a
e B
d i a T F o r
Me
stepping
Bit 31 30 29 28 27 26
7/Port 4
25 24 23 22 21 20 19 18
f
17
o r 16
se
MIN_S
Name
P_WRR
_Q7_P
4
e l e a
Type
Reset
RW
0
i a l R
Bit
MIN_R
15 14 13
e n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q7_
n f i d n a P
7_P4
o
P4
Type
Reset
RW
0
k C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
F
Me d
31
15
MIN_SP_WRR_Q7_P4
MIN_RATE_EN_Q7_P4
0: Round-Robin (RR)
r
ef o
s
ele a
7:0

i
t
i d e n P i
f
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit 31 30
f i d e
29
a P
28
i 27 26
7/Port 4
25 24 23 22 21 20 19 18 17 16
Name
MAX_S
P_WFQ
k a
_Q7_P
Type
i a
4
T e
RW
o r B RW
Me d
Reset
Bit
Name
MAX_R
ATE_E
N_Q7_
0
15
F 14 13 12
0
11
0
10
0
9
7_P4
0
8 7 6 5 4 3
2 1 0
P4
Type
Reset
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0
f0
o r 0
Bit(s) Name
e a
Description
l se
e
R

n
15
f i d e
MAX_RATE_EN_Q7_P4
a P i
n
11:8
C o n a n

Me
value range: 0..14
stepping
o r
a s ef
le
Bit
Name
31 30 29
l R e28 27 26 25 24 23
22 21 20 19 18 17 16
Type
Reset 0 0
n t i
0
a 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit
EG_RA
15
f
EGC_T
14
i d e 13
a P i
12
EGC_R
11 10 9 8 7 6 5 4 3 2 1 0
n
n
o a
P4
Type
e
P4
k CRW
B
RW
a n
4
RW RW RW
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31:16
k C o a n a
EGC_RATE_CIR_15_0_P4 When EGC_TB_EN = 1, total 17 bits EGC_RATE_CIR include
e B
up to 2.5Gbps
T r
d i a F o
Me
15 EG_RATE_LIMIT_EN_P4 Port 4 Egress rate limit control is enabled
1: Enable
14 EGC_TB_EN_P4 When this bit is disabled, the Egress rate control acts like a leaky bucket
principle.
f o r
se
12 EGC_RATE_CIR_16_P4
e l e a
R
t i a l TB_T period for token bucket

value range: 0..5
i d e n P i
0: 1Kbps
1: 10Kbps
o n f a n a
2: 100Kbps
3: 1Mbps
C
4: 10Mbps
e k B a n 5: 100Mbps
d i a T F o r value range: 0..14

0: 1/128ms
1: 1/64ms
Me
2: 1/32ms
3: 1/16ms
4: 1/8ms
5: 1/4ms
6: 1/2ms
7: 1ms
o r
ef
8: 2ms
9: 4ms
10: 8ms
a s
ele
11: 16ms
12: 32ms
R
13: 64ms
l
14: 128ms
7:0
_P4
n t i a
EG_RATE_LIMIT_MAN_P4_EGC_TB_CBS Depend on EGC_TB_EN, it can be mantissa part for leaky bucket or
TB_CBS stepping for token bucket
e
n f i d a P i value range: 1..255

n
k C o a n a When EGC_TB_EN = 1, support max. bucket size CBS 512 Bytes stepping,
and
e B
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001450
C o n
MMSCR2_Q0P4
k a
0/Port 4
Bit
i a T e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
d F
ATE_CI
Name
Me
R_Q0_
P4
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
MIN_RATE_CIR_Q0_P4
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description

2.5Gbps
e n t i
00001454
n f i d
MMSCR3_Q0P4

0/Port 4
00000000
Bit 31
k C o30
a
29
n a 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
e B
ATE_CI
Name
T r
R_Q0_
d
Type
i a F o P4
RW
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q0_P4
Description
a s
ef
ele
2.5Gbps
i a l R
00001458 MMSCR2_Q1P4
e n t i
1/Port 4
00000000
Bit 31
n
30
f i d 29
n a P
28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
k C o a n a
ATE_CI
R_Q1_
P4
i a T e o r B
M e d F
Page 284 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Type RW
Reset
Bit 15 14
n f i d13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) Name
F o Description
Me
2.5Gbps

1/Port 4
f r
00000000
o
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a
MAX_R
Name
R e l e ATE_CI
R_Q1_
P4
Type
Reset
t i a l RW
0
Bit
Name
15 14
i d e
13
n 12
P i
11 10 9 8
MAX_RATE_CIR_Q1_P4
7 6 5 4 3 2 1 0
Type
Reset 0
o0
n f 0
a n a 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
e k
16:0
d i a T F o r
2.5Gbps

2/Port 4
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ef o MIN_R
ATE_CI
s
R_Q2_
Type
ele a P4
RW
R
Reset 0
Bit
Name
15 14 13
t i a l12 11 10 9 8
MIN_RATE_CIR_Q2_P4
7 6 5 4 3 2 1 0
Type
Reset 0 0
i d e n
0
P i
0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
16:0
e k C B a n
2.5Gbps
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001464
C o n
MMSCR3_Q2P4
k a
2/Port 4
Bit
i a T e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
d F
ATE_CI
Name
Me
R_Q2_
P4
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
MAX_RATE_CIR_Q2_P4
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description

2.5Gbps
e n t i
00001468
n f i d
MMSCR2_Q3P4

3/Port 4
00000000
Bit 31
k C o30
a
29
n a 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
e B
ATE_CI
Name
T r
R_Q3_
d
Type
i a F o P4
RW
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
16:0
Name
MIN_RATE_CIR_Q3_P4
Description
a s
ef
ele
2.5Gbps
i a l R
e n t i
3/Port 4
00000000
Bit 31
n
30
f i d 29
n a P
28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
k C o a n a
ATE_CI
R_Q3_
P4
i a T e o r B
M e d F
Page 286 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Type RW
Reset
Bit 15 14
n f i d13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) Name
F o Description
Me
2.5Gbps

4/Port 4
f r
00000000
o
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a
MIN_R
Name
R e l e ATE_CI
R_Q4_
P4
Type
Reset
t i a l RW
0
Bit
Name
15 14
i d e
13
n 12
P i
11 10 9 8
MIN_RATE_CIR_Q4_P4
7 6 5 4 3 2 1 0
Type
Reset 0
o0
n f 0
a n a 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
e k
16:0
d i a T F o r
2.5Gbps

4/Port 4
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ef o MAX_R
ATE_CI
s
R_Q4_
Type
ele a P4
RW
R
Reset 0
Bit
Name
15 14 13
t i a l12 11 10 9 8
MAX_RATE_CIR_Q4_P4
7 6 5 4 3 2 1 0
Type
Reset 0 0
i d e n
0
P i
0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
16:0
e k C B a n
2.5Gbps
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001478
C o n
MMSCR2_Q5P4
k a
5/Port 4
Bit
i a T e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
d F
ATE_CI
Name
Me
R_Q5_
P4
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
MIN_RATE_CIR_Q5_P4
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description

2.5Gbps
e n t i
0000147C
n f i d
MMSCR3_Q5P4

5/Port 4
00000000
Bit 31
k C o30
a
29
n a 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
e B
ATE_CI
Name
T r
R_Q5_
d
Type
i a F o P4
RW
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q5_P4
Description
a s
ef
ele
2.5Gbps
i a l R
00001480 MMSCR2_Q6P4
e n t i
6/Port 4
00000000
Bit 31
n
30
f i d 29
n a P
28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
k C o a n a
ATE_CI
R_Q6_
P4
i a T e o r B
M e d F
Page 288 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Type RW
Reset
Bit 15 14
n f i d13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) Name
F o Description
Me
2.5Gbps

6/Port 4
f r
00000000
o
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a
MAX_R
Name
R e l e ATE_CI
R_Q6_
P4
Type
Reset
t i a l RW
0
Bit
Name
15 14
i d e
13
n 12
P i
11 10 9 8
MAX_RATE_CIR_Q6_P4
7 6 5 4 3 2 1 0
Type
Reset 0
o0
n f 0
a n a 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s)
e k
16:0
d i a T F o r
2.5Gbps

7/Port 4
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
ef o MIN_R
ATE_CI
s
R_Q7_
Type
ele a P4
RW
R
Reset 0
Bit
Name
15 14 13
t i a l12 11 10 9 8
MIN_RATE_CIR_Q7_P4
7 6 5 4 3 2 1 0
Type
Reset 0 0
i d e n
0
P i
0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit(s) Name
16:0
e k C B a n
2.5Gbps
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
0000148C
C o n
MMSCR3_Q7P4
k a
7/Port 4
Bit
i a T e
31
o
30
r B 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
d F
ATE_CI
Name
Me
R_Q7_
P4
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
MAX_RATE_CIR_Q7_P4
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description

2.5Gbps
e n t i
00001490
Bit 31
n
30
f i d
MMSCR_P4
29
n a P
28 27 26
25 24 23 22 21 20 19 18
00000001
17 16
Name
Type
k C o a n a
Reset
Bit
i a T e
15
o r
14
B 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me d
Name
Type
F MIN_
MAX_T
B_EN_
P4
RW
Reset 1
o r
ef
0 MIN_MAX_TB_EN_P4
s
a
ele
R
t i a l 1: Token bucket mode Enable
00001500
i d e n
MMSCR0_Q0P5
P i Max-Min Scheduler Control Register 0 of Queue 00000000
Bit 31
o n f
30
a
29
n a 28 27 26
0/Port 5
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
e
P_WRR
k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
_Q0_P
n t i a
Type
5
RW
f i d e a P i
Reset
Bit
0
15
C o n
14
n a
13
n 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
MIN_R
ATE_E
a o
N_Q0_ 0_P5
d i P5
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
0: Round-Robin (RR)
f o
se
e l a
e
11:8
i a l
e n t i
d
7:0

o
e B
T r
d i a F o stepping
Me 00001504
Bit 31
MMSCR1_Q0P5
30 29 28 27 26
0/Port 5
25 24 23 22 21 20 19 18
00000000
17 16
MAX_S
o r
ef
P_WFQ
s
_Q0_P
a
5
ele
Type RW RW
Reset 0 0 0 0 0
Bit
MAX_R
15 14 13
i a l R12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q0_
e n t i
0_P5
d
P5
Type
Reset
RW
o n f i n a P RW RW
a
0 0 0 0 0 0 0 0 0 0 0 0 0
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
31
f i d
MAX_SP_WFQ_Q0_P5
27:24
C o n
MAX_WEIGHT_Q0_P5

k a
15
i a T e o r B
Me d
11:8
F
7:0
value range: 0..14
f o r
se
e l e a
R
stepping
t i a l
00001508
i d e
MMSCR0_Q1P5
n P i
1/Port 5
00000000
Bit
MIN_S
31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
P_WRR
_Q1_P
e k C B a n
T
5
Type
d i
Reset
a RW
0
F o r
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_R
N_Q1_ 1_P5
P5
Type RW RW RW
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
a s
ele
t
i d e n P i
f
11:8
C o n a n a

d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description

value range: 0..14
7:0
o n n
k a
e B
d i a T F o r
stepping

1/Port 5
00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_S
P_WFQ
f o
se
_Q1_P
a
5
Type
Reset
RW
0
R e l e 0 0
RW
0 0
Bit
MAX_R
15 14 13
t i a l
12 11 10 9 8 7 6 5 4 3 2 1 0
n
e
N_Q1_ 1_P5
Type
P5
RW
n f i d a P i RW RW
Reset 0
C o n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
T e k
Name
r B a Description
a
Me
r
ef o
s
ele a
7:0

i
t
i d e n P i
f
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
00001510
n
MMSCR0_Q2P5
Bit 31 30
f i d e29
a P i
28 27 26
2/Port 5
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
C o n n a n
k a
_Q2_P
Type
i a
5
T eRW
o r B
Me d
Reset
Bit
Name
MIN_R
ATE_E
N_Q2_
0
15
F 14 13 12 11 10 9
2_P5
8 7 6 5 4 3
2 1 0
P5
Type
Reset
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0
f0
o r 0
Bit(s) Name
e a
Description
l se
e
R
0: Round-Robin (RR)

n
f i d e a P i
n


value range: 0..14
i
7:0
d a F o
Me
stepping
o r
2/Port 5
a s ef
00000000
ele
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MAX_S
l
P_WFQ
i a
_Q2_P
Type
5
RW
e n t i
RW
Reset
Bit
0
15
n f
14
i d 13
n a P 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
C o
MAX_R
ATE_E
k a n a
2_P5
i a T e o r B
M e d F
Page 294 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
N_Q2_
n t i a
Type
P5
RW
f i d e a P i RW RW
Reset 0
C o n n a n 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
T e k
Name
r B a
MAX_SP_WFQ_Q2_P5
Description

Me
f o r
se
a
R e e
l
value range: 0..14
7:0
t i a l
n
f i d e a P i
n
stepping
C o n a n
00001518
T e k B a
MMSCR0_Q3P5
r
a o
3/Port 5
d
Bit
i 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_S
P_WRR
Name
_Q3_P
5
Type RW
Reset 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
MIN_R
a
Name
ele
N_Q3_ 3_P5
P5
Type
Reset
RW
0
i a l R 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
e n t i
Description
31
f i d
MIN_SP_WRR_Q3_P5

0: Round-Robin (RR)
15
k C o n a
MIN_RATE_EN_Q3_P5
a
i a T e o r B
Med F
Page 295 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
11:8
C o n a n
n
a
T e k r B

value range: 0..14
Me
stepping
f o r

se 00000000
e
3/Port 5
Bit
MAX_S
31 30 29
i a
28
l R 27 26 25 24 23 22 21 20 19 18 17 16
t
P_WFQ
n
_Q3_P
Type
5
RW
f i d e a P i RW
Reset
Bit
0
15
C o n
14 13
n a n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
k a
MAX_R
e B
T
d
Type
i
N_Q3_
aP5
RW
F o r 3_P5
RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
s
a
ele

t
i d e n P i
f

value range: 0..14
7:0
e k B n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


stepping
T e k r B a
d i a
00001520
Me
4/Port 5
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_S
P_WRR
Name
_Q4_P
r
5
Type RW
f o
se
Reset 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l e
MIN_R
e
R
N_Q4_ 4_P5
Type
P5
RW
t i a l RW RW
Reset 0
i d e n P i
0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
o n f
MIN_SP_WRR_Q4_P5
a n a Description
e k C B a n
0: Round-Robin (RR)
T
Me
r
7:0
value range: 0..14
ef o
s
ele a
i a l R stepping
e n t i
d
Bit 31
o n f
30
i n
29
a P 28 27 26
4/Port 5
25 24 23 22 21 20 19 18 17 16
Name
k C
MAX_S
P_WFQ
i a T e o r B
M e d F
Page 297 of 830
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l R e Scheduler
Confidential A
_Q4_P
n t i a
Type
5
RW
f i d e a P i RW
Reset
Bit
0
15
C o n
14
n a
13
n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
MAX_R
ATE_E
a o
N_Q4_ 4_P5
d i P5
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
f o
se
e l e a

11:8
e n t
i
d

7:0
k a
e B
T r

Me
stepping

5/Port 5
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
MIN_S
a
P_WRR
Name
ele
_Q5_P
5
Type
Reset
RW
0
i a l R
Bit
MIN_R
15 14
e n t
13
i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q5_
P5
n f i d n a P
5_P5
Type
Reset
k C
RW
0 o a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
M e d F
Page 298 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
Bit(s) Name
n
15
T e k r B a
a o
d i F
Me
r
value range: 0..14
f o
se
a
R e l e
stepping
t i a l
i d e n P i
5/Port 5
00000000
Bit
MAX_S
31
o
30
n f 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
C
P_WFQ
Name
_Q5_P
5
Type
i
Reset
d a T RW
0
F o r 0 0
RW
0 0
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_R
N_Q5_ 5_P5
P5
r
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele

15
e n
MAX_RATE_EN_Q5_P5
t i
n f i d n a P
o
11:8
k C a n a
i a T e o r B
M e d F
Page 299 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


value range: 0..14
k a
e B
d i a T F o r
Me
stepping
Bit 31 30 29 28 27 26
6/Port 5
25 24 23 22 21 20 19 18
f
17
o r 16
se
MIN_S
Name
P_WRR
_Q6_P
5
e l e a
Type
Reset
RW
0
i a l R
Bit
MIN_R
15 14 13
e n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q6_
n f i d n a P
6_P5
o
P5
Type
Reset
RW
0
k C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
F
Me d
31
15
MIN_SP_WRR_Q6_P5
MIN_RATE_EN_Q6_P5
0: Round-Robin (RR)
r
ef o
s
ele a
7:0

i
t
i d e n P i
f
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
00001534 MMSCR1_Q6P5
Bit 31 30
f i d e
29
a P
28
i 27 26
6/Port 5
25 24 23 22 21 20 19 18 17 16
Name
MAX_S
P_WFQ
k a
_Q6_P
Type
i a
5
T e
RW
o r B RW
Me d
Reset
Bit
Name
MAX_R
ATE_E
N_Q6_
0
15
F 14 13 12
0
11
0
10
0
9
6_P5
0
8 7 6 5 4 3
2 1 0
P5
Type
Reset
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0
f0
o r 0
Bit(s) Name
e a
Description
l se
e
R

n
15
f i d e
MAX_RATE_EN_Q6_P5
a P i
n
11:8
C o n a n

Me
value range: 0..14
stepping
o r
a s ef
le
Bit 31 30 29
l R e28 27 26
7/Port 5
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
_Q7_P
n t i a
Type
5
RW
f i d e a P i
Reset
Bit
C o
0
15
n 14
n a n13 12 11 10 9 8 7 6 5 4 3 2 1 0
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
MIN_R
n t i a
Name
ATE_E
N_Q7_
7_P5
Type
P5
RW
C o n n a n RW RW
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a
Bit(s)
T e
Name
o r B Description
Me d
31
15
F
MIN_SP_WRR_Q7_P5
MIN_RATE_EN_Q7_P5
0: Round-Robin (RR)
f o r
se
a
e
R e l
value range: 0..14
7:0
t i a l
n
e

stepping
C o n a n
0000153C
T e k B a
MMSCR1_Q7P5
r
7/Port 5
00000000
d
Bit
i a 31
F o30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_S
P_WFQ
_Q7_P
5
Type RW RW
Reset 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
MAX_R
a
ele
N_Q7_ 7_P5
P5
Type
Reset
RW
0
i a l R 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
e n t i
Description
31
f i d
MAX_SP_WFQ_Q7_P5

27:24
k C o n a
MAX_WEIGHT_Q7_P5
a
i a T e o r B
Med F
Page 302 of 830
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l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
15
f i d e
MAX_RATE_EN_Q7_P5

C o n n a n
k a
e B
d i a T F o r
Me
value range: 0..14
stepping
f o r
00001540 ERLCR_P5 Egress Rate Limit Control Register of Port 5
l e a se 00000000
Bit 31 30 29
l R
28 27 26 25 24 23 22 21
e20 19 18 17 16
a
Type
Reset 0 0
e n0
t i 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
Bit
EG_RA
15
n
14
f i d
13
a P i
12
EGC_R
11 10 9 8 7 6 5 4 3 2 1 0
n
EGC_T
o
a
C
n
P5
a
P5 5
Type
T e k
RW
r B
RW RW RW RW
a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e d i
Bit(s)
F
Nameo Description
M 31:16 EGC_RATE_CIR_15_0_P5 When EGC_TB_EN = 1, total 17 bits EGC_RATE_CIR include

up to 2.5Gbps
o r
ef
15 EG_RATE_LIMIT_EN_P5 Port 5 Egress rate limit control is enabled
a s
ele
1: Enable
14 EGC_TB_EN_P5
i a l R When this bit is disabled, the Egress rate control acts like a leaky bucket
principle.
e n t i
12
n f i d
EGC_RATE_CIR_16_P5
n a P
11:8
k C o a n a
EG_RATE_LIMIT_EXP_P5_EGC_TB_T_P5 Depend on EGC_TB_EN, it can be exponent part for leaky bucket or
i a T e o r B
M e d F
Page 303 of 830
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Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When EGC_TB_EN = 0, exponent part of Port 5 Egress rate limit control,

value range: 0..5
C o n n a n 0: 1Kbps
1: 10Kbps
k a
2: 100Kbps
e B
3: 1Mbps
d i a T F o r
4: 10Mbps
5: 100Mbps
Me
value range: 0..14
0: 1/128ms
1: 1/64ms
2: 1/32ms
3: 1/16ms
4: 1/8ms
5: 1/4ms
f o r
se
6: 1/2ms
7: 1ms
e l e a
8: 2ms
9: 4ms
R
10: 8ms
l
11: 16ms
n t i a 12: 32ms
13: 64ms
e
14: 128ms
7:0
_P5
n f d a P i
i TB_CBS stepping for token bucket
n
k C o a n a value range: 1..255

e B
T r
d i a F o and

0/Port 5
00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r16
ef
MIN_R
s
ATE_CI
Name
a
R_Q0_
ele
P5
Type RW
Reset
Bit 15 14
i
13
a l R 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
e n t i
MIN_RATE_CIR_Q0_P5
RW
Reset 0
n f i0
d n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 304 of 830
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l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MIN_RATE_CIR_Q0_P5

2.5Gbps
C o n n a n
00001554
T e k B a
MMSCR3_Q0P5
r
0/Port 5
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q0_
P5
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q0_P5
t i a l Description
n
2.5Gbps
f i d e a P i
00001558
C o n
MMSCR2_Q1P5

1/Port 5
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
d i a F o ATE_CI
R_Q1_
Me
P5
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
1/Port 5
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MAX_R
ATE_CI
i a T e o r B
M e d F
Page 305 of 830
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l R e Scheduler
Confidential A
n t i a R_Q1_
Type
f i d e a P i P5
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
2/Port 5
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
R
ATE_CI
l
Name
R_Q2_
Type
n t i a P5
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MIN_RATE_CIR_Q2_P5
Description
Me
2.5Gbps

2/Port 5
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MAX_R
ATE_CI
ele
Name
R_Q2_
P5
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MAX_RATE_CIR_Q2_P5
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
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l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MAX_RATE_CIR_Q2_P5

2.5Gbps
C o n n a n
00001568
T e k B a
MMSCR2_Q3P5
r
3/Port 5
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MIN_R
ATE_CI
Name
R_Q3_
P5
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MIN_RATE_CIR_Q3_P5
t i a l Description
n
2.5Gbps
f i d e a P i
0000156C
C o n
MMSCR3_Q3P5

3/Port 5
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
Name
d i a F o ATE_CI
R_Q3_
Me
P5
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
4/Port 5
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MIN_R
ATE_CI
i a T e o r B
M e d F
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Confidential A
n t i a R_Q4_
Type
f i d e a P i P5
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
4/Port 5
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MAX_R
R
ATE_CI
l
Name
R_Q4_
Type
n t i a P5
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MAX_RATE_CIR_Q4_P5
Description
Me
2.5Gbps

5/Port 5
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MIN_R
ATE_CI
ele
Name
R_Q5_
P5
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MIN_RATE_CIR_Q5_P5
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 308 of 830
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l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MIN_RATE_CIR_Q5_P5

2.5Gbps
C o n n a n
0000157C
T e k B a
MMSCR3_Q5P5
r
5/Port 5
00000000
Bit
d i a 31
F o
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q5_
P5
Type RW
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f1
o r 0
0
se
a
Type RW
Reset 0 0 0 0
R e l e0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
MAX_RATE_CIR_Q5_P5
t i a l Description
n
2.5Gbps
f i d e a P i
00001580
C o n
MMSCR2_Q6P5

6/Port 5
00000000
Bit
T e
31
k 30
r B a29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
Name
d i a F o ATE_CI
R_Q6_
Me
P5
Type RW
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0 0 0 0
ef
0
o 0
a s
ele
i a l R 2.5Gbps
e n t i
d
Bit 31
o n
30
f i 29
n a P28 27 26
6/Port 5
25 24 23 22 21 20 19 18 17 16
Name
k C a n a MAX_R
ATE_CI
i a T e o r B
M e d F
Page 309 of 830
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l R e Scheduler
Confidential A
n t i a R_Q6_
Type
f i d e a P i P5
RW
Reset
Bit 15
C o
14
n n
13
a n 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
d i
Reset
a 0
F o0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
2.5Gbps
f o r
se
7/Port 5
Bit 31 30 29 28
e l e a
27 26 25 24 23 22 21 20 19 18 17 16
MIN_R
R
ATE_CI
l
Name
R_Q7_
Type
n t i a P5
RW
Reset
Bit 15 14
f i d e
13
a P
12
i 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
Reset
T e
0
k
0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
16:0
a
Bit(s) Name
F o
MIN_RATE_CIR_Q7_P5
Description
Me
2.5Gbps

7/Port 5
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
a s MAX_R
ATE_CI
ele
Name
R_Q7_
P5
Type
Reset
i a l R RW
0
Bit
Name
15 14
e n t
13
i
12 11 10 9 8
MAX_RATE_CIR_Q7_P5
7 6 5 4 3 2 1 0
Type
Reset 0
n f i
0
d n
0
a P 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
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l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
16:0
f i d e
MAX_RATE_CIR_Q7_P5

2.5Gbps
C o n n a n
00001590
Bit
T e
31
k 30
r B
MMSCR_P5
a29 28 27 26
25 24 23 22 21 20 19 18
00000001
17 16
d
Name
i a F o
Me
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_
r
MAX_T
Name
o
B_EN_
Type
se f P5
RW
Reset
e l e a 1
Bit(s)
0
Name
MIN_MAX_TB_EN_P5
i a l R Description
t
i d e n P i
f
C o n a n a
00001600
e k B a
MMSCR0_Q0P6
Bit
d i a T 31
F o
30
r 29 28 27 26
0/Port 6
25 24 23 22 21 20 19 18 17 16
Me
MIN_S
P_WRR
Name
_Q0_P
6
Type RW
r
Reset 0
Bit
MIN_R
15 14 13 12 11 10 9 8 7 6 5 4 3 2
ef
1
o 0
Name
a s
ele
N_Q0_ 0_P6
P6
R
Type RW RW RW
Reset 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
i d e
MIN_SP_WRR_Q0_P6
n P i
Description
o n f a n a
0: Round-Robin (RR)
15
e k C B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
11:8
C o n a n
n
a
T e k r B

value range: 0..14
Me
stepping
f o r
00001604 MMSCR1_Q0P6

se 00000000
e
0/Port 6
Bit
MAX_S
31 30 29
i a
28
l R 27 26 25 24 23 22 21 20 19 18 17 16
t
P_WFQ
n
_Q0_P
Type
6
RW
f i d e a P i RW
Reset
Bit
0
15
C o n
14 13
n a n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
k a
MAX_R
e B
T
d
Type
i
N_Q0_
aP6
RW
F o r 0_P6
RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
s
a
ele

t
i d e n P i
f

value range: 0..14
7:0
e k B n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


stepping
T e k r B a
d i a
00001608
Me
1/Port 6
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIN_S
P_WRR
Name
_Q1_P
r
6
Type RW
f o
se
Reset 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l e
MIN_R
e
R
N_Q1_ 1_P6
Type
P6
RW
t i a l RW RW
Reset 0
i d e n P i
0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
o n f
MIN_SP_WRR_Q1_P6
a n a Description
e k C B a n
0: Round-Robin (RR)
T
Me
r
7:0
value range: 0..14
ef o
s
ele a
i a l R stepping
e n t i
d
Bit 31
o n f
30
i n
29
a P 28 27 26
1/Port 6
25 24 23 22 21 20 19 18 17 16
Name
k C
MAX_S
P_WFQ
i a T e o r B
M e d F
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Confidential A
_Q1_P
n t i a
Type
6
RW
f i d e a P i RW
Reset
Bit
0
15
C o n
14
n a
13
n 12
0
11
0
10
0
9
0
8 7 6 5 4 3 2 1 0
Name
MAX_R
ATE_E
a o
N_Q1_ 1_P6
d i P6
F
Me
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
r
f o
se
e l e a

11:8
e n t
i
d

7:0
k a
e B
T r

Me
stepping

2/Port 6
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
MIN_S
a
P_WRR
Name
ele
_Q2_P
6
Type
Reset
RW
0
i a l R
Bit
MIN_R
15 14
e n t
13
i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q2_
P6
n f i d n a P
2_P6
Type
Reset
k C
RW
0 o a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
M e d F
Page 314 of 830
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Confidential A
n t i a
Bit(s) Name
n
15
T e k r B a
a o
d i F
Me
r
value range: 0..14
f o
se
a
R e l e
stepping
t i a l
00001614 MMSCR1_Q2P6
i d e n P i
2/Port 6
00000000
Bit
MAX_S
31
o
30
n f 29
a n a
28 27 26 25 24 23 22 21 20 19 18 17 16
C
P_WFQ
Name
_Q2_P
6
Type
i
Reset
d a T RW
0
F o r 0 0
RW
0 0
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_R
N_Q2_ 2_P6
P6
r
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele

15
e n
MAX_RATE_EN_Q2_P6
t i
n f i d n a P
o
11:8
k C a n a
i a T e o r B
M e d F
Page 315 of 830
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Confidential A
Bit(s) Name
n t i a Description


value range: 0..14
k a
e B
d i a T F o r
Me
stepping
Bit 31 30 29 28 27 26
3/Port 6
25 24 23 22 21 20 19 18
f
17
o r 16
se
MIN_S
Name
P_WRR
_Q3_P
6
e l e a
Type
Reset
RW
0
i a l R
Bit
MIN_R
15 14 13
e n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q3_
n f i d n a P
3_P6
o
P6
Type
Reset
RW
0
k C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
F
Me d
31
15
MIN_SP_WRR_Q3_P6
MIN_RATE_EN_Q3_P6
0: Round-Robin (RR)
r
ef o
s
ele a
7:0

i
t
i d e n P i
f
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit 31 30
f i d e
29
a P
28
i 27 26
3/Port 6
25 24 23 22 21 20 19 18 17 16
Name
MAX_S
P_WFQ
k a
_Q3_P
Type
i a
6
T e
RW
o r B RW
Me d
Reset
Bit
Name
MAX_R
ATE_E
N_Q3_
0
15
F 14 13 12
0
11
0
10
0
9
3_P6
0
8 7 6 5 4 3
2 1 0
P6
Type
Reset
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0
f0
o r 0
Bit(s) Name
e a
Description
l se
e
R

n
15
f i d e
MAX_RATE_EN_Q3_P6
a P i
n
11:8
C o n a n

Me
value range: 0..14
stepping
o r
a s ef
le
Bit 31 30 29
l R e28 27 26
4/Port 6
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
_Q4_P
n t i a
Type
6
RW
f i d e a P i
Reset
Bit
C o
0
15
n 14
n a n13 12 11 10 9 8 7 6 5 4 3 2 1 0
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
MIN_R
n t i a
Name
ATE_E
N_Q4_
4_P6
Type
P6
RW
C o n n a n RW RW
k a
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a
Bit(s)
T e
Name
o r B Description
Me d
31
15
F
MIN_SP_WRR_Q4_P6
MIN_RATE_EN_Q4_P6
0: Round-Robin (RR)
f o r
se
a
e
R e l
value range: 0..14
7:0
t i a l
n
e

stepping
C o n a n
00001624
T e k B a
MMSCR1_Q4P6
r
4/Port 6
00000000
d
Bit
i a 31
F o30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAX_S
P_WFQ
_Q4_P
6
Type RW RW
Reset 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
MAX_R
a
ele
N_Q4_ 4_P6
P6
Type
Reset
RW
0
i a l R 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Bit(s) Name
e n t i
Description
31
f i d
MAX_SP_WFQ_Q4_P6

27:24
k C o n a
MAX_WEIGHT_Q4_P6
a
i a T e o r B
Med F
Page 318 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
15
f i d e
MAX_RATE_EN_Q4_P6

C o n n a n
k a
e B
d i a T F o r
Me
value range: 0..14
stepping
f o r
l e a se 00000000
Bit 31 30 29
l R
28 27 26
5/Port 6
25 24 23 22 21 e20 19 18 17 16
MIN_S
P_WRR
n t i a
e
Name
i
_Q5_P
Type
6
RW
n f i d n a P
Reset
Bit
k
0
15
C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a T e
MIN_R
ATE_E
N_Q5_
5_P6
M e d
Type
Reset
P6
RW
0
F 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0

o r
ef
0: Round-Robin (RR)
a s
ele
11:8
a l R
i
t
i d e n P i
f
7:0

C
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


stepping
T e k r B a
d i a
0000162C
Me
5/Port 6
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_S
P_WFQ
_Q5_P
r
6
Type RW RW
f o
se
Reset 0 0 0 0 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
l e
MAX_R
e
R
N_Q5_ 5_P6
Type
P6
RW
t i a l RW RW
Reset 0
i d e n P i
0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
o n f
MAX_SP_WFQ_Q5_P6
a n a Description
e k C B a n
T
d
15
i a F o r
MAX_RATE_EN_Q5_P6
Me
r
ef o
s
value range: 0..14
ele a
t
stepping
i d e n P i
00001630
o n f
MMSCR0_Q6P6

6/Port 6
00000000
Bit
e k
31
C 30
B a n 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
MIN_S
n t i a
Name
P_WRR
_Q6_P
f i d e a P i
Type
6
RW
C o n n a n
k a
Reset 0
Bit
i a T
MIN_R
e
15
o
14
r B 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F
d
Me
N_Q6_ 6_P6
P6
Type RW RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
MIN_SP_WRR_Q6_P6
Description
f o r
se
0: Round-Robin (RR)
e l e a

11:8
e n t
i
d

7:0

k a
e


stepping

6/Port 6
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
MAX_S
a
P_WFQ
ele
_Q6_P
6
Type
Reset
RW
0
i a l R 0 0
RW
0 0
Bit
MAX_R
15 14
e
13
n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
d
Name
N_Q6_
P6
o n f i n a P 6_P6
Type
Reset
RW
k
0
C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
M e d F
Page 321 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
Bit(s) Name
n

27:24
T e k r B a
a o
d i F
Me
r
value range: 0..14
f o
se
a
R e l e
t i a l stepping
i d e n P i
f
Bit 31
C o n
30 29
a n a 28 27 26
7/Port 6
25 24 23 22 21 20 19 18 17 16
Name
MIN_S
P_WRR
e k B a n
d
Type
i
6
T
_Q7_P
a RW
F o r
Me
Reset 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIN_R
r
N_Q7_ 7_P6
Type
P6
RW RW RW
ef o
Reset 0 0 0 0 0 0 0 0 0
a s 0 0 0 0
Bit(s)
31
Name
MIN_SP_WRR_Q7_P6
l R
Description
ele
e
11:8
C o a n
n
k a
i a T e o r B
M e d F
Page 322 of 830
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description


value range: 0..14
k a
e B
d i a T F o r
Me
stepping
Bit 31 30 29 28 27 26
7/Port 6
25 24 23 22 21 20 19 18
f
17
o r 16
se
MAX_S
Name
P_WFQ
_Q7_P
6
Type
Reset
RW
0
i a l R 0 0
RW
0 0
Bit
MAX_R
15 14 13
e n t 12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
ATE_E
N_Q7_
n f i d n a P
7_P6
o
P6
Type
Reset
RW
0
k C a n a 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a T e o r B
F
Me d
31
27:24
MAX_SP_WFQ_Q7_P6
MAX_WEIGHT_Q7_P6
r
ef o
s
ele a
t
value range: 0..14
7:0
i d n
e P i
f

e k B a n stepping
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001640
C o n
ERLCR_P6
n a n Egress Rate Limit Control Register of Port 6 00000000
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
i a T e o r B EGC_RATE_CIR_15_0_P6
RW
Me d
Reset
Bit
Name
EG_RA
TE_LIM
IT_EN_
0
15
F
EGC_T
B_EN_
0
14
0
13
0
12
EGC_R
0
11
0
10
ATE_CI EG_RATE_LIMIT_EXP_P6_EGC_
R_16_P TB_T_P6
0
9
0
8
0
7
0
6
0
5
0
4
0
3
EG_RATE_LIMIT_MAN_P6_EGC_TB_CBS_P6
0
2
0
1
0
0
P6
P6 6
Type
Reset
RW
0
RW
0
RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0
f0
o r 0
Bit(s) Name
l e a
Description
se
e
31:16 EGC_RATE_CIR_15_0_P6 When EGC_TB_EN = 1, total 17 bits EGC_RATE_CIR include
R
t i a l up to 2.5Gbps
n
e
15
f i d
EG_RATE_LIMIT_EN_P6
n a P i * (1/EGC_TB_T) (bps) ]
C o n a n 0: Egress rate limit control disable

1: Enable
14
T e k
EGC_TB_EN_P6
r B a When this bit is disabled, the Egress rate control acts like a leaky bucket
principle.
a
d i F o this approach guarantees some burst level for TCP transaction.
Me
r
value range: 0..5
0: 1Kbps
ef o
s
1: 10Kbps
a
2: 100Kbps
ele
3: 1Mbps
4: 10Mbps
i a l R 5: 100Mbps
t
value range: 0..14
i d e n P i
0: 1/128ms
1: 1/64ms
f
2: 1/32ms
C o n a n a 3: 1/16ms
4: 1/8ms
n
5: 1/4ms
T e k r B a 6: 1/2ms
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 7: 1ms
8: 2ms
C o n n a n 9: 4ms
10: 8ms
k a
11: 16ms
e B
12: 32ms
d i
7:0
a T F o r
13: 64ms
14: 128ms
Me
value range: 1..255
and
f o r
se
e l e a
R
Bit 31 30 29
t i a l
28 27 26
0/Port 6
25 24 23 22 21 20 19 18 17 16
Name
i d e n P i
MIN_R
ATE_CI
f
R_Q0_
Type
C o n a n a P6
RW
Reset
Bit
e
15
k 14
B a n
13 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
d i a T F o r MIN_RATE_CIR_Q0_P6
RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

r
2.5Gbps
ef o
a s 00000000
ele
0/Port 6
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
i a l R MAX_R
ATE_CI
t
Name
R_Q0_
Type
i d e n P i
P6
RW
Reset
Bit 15
o n f
14
a
13
n a 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
e k C B a n MAX_RATE_CIR_Q0_P6
RW
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
16:0
k C o
MAX_RATE_CIR_Q0_P6
a n a
2.5Gbps
i a T e o r B
Me d
00001658
Bit 31 FMMSCR2_Q1P6
30 29 28 27 26
1/Port 6
25 24 23 22 21 20 19 18
00000000
17 16
MIN_R
ATE_CI
Name
R_Q1_
Type
f o r P6
RW
se
Reset 0
Bit
Name
15 14 13 12
e l e a
11 10 9 8
MIN_RATE_CIR_Q1_P6
7 6 5 4 3 2 1 0
R
Type RW
Reset 0 0 0
t i a l
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
i d e
MIN_RATE_CIR_Q1_P6
n P i
Description
o n f a n a
2.5Gbps
0000165C
e k C B a
MMSCR3_Q1P6
d
Bit
i a T 31
F o
30
r 29 28 27 26
1/Port 6
25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q1_
P6
Type RW
Reset
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0
ele
0
a 0 0 0 0
Bit(s) Name
i a l R Description
t
i d e n P i
2.5Gbps
00001660
o n f
MMSCR2_Q2P6
a n a Max-Min Scheduler Control Register 2 of Queue 00000000
e k C B a n 2/Port 6
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
31 30 29
n t i a28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
n f i d a P i MIN_R
ATE_CI
o n
R_Q2_
Type
k C a n a P6
RW
Reset
Bit
i a T e
15
o
14
r B 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Me d
Name
Type
Reset 0 F 0 0 0 0 0 0
MIN_RATE_CIR_Q2_P6
0
RW
0 0 0 0 0 0 0 0

2.5Gbps
f o r
l e a se 00000000
Bit 31 30 29
l R
28 27 26
2/Port 6
25 24 23 22 21
e20 19 18 17 16
n t i a MAX_R
ATE_CI
e
Name
i
R_Q2_
Type
n f i d n a P
P6
RW
Reset
Bit 15
k C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
i a T e o r B
MAX_RATE_CIR_Q2_P6
RW
F
Reset
d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M e Bit(s)
16:0
Name
MAX_RATE_CIR_Q2_P6
Description
2.5Gbps
o r
3/Port 6
a s ef
00000000
ele
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MIN_R
l
ATE_CI
Name
a
R_Q3_
Type
e n t i P6
RW
Reset
Bit 15
n
14
f i d 13
a P i
12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
16:0
k C o
MIN_RATE_CIR_Q3_P6
a n a
2.5Gbps
i a T e o r B
Me d
0000166C
Bit 31 FMMSCR3_Q3P6
30 29 28 27 26
3/Port 6
25 24 23 22 21 20 19 18
00000000
17 16
MAX_R
ATE_CI
Name
R_Q3_
Type
f o r P6
RW
se
Reset 0
Bit
Name
15 14 13 12
e l e a
11 10 9 8
MAX_RATE_CIR_Q3_P6
7 6 5 4 3 2 1 0
R
Type RW
Reset 0 0 0
t i a l
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
i d e
MAX_RATE_CIR_Q3_P6
n P i
Description
o n f a n a
2.5Gbps
00001670
e k C B a
MMSCR2_Q4P6
d
Bit
i a T 31
F o
30
r 29 28 27 26
4/Port 6
25 24 23 22 21 20 19 18 17 16
Me
MIN_R
ATE_CI
Name
R_Q4_
P6
Type RW
Reset
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0
ele
0
a 0 0 0 0
Bit(s) Name
i a l R Description
t
i d e n P i
2.5Gbps
00001674
o n f
MMSCR3_Q4P6
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
31 30 29
n t i a28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
n f i d a P i MAX_R
ATE_CI
o n
R_Q4_
Type
k C a n a P6
RW
Reset
Bit
i a T e
15
o
14
r B 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Me d
Name
Type
Reset 0 F 0 0 0 0 0 0
MAX_RATE_CIR_Q4_P6
0
RW
0 0 0 0 0 0 0 0

2.5Gbps
f o r
l e a se 00000000
Bit 31 30 29
l R
28 27 26
5/Port 6
25 24 23 22 21
e20 19 18 17 16
n t i a MIN_R
ATE_CI
e
Name
i
R_Q5_
Type
n f i d n a P
P6
RW
Reset
Bit 15
k C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
i a T e o r B
MIN_RATE_CIR_Q5_P6
RW
F
Reset
d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M e Bit(s)
16:0
Name
MIN_RATE_CIR_Q5_P6
Description
2.5Gbps
o r
5/Port 6
a s ef
00000000
ele
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MAX_R
l
ATE_CI
Name
a
R_Q5_
Type
e n t i P6
RW
Reset
Bit 15
n
14
f i d 13
a P i
12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
RW
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
16:0
k C o
MAX_RATE_CIR_Q5_P6
a n a
2.5Gbps
i a T e o r B
Me d
00001680
Bit 31 FMMSCR2_Q6P6
30 29 28 27 26
6/Port 6
25 24 23 22 21 20 19 18
00000000
17 16
MIN_R
ATE_CI
Name
R_Q6_
Type
f o r P6
RW
se
Reset 0
Bit
Name
15 14 13 12
e l e a
11 10 9 8
MIN_RATE_CIR_Q6_P6
7 6 5 4 3 2 1 0
R
Type RW
Reset 0 0 0
t i a l
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
16:0
Name
i d e
MIN_RATE_CIR_Q6_P6
n P i
Description
o n f a n a
2.5Gbps
00001684
e k C B a
MMSCR3_Q6P6
d
Bit
i a T 31
F o
30
r 29 28 27 26
6/Port 6
25 24 23 22 21 20 19 18 17 16
Me
MAX_R
ATE_CI
Name
R_Q6_
P6
Type RW
Reset
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Type
Reset 0 0 0 0 0 0 0 0
RW
0 0 0
ele
0
a 0 0 0 0
Bit(s) Name
i a l R Description
t
i d e n P i
2.5Gbps
00001688
o n f
MMSCR2_Q7P6
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
31 30 29
n t i a28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
n f i d a P i MIN_R
ATE_CI
o n
R_Q7_
Type
k C a n a P6
RW
Reset
Bit
i a T e
15
o
14
r B 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Me d
Name
Type
Reset 0 F 0 0 0 0 0 0
MIN_RATE_CIR_Q7_P6
0
RW
0 0 0 0 0 0 0 0

2.5Gbps
f o r
l e a se 00000000
Bit 31 30 29
l R
28 27 26
7/Port 6
25 24 23 22 21
e20 19 18 17 16
n t i a MAX_R
ATE_CI
e
Name
i
R_Q7_
Type
n f i d n a P
P6
RW
Reset
Bit 15
k C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1
0
0
Name
Type
i a T e o r B
MAX_RATE_CIR_Q7_P6
RW
F
Reset
d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
M e Bit(s)
16:0
Name
MAX_RATE_CIR_Q7_P6
Description
2.5Gbps
o r
00001690
Bit 31
MMSCR_P6
30 29 28 27 26
25 24 23 22 21 20
a s 19 18
ef
00000001
17 16
ele
Name
R
Type
Reset
Bit 15 14 13
t i a l12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
MIN_
MAX_T
f
B_EN_
Type
C o n a n a P6
RW
Reset
e k B a n 1
d i a T F o r

f o r
l e a se MT7531
l R e Scheduler
Confidential A
n t i a
Bit(s) Name
n
0 MIN_MAX_TB_EN_P6 When this bit is disabled, the rate limit acts like a leaky bucket principle.
C o n a n Otherwise, the rate limit uses the token bucket method, and this
T e k r B a 0: CIR/CBS mode token bucket Disable

d i a F o
Me
f o r
l e a se
l R e
n t i a
f i d e a P i
C o n n a n
T e k r B a
d i a F o
Me
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a seMT7531
l R e Buffer Management Unit

Confidential A
n t i a
4
f i d e
Buffer Management Unit (BMU)
a P i
C o n
Introduction
n a n
a
4.1
T e k r B
A total of 1536 memory blocks (pages) are used to store frames in PB_CTRL, which are managed and processed
d i a F o
in Buffer Management Unit (BMU). The key concept is the use of linking lists to maintain these blocks.
Me
Before receiving a frame, RX_CTRL will request memory blocks to store the frame. If multiple blocks are used for
a specific frame, the interconnections among these blocks are kept inside BMU as page linkers. After the frame
is fully received, ARL will determine the egress ports of this frame by looking up its contents. Thus, BMU will
store the 1st page linker (called frame linker) of this frame into the corresponding egress queues of egress ports.
Once the egress queues of an egress port are not empty, the Scheduler (SCH) will get a frame linker from BMU
f o r
se
and then inform the corresponding TX_CTRL to pop data from that page in PB_CTRL.
BMU also supports the flow control (FC) and the priority flow control (PFC) mechanisms. Once the flow control
l e a
is enabled, there will be no packet dropped in this switch. Besides, the port-based ingress rate limit is also
e
implemented in BMU. To support the TRTCM (Two-Rate Three-Color Meter) function in ARL, drop profiles for
l R
different drop precedence are also provided in BMU.
i a
e n t i
4.2 Features
n f i d n a P


k o a n a
Support 1536 pages, per page is 256 bytes
C
Packet buffer size is 3*128K Bytes

T e r B
Support 8 egress queues per egress port
i a o
Me



d F
Support the flow control and priority flow control mechanisms
Support the port-based ingress rate control
Support the 2-bit drop precedence with different drop profiles
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a seMT7531

Confidential A
4.3
n t
Register Definition i a
f i d e a P i
4.3.1
C o n
BMU_FC Register
n a n
Module name: BMU_FC Base address: (+0x0000)
T e
Address
a
00001800 IRLCR_P0 32 Ingress Rate Limit Control Register of Port 0
d i
00001804
F o FPC_RXCTRL_P0 32 Free Page Count at RX_CTRL of Port 0
Me
0000180C MMDPR_10_Q0P0 32 Drop Precedence control 10 of Q0 Port 0
00001810 MMDPR_10_Q1P0 32 Drop Precedence control 10 of Q1 Port 0
00001820
00001824
MMDPR_10_Q5P0
MMDPR_10_Q6P0
32
32
Drop Precedence control 10 of Q5 Port 0
f o r
se
0000182C
00001830
MMDPR_11_Q0P0
MMDPR_11_Q1P0
e l e a 32
32
R
00001838
0000183C
MMDPR_11_Q3P0
t
MMDPR_11_Q4P0
i a l 32
32
00001840
00001844
i d e n
MMDPR_11_Q5P0
MMDPR_11_Q6P0
P i
32
32
00001848
00001900
o n f
MMDPR_11_Q7P0
IRLCR_P1
a n a
32
32
Ingress Rate Limit Control Register of Port 1
C
00001904 FPC_RXCTRL_P1 32 Free Page Count at RX_CTRL of Port 1
0000190C
e
00001910
k B a n
MMDPR_10_Q0P1
MMDPR_10_Q1P1
32
32
d i a T
00001914
00001918
F o r
MMDPR_10_Q2P1
MMDPR_10_Q3P1
32
32
Me
r
00001930
00001934
MMDPR_11_Q1P1
MMDPR_11_Q2P1
32
32
ef o
00001938 MMDPR_11_Q3P1 32
s
a
ele
00001944
00001948
MMDPR_11_Q6P1
MMDPR_11_Q7P1
i a l R 32
32
t
00001A00 IRLCR_P2 32 Ingress Rate Limit Control Register of Port 2
00001A04
00001A0C
i d e n
FPC_RXCTRL_P2
MMDPR_10_Q0P2
P i
32
32
Free Page Count at RX_CTRL of Port 2
00001A10
00001A14
o n f
MMDPR_10_Q1P2
n
MMDPR_10_Q2P2
a a
32
32
00001A18
e k
00001A1C
C n
MMDPR_10_Q3P2
a
MMDPR_10_Q4P2
B
32
32
d i a T F o r

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Confidential A
n t i a
e
00001A20 MMDPR_10_Q5P2 32 Drop Precedence control 10 of Q5 Port 2
00001A24
00001A28
f i d
MMDPR_10_Q6P2
MMDPR_10_Q7P2
n a P i 32
32
00001A2C
00001A30
C o n a n
MMDPR_11_Q0P2
MMDPR_11_Q1P2
32
32
00001A34
T e
00001A38
k r B a
MMDPR_11_Q2P2
MMDPR_11_Q3P2
32
32
d i a
00001A3C
00001A40
F o MMDPR_11_Q4P2
MMDPR_11_Q5P2
32
32
Me
00001B00 IRLCR_P3 32 Ingress Rate Limit Control Register of Port 3
00001B04 FPC_RXCTRL_P3 32 Free Page Count at RX_CTRL of Port 3
00001B0C
00001B10
MMDPR_10_Q0P3
MMDPR_10_Q1P3
32
32
f o r
se
00001B14 MMDPR_10_Q2P3 32 Drop Precedence control 10 of Q2 Port 3
a
00001B18 MMDPR_10_Q3P3 32 Drop Precedence control 10 of Q3 Port 3
00001B1C
00001B20
00001B24
MMDPR_10_Q4P3
MMDPR_10_Q5P3
MMDPR_10_Q6P3
R e l e 32
32
32
00001B28
00001B2C
MMDPR_10_Q7P3
t
MMDPR_11_Q0P3
i a l 32
32
00001B30
00001B34
i d e n
MMDPR_11_Q1P3
MMDPR_11_Q2P3
P i
32
32
00001B38
00001B3C
o n f
MMDPR_11_Q3P3
a n
MMDPR_11_Q4P3
a 32
32
00001B40
e
00001B44
k C B n
MMDPR_11_Q5P3
a
MMDPR_11_Q6P3
32
32
d i a T
00001B48
00001C00
F o r
MMDPR_11_Q7P3
IRLCR_P4
32
32
Me
00001C04 FPC_RXCTRL_P4 32 Free Page Count at RX_CTRL of Port 4
00001C0C MMDPR_10_Q0P4 32 Drop Precedence control 10 of Q0 Port 4
00001C10 MMDPR_10_Q1P4 32 Drop Precedence control 10 of Q1 Port 4
o r
ef
00001C28 MMDPR_10_Q7P4 32
a s
ele
00001C34
00001C38
MMDPR_11_Q2P4
MMDPR_11_Q3P4
i a l R 32
32
00001C3C
00001C40
e n t
MMDPR_11_Q4P4
MMDPR_11_Q5P4
i
32
32
00001C44
00001C48
n f i d
MMDPR_11_Q6P4
MMDPR_11_Q7P4
n a P
32
32
00001D00
00001D04
k C o IRLCR_P5
a n a
FPC_RXCTRL_P5
32
32
i a T e o r B
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n t i a
e
00001D0C MMDPR_10_Q0P5 32 Drop Precedence control 10 of Q0 Port 5
00001D10
00001D14
f i d
MMDPR_10_Q1P5
MMDPR_10_Q2P5
n a P i 32
32
00001D18
00001D1C
C o n a n
MMDPR_10_Q3P5
MMDPR_10_Q4P5
32
32
00001D20
T e
00001D24
k r B a
MMDPR_10_Q5P5
MMDPR_10_Q6P5
32
32
d i a
00001D28
00001D2C
F o MMDPR_10_Q7P5
MMDPR_11_Q0P5
32
32
Me
00001D30 MMDPR_11_Q1P5 32 Drop Precedence control 11 of Q1 Port 5
00001D3C MMDPR_11_Q4P5 32 Drop Precedence control 11 of Q4 Port 5
00001D40
00001D44
MMDPR_11_Q5P5
MMDPR_11_Q6P5
32
32
f o r
se
a
00001E00 IRLCR_P6 32 Ingress Rate Limit Control Register of Port 6
00001E04
00001E0C
00001E10
FPC_RXCTRL_P6
MMDPR_10_Q0P6
MMDPR_10_Q1P6
R e l e 32
32
32
00001E14
00001E18
MMDPR_10_Q2P6
t
MMDPR_10_Q3P6
i a l 32
32
00001E1C
00001E20
i d e n
MMDPR_10_Q4P6
MMDPR_10_Q5P6
P i
32
32
00001E24
00001E28
o n f
MMDPR_10_Q6P6
a n
MMDPR_10_Q7P6
a 32
32
00001E2C
e
00001E30
k C B n
MMDPR_11_Q0P6
a
MMDPR_11_Q1P6
32
32
d i a T
00001E34
00001E38
F o r
MMDPR_11_Q2P6
MMDPR_11_Q3P6
32
32
Me
00001E3C MMDPR_11_Q4P6 32 Drop Precedence control 11 of Q4 Port 6
00001E40 MMDPR_11_Q5P6 32 Drop Precedence control 11 of Q5 Port 6
00001FC0 FPLC 32 Free Page Link Count Register
00001FE0 GFCCR0 32 Global Flow_Control Control Register 0
o r
ef
00001FEC GFCCR3 32
a s
Global Flow_Control Control Register 3
ele
00001FF0 GFCCR4 32 Global Flow_Control Control Register 4
00001FF4 FCBRCR0 32 Flow Control Block Reservation Control Register
00001FFC GIRLCR
i a l R 32 Global Ingress Rate Limit Control Register
e n t i
d
00001800 IRLCR_P0 Ingress Rate Limit Control Register of Port 0 00000000
Bit 31
o n f
30
i 29
n a P 28 27 26 25 24 23 22 21 20 19 18 17 16
a
Name IGC_RATE_CIR_15_0_P0
Type
Reset
e k
0
C 0
B a n 0 0 0 0 0 0
RW
0 0 0 0 0 0 0 0
d i a T F o r

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Confidential A
15 14
n
13
t i a 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Bit
IGC_RA
Name TE_EN_
IGC_TB
n
_EN_P0
f i d a i
IGC_RA
P
TE_CIR
IGC_RATE_EXP_P0_IGC_TB_T_
P0
IGC_RATE_MAN_P0_IGC_TB_CBS_P0
n
P0 _16_P0
Type
Reset
RW
0
k C o
RW
0
a n a RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i a
Bit(s)
T e
Name
o r B Description
Me d
31:16
F
IGC_RATE_CIR_15_0_P0 When IGC_TB_EN = 1, total 17 bits IGC_CIR include IGC_RATE_CIR_16 in
bit 12 location, support 32Kbps stepping CIR cover up to 2.5Gbps
In MT7531AE/BE, IGC_RATE_CIR = [ Ingress Port Rate Limitation(bps) / 8
* (1/IGC_TB_T) (bps) ]
In MT7531DE, IGC_RATE_CIR = [ 2 * Ingress Port Rate Limitation(bps) / 8
15 IGC_RATE_EN_P0 Port 0 Ingress rate limit control is enabled
0: Ingress rate limit control is disabled
f o r
se
1: Ingress rate limit control is enabled
a
14 IGC_TB_EN_P0 When this bit is disabled, the Ingress rate control acts like a leaky
e
bucket principle.
R e l Otherwise, the Ingress rate control uses the token bucket method, and
t i a l 0: CIR/CBS mode token bucket Disable

n
12 IGC_RATE_CIR_16_P0 Combined with IGC_RATE_CIR_15_0 to form a 17 bits CIR value
11:8
f i d e
IGC_RATE_EXP_P0_IGC_TB_T_P0
a P i
Depend on IGC_TB_EN, it can be exponent part for leaky bucket or TB_T
period for token bucket
n
When IGC_TB_EN = 0, exponent part of Port 0 Ingress rate limit control,
C o n a n value range: 0..5

0: 1Kbps
T e k r B a 1: 10Kbps
2: 100Kbps
a
3: 1Mbps
d i F o 4: 10Mbps
Me
5: 100Mbps
When IGC_TB_EN = 1, support IGC_TB_T period for rate measurement,
value range: 0..14
0: 1/128ms
1: 1/64ms
r
2: 1/32ms
o
3: 1/16ms
ef
4: 1/8ms
5: 1/4ms
6: 1/2ms
a s
ele
7: 1ms
8: 2ms
i a l R 9: 4ms
10: 8ms
11: 16ms
e n t i
12: 32ms
13: 64ms
7:0
n f i d a P
n
14: 128ms
Depend on IGC_TB_EN, it can be mantissa part for leaky bucket or
o
k C a n a When IGC_TB_EN = 0, mantissa part of Port 0 Ingress rate limit control,

value range: 1..255
i a T e o r B
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Confidential A
Bit(s) Name
n t i a Description
f i d e a P i In MT7531AE/BE, Ingress Port Rate Limitation = MAN*10^(EXP)*1Kbps

In MT7531DE, Ingress Port Rate Limitation = (MAN/2)*10^(EXP)*1Kbps
C o n n a n When IGC_TB_EN = 1, support max. bucket size CBS 512 Bytes stepping,
and
k a
Token Bucket = Max ( IGC_RATE_CIR*IGC_TB_T, IGC_TB_CBS*512 )
i a T e o r B
Me d
00001804
Bit
Name
Type
31
F FPC_RXCTRL_P0
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000003
16
Reset
Bit
Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o
1
r 0
se
FPC_RXCTRL_P0
Type RO
Reset
e l e a 0 1 1
Bit(s)
2:0
Name
FPC_RXCTRL_P0
i a l R Description
It indicates the free page count at RX_CTRL module.
e n t i
0000180C
f i d
MMDPR_10_Q0P0
n n a P Drop Precedence control 10 of Q0 Port 0 00000000

Bit
Name
31
C
P0_DP
k
_en o 30
a n a
29 28 27 26 25
P0Q0_pr_dp10
24 23 22 21 20 19 18 17
P0Q0_ht_dp10
16
Type
i
Reset
a T eRW
0
o r B 0
RW
0 0 0 0
RW
0 0 0
Me d
Bit
Name
Type
15
F 14 13
P0Q0_ht_dp10
RW
12 11 10 9 8 7 6 5 4
P0Q0_lt_dp10
RW
3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
31 P0_DP_en Enable Drop Precedence function ofP0.(If the function is enabled, some
a s
packets will be dropped no matter the flow control is ON or OFF)
(1) When queue depth >= P0Q0_ht_dp10, the drop probability of the
ele
incoming packet is 100%.
(2) When queue depth < P0Q0_lt_dp10, the drop probability of the
i a l R incoming packet is 0%.

(3) When P0Q0_lt_dp10 <= queue depth < P0Q0_ht_dp10, the drop
e n t i
probability of incoming packet is based on the setting P0Q0_pr_dp10.
0: Disable
d
1: Enable
26:24
f i
P0Q0_pr_dp10
o n n a P Drop probability of P0 Q0 for drop precedence = 2'b10.

0x0: 0%
k C a n a 0x1: 12.5%
0xn: n* 12.5%
i a T e o r B
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Confidential A
Bit(s) Name
n t i a Description
20:12
f
P0Q0_ht_dp10
i d e a P i 0x7: 87.5%(n=2~6)
High threshold of P0 Q0 depth for drop precedence = 2'b10. Unit: page
8:0
C o n
P0Q0_lt_dp10
n a n size
Low threshold of P0 Q0 depth for drop precedence = 2'b10. Unit: page
a
size
T e k r B
d i a
00001810
F oMMDPR_10_Q1P0 Drop Precedence control 10 of Q1 Port 0 00000000
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name P0Q1_pr_dp10 P0Q1_ht_dp10
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o
1
r 0
se
P0Q1_ht_dp10 P0Q1_lt_dp10
Type RW RW
Reset 0 0 0 0
e l e a 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P0Q1_pr_dp10
i a l R Description
Drop probability of P0 Q1 for drop precedence = 2'b10.
e n t i
0x0: 0%
0x1: 12.5%
n f i d n a P
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
8:0
k o
P0Q1_ht_dp10
C
P0Q1_lt_dp10
a n a
size
i a T e o r B size
Me d
00001814
Bit 31
F MMDPR_10_Q2P0
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
r
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
ef
0
1
o 0
0
Name P0Q2_ht_dp10
a s
P0Q2_lt_dp10
ele
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
26:24 P0Q2_pr_dp10
i d e n P i
0x0: 0%
f
0x1: 12.5%
C o n a n a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
e
P0Q2_ht_dp10
k B a n High threshold of P0 Q2 depth for drop precedence = 2'b10. Unit: page

size
d i a T F o r

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l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
8:0 P0Q2_lt_dp10
f i d e a P i Low threshold of P0 Q2 depth for drop precedence = 2'b10. Unit: page

size
C o n n a n
00001818
Bit
T e k
31
r
30
B a
MMDPR_10_Q3P0
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
d
Name
i a F o P0Q3_pr_dp10 P0Q3_ht_dp10
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name P0Q3_ht_dp10 P0Q3_lt_dp10
Type
Reset 0 0
RW
0 0 0 0 0 0
RW
0 0 0
f o0
r 0
Bit(s)
26:24
Name
P0Q3_pr_dp10
l e a Description
Drop probability of P0 Q3 for drop precedence = 2'b10. se
l R e 0x0: 0%
0x1: 12.5%
n t i a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P0Q3_ht_dp10
f i d e a P i
size
n
8:0 P0Q3_lt_dp10 Low threshold of P0 Q3 depth for drop precedence = 2'b10. Unit: page
C o n a n size
T e k r B a
a o
0000181C MMDPR_10_Q4P0 Drop Precedence control 10 of Q4 Port 0 00000000
d i
Bit 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o r
ef
Type RW RW
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ele a
26:24 P0Q4_pr_dp10
i a l R Drop probability of P0 Q4 for drop precedence = 2'b10.

0x0: 0%
t
0x1: 12.5%
i d e n P i
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
o n f
P0Q4_ht_dp10
a n a
size
C
e k B a n size
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001820
C o n a
MMDPR_10_Q5P0
n n Drop Precedence control 10 of Q5 Port 0 00000000
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
i
Type
a T e o r B P0Q5_pr_dp10
RW
P0Q5_ht_dp10
RW
Me d
Reset
Bit
Name
Type
15
F 14 13
P0Q5_ht_dp10
RW
12 11
0
10
0
9
0
8 7 6 5
0
4
P0Q5_lt_dp10
RW
0
3
0
2
0
1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
26:24 P0Q5_pr_dp10 Drop probability of P0 Q5 for drop precedence = 2'b10.
e l e a 0x0: 0%
0x1: 12.5%
R
0xn: n* 12.5%
20:12 P0Q5_ht_dp10
t i a l 0x7: 87.5%(n=2~6)
n
size
8:0 P0Q5_lt_dp10
f i d e a P i
size
C o n n a n
00001824
Bit
T e k
31
r
30
B a
MMDPR_10_Q6P0
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
d i a F o P0Q6_pr_dp10 P0Q6_ht_dp10
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
r
RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele
0x0: 0%
i a l R 0x1: 12.5%
0xn: n* 12.5%
20:12 P0Q6_ht_dp10
e n t i
0x7: 87.5%(n=2~6)
d
size
8:0
f i
P0Q6_lt_dp10
o n n a P Low threshold of P0 Q6 depth for drop precedence = 2'b10. Unit: page

size
k C a n a
i a T e o r B
M e d F
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Confidential A
00001828
n
MMDPR_10_Q7P0
t i a Drop Precedence control 10 of Q7 Port 0 00000000
Bit 31 30
f i d e29
a P i
28 27 26 25 24 23 22 21 20 19 18 17 16
n
Type
Reset
C o n a n RW RW
a
0 0 0 0 0 0 0 0
Bit
T e k
15 14
r B
13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
d i
Type
F o RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0: 0%
0x1: 12.5%
f o r
se
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P0Q7_ht_dp10
e l e a High threshold of P0 Q7 depth for drop precedence = 2'b10. Unit: page

size
R
t i a l size
0000182C
i d e n
MMDPR_11_Q0P0
P i Drop Precedence control 11 of Q0 Port 0 00000000

Bit
Name
31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
C
P0Q0_pr_dp11 P0Q0_ht_dp11
Type
Reset
e k B a n 0
RW
0 0 0 0
RW
0 0 0
Bit
d
Name
i a T 15
F o r
14 13
P0Q0_ht_dp11
12 11 10 9 8 7 6 5 4
P0Q0_lt_dp11
3 2 1 0
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
a s
ele
0x7: 87.5%(n=2~6)
20:12 P0Q0_ht_dp11 High threshold of P0 Q0 depth for drop precedence = 2'b11. Unit: page
8:0 P0Q0_lt_dp11
i a l R size
t
size
i d e n P i
00001830
o n f n
MMDPR_11_Q1P0
a a Drop Precedence control 11 of Q1 Port 0 00000000
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e k B a n P0Q1_pr_dp11 P0Q1_ht_dp11
d i a T F o r

f o r
l e a se
MT7531

Confidential A
n t i a
e
Type RW RW
Reset
Bit 15
n
14
f i d 13
a P i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
C o
P0Q1_ht_dp11
n a n P0Q1_lt_dp11
a
Type
k
RW RW
Reset
i a T e0
o
0
r B 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit(s)
26:24
Name
F
P0Q1_pr_dp11
Description
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
r
0x7: 87.5%(n=2~6)
size
f o
se
a
size
R e l e
00001834
Bit 31
MMDPR_11_Q2P0
30 29
t i a l28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
i d e n P i
P0Q2_pr_dp11
RW
P0Q2_ht_dp11
RW
Reset
o n f a n a 0 0 0 0 0 0 0 0
C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e k B RW
a n
RW
Reset
d i a T 0
F o r
0 0 0 0 0 0 0 0 0 0 0 0
Me
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
o r
ef
0x7: 87.5%(n=2~6)
size
a s
ele
size
i a l R
00001838
Bit 31 30
e n t
MMDPR_11_Q3P0
29
i
28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
n f i d n a P P0Q3_pr_dp11
RW
P0Q3_ht_dp11
RW
Reset
Bit
k C
15 o 14
a n a13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
i a T e o r B
M e d F
Page 343 of 830
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MT7531

Confidential A
n t i a
e
Type
Reset 0
n
0
f i
RW
d 0
a P i
0 0 0 0 0
RW
0 0 0 0 0
C o n a n
Bit(s)
26:24
T k
Name
e r B
P0Q3_pr_dp11
a Description
0x0: 0%
d i a F o 0x1: 12.5%
Me
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
size
f o r
0000183C MMDPR_11_Q4P0 Drop Precedence control 11 of Q4 Port 0
l e a se 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
i a l R P0Q4_pr_dp11
RW
P0Q4_ht_dp11
RW
Reset
Bit 15 14
e n t 13
i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
n f i d
P0Q4_ht_dp11
RW
n a P
P0Q4_lt_dp11
RW
Reset
k C o
0 0
a n a 0 0 0 0 0 0 0 0 0 0 0
i a T e
Bit(s)
26:24
o r
Name
B
P0Q4_pr_dp11
Description
Med F 0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
o r
ef
size
a s
ele
00001840 MMDPR_11_Q5P0 Drop Precedence control 11 of Q5 Port 0 00000000
Bit
Name
31 30 29
i a l R 28 27 26 25
P0Q5_pr_dp11
24 23 22 21 20 19 18 17
P0Q5_ht_dp11
16
Type
Reset
e n t i
0
RW
0 0 0 0
RW
0 0 0
Bit
Name
15
n f i
14
d n
13
P0Q5_ht_dp11
a P 12 11 10 9 8 7 6 5 4
P0Q5_lt_dp11
3 2 1 0
Type
Reset
k C o
0 0
a n a
RW
0 0 0 0 0 0
RW
0 0 0 0 0
i a T e o r B
Med F
Page 344 of 830
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Confidential A
n t i a
Bit(s) Name
n
C o n a n 0x0: 0%
0x1: 12.5%
T e k r B a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
d i a F o
P0Q5_ht_dp11 High threshold of P0 Q5 depth for drop precedence = 2'b11. Unit: page
size
Me
size
00001844
Bit 31
MMDPR_11_Q6P0
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17
r 00000000
16
se
Type
Reset 0
RW
0 0
e l0
e a 0
RW
0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
P0Q6_ht_dp11
RW
t i a l P0Q6_lt_dp11
RW
Reset 0 0
i d e n 0
P i
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
o n f
P0Q6_pr_dp11
a n a Description
e k C B a n 0x0: 0%
0x1: 12.5%
d i a T
20:12
F o r
P0Q6_ht_dp11
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
M e 8:0 P0Q6_lt_dp11
size
size
o r
ef
s
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
P0Q7_pr_dp11
RW
ele a P0Q7_ht_dp11
RW
Reset
Bit 15 14 13
i a l R 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
e
RW
t
P0Q7_ht_dp11
n i
P0Q7_lt_dp11
RW
Reset 0
n f i
0
d n
0
a P
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
k C o
Name
a
P0Q7_pr_dp11
n a Description
i a T e o r B
M ed F
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MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0x0: 0%
0x1: 12.5%
C o n n a n 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
8:0
T k
P0Q7_ht_dp11
e r B
P0Q7_lt_dp11 a High threshold of P0 Q7 depth for drop precedence = 2'b11. Unit: page
size
d i a F o size
Me 00001900
Bit 31
IRLCR_P1
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
IGC_RATE_CIR_15_0_P1
RW
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGC_RA
Name TE_EN_
P1
IGC_TB
_EN_P1
IGC_RA
e
TE_CIR
R
_16_P1
l e
P1
Type
Reset
RW
0
RW
0
t i a lRW
0 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
i d e n P i
f
31:16
C o n
a n a When IGC_TB_EN = 1, total 17 bits IGC_CIR include IGC_RATE_CIR_16 in

e k B a n In MT7531AE/BE, IGC_RATE_CIR = [ Ingress Port Rate Limitation(bps) / 8

T
d
15
i a F o r
IGC_RATE_EN_P1
Port 1 Ingress rate limit control is enabled
Me
bucket principle.
Otherwise, the Ingress rate control uses the token bucket method, and
o r
ef
12 IGC_RATE_CIR_16_P1
s
Combined with IGC_RATE_CIR_15_0 to form a 17 bits CIR value
a
ele
11:8 IGC_RATE_EXP_P1_IGC_TB_T_P1 Depend on IGC_TB_EN, it can be exponent part for leaky bucket or TB_T
R
l
value range: 0..5
n t i a 0: 1Kbps
1: 10Kbps
e
2: 100Kbps
n f i d a P i 3: 1Mbps
4: 10Mbps
n
5: 100Mbps
k C o a n a When IGC_TB_EN = 1, support IGC_TB_T period for rate measurement,

value range: 0..14
e B
0: 1/128ms
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 1: 1/64ms
2: 1/32ms
C o n n a n 3: 1/16ms
4: 1/8ms
k a
5: 1/4ms
e B
6: 1/2ms
d i a T F o r
7: 1ms
8: 2ms
9: 4ms
Me
10: 8ms
11: 16ms
12: 32ms
13: 64ms
14: 128ms
7:0 IGC_RATE_MAN_P1_IGC_TB_CBS_P1 Depend on IGC_TB_EN, it can be mantissa part for leaky bucket or
f o r
se
When IGC_TB_EN = 0, mantissa part of Port 1 Ingress rate limit control,
value range: 1..255
e l e a In MT7531AE/BE, Ingress Port Rate Limitation = MAN*10^(EXP)*1Kbps

R
Ingress Port Rate Limitation = MAN*10^(EXP)*1Kbps
l
When IGC_TB_EN = 1, support max. bucket size CBS 512 Bytes stepping,
n t i a and
f i d e a P i
00001904
Bit 31
C o n30
n a n
FPC_RXCTRL_P1
29 28 27 26
25 24 23 22 21 20 19 18 17
00000003
16
Name
Type
T e k r B a
i
Reset
d a F o
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FPC_RXCTRL_P1
Type RO
Reset 0 1 1
o r
ef
2:0 FPC_RXCTRL_P1 It indicates the free page count at RX_CTRL module.
a s
0000190C
Bit 31
MMDPR_10_Q0P1
30 29
l R 28 27 26
25 24 23 22 21 ele
20 19 18 17
00000000
16
Name
P1_DP
_en
n t i a P1Q0_pr_dp10 P1Q0_ht_dp10
Type
Reset
RW
0
f i d e a P i 0
RW
0 0 0 0
RW
0 0 0
Bit
Name
15
C o n 14
n a n13
P1Q0_ht_dp10
12 11 10 9 8 7 6 5 4
P1Q0_lt_dp10
3 2 1 0
Type
T e k r B a RW RW
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31
k C o
P1_DP_en
a n a Enable Drop Precedence function ofP1.(If the function is enabled, some

e B
T r
d i a F o
Me
0: Disable
1: Enable
0x0: 0%
0x1: 12.5%
f o r
se
0xn: n* 12.5%
a
0x7: 87.5%(n=2~6)
20:12
8:0
P1Q0_ht_dp10
P1Q0_lt_dp10
R e l e High threshold of P1 Q0 depth for drop precedence = 2'b10. Unit: page

size
t i a l size
00001910
i d e n
MMDPR_10_Q1P1

Bit 31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
C
Type
Reset
e k B a n 0
RW
0 0 0 0
RW
0 0 0
Bit
d
Name
i a T 15
F o r
14 13
P1Q1_ht_dp10
12 11 10 9 8 7 6 5 4
P1Q1_lt_dp10
3 2 1 0
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
0x0: 0%
s
0x1: 12.5%
20:12 P1Q1_ht_dp10
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
ele a
8:0 P1Q1_lt_dp10
i a l R size
e n t i
size
00001914
n f i d n
MMDPR_10_Q2P1
a P Drop Precedence control 10 of Q2 Port 1 00000000
Bit
Name
k C
31
o 30
a n a29 28 27 26 25
P1Q2_pr_dp10
24 23 22 21 20 19 18 17
P1Q2_ht_dp10
16
i a T e o r B
M e d F
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Confidential A
n t i a
e
Type RW RW
Reset
Bit 15
n
14
f i d 13
a P i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
C o
P1Q2_ht_dp10
n a n P1Q2_lt_dp10
a
Type
k
RW RW
Reset
i a T e0
o
0
r B 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit(s)
26:24
Name
F
P1Q2_pr_dp10
Description
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
r
0x7: 87.5%(n=2~6)
size
f o
se
a
size
R e l e
00001918
Bit 31
MMDPR_10_Q3P1
30 29
t i a l28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
i d e n P i
P1Q3_pr_dp10
RW
P1Q3_ht_dp10
RW
Reset
o n f a n a 0 0 0 0 0 0 0 0
C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e k B RW
a n
RW
Reset
d i a T 0
F o r
0 0 0 0 0 0 0 0 0 0 0 0
Me
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
o r
ef
0x7: 87.5%(n=2~6)
size
a s
ele
size
i a l R
0000191C
Bit 31 30
e n t
MMDPR_10_Q4P1
29
i
28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
RW
P1Q4_ht_dp10
RW
Reset
Bit
k C
15 o 14
a n a13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
i a T e o r B
M e d F
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Confidential A
n t i a
e
Type
Reset 0
n
0
f i
RW
d 0
a P i
0 0 0 0 0
RW
0 0 0 0 0
C o n a n
Bit(s)
26:24
T k
Name
e r B
P1Q4_pr_dp10
a Description
0x0: 0%
d i a F o 0x1: 12.5%
Me
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
size
f o r
00001920 MMDPR_10_Q5P1 Drop Precedence control 10 of Q5 Port 1
l e a se 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
RW
P1Q5_ht_dp10
RW
Reset
Bit 15 14
e n t 13
i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
n f i d
P1Q5_ht_dp10
RW
n a P
P1Q5_lt_dp10
RW
Reset
k C o
0 0
a n a 0 0 0 0 0 0 0 0 0 0 0
i a T e
Bit(s)
26:24
o r
Name
B
P1Q5_pr_dp10
Description
Med F 0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
o r
ef
size
a s
ele
Bit
Name
31 30 29
i a l R 28 27 26 25
P1Q6_pr_dp10
24 23 22 21 20 19 18 17
P1Q6_ht_dp10
16
Type
Reset
e n t i
0
RW
0 0 0 0
RW
0 0 0
Bit
Name
15
n f i
14
d n
13
P1Q6_ht_dp10
a P 12 11 10 9 8 7 6 5 4
P1Q6_lt_dp10
3 2 1 0
Type
Reset
k C o
0 0
a n a
RW
0 0 0 0 0 0
RW
0 0 0 0 0
i a T e o r B
Med F
Page 350 of 830
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Confidential A
n t i a
Bit(s) Name
n
C o n a n 0x0: 0%
0x1: 12.5%
T e k r B a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
d i a F o
size
Me
size
00001928
Bit 31
MMDPR_10_Q7P1
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17
r 00000000
16
se
Type
Reset 0
RW
0 0
e l0
e a 0
RW
0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
P1Q7_ht_dp10
RW
RW
Reset 0 0
i d e n 0
P i
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
o n f
P1Q7_pr_dp10
a n a Description
e k C B a n 0x0: 0%
0x1: 12.5%
d i a T
20:12
F o r
P1Q7_ht_dp10
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
size
o r
ef
0000192C MMDPR_11_Q0P1 Drop Precedence control 11 of Q0 Port 1 00000000
s
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
P1Q0_pr_dp11
RW
ele a P1Q0_ht_dp11
RW
Reset
Bit 15 14 13
i a l R 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
e
RW
t
P1Q0_ht_dp11
n i
P1Q0_lt_dp11
RW
Reset 0
n f i
0
d n
0
a P
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
k C o
Name
a
P1Q0_pr_dp11
n a Description
i a T e o r B
M ed F
Page 351 of 830
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MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0x0: 0%
0x1: 12.5%
C o n n a n 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
8:0
T k
P1Q0_ht_dp11
e r B
size
d i a F o size
Me 00001930
Bit 31
MMDPR_11_Q1P1
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
P1Q1_pr_dp11
RW
P1Q1_ht_dp11
RW
f o r
se
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P1Q1_ht_dp11
12
e l e a11 10 9 8 7 6 5 4
P1Q1_lt_dp11
3 2 1 0
R
Type RW RW
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P1Q1_pr_dp11
i d e n P i
Description
o n f a n a 0x0: 0%
0x1: 12.5%
e k C B a n 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
T r
d i
8:0
a F o
P1Q1_lt_dp11
size
Me
size

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
s
Type RW RW
Reset
Bit 15 14 13
e
12 11
0
10
0
9
0
8 7 6 5
0
4
le a 0
3
0
2
0
1
0
0
Name
Type
P1Q2_ht_dp11
RW
i a l R P1Q2_lt_dp11
RW
Reset 0 0
e n t 0
i
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
n f i d
P1Q2_pr_dp11
n a P Description
k C o a n a 0x0: 0%
0x1: 12.5%
i a T e o r B
Med F
Page 352 of 830
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Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
C o n
P1Q2_ht_dp11
n a n High threshold of P1 Q2 depth for drop precedence = 2'b11. Unit: page

size
k a
e B
size
d i a T F o r
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
f o
0
1
r 0
0
Name
se
Type
Reset 0 0
RW
0 0 0 0 0 0
e
RW
l0
e a 0 0 0 0
Bit(s) Name
i a l R Description
26:24 P1Q3_pr_dp11
e n t i
0x0: 0%
n f i d n a P
0x1: 12.5%
0xn: n* 12.5%
20:12
C o
P1Q3_ht_dp11
k a n a
0x7: 87.5%(n=2~6)
size
8:0
i a T e o r B
P1Q3_lt_dp11 Low threshold of P1 Q3 depth for drop precedence = 2'b11. Unit: page
size
M e d
0000193C
Bit
F
31
MMDPR_11_Q4P1
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Type RW RW
o r
ef
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
a s 3 2 1 0
ele
Type RW RW
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
d
o n f i n a P 0x0: 0%
0x1: 12.5%
k C a n a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
i a T e o r B
M e d F
Page 353 of 830
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
20:12 P1Q4_ht_dp11
f i d e a P i High threshold of P1 Q4 depth for drop precedence = 2'b11. Unit: page

size
8:0
C o n
P1Q4_lt_dp11
n a n
size
T e k r B a
d i a
00001940
F o
MMDPR_11_Q5P1 Drop Precedence control 11 of Q5 Port 1 00000000
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f o r
se
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
26:24 P1Q5_pr_dp11

0x0: 0%
e n t i
0x1: 12.5%
0xn: n* 12.5%
20:12
n f
P1Q5_ht_dp11
i d n a P
0x7: 87.5%(n=2~6)
8:0
C o
P1Q5_lt_dp11
k a n a
size
size
i a T e o r B
Me d
00001944
Bit
Name
31 F MMDPR_11_Q6P1
30 29 28 27 26
25
P1Q6_pr_dp11
24 23 22 21 20 19 18 17
P1Q6_ht_dp11
00000000
16
Type RW RW
r
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P1Q6_ht_dp11
12 11 10 9 8 7 6 5 4
P1Q6_lt_dp11
3 2
ef
1
o 0
Type RW RW
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
i a l R Description
t
n
0x0: 0%
f i d e a P i
0x1: 12.5%
0xn: n* 12.5%
20:12
C o n
P1Q6_ht_dp11
n a n
0x7: 87.5%(n=2~6)
size
T e k r B a
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
8:0 P1Q6_lt_dp11

size
C o n n a n
00001948
Bit
T e k
31
r B30 a
MMDPR_11_Q7P1
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
d
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 0 0
RW
0 0 0 0 0 0
RW
0 0 0
f o0
r 0
Bit(s)
26:24
Name
P1Q7_pr_dp11
l e a Description
l R e 0x0: 0%
0x1: 12.5%
n t i a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P1Q7_ht_dp11
f i d e a P i
size
n
C o n a n size
T e k r B a
a o
00001A00 IRLCR_P2 Ingress Rate Limit Control Register of Port 2 00000000
d i
Bit 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
IGC_RA IGC_RA
IGC_TB IGC_RATE_EXP_P2_IGC_TB_T_
Name TE_EN_
P2
_EN_P2
TE_CIR
_16_P2
P2
ef o
s
Type RW RW RW RW RW
Reset 0 0
e
0 0 0 0 0 0 0 0 0
le a 0 0 0 0
Bit(s)
31:16
Name
a
i l R Description
When IGC_TB_EN = 1, total 17 bits IGC_CIR include IGC_RATE_CIR_16 in
e n t i
d
o n f i n a P In MT7531DE, IGC_RATE_CIR = [ 2 * Ingress Port Rate Limitation(bps) / 8

a
e k C B a n 0: Ingress rate limit control is disabled

i a T F o r
ed
M
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
14 IGC_TB_EN_P2
f i d e a P i When this bit is disabled, the Ingress rate control acts like a leaky
bucket principle.
C o n n a n
12
T e k r B a
IGC_RATE_CIR_16_P2
d i
11:8
a o
F
Me
value range: 0..5
0: 1Kbps
1: 10Kbps
2: 100Kbps
3: 1Mbps
4: 10Mbps
f o r
se
5: 100Mbps
e l e a value range: 0..14

0: 1/128ms
R
1: 1/64ms
l
2: 1/32ms
n t i a 3: 1/16ms
4: 1/8ms
e
5: 1/4ms
n f i d a P i 6: 1/2ms
7: 1ms
C o n a n 8: 2ms
9: 4ms
a
10: 8ms
T e k r B
11: 16ms
12: 32ms
d i a F o 13: 64ms
14: 128ms
Me
value range: 1..255
In MT7531AE/BE, Ingress Port Rate Limitation = MAN*10^(EXP)*1Kbps
o r
ef
and
s
a
00001A04 FPC_RXCTRL_P2
l R Free Page Count at RX_CTRL of Port 2

ele 00000003
Bit
Name
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
f i d e a P i
Bit
Name
15
C o n14
n a n
13 12 11 10 9 8 7 6 5 4 3 2 1
FPC_RXCTRL_P2
0
Type
T e k r B a RO
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
n t i a
e
Reset 0 1 1
n f i d a P i
n
2:0
k C o
FPC_RXCTRL_P2
a n a It indicates the free page count at RX_CTRL module.
i a
00001A0C
T e o r B
Me d
Bit
Name
Type
31
F
P2_DP
_en
RW
30 29 28 27 26 25
P2Q0_pr_dp10
RW
24 23 22 21 20 19 18 17
P2Q0_ht_dp10
RW
16
Reset 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P2Q0_ht_dp10
12 11 10 9 8 7 6 5 4
P2Q0_lt_dp10
3 2
f o
1
r 0
se
Type RW RW
Reset 0 0 0 0
e l e a 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
P2_DP_en
i a l R Description
Enable Drop Precedence function ofP2.(If the function is enabled, some
t
i d e n P i
f
C o n a n a incoming packet is 0%.

e k B a n probability of incoming packet is based on the setting P2Q0_pr_dp10.

0: Disable
T
1: Enable
d i
26:24
a o r
P2Q0_pr_dp10
F
0x0: 0%
Me
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
o r
ef
size
a s
ele
00001A10 MMDPR_10_Q1P2 Drop Precedence control 10 of Q1 Port 2 00000000
Bit
Name
31 30
i
29
a l R 28 27 26 25
P2Q1_pr_dp10
24 23 22 21 20 19 18 17
P2Q1_ht_dp10
16
Type
Reset
e n t i
0
RW
0 0 0 0
RW
0 0 0
Bit
Name
15
n f i d
14
n
13
a
P2Q1_ht_dp10
P 12 11 10 9 8 7 6 5 4
P2Q1_lt_dp10
3 2 1 0
Type
Reset
k C o0
a0
n aRW
0 0 0 0 0 0
RW
0 0 0 0 0
i a T e o r B
Med F
Page 357 of 830
f o r
l e a se
MT7531

Confidential A
n t i a
Bit(s) Name
n
C o n a n 0x0: 0%
0x1: 12.5%
T e k r B a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
d i a F o
size
Me
size
00001A14
Bit 31
MMDPR_10_Q2P2
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17
r 00000000
16
se
Type
Reset 0
RW
0 0
e l0
e a 0
RW
0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
P2Q2_ht_dp10
RW
RW
Reset 0 0
i d e n 0
P i
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
o n f
P2Q2_pr_dp10
a n a Description
e k C B a n 0x0: 0%
0x1: 12.5%
d i a T
20:12
F o r
P2Q2_ht_dp10
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
size
o r
ef
s
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
P2Q3_pr_dp10
RW
ele a P2Q3_ht_dp10
RW
Reset
Bit 15 14 13
i a l R 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
e
RW
t
P2Q3_ht_dp10
n i
P2Q3_lt_dp10
RW
Reset 0
n f i
0
d n
0
a P
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
k C o
Name
a
P2Q3_pr_dp10
n a Description
i a T e o r B
M ed F
Page 358 of 830
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0x0: 0%
0x1: 12.5%
C o n n a n 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
8:0
T k
P2Q3_ht_dp10
e r B
size
d i a F o size
Me 00001A1C
Bit 31
MMDPR_10_Q4P2
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
P2Q4_pr_dp10
RW
P2Q4_ht_dp10
RW
f o r
se
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P2Q4_ht_dp10
12
e l e a11 10 9 8 7 6 5 4
P2Q4_lt_dp10
3 2 1 0
R
Type RW RW
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P2Q4_pr_dp10
i d e n P i
Description
o n f a n a 0x0: 0%
0x1: 12.5%
e k C B a n 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
T r
d i
8:0
a F o
P2Q4_lt_dp10
size
Me
size

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
s
Type RW RW
Reset
Bit 15 14 13
e
12 11
0
10
0
9
0
8 7 6 5
0
4
le a 0
3
0
2
0
1
0
0
Name
Type
P2Q5_ht_dp10
RW
RW
Reset 0 0
e n t 0
i
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
n f i d
P2Q5_pr_dp10
n a P Description
k C o a n a 0x0: 0%
0x1: 12.5%
i a T e o r B
Med F
Page 359 of 830
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
C o n
P2Q5_ht_dp10

size
k a
e B
size
d i a T F o r
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
f o
0
1
r 0
0
Name
se
Type
Reset 0 0
RW
0 0 0 0 0 0
e
RW
l0
e a 0 0 0 0
Bit(s) Name
i a l R Description
26:24 P2Q6_pr_dp10
e n t i
0x0: 0%
n f i d n a P
0x1: 12.5%
0xn: n* 12.5%
20:12
C o
P2Q6_ht_dp10
k a n a
0x7: 87.5%(n=2~6)
size
8:0
i a T e o r B
size
M e d
00001A28
Bit
F
31
MMDPR_10_Q7P2
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Type RW RW
o r
ef
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
a s 3 2 1 0
ele
Type RW RW
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
d
o n f i n a P 0x0: 0%
0x1: 12.5%
k C a n a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
i a T e o r B
M e d F
Page 360 of 830
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
20:12 P2Q7_ht_dp10

size
8:0
C o n
P2Q7_lt_dp10
n a n
size
T e k r B a
d i a
00001A2C
F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f o r
se
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
26:24 P2Q0_pr_dp11

0x0: 0%
e n t i
0x1: 12.5%
0xn: n* 12.5%
20:12
n f
P2Q0_ht_dp11
i d n a P
0x7: 87.5%(n=2~6)
8:0
C o
P2Q0_lt_dp11
k a n a
size
size
i a T e o r B
Me d
00001A30
Bit
Name
31 F MMDPR_11_Q1P2
30 29 28 27 26
25
P2Q1_pr_dp11
24 23 22 21 20 19 18 17
P2Q1_ht_dp11
00000000
16
Type RW RW
r
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P2Q1_ht_dp11
12 11 10 9 8 7 6 5 4
P2Q1_lt_dp11
3 2
ef
1
o 0
Type RW RW
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
i a l R Description
t
n
0x0: 0%
f i d e a P i
0x1: 12.5%
0xn: n* 12.5%
20:12
C o n
P2Q1_ht_dp11
n a n
0x7: 87.5%(n=2~6)
size
T e k r B a
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
8:0 P2Q1_lt_dp11

size
C o n n a n
00001A34
Bit
T e k
31
r
30
B a
MMDPR_11_Q2P2
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
d
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 0 0
RW
0 0 0 0 0 0
RW
0 0 0
f o0
r 0
Bit(s)
26:24
Name
P2Q2_pr_dp11
l e a Description
l R e 0x0: 0%
0x1: 12.5%
n t i a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P2Q2_ht_dp11
f i d e a P i
size
n
C o n a n size
T e k r B a
a o
d i
Bit 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o r
ef
Type RW RW
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ele a
26:24 P2Q3_pr_dp11

0x0: 0%
t
0x1: 12.5%
i d e n P i
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
o n f
P2Q3_ht_dp11
a n a
size
C
e k B a n size
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001A3C
C o n a
MMDPR_11_Q4P2
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
i
Type
RW
P2Q4_ht_dp11
RW
Me d
Reset
Bit
Name
Type
15
F 14 13
P2Q4_ht_dp11
RW
12 11
0
10
0
9
0
8 7 6 5
0
4
P2Q4_lt_dp11
RW
0
3
0
2
0
1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
e l e a 0x0: 0%
0x1: 12.5%
R
0xn: n* 12.5%
20:12 P2Q4_ht_dp11
t i a l 0x7: 87.5%(n=2~6)
n
size
8:0 P2Q4_lt_dp11
f i d e a P i
size
C o n n a n
00001A40
Bit
T e k
31
r
30
B a
MMDPR_11_Q5P2
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
r
RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele
0x0: 0%
i a l R 0x1: 12.5%
0xn: n* 12.5%
20:12 P2Q5_ht_dp11
e n t i
0x7: 87.5%(n=2~6)
d
size
8:0
f i
P2Q5_lt_dp11

size
k C a n a
i a T e o r B
M e d F
Page 363 of 830
f o r
l e a se
MT7531

Confidential A
00001A44
n
MMDPR_11_Q6P2
Bit 31 30
f i d e29
a P i
28 27 26 25 24 23 22 21 20 19 18 17 16
n
Type
Reset
C o n a n RW RW
a
0 0 0 0 0 0 0 0
Bit
T e k
15 14
r B
13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
d i
Type
F o RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0: 0%
0x1: 12.5%
f o r
se
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P2Q6_ht_dp11

size
R
t i a l size
00001A48
i d e n
MMDPR_11_Q7P2

Bit
Name
31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
C
Type
Reset
e k B a n 0
RW
0 0 0 0
RW
0 0 0
Bit
d
Name
i a T 15
F o r
14 13
P2Q7_ht_dp11
12 11 10 9 8 7 6 5 4
P2Q7_lt_dp11
3 2 1 0
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
a s
ele
0x7: 87.5%(n=2~6)
8:0 P2Q7_lt_dp11
i a l R size
t
size
i d e n P i
00001B00
o n f
IRLCR_P3
a n a Ingress Rate Limit Control Register of Port 3 00000000
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e k B a n IGC_RATE_CIR_15_0_P3
d i a T F o r

f o r
l e a seMT7531

Confidential A
n t i a
e
Type RW
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
IGC_RA
Name TE_EN_
C o
IGC_TB
_EN_P3
n a n IGC_RA
TE_CIR
P3
k a
P3 _16_P3
Type
Reset
i a T e
RW
0
RW
o
0
r B RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Me d
Bit(s)
31:16
NameF
Description
r
o
15 IGC_RATE_EN_P3
se f
a
14 IGC_TB_EN_P3
R e l e 1: Ingress rate limit control is enabled

When this bit is disabled, the Ingress rate control acts like a leaky
bucket principle.
t i a l Otherwise, the Ingress rate control uses the token bucket method, and
i d e n P i
12
11:8
o n f
IGC_RATE_CIR_16_P3
a n a
e k C B a n When IGC_TB_EN = 0, exponent part of Port 3 Ingress rate limit control,

value range: 0..5
T r
0: 1Kbps
d i a F o 1: 10Kbps
2: 100Kbps
Me
3: 1Mbps
4: 10Mbps
5: 100Mbps
value range: 0..14
0: 1/128ms
o r
ef
1: 1/64ms
2: 1/32ms
s
3: 1/16ms
4: 1/8ms
5: 1/4ms
6: 1/2ms
ele a
i a l R 7: 1ms
8: 2ms
e n t i
9: 4ms
10: 8ms
d
11: 16ms
13: 64ms
a
14: 128ms
7:0
e k C B a n
IGC_RATE_MAN_P3_IGC_TB_CBS_P3 Depend on IGC_TB_EN, it can be mantissa part for leaky bucket or
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When IGC_TB_EN = 0, mantissa part of Port 3 Ingress rate limit control,

value range: 1..255
C o n n a n In MT7531AE/BE, Ingress Port Rate Limitation = MAN*10^(EXP)*1Kbps

k a
e B
and
d i a T F o r
Me 00001B04
Bit
Name
31
FPC_RXCTRL_P3
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000003
16
Type
Reset
f o r
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e l e a FPC_RXCTRL_P3
RO
R
Reset 0 1 1
Bit(s) Name
t i a l Description
2:0 FPC_RXCTRL_P3
i d e n P i
o n f a n a
00001B0C
Bit
e k C
31
B
30
a n
MMDPR_10_Q0P3
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
T r
P3_DP
a o
_en
e d i
Type
Reset
F
RW
0 0
RW
0 0 0 0
RW
0 0 0
M Bit
Name
Type
15 14 13
P3Q0_ht_dp10
RW
12 11 10 9 8 7 6 5 4
P3Q0_lt_dp10
RW
3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
31
Name
P3_DP_en
Description
a s
ef
ele

e n t i
d
o n f i n a P 0: Disable
1: Enable
26:24
k C
P3Q0_pr_dp10
a n a Drop probability of P3 Q0 for drop precedence = 2'b10.

0x0: 0%
i a T e o r B
M e d F
Page 366 of 830
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MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0x1: 12.5%
0xn: n* 12.5%
20:12
C o n
P3Q0_ht_dp10
n a n 0x7: 87.5%(n=2~6)
k a
size
8:0
i a T e o r B
size
Me d
00001B10
Bit 31
F MMDPR_10_Q1P3
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Type
Reset 0
RW
0 0 0 0
RW
0
f o0
r 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
P3Q1_ht_dp10
RW
e l e a P3Q1_lt_dp10
RW
Reset 0 0 0
i a l R0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P3Q1_pr_dp10
e n t i
Description
n f i d n a P
0x0: 0%
0x1: 12.5%
20:12
k C o
P3Q1_ht_dp10
a n a
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
8:0
i a T e o r B
P3Q1_lt_dp10
size
Me d
00001B14
F MMDPR_10_Q2P3
size
Drop Precedence control 10 of Q2 Port 3 00000000

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o r
ef
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
le a s
0
3
0
2
0
1
0
0
e
Type
Reset 0 0
RW
i a
0
l R 0 0 0 0 0
RW
0 0 0 0 0
e n t i
d
26:24
o n f i
P3Q2_pr_dp10
n a P Drop probability of P3 Q2 for drop precedence = 2'b10.

0x0: 0%
k C a n a 0x1: 12.5%
0xn: n* 12.5%
i a T e o r B
Med F
Page 367 of 830
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MT7531

Confidential A
Bit(s) Name
n t i a Description
20:12
f
P3Q2_ht_dp10
i d e a P i 0x7: 87.5%(n=2~6)
8:0
C o n
P3Q2_lt_dp10
n a n size
a
size
T e k r B
d i a
00001B18
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o
1
r 0
se
Type RW RW
Reset 0 0 0 0
e l e a 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P3Q3_pr_dp10
i a l R Description
e n t i
0x0: 0%
0x1: 12.5%
n f i d n a P
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
8:0
k o
P3Q3_ht_dp10
C
P3Q3_lt_dp10
a n a
size
i a T e o r B size
Me d
00001B1C
Bit 31
F MMDPR_10_Q4P3
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
r
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
ef
0
1
o 0
0
Name P3Q4_ht_dp10
a s
P3Q4_lt_dp10
ele
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
26:24 P3Q4_pr_dp10
i d e n P i
0x0: 0%
f
0x1: 12.5%
C o n a n a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
e
P3Q4_ht_dp10

size
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
8:0 P3Q4_lt_dp10

size
C o n n a n
00001B20
Bit
T e k
31
r
30
B a
MMDPR_10_Q5P3
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
d
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 0 0
RW
0 0 0 0 0 0
RW
0 0 0
f o0
r 0
Bit(s)
26:24
Name
P3Q5_pr_dp10
l e a Description
l R e 0x0: 0%
0x1: 12.5%
n t i a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P3Q5_ht_dp10
f i d e a P i
size
n
C o n a n size
T e k r B a
a o
00001B24 MMDPR_10_Q6P3 Drop Precedence control 10 of Q6 Port 3 00000000
d i
Bit 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o r
ef
Type RW RW
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ele a
26:24 P3Q6_pr_dp10

0x0: 0%
t
0x1: 12.5%
i d e n P i
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
o n f
P3Q6_ht_dp10
a n a
size
C
e k B a n size
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001B28
C o n a
MMDPR_10_Q7P3
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
i
Type
RW
P3Q7_ht_dp10
RW
Me d
Reset
Bit
Name
Type
15
F 14 13
P3Q7_ht_dp10
RW
12 11
0
10
0
9
0
8 7 6 5
0
4
P3Q7_lt_dp10
RW
0
3
0
2
0
1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
e l e a 0x0: 0%
0x1: 12.5%
R
0xn: n* 12.5%
20:12 P3Q7_ht_dp10
t i a l 0x7: 87.5%(n=2~6)
n
size
8:0 P3Q7_lt_dp10
f i d e a P i
size
C o n n a n
00001B2C
Bit
T e k
31
r
30
B a
MMDPR_11_Q0P3
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
r
RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele
0x0: 0%
i a l R 0x1: 12.5%
0xn: n* 12.5%
20:12 P3Q0_ht_dp11
e n t i
0x7: 87.5%(n=2~6)
d
size
8:0
f i
P3Q0_lt_dp11

size
k C a n a
i a T e o r B
M e d F
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Confidential A
00001B30
n
MMDPR_11_Q1P3
Bit 31 30
f i d e29
a P i
28 27 26 25 24 23 22 21 20 19 18 17 16
n
Type
Reset
C o n a n RW RW
a
0 0 0 0 0 0 0 0
Bit
T e k
15 14
r B
13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
d i
Type
F o RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0: 0%
0x1: 12.5%
f o r
se
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P3Q1_ht_dp11

size
R
t i a l size
00001B34
i d e n
MMDPR_11_Q2P3

Bit
Name
31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
C
Type
Reset
e k B a n 0
RW
0 0 0 0
RW
0 0 0
Bit
d
Name
i a T 15
F o r
14 13
P3Q2_ht_dp11
12 11 10 9 8 7 6 5 4
P3Q2_lt_dp11
3 2 1 0
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
a s
ele
0x7: 87.5%(n=2~6)
8:0 P3Q2_lt_dp11
i a l R size
t
size
i d e n P i
00001B38
o n f n
MMDPR_11_Q3P3
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
d i a T F o r

f o r
l e a se
MT7531

Confidential A
n t i a
e
Type RW RW
Reset
Bit 15
n
14
f i d 13
a P i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
C o
P3Q3_ht_dp11
n a n P3Q3_lt_dp11
a
Type
k
RW RW
Reset
i a T e0
o
0
r B 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit(s)
26:24
Name
F
P3Q3_pr_dp11
Description
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
r
0x7: 87.5%(n=2~6)
size
f o
se
a
size
R e l e
00001B3C
Bit 31
MMDPR_11_Q4P3
30 29
t i a l28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
i d e n P i
P3Q4_pr_dp11
RW
P3Q4_ht_dp11
RW
Reset
o n f a n a 0 0 0 0 0 0 0 0
C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e k B RW
a n
RW
Reset
d i a T 0
F o r
0 0 0 0 0 0 0 0 0 0 0 0
Me
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
o r
ef
0x7: 87.5%(n=2~6)
size
a s
ele
size
i a l R
00001B40
Bit 31 30
e n t
MMDPR_11_Q5P3
29
i
28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
RW
P3Q5_ht_dp11
RW
Reset
Bit
k C
15 o 14
a n a13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
i a T e o r B
M e d F
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Confidential A
n t i a
e
Type
Reset 0
n
0
f i
RW
d 0
a P i
0 0 0 0 0
RW
0 0 0 0 0
C o n a n
Bit(s)
26:24
T k
Name
e r B
P3Q5_pr_dp11
a Description
0x0: 0%
d i a F o 0x1: 12.5%
Me
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
size
f o r
00001B44 MMDPR_11_Q6P3 Drop Precedence control 11 of Q6 Port 3
l e a se 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
RW
P3Q6_ht_dp11
RW
Reset
Bit 15 14
e n t 13
i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
n f i d
P3Q6_ht_dp11
RW
n a P
P3Q6_lt_dp11
RW
Reset
k C o
0 0
a n a 0 0 0 0 0 0 0 0 0 0 0
i a T e
Bit(s)
26:24
o r
Name
B
P3Q6_pr_dp11
Description
Med F 0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
o r
ef
size
a s
ele
00001B48 MMDPR_11_Q7P3 Drop Precedence control 11 of Q7 Port 3 00000000
Bit
Name
31 30 29
i a l R 28 27 26 25
P3Q7_pr_dp11
24 23 22 21 20 19 18 17
P3Q7_ht_dp11
16
Type
Reset
e n t i
0
RW
0 0 0 0
RW
0 0 0
Bit
Name
15
n f i
14
d n
13
P3Q7_ht_dp11
a P 12 11 10 9 8 7 6 5 4
P3Q7_lt_dp11
3 2 1 0
Type
Reset
k C o
0 0
a n a
RW
0 0 0 0 0 0
RW
0 0 0 0 0
i a T e o r B
Med F
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Confidential A
n t i a
Bit(s) Name
n
C o n a n 0x0: 0%
0x1: 12.5%
T e k r B a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
d i a F o
size
Me
size
00001C00
Bit 31
IRLCR_P4
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17
r
00000000
16
se
a
Type RW
Reset
Bit
0
15
0
14
0
13
0
12
R e l e 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
l
IGC_RA IGC_RA
Name TE_EN_
i a
TE_CIR IGC_RATE_MAN_P4_IGC_TB_CBS_P4
_EN_P4 P4
Type
P4
RW RW
e n t _16_P4
RW
i
RW RW
Reset 0 0
n f i d n a P
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
31:16
Name
k C o a n a
Description
e B
d i a T F o r In MT7531AE/BE, IGC_RATE_CIR = [ Ingress Port Rate Limitation(bps) / 8

Me
bucket principle.
o r
ef
a s
ele
12 IGC_RATE_CIR_16_P4 Combined with IGC_RATE_CIR_15_0 to form a 17 bits CIR value
11:8
i a l R
IGC_RATE_EXP_P4_IGC_TB_T_P4 Depend on IGC_TB_EN, it can be exponent part for leaky bucket or TB_T
t
n
value range: 0..5
f i d e a P i
0: 1Kbps
1: 10Kbps
n
2: 100Kbps
C o n a n 3: 1Mbps
4: 10Mbps
T e k r B a 5: 100Mbps
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When IGC_TB_EN = 1, support IGC_TB_T period for rate measurement,

value range: 0..14
C o n n a n 0: 1/128ms
1: 1/64ms
k a
2: 1/32ms
e B
3: 1/16ms
d i a T F o r
4: 1/8ms
5: 1/4ms
6: 1/2ms
Me
7: 1ms
8: 2ms
9: 4ms
10: 8ms
11: 16ms
12: 32ms
13: 64ms
f o r
se
14: 128ms
e l e a TB_CBS stepping for token bucket

value range: 1..255
i a l R In MT7531AE/BE, Ingress Port Rate Limitation = MAN*10^(EXP)*1Kbps

e n t i
and
d
o n f i n a P
00001C04
k C a n a
FPC_RXCTRL_P4 Free Page Count at RX_CTRL of Port 4 00000003
Bit
Name
i a T e31
o r B
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me d
Type
Reset
Bit
Name
15
F 14 13 12 11 10 9 8 7 6 5 4 3 2 1
FPC_RXCTRL_P4
0
Type RO
Reset 0 1
o r 1
a s ef
ele
2:0 FPC_RXCTRL_P4 It indicates the free page count at RX_CTRL module.
00001C0C
i
MMDPR_10_Q0P4
a l R Drop Precedence control 10 of Q0 Port 4 00000000

Bit 31
P4_DP
30
e n t29
i
28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
_en
RW
n f i d n a P
P4Q0_pr_dp10
RW
P4Q0_ht_dp10
RW
Reset
Bit
k C
0
15
o 14
a n a 13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
i a T e o r B
M e d F
Page 375 of 830
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Confidential A
n t i a
e
Type
Reset 0
n
0
f i
RW
d 0
a P i
0 0 0 0 0
RW
0 0 0 0 0
C o n a n
Bit(s)
31
T k
Name
e
P4_DP_en
r B a Description
d i a F o (1) When queue depth >= P4Q0_ht_dp10, the drop probability of the
Me
0: Disable
26:24 P4Q0_pr_dp10
1: Enable
f o r
se
0x0: 0%
e l e a 0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P4Q0_ht_dp10
i a l R High threshold of P4 Q0 depth for drop precedence = 2'b10. Unit: page

size
8:0 P4Q0_lt_dp10
e n t i
size
n f i d n a P
00001C10
Bit
k
31
C o30
a n a
MMDPR_10_Q1P4
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
i
Type
RW
P4Q1_ht_dp10
RW
Me d
Reset
Bit
Name
Type
15
F 14 13
P4Q1_ht_dp10
RW
12 11
0
10
0
9
0
8 7 6 5
0
4
P4Q1_lt_dp10
RW
0
3
0
2
0
1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
a s
ele
0x0: 0%
0x1: 12.5%
R
0xn: n* 12.5%
20:12 P4Q1_ht_dp10
t i a l 0x7: 87.5%(n=2~6)
n
size
8:0 P4Q1_lt_dp10
f i d e a P i
size
C o n n a n
00001C14
T e k r B a
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
Type
n f i d a P i P4Q2_pr_dp10
RW
P4Q2_ht_dp10
RW
Reset
C o n a n 0 0 0 0 0 0 0 0
a
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
k
Bit
Name
Type
i a T e o r B
P4Q2_ht_dp10
RW
P4Q2_lt_dp10
RW
Me d
Reset
Bit(s)
26:24
0
Name
F 0
P4Q2_pr_dp10
0 0
Description
0 0 0 0

0 0 0 0 0
0x0: 0%
r
0x1: 12.5%
0xn: n* 12.5%
f o
se
0x7: 87.5%(n=2~6)
8:0 P4Q2_lt_dp10
e l e a size
R
size
t i a l
00001C18
Bit 31 30
i d e n
MMDPR_10_Q3P4
29
P i
28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
o n f a n a P4Q3_pr_dp10 P4Q3_ht_dp10
C
Type RW RW
Reset
Bit
e k
15 14
B a n13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
d i
Type
a T F o r
P4Q3_ht_dp10
RW
P4Q3_lt_dp10
RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0: 0%
o r
ef
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
a s
ele
size
8:0 P4Q3_lt_dp10
i a l R Low threshold of P4 Q3 depth for drop precedence = 2'b10. Unit: page

size
e n t i
00001C1C
Bit 31
n f
30
i d
MMDPR_10_Q4P4
n
29
a P 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
k C o a n a P4Q4_pr_dp10
RW
P4Q4_ht_dp10
RW
i a T e o r B
M e d F
Page 377 of 830
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MT7531

Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14
n f i d 13
P4Q4_ht_dp10
a P i
12 11 10 9 8 7 6 5 4
P4Q4_lt_dp10
3 2 1 0
Type
C o RW
n a n RW
a
Reset
k
0 0 0 0 0 0 0 0 0 0 0 0 0
i a
Bit(s)
T e
Name
o r B Description
Me d
26:24
F
P4Q4_pr_dp10 Drop probability of P4 Q4 for drop precedence = 2'b10.
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
8:0 P4Q4_lt_dp10
size
f o r
se
size
e l e a
00001C20
Bit 31
MMDPR_10_Q5P4
30 29
i a l R
28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
e n t i
P4Q5_pr_dp10
RW
P4Q5_ht_dp10
RW
Reset
Bit 15
n
14
f i d 13
n a P12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
k C o
P4Q5_ht_dp10
RW
a n a P4Q5_lt_dp10
RW
Reset
i a T e0
o
0
r B 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit(s)
26:24
Name
F
P4Q5_pr_dp10
Description
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
r
0x7: 87.5%(n=2~6)
size
ef o
s
size
ele a
00001C24 MMDPR_10_Q6P4
i a l R Drop Precedence control 10 of Q6 Port 4 00000000

Bit
Name
31 30
e n t 29
i
28 27 26 25
P4Q6_pr_dp10
24 23 22 21 20 19 18 17
P4Q6_ht_dp10
16
Type
Reset
n f i d n a P 0
RW
0 0 0 0
RW
0 0 0
Bit
Name
k C o
15 14
a n a 13
P4Q6_ht_dp10
12 11 10 9 8 7 6 5 4
P4Q6_lt_dp10
3 2 1 0
i a T e o r B
Med F
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Confidential A
n t i a
e
Type RW RW
Reset 0 0
n f i d 0
a P i
0 0 0 0 0 0 0 0 0 0
Bit(s) Name
k a
e B
0x0: 0%
d i a T F o r 0x1: 12.5%
0xn: n* 12.5%
Me
0x7: 87.5%(n=2~6)
size
size
f o r
se
00001C28 MMDPR_10_Q7P4 Drop Precedence control 10 of Q7 Port 4 00000000
Bit
Name
31 30 29 28
e l e a
27 26 25
P4Q7_pr_dp10
24 23 22 21 20 19 18 17
P4Q7_ht_dp10
16
Type
Reset
i a l R 0
RW
0 0 0 0
RW
0 0 0
Bit
Name
15 14
e
13
P4Q7_ht_dp10
n t 12
i
11 10 9 8 7 6 5 4
P4Q7_lt_dp10
3 2 1 0
Type
Reset 0
n
0
f i
RW
d 0
n a P 0 0 0 0 0
RW
0 0 0 0 0
Bit(s)
k
Name
26:24
i a T e o r B
P4Q7_pr_dp10 Drop probability of P4 Q7 for drop precedence = 2'b10.
0x0: 0%
Me d
20:12
F
P4Q7_ht_dp10
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
size
o r
a s ef
le
00001C2C MMDPR_11_Q0P4 Drop Precedence control 11 of Q0 Port 4 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
RW
P4Q0_ht_dp11
RW
Reset
Bit 15 14
e n t 13
i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
n f i d
P4Q0_ht_dp11
RW
n a P P4Q0_lt_dp11
RW
Reset
k C o
0 0
a n a 0 0 0 0 0 0 0 0 0 0 0
i a T e o r B
Med F
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MT7531

Confidential A
Bit(s) Name
n t i a Description
26:24 P4Q0_pr_dp11
f i d e a P i Drop probability of P4 Q0 for drop precedence = 2'b11.

0x0: 0%
C o n n a n 0x1: 12.5%
0xn: n* 12.5%
k a
0x7: 87.5%(n=2~6)
20:12
i a T e o r B
size
F
Me d size
00001C30 MMDPR_11_Q1P4 Drop Precedence control 11 of Q1 Port 4 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name P4Q1_pr_dp11
f o
P4Q1_ht_dp11
se
Type RW RW
a
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P4Q1_ht_dp11
R
12 11 10 9 8 7 6 5
e l4
e
P4Q1_lt_dp11
3 2 1 0
Type
Reset 0 0
RW
t
0
i a l 0 0 0 0 0
RW
0 0 0 0 0
Bit(s) Name
26:24
o n f
P4Q1_pr_dp11

0x0: 0%
e k C B a n 0x1: 12.5%
0xn: n* 12.5%
T r
0x7: 87.5%(n=2~6)
e d i a
20:12
8:0
F o
P4Q1_ht_dp11
P4Q1_lt_dp11
size
M size
00001C34 MMDPR_11_Q2P4 Drop Precedence control 11 of Q2 Port 4
o r
00000000
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type
Reset 0
RW
0 0
ele
0
a 0
RW
0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
P4Q2_ht_dp11
RW
RW
Reset 0 0
i d e n 0
P i
0 0 0 0 0 0 0 0 0 0
Bit(s) Name
C
e k B a n 0x0: 0%
i a T F o r
ed
M
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0x1: 12.5%
0xn: n* 12.5%
20:12
C o n
P4Q2_ht_dp11
n a n 0x7: 87.5%(n=2~6)
k a
size
8:0
i a T e o r B
size
Me d
00001C38
Bit 31
F MMDPR_11_Q3P4
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Type
Reset 0
RW
0 0 0 0
RW
0
f o0
r 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
P4Q3_ht_dp11
RW
RW
Reset 0 0 0
i a l R0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P4Q3_pr_dp11
e n t i
Description
n f i d n a P
0x0: 0%
0x1: 12.5%
20:12
k C o
P4Q3_ht_dp11
a n a
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
8:0
i a T e o r B
P4Q3_lt_dp11
size
Me d
00001C3C
F MMDPR_11_Q4P4
size

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o r
ef
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
le a s
0
3
0
2
0
1
0
0
e
Type
Reset 0 0
RW
i a
0
l R 0 0 0 0 0
RW
0 0 0 0 0
e n t i
d
26:24
o n f i
P4Q4_pr_dp11

0x0: 0%
k C a n a 0x1: 12.5%
0xn: n* 12.5%
i a T e o r B
Med F
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Confidential A
Bit(s) Name
n t i a Description
20:12
f
P4Q4_ht_dp11
i d e a P i 0x7: 87.5%(n=2~6)
8:0
C o n
P4Q4_lt_dp11
n a n size
a
size
T e k r B
d i a
00001C40
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o
1
r 0
se
Type RW RW
Reset 0 0 0 0
e l e a 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P4Q5_pr_dp11
i a l R Description
e n t i
0x0: 0%
0x1: 12.5%
n f i d n a P
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
8:0
k o
P4Q5_ht_dp11
C
P4Q5_lt_dp11
a n a
size
i a T e o r B size
Me d
00001C44
Bit 31
F MMDPR_11_Q6P4
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
r
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
ef
0
1
o 0
0
Name P4Q6_ht_dp11
a s
P4Q6_lt_dp11
ele
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
26:24 P4Q6_pr_dp11
i d e n P i
0x0: 0%
f
0x1: 12.5%
C o n a n a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
e
P4Q6_ht_dp11

size
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
8:0 P4Q6_lt_dp11

size
C o n n a n
00001C48
Bit
T e k
31
r B30 a
MMDPR_11_Q7P4
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
d
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 0 0
RW
0 0 0 0 0 0
RW
0 0 0
f o0
r 0
Bit(s)
26:24
Name
P4Q7_pr_dp11
l e a Description
l R e 0x0: 0%
0x1: 12.5%
n t i a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P4Q7_ht_dp11
f i d e a P i
size
n
C o n a n size
T e k r B a
a o
00001D00 IRLCR_P5 Ingress Rate Limit Control Register of Port 5 00000000
d i
Bit 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
IGC_RA IGC_RA
Name TE_EN_
P5
_EN_P5
TE_CIR
_16_P5
P5
ef o
s
Type RW RW RW RW RW
Reset 0 0
e
0 0 0 0 0 0 0 0 0
le a 0 0 0 0
Bit(s)
31:16
Name
a
i l R Description
e n t i
d
o n f i n a P In MT7531DE, IGC_RATE_CIR = [ 2 * Ingress Port Rate Limitation(bps) / 8

a
e k C B a n 0: Ingress rate limit control is disabled

i a T F o r
ed
M
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
14 IGC_TB_EN_P5
f i d e a P i When this bit is disabled, the Ingress rate control acts like a leaky
bucket principle.
C o n n a n
12
T e k r B a
IGC_RATE_CIR_16_P5
d i
11:8
a o
F
Me
value range: 0..5
0: 1Kbps
1: 10Kbps
2: 100Kbps
3: 1Mbps
4: 10Mbps
f o r
se
5: 100Mbps
e l e a value range: 0..14

0: 1/128ms
R
1: 1/64ms
l
2: 1/32ms
n t i a 3: 1/16ms
4: 1/8ms
e
5: 1/4ms
n f i d a P i 6: 1/2ms
7: 1ms
C o n a n 8: 2ms
9: 4ms
a
10: 8ms
T e k r B
11: 16ms
12: 32ms
d i a F o 13: 64ms
14: 128ms
Me
value range: 1..255
In MT7531AE/BE, Ingress Port Rate Limitation = MAN*10^(EXP)*1Kbps
o r
ef
and
s
a
00001D04 FPC_RXCTRL_P5
l R Free Page Count at RX_CTRL of Port 5

ele 00000003
Bit
Name
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
f i d e a P i
Bit
Name
15
C o n14
n a n
13 12 11 10 9 8 7 6 5 4 3 2 1
FPC_RXCTRL_P5
0
Type
T e k r B a RO
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
n t i a
e
Reset 0 1 1
n f i d a P i
n
2:0
k C o
FPC_RXCTRL_P5
a n a It indicates the free page count at RX_CTRL module.
i a
00001D0C
T e o r B
Me d
Bit
Name
Type
31
F
P5_DP
_en
RW
30 29 28 27 26 25
P5Q0_pr_dp10
RW
24 23 22 21 20 19 18 17
P5Q0_ht_dp10
RW
16
Reset 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P5Q0_ht_dp10
12 11 10 9 8 7 6 5 4
P5Q0_lt_dp10
3 2
f o
1
r 0
se
Type RW RW
Reset 0 0 0 0
e l e a 0 0 0 0 0 0 0 0 0
Bit(s)
31
Name
P5_DP_en
i a l R Description
t
i d e n P i
f
C o n a n a incoming packet is 0%.

e k B a n probability of incoming packet is based on the setting P5Q0_pr_dp10.

0: Disable
T
1: Enable
d i
26:24
a o r
P5Q0_pr_dp10
F
0x0: 0%
Me
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
o r
ef
size
a s
ele
00001D10 MMDPR_10_Q1P5 Drop Precedence control 10 of Q1 Port 5 00000000
Bit
Name
31 30
i
29
a l R 28 27 26 25
P5Q1_pr_dp10
24 23 22 21 20 19 18 17
P5Q1_ht_dp10
16
Type
Reset
e n t i
0
RW
0 0 0 0
RW
0 0 0
Bit
Name
15
n f i d
14
n
13
a
P5Q1_ht_dp10
P 12 11 10 9 8 7 6 5 4
P5Q1_lt_dp10
3 2 1 0
Type
Reset
k C o0
a0
n aRW
0 0 0 0 0 0
RW
0 0 0 0 0
i a T e o r B
Med F
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Confidential A
n t i a
Bit(s) Name
n
C o n a n 0x0: 0%
0x1: 12.5%
T e k r B a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
d i a F o
size
Me
size
00001D14
Bit 31
MMDPR_10_Q2P5
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17
r 00000000
16
se
Type
Reset 0
RW
0 0
e l0
e a 0
RW
0 0 0
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
P5Q2_ht_dp10
RW
RW
Reset 0 0
i d e n 0
P i
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
o n f
P5Q2_pr_dp10
a n a Description
e k C B a n 0x0: 0%
0x1: 12.5%
d i a T
20:12
F o r
P5Q2_ht_dp10
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
size
o r
ef
s
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
P5Q3_pr_dp10
RW
ele a P5Q3_ht_dp10
RW
Reset
Bit 15 14 13
i a l R 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
e
RW
t
P5Q3_ht_dp10
n i
P5Q3_lt_dp10
RW
Reset 0
n f i
0
d n
0
a P
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
k C o
Name
a
P5Q3_pr_dp10
n a Description
i a T e o r B
M ed F
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MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0x0: 0%
0x1: 12.5%
C o n n a n 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
8:0
T k
P5Q3_ht_dp10
e r B
size
d i a F o size
Me 00001D1C
Bit 31
MMDPR_10_Q4P5
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
P5Q4_pr_dp10
RW
P5Q4_ht_dp10
RW
f o r
se
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P5Q4_ht_dp10
12
e l e a11 10 9 8 7 6 5 4
P5Q4_lt_dp10
3 2 1 0
R
Type RW RW
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P5Q4_pr_dp10
i d e n P i
Description
o n f a n a 0x0: 0%
0x1: 12.5%
e k C B a n 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
T r
d i
8:0
a F o
P5Q4_lt_dp10
size
Me
size

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
o r 16
ef
s
Type RW RW
Reset
Bit 15 14 13
e
12 11
0
10
0
9
0
8 7 6 5
0
4
le a 0
3
0
2
0
1
0
0
Name
Type
P5Q5_ht_dp10
RW
RW
Reset 0 0
e n t 0
i
0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
n f i d
P5Q5_pr_dp10
n a P Description
k C o a n a 0x0: 0%
0x1: 12.5%
i a T e o r B
Med F
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l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
C o n
P5Q5_ht_dp10

size
k a
e B
size
d i a T F o r
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
f o
0
1
r 0
0
Name
se
Type
Reset 0 0
RW
0 0 0 0 0 0
e
RW
l0
e a 0 0 0 0
Bit(s) Name
i a l R Description
26:24 P5Q6_pr_dp10
e n t i
0x0: 0%
n f i d n a P
0x1: 12.5%
0xn: n* 12.5%
20:12
C o
P5Q6_ht_dp10
k a n a
0x7: 87.5%(n=2~6)
size
8:0
i a T e o r B
size
M e d
00001D28
Bit
F
31
MMDPR_10_Q7P5
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Type RW RW
o r
ef
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
a s 3 2 1 0
ele
Type RW RW
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
d
o n f i n a P 0x0: 0%
0x1: 12.5%
k C a n a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
i a T e o r B
M e d F
Page 388 of 830
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
20:12 P5Q7_ht_dp10

size
8:0
C o n
P5Q7_lt_dp10
n a n
size
T e k r B a
d i a
00001D2C
F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
f o r
se
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e l e a Description
26:24 P5Q0_pr_dp11

0x0: 0%
e n t i
0x1: 12.5%
0xn: n* 12.5%
20:12
n f
P5Q0_ht_dp11
i d n a P
0x7: 87.5%(n=2~6)
8:0
C o
P5Q0_lt_dp11
k a n a
size
size
i a T e o r B
Me d
00001D30
Bit
Name
31 F MMDPR_11_Q1P5
30 29 28 27 26
25
P5Q1_pr_dp11
24 23 22 21 20 19 18 17
P5Q1_ht_dp11
00000000
16
Type RW RW
r
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
P5Q1_ht_dp11
12 11 10 9 8 7 6 5 4
P5Q1_lt_dp11
3 2
ef
1
o 0
Type RW RW
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
i a l R Description
t
n
0x0: 0%
f i d e a P i
0x1: 12.5%
0xn: n* 12.5%
20:12
C o n
P5Q1_ht_dp11
n a n
0x7: 87.5%(n=2~6)
size
T e k r B a
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
8:0 P5Q1_lt_dp11

size
C o n n a n
00001D34
Bit
T e k
31
r
30
B a
MMDPR_11_Q2P5
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
d
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 0 0
RW
0 0 0 0 0 0
RW
0 0 0
f o0
r 0
Bit(s)
26:24
Name
P5Q2_pr_dp11
l e a Description
l R e 0x0: 0%
0x1: 12.5%
n t i a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P5Q2_ht_dp11
f i d e a P i
size
n
C o n a n size
T e k r B a
a o
d i
Bit 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o r
ef
Type RW RW
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ele a
26:24 P5Q3_pr_dp11

0x0: 0%
t
0x1: 12.5%
i d e n P i
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
o n f
P5Q3_ht_dp11
a n a
size
C
e k B a n size
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001D3C
C o n a
MMDPR_11_Q4P5
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
i
Type
RW
P5Q4_ht_dp11
RW
Me d
Reset
Bit
Name
Type
15
F 14 13
P5Q4_ht_dp11
RW
12 11
0
10
0
9
0
8 7 6 5
0
4
P5Q4_lt_dp11
RW
0
3
0
2
0
1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
e l e a 0x0: 0%
0x1: 12.5%
R
0xn: n* 12.5%
20:12 P5Q4_ht_dp11
t i a l 0x7: 87.5%(n=2~6)
n
size
8:0 P5Q4_lt_dp11
f i d e a P i
size
C o n n a n
00001D40
Bit
T e k
31
r
30
B a
MMDPR_11_Q5P5
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
r
RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele
0x0: 0%
i a l R 0x1: 12.5%
0xn: n* 12.5%
20:12 P5Q5_ht_dp11
e n t i
0x7: 87.5%(n=2~6)
d
size
8:0
f i
P5Q5_lt_dp11

size
k C a n a
i a T e o r B
M e d F
Page 391 of 830
f o r
l e a se
MT7531

Confidential A
00001D44
n
MMDPR_11_Q6P5
Bit 31 30
f i d e29
a P i
28 27 26 25 24 23 22 21 20 19 18 17 16
n
Type
Reset
C o n a n RW RW
a
0 0 0 0 0 0 0 0
Bit
T e k
15 14
r B
13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
d i
Type
F o RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0: 0%
0x1: 12.5%
f o r
se
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P5Q6_ht_dp11

size
R
t i a l size
00001D48
i d e n
MMDPR_11_Q7P5

Bit
Name
31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
C
Type
Reset
e k B a n 0
RW
0 0 0 0
RW
0 0 0
Bit
d
Name
i a T 15
F o r
14 13
P5Q7_ht_dp11
12 11 10 9 8 7 6 5 4
P5Q7_lt_dp11
3 2 1 0
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
a s
ele
0x7: 87.5%(n=2~6)
8:0 P5Q7_lt_dp11
i a l R size
t
size
i d e n P i
00001E00
o n f
IRLCR_P6
a n a Ingress Rate Limit Control Register of Port 6 00000000
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e k B a n IGC_RATE_CIR_15_0_P6
d i a T F o r

f o r
l e a seMT7531

Confidential A
n t i a
e
Type RW
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
IGC_RA
Name TE_EN_
C o
IGC_TB
_EN_P6
n a n IGC_RA
TE_CIR
P6
k a
P6 _16_P6
Type
Reset
i a T e
RW
0
RW
o
0
r B RW
0 0 0
RW
0 0 0 0 0 0
RW
0 0 0 0
Me d
Bit(s)
31:16
NameF
Description
r
o
15 IGC_RATE_EN_P6
se f
a
14 IGC_TB_EN_P6
R e l e 1: Ingress rate limit control is enabled

When this bit is disabled, the Ingress rate control acts like a leaky
bucket principle.
t i a l Otherwise, the Ingress rate control uses the token bucket method, and
i d e n P i
12
11:8
o n f
IGC_RATE_CIR_16_P6
a n a
e k C B a n When IGC_TB_EN = 0, exponent part of Port 6 Ingress rate limit control,

value range: 0..5
T r
0: 1Kbps
d i a F o 1: 10Kbps
2: 100Kbps
Me
3: 1Mbps
4: 10Mbps
5: 100Mbps
value range: 0..14
0: 1/128ms
o r
ef
1: 1/64ms
2: 1/32ms
s
3: 1/16ms
4: 1/8ms
5: 1/4ms
6: 1/2ms
ele a
i a l R 7: 1ms
8: 2ms
e n t i
9: 4ms
10: 8ms
d
11: 16ms
13: 64ms
a
14: 128ms
7:0
e k C B a n
IGC_RATE_MAN_P6_IGC_TB_CBS_P6 Depend on IGC_TB_EN, it can be mantissa part for leaky bucket or
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When IGC_TB_EN = 0, mantissa part of Port 6 Ingress rate limit control,

value range: 1..255
C o n n a n In MT7531AE/BE, Ingress Port Rate Limitation = MAN*10^(EXP)*1Kbps

k a
e B
and
d i a T F o r
Me 00001E04
Bit
Name
31
FPC_RXCTRL_P6
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000003
16
Type
Reset
f o r
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e l e a FPC_RXCTRL_P6
RO
R
Reset 0 1 1
Bit(s) Name
t i a l Description
2:0 FPC_RXCTRL_P6
i d e n P i
o n f a n a
00001E0C
Bit
e k C
31
B
30
a n
MMDPR_10_Q0P6
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
T r
P6_DP
a o
_en
e d i
Type
Reset
F
RW
0 0
RW
0 0 0 0
RW
0 0 0
M Bit
Name
Type
15 14 13
P6Q0_ht_dp10
RW
12 11 10 9 8 7 6 5 4
P6Q0_lt_dp10
RW
3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
Bit(s)
31
Name
P6_DP_en
Description
a s
ef
ele

e n t i
d
o n f i n a P 0: Disable
1: Enable
26:24
k C
P6Q0_pr_dp10

0x0: 0%
i a T e o r B
M e d F
Page 394 of 830
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0x1: 12.5%
0xn: n* 12.5%
20:12
C o n
P6Q0_ht_dp10
n a n 0x7: 87.5%(n=2~6)
k a
size
8:0
i a T e o r B
size
Me d
00001E10
Bit 31
F MMDPR_10_Q1P6
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Type
Reset 0
RW
0 0 0 0
RW
0
f o0
r 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
P6Q1_ht_dp10
RW
RW
Reset 0 0 0
i a l R0 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P6Q1_pr_dp10
e n t i
Description
n f i d n a P
0x0: 0%
0x1: 12.5%
20:12
k C o
P6Q1_ht_dp10
a n a
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
8:0
i a T e o r B
P6Q1_lt_dp10
size
Me d
00001E14
F MMDPR_10_Q2P6
size

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o r
ef
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
le a s
0
3
0
2
0
1
0
0
e
Type
Reset 0 0
RW
i a
0
l R 0 0 0 0 0
RW
0 0 0 0 0
e n t i
d
26:24
o n f i
P6Q2_pr_dp10

0x0: 0%
k C a n a 0x1: 12.5%
0xn: n* 12.5%
i a T e o r B
Med F
Page 395 of 830
f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
20:12
f
P6Q2_ht_dp10
i d e a P i 0x7: 87.5%(n=2~6)
8:0
C o n
P6Q2_lt_dp10
n a n size
a
size
T e k r B
d i a
00001E18
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o
1
r 0
se
Type RW RW
Reset 0 0 0 0
e l e a 0 0 0 0 0 0 0 0 0
Bit(s)
26:24
Name
P6Q3_pr_dp10
i a l R Description
e n t i
0x0: 0%
0x1: 12.5%
n f i d n a P
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
8:0
k o
P6Q3_ht_dp10
C
P6Q3_lt_dp10
a n a
size
i a T e o r B size
Me d
00001E1C
Bit 31
F MMDPR_10_Q4P6
30 29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
r
Type RW RW
Reset
Bit 15 14 13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
ef
0
1
o 0
0
Name P6Q4_ht_dp10
a s
P6Q4_lt_dp10
ele
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
26:24 P6Q4_pr_dp10
i d e n P i
0x0: 0%
f
0x1: 12.5%
C o n a n a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
e
P6Q4_ht_dp10

size
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
8:0 P6Q4_lt_dp10

size
C o n n a n
00001E20
Bit
T e k
31
r
30
B a
MMDPR_10_Q5P6
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
d
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 0 0
RW
0 0 0 0 0 0
RW
0 0 0
f o0
r 0
Bit(s)
26:24
Name
P6Q5_pr_dp10
l e a Description
l R e 0x0: 0%
0x1: 12.5%
n t i a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P6Q5_ht_dp10
f i d e a P i
size
n
C o n a n size
T e k r B a
a o
00001E24 MMDPR_10_Q6P6 Drop Precedence control 10 of Q6 Port 6 00000000
d i
Bit 31
F 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o r
ef
Type RW RW
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
ele a
26:24 P6Q6_pr_dp10

0x0: 0%
t
0x1: 12.5%
i d e n P i
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
o n f
P6Q6_ht_dp10
a n a
size
C
e k B a n size
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
00001E28
C o n a
MMDPR_10_Q7P6
k a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
i
Type
RW
P6Q7_ht_dp10
RW
Me d
Reset
Bit
Name
Type
15
F 14 13
P6Q7_ht_dp10
RW
12 11
0
10
0
9
0
8 7 6 5
0
4
P6Q7_lt_dp10
RW
0
3
0
2
0
1
0
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
e l e a 0x0: 0%
0x1: 12.5%
R
0xn: n* 12.5%
20:12 P6Q7_ht_dp10
t i a l 0x7: 87.5%(n=2~6)
n
size
8:0 P6Q7_lt_dp10
f i d e a P i
size
C o n n a n
00001E2C
Bit
T e k
31
r
30
B a
MMDPR_11_Q0P6
29 28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
r
RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
ele
0x0: 0%
i a l R 0x1: 12.5%
0xn: n* 12.5%
20:12 P6Q0_ht_dp11
e n t i
0x7: 87.5%(n=2~6)
d
size
8:0
f i
P6Q0_lt_dp11

size
k C a n a
i a T e o r B
M e d F
Page 398 of 830
f o r
l e a se
MT7531

Confidential A
00001E30
n
MMDPR_11_Q1P6
Bit 31 30
f i d e29
a P i
28 27 26 25 24 23 22 21 20 19 18 17 16
n
Type
Reset
C o n a n RW RW
a
0 0 0 0 0 0 0 0
Bit
T e k
15 14
r B
13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
d i
Type
F o RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0: 0%
0x1: 12.5%
f o r
se
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12 P6Q1_ht_dp11

size
R
t i a l size
00001E34
i d e n
MMDPR_11_Q2P6

Bit
Name
31
o n
30
f 29
a n a 28 27 26 25 24 23 22 21 20 19 18 17 16
C
Type
Reset
e k B a n 0
RW
0 0 0 0
RW
0 0 0
Bit
d
Name
i a T 15
F o r
14 13
P6Q2_ht_dp11
12 11 10 9 8 7 6 5 4
P6Q2_lt_dp11
3 2 1 0
Me
Type RW RW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

o r
ef
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
a s
ele
0x7: 87.5%(n=2~6)
8:0 P6Q2_lt_dp11
i a l R size
t
size
i d e n P i
00001E38
o n f n
MMDPR_11_Q3P6
C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
d i a T F o r

f o r
l e a se
MT7531

Confidential A
n t i a
e
Type RW RW
Reset
Bit 15
n
14
f i d 13
a P i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
C o
P6Q3_ht_dp11
n a n P6Q3_lt_dp11
a
Type
k
RW RW
Reset
i a T e0
o
0
r B 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit(s)
26:24
Name
F
P6Q3_pr_dp11
Description
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
r
0x7: 87.5%(n=2~6)
size
f o
se
a
size
R e l e
00001E3C
Bit 31
MMDPR_11_Q4P6
30 29
t i a l28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
i d e n P i
P6Q4_pr_dp11
RW
P6Q4_ht_dp11
RW
Reset
o n f a n a 0 0 0 0 0 0 0 0
C
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e k B RW
a n
RW
Reset
d i a T 0
F o r
0 0 0 0 0 0 0 0 0 0 0 0
Me
0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
o r
ef
0x7: 87.5%(n=2~6)
size
a s
ele
size
i a l R
00001E40
Bit 31 30
e n t
MMDPR_11_Q5P6
29
i
28 27 26
25 24 23 22 21 20 19 18 17
00000000
16
Name
Type
RW
P6Q5_ht_dp11
RW
Reset
Bit
k C
15 o 14
a n a13 12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
i a T e o r B
M e d F
Page 400 of 830
f o r
l e a se
MT7531

Confidential A
n t i a
e
Type
Reset 0
n
0
f i
RW
d 0
a P i
0 0 0 0 0
RW
0 0 0 0 0
C o n a n
Bit(s)
26:24
T k
Name
e r B
P6Q5_pr_dp11
a Description
0x0: 0%
d i a F o 0x1: 12.5%
Me
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
size
f o r
00001E44 MMDPR_11_Q6P6 Drop Precedence control 11 of Q6 Port 6
l e a se 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
RW
P6Q6_ht_dp11
RW
Reset
Bit 15 14
e n t 13
i
12 11
0
10
0
9
0
8 7 6 5
0
4
0
3
0
2
0
1
0
0
Name
Type
n f i d
P6Q6_ht_dp11
RW
n a P
P6Q6_lt_dp11
RW
Reset
k C o
0 0
a n a 0 0 0 0 0 0 0 0 0 0 0
i a T e
Bit(s)
26:24
o r
Name
B
P6Q6_pr_dp11
Description
Med F 0x0: 0%
0x1: 12.5%
0xn: n* 12.5%
0x7: 87.5%(n=2~6)
size
o r
ef
size
a s
ele
00001E48 MMDPR_11_Q7P6 Drop Precedence control 11 of Q7 Port 6 00000000
Bit
Name
31 30 29
i a l R 28 27 26 25
P6Q7_pr_dp11
24 23 22 21 20 19 18 17
P6Q7_ht_dp11
16
Type
Reset
e n t i
0
RW
0 0 0 0
RW
0 0 0
Bit
Name
15
n f i
14
d n
13
P6Q7_ht_dp11
a P 12 11 10 9 8 7 6 5 4
P6Q7_lt_dp11
3 2 1 0
Type
Reset
k C o
0 0
a n a
RW
0 0 0 0 0 0
RW
0 0 0 0 0
i a T e o r B
Med F
Page 401 of 830
f o r
l e a se
MT7531

Confidential A
n t i a
Bit(s) Name
n
C o n a n 0x0: 0%
0x1: 12.5%
T e k r B a 0xn: n* 12.5%
0x7: 87.5%(n=2~6)
20:12
d i a F o
size
Me
size
00001FC0
Bit 31
FPLC
30 29 28 27 26
Free Page Link Count Register
25 24 23 22 21 20 19 18
f o
17
r
0FFF0600
16
se
Name MIN_FREE_PL_CNT
Type
Reset 1 1 1 1 1 1
RO
1
e l1
e a 1 1 1 1
R
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
t i a l FREE_PL_CNT
RO
Reset
i d e n P i
0 1 1 0 0 0 0 0 0 0 0 0
Bit(s)
27:16
Name
o n f
MIN_FREE_PL_CNT
a n a Description
Minimal Free Page Link Count in LMU from last read access
11:0
e k C
FREE_PL_CNT
B a n Free Page Link Count in LMU
d i a T
00001FE0
F o r
GFCCR0 Global Flow_Control Control Register 0 20F000B0
M e Bit
Name
31 30 29
FC_OFF FC_ON
2ON_O 2OFF_
PT OPT
28 27 26 25 24 23 22 21 20
FC_FREE_BLK_HITHD
19 18 17 16
Type RW RW RW
o r
ef
Reset 1 0 0 0 1 1 1 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FC_FREE_BLK_LOTHD
a s
ele
Type RW
Reset 0 0 1 0 1 1 0 0 0 0
i a l R
t
29 FC_OFF2ON_OPT
i d e n P i
Flow control assertion option
0: Disable
f
1: Enable aggressive frame discard option in flow control transition from
28
o n
FC_ON2OFF_OPT
C a n a OFF to ON
Flow control de-assertion option
e k B a n 0: Disable
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 1: Enable aggressive frame discard option in flow control transition from

ON to OFF
25:16
9:0
C n
FC_FREE_BLK_HITHD
o n
FC_FREE_BLK_LOTHD
a n
High water mark of memory buffer (in unit of 2 blocks) associated with
flow control and packet discard mechanism. (not include reserve block)
Low water mark of memory buffer (in unit of 2 blocks) associated with
T e k r B a flow control and packet discard mechanism. (not include reserve block)
d i a F o
Me
00001FE4 GFCCR1 Global Flow_Control Control Register 1 00120008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name FC_PORT_BLK_HI_THD
Type RW
Reset
Bit 15 14 13 12 11 10
0
9
0
8
0
7
0
6
0
5
1
4
0
3
0
2
f
1
1
o r 0
0
se
Name FC_PORT_BLK_THD
Type
Reset 0 0 0 0 0
RW
e l0
e a 1 0 0 0
Bit(s) Name
i a l R Description
25:16 FC_PORT_BLK_HI_THD
e n t i
Number of port block high threshold (unit: 2 blocks) associated with
packet discard mechanism
d
9:0 FC_PORT_BLK_THD Per port memory buffer (in unit of 2 blocks) associated with flow
o n f i n a P control and packet discard mechanism. (not include reserve block)
k C a n a
e B
00001FE8 GFCCR2 Global Flow_Control Control Register 2 04040404
d
Bit
i
Name
a T 31
F o r 30 29 28 27
FC_BLK_THD_Q3
26 25 24 23 22 21 20 19
FC_BLK_THD_Q2
18 17 16
M e Type
Reset
Bit
Name
15 14
0
13
0
12
0
11
RW
FC_BLK_THD_Q1
1
10
0
9
0
8 7 6
0
5
0
4
0
3
RW
FC_BLK_THD_Q0
1
2
0
1
0
0
Type RW RW
o r
ef
Reset 0 0 0 1 0 0 0 0 0 1 0 0
a s
ele
29:24 FC_BLK_THD_Q3 TX Queue 3 block threshold for flow control
R
l
5:0 FC_BLK_THD_Q0
n t i a TX Queue 0 block threshold for flow control
00001FEC
f i d
GFCCR3 e a P i Global Flow_Control Control Register 3 04040404
Bit
Name
31
C o n 30
n a n
29 28 27
FC_BLK_THD_Q7
26 25 24 23 22 21 20 19
FC_BLK_THD_Q6
18 17 16
T e k r B a
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
n t i a
e
Type RW RW
Reset
Bit 15
n
14
f i d 0
13
a P i
0
12
0
11
1
10
0
9
0
8 7 6
0
5
0
4
0
3
1
2
0
1
0
0
Name
C o n a n FC_BLK_THD_Q5 FC_BLK_THD_Q4
a
Type
k
RW RW
Reset
i a T e o r B 0 0 0 1 0 0 0 0 0 1 0 0
Me d
Bit(s)
29:24
21:16
13:8
Name
F
FC_BLK_THD_Q7
FC_BLK_THD_Q6
FC_BLK_THD_Q5
Description
TX Queue 7 block threshold for flow control
f o r
se
00001FF0 GFCCR4 Global Flow_Control Control Register 4 0000000C
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
R e l e
Reset
Bit 15 14 13
t i a l12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i d e n P i
FC_QUE_BLK_HI_THD
RW
Reset
o n f a n a 0 0 0 0 0 0 1 1 0 0
Bit(s)
9:0
e k
Name
C B a n
FC_QUE_BLK_HI_THD
Description
Number of queue block high threshold (unit: 2 blocks) associated with
d i a T F o r packet discard mechanism
Me 00001FF4
Bit
Name
FC_RSV
31
FCBRCR0
30 29 28 27 26
Flow Control Block Reservation Control Register
25 24 23 22 21 20
FC_RSV_PMAP
19 18
00000000
17 16
r
_EN
Type
Reset
RW
0 0 0 0 0
RW
0 0
ef
0
o 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
a s 3 2 1 0
ele
Name FC_RSV_BLK_NUM FC_RSV_QMAP
Type RW RW
Reset
i a l R 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
d
31 FC_RSV_EN 0: Disable
23:16
o n f i
FC_RSV_PMAP
n a P 1: Enable queue block reservation

When FC_RSV_EN=1,
k C a n a Port map for queue block reservation

Note: assume 8 port
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
11:8 FC_RSV_BLK_NUM
f i d e a P i When FC_RSV_EN=1,
Block size for queue block reservation
7:0
C o n
FC_RSV_QMAP
n a n
Unit: 1 block
When FC_RSV_EN=1,
a
Queue map for queue block reservation
T e k r B
Unit: 1 block
d i a F o
Me
00001FFC GIRLCR Global Ingress Rate Limit Control Register 00110118
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name IGC_FC_OFF_THD IGC_FC_DROP_THD
Type RW RW
Reset
Bit 15 14 13 12 11 10 9 8
0
7
0
6
0
5
1
4
0
3
0
2
f o r 0
1
1
0
se
IGC_M
IGC_IP
a
Name FRM_E IGC_IPG_BYTE
G_OP
Type
R e l e X
RW RW RW
l
Reset 0 1 0 0 0 1 1 0 0 0
Bit(s) Name
n t i a Description
23:20 IGC_FC_OFF_THD
f i d e a P i
Ingress Rate Limit Pause-Off Threshold
Pause-off frame is sent when the ingress token bucket is higher than
19:16
C o n
IGC_FC_DROP_THD
n a n
pause-off threshold.
Threshold = max_bucket_size >> igc_fc_off_thd
Ingress Rate Limit Drop Threshold
T e k r B a If Port Flow Control and rate limit control is enabled, frame is drop when
the ingress token bucket is less than drop threshold.
a o
Threshold = -(max_bucket_size >> igc_fc_drop_thd)
d
9
i F
IGC_MFRM_EX Ingress Rate Excludes Management Frames
Me
Management frames will be ignored by rate limit.
(management frame type is set by ARL registers)
0: Include management frames
1: Exclude management frames
8 IGC_IPG_OP Ingress Rate IPG Byte Addition or Subtraction Byte count should be
added or subtracted on the rate calculation.
o r
ef
0: IPG byte is excluded
1: IPG byte is included
7:0 IGC_IPG_BYTE Ingress Rate IPG Byte Count
a s
ele
Byte count should be added while calculating the rate limit
8'h4: add 4 byte CRC (byte rate calculation)
8'h18: add 4 byte CRC + 8 byte Preamble + 12 byte IPG (line rate
i a l R calculation)
e n t i
n f i d n a P
k C o a n a
i a T e o r B
M e d F
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l R e Media Access Controller

Confidential A
n t i a
5
f i d e
Media Access Controller (MAC)
a P i
C o n
Introduction
n a n
a
5.1
T e k r B
The Ethernet MAC provides a solution for Ethernet applications operating at 10/100 Mbps using MII
i a F o
and 1000 Mbps using GMII interface, and it also support RGMII/revMII/SGMII in MT7531 port5. In
d
Me
addition to MAC layer function, it can also T/Rx some control frame to perform other network function,
such as flow control, PFC, EEE, loop detection. Currently, WOL is not supported on 7531BE.
5.2 Features
f o r
5.2.1 MAC Layer function
It supports MAC layer functions in IEEE 802.3

l e a se
 Support 10/100/1000 Mbps bit rates
l R e


n t i a
Support Half/Full duplex (1000Mbps Half Duplex Mode is not support)
Automatic 32-bit CRC generation and checking

f i d e a P i
Report packet status (good, CRC error, alignment, oversize, undersize, other MIBs information)

protocol)
C o n n a n
Support collision detection and auto retransmission on collisions in half duplex mode (CSMA/CD
e k B a
PHY auto-polling, containing link status, speed mode, duplex mode, T/RX flow control ability,
T
EEE ability
r

d i a F o
Support packet length up to 15K for jumbo frames application
Me 5.2.2 Interface translation

MT7531 supports GMII or MII in each MAC, and additionally supports RGMII/revMII/SGMII in port 5,
o r
ef
users can select appropriate interface to fit their application.
5.2.3 Inter-Frame Gap Shrink
a s
To resolve different frequency issue between two devices, user can enable inter-frame gap shrinkage
R
function to shorten inter-frame gap from 96bits to 64bits. Besides, user can also select inter-frame
l ele
i a
gap random shrink, which will randomly shorten inter-frame gap to 64bits.
n t
5.2.4
f i d e
Flow Control
a P i
C o n
It support IEEE 802.3x flow control and automatic generation of control frames in full duplex mode.
n a n
When flow-control is enabled and in full-duplex mode, if buffer space in MT7531 is lower than a
k a
programmable pause-on threshold, MAC will generate pause-on packet to stop link partner from
i a T e o r B
M e d F
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Confidential A
n t i a
sending packet. If buffer space is released and higher than another programmable pause-off
f i d e a P i
threshold, MAC will send pause-off packet to tell link partner to start sending packet. The flow control
mechanism can prevent packet drop due to buffer space empty.
5.2.5
C o n n a n
Energy Efficient Ethernet (EEE)
T e k B a
MT7531 MAC supports IEEE 802.3az Energy Efficient Ethernet (EEE) capability for full duplex mode,
r
i a o
containing 100Base/1000Base EEE. User can enable EEE function for saving power. For example, if
d F
EEE function is enabled and there is no data to transmit for a while, MAC will send sleep signal to link
Me partner and stop MAC clock for saving power, besides, MAC will periodically send refresh signal to
maintain link status between devices. On the other hand, MAC can also detect EEE signal sent from
remote link, and decide to enter or leave low power idle mode for saving power.
5.2.6 Priority Flow Control (PFC)
f o r
It support sending & receiving PFC (priority flow control) packet. If PFC function is enabled, SCH in
a
MT7531 can pause input packet by priority instead of by input port. And if link partner support PFC, it
l e se
e
can pause output packet by priority instead of by output port. MAC in MT7531 can generate PFC
a R
packet if SCH request and can parse PFC packet from link partner. User can use PFC function to
l
pause some flow without stopping all packet from link partner.
i
e t
Besides, MT7531 support PFC auto-sync function, which can sync PFC ability automatically between
n
different devices. If PFC auto-sync function is enabled, devices will automatically send PFC packet
i
f i d P
when linked-up, and will automatically enable PFC function if receiving any PFC packet from link
partner.
n n a
5.2.7
k C o a
Loop detection
n a
T e r B
MT7531 MAC support loop detection function, it can detect the loop in the network without running
i a o
Me d F
STP, which needs at least a processor with external memory.
If loop detection function is enabled, MAC will broadcast loop detection frames to each port when
broadcast storm happens. If any port receives loop-detection frame just sent, it will detect loop
condition occurrence at the port.
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
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Confidential A
5.3
n t
Register Definition i a
f i d e a P i
5.3.1
C o n
MAC Register
n a n
Module name: MAC Base address: (+0x0000)
T e
Address
a
00003000 PMCR_P0 32 PORT 0 MAC Control Register
d i
00003004
F o PMEEECR_P0 32 PORT 0 MAC EEE Control Register
Me
00003008 PMSR_P0 32 PORT 0 MAC Status Register
00003010 PINT_EN_P0 32 PORT 0 Interrupt Enable Register
00003014 PINT_STS_P0 32 PORT 0 Interrupt Status Register
00003018 P0_DBG_CNT 32 PORT 0 DEBUG COUNT
00003020 P0_WOL 32 PORT 0 WOL
00003024
00003030
P0_PFC_STS
P0_PFC_RX_PSON_CNT_L
32
32
PORT 0 PFC STATUS
Port 0 RX PFC pause on counter for low priority
f o r
se
00003034 P0_PFC_RX_PSON_CNT_H 32 Port 0 RX PFC pause on counter for high priority
00003038
0000303C
P0_PFC_RX_PSOFF_CNT_L
P0_PFC_RX_PSOFF_CNT_H
e l e a 32
32
Port 0 RX PFC pause off counter for low priority
Port 0 RX PFC pause off counter for high priority
R
00003040 P0_PFC_TX_PSON_CNT_L 32 Port 0 TX PFC pause on counter for low priority
00003044
00003048
t i a l
P0_PFC_TX_PSON_CNT_H
P0_PFC_TX_PSOFF_CNT_L
32
32
Port 0 TX PFC pause on counter for high priority
Port 0 TX PFC pause off counter for low priority
0000304C
000030B0
i d
PFC_CTRL
e n
P0_PFC_TX_PSOFF_CNT_H
P i
32
32
Port 0 TX PFC pause off counter for high priority
PFC CONTROL REGISTER
000030B4
000030B8
o n f
PFC_AUTO_SYNC_DLY_SEL
n a
SGMII_2P5G_SPD_CTRL
a
32
32
PFC AUTO SYNC DELAY SELECION
SGMII SPEED STATUS CONTROL REGISTER
C
000030C0 LPDET_CTRL 32 LOOP DETECTION CONTROL REGISTER
000030C8
e
000030CC
k B a n
LPDET_SA_MSB
LPDET_SA_LSB
32
32
LOOP DETECTION SA MSB
LOOP DETECTION SA LSB
d i a T
000030D0
000030E0
F o r
LPDET_RXSA_MSB
GMACCR
32
32
LOOP DETECTION RX SA MSB
Global MAC Control Register
Me
000030E4 SMACCR0 32 System MAC Control Register 0
000030E8 SMACCR1 32 System MAC Control Register 1
000030F0 CKGCR 32 Clock Gating Control Register
000030F4 GPINT_EN 32 Global Port Interrupt Enable Register
r
000030F8 GPINT_STS 32 Global Port Interrupt Status Register
00003100
00003104
PMCR_P1
PMEEECR_P1
32
32
PORT 1 MAC Control Register
PORT 1 MAC EEE Control Register
ef o
a s
ele
00003118
00003120
P1_DBG_CNT
P1_WOL
i a l R 32
32
PORT 1 DEBUG COUNT
PORT 1 WOL
t
00003124 P1_PFC_STS 32 PORT 1 PFC STATUS
00003130
00003134
i d e n
i
P1_PFC_RX_PSON_CNT_H
P
32
32
Port 1 RX PFC pause on counter for high priority
00003138
0000313C
o n f n a
a
32
32
00003140
e k
00003144
C n
P1_PFC_TX_PSON_CNT_L
a
B
32
32
Port 1 TX PFC pause on counter for low priority
d i a T F o r

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Confidential A
n t i a
e
00003148 P1_PFC_TX_PSOFF_CNT_L 32 Port 1 TX PFC pause off counter for low priority
0000314C
00003200
f i d
PMCR_P2
n a P i
P1_PFC_TX_PSOFF_CNT_H 32
32
00003204
00003208
C o
PMEEECR_P2
PMSR_P2
n a n 32
32
PORT 2 MAC Status Register
00003210
T e
00003214
k r B a
PINT_EN_P2
PINT_STS_P2
32
32
PORT 2 Interrupt Enable Register
PORT 2 Interrupt Status Register
d i a
00003218
00003220
F o P2_DBG_CNT
P2_WOL
32
32
PORT 2 DEBUG COUNT
PORT 2 WOL
Me
00003224 P2_PFC_STS 32 PORT 2 PFC STATUS
00003230 P2_PFC_RX_PSON_CNT_L 32 Port 2 RX PFC pause on counter for low priority
00003238 P2_PFC_RX_PSOFF_CNT_L 32 Port 2 RX PFC pause off counter for low priority
0000323C
00003240
32
32
f o r
se
00003244 P2_PFC_TX_PSON_CNT_H 32 Port 2 TX PFC pause on counter for high priority
a
0000324C
00003300
00003304
PMCR_P3
PMEEECR_P3
R e l e 32
32
32
00003308
00003310
PMSR_P3
PINT_EN_P3
t i a l 32
32
00003314
00003318
i d e
P3_DBG_CNT
n
PINT_STS_P3
P i
32
32
PORT 3 DEBUG COUNT
00003320
00003324
o n f
P3_WOL
P3_PFC_STS
a n a 32
32
PORT 3 WOL
PORT 3 PFC STATUS
00003330
e
00003334
k C B n
a
32
32
d i a T
00003338
0000333C
F o r
32
32
Me
00003340 P3_PFC_TX_PSON_CNT_L 32 Port 3 TX PFC pause on counter for low priority
0000334C P3_PFC_TX_PSOFF_CNT_H 32 Port 3 TX PFC pause off counter for high priority
00003400 PMCR_P4 32 PORT 4 MAC Control Register
00003404 PMEEECR_P4 32 PORT 4 MAC EEE Control Register
o r
ef
a s
ele
00003418 P4_DBG_CNT 32 PORT 4 DEBUG COUNT
00003420 P4_WOL 32 PORT 4 WOL
00003424
00003430
P4_PFC_STS
i a l R
32
32
PORT 4 PFC STATUS
00003434
00003438
e n t
i
32
32
0000343C
00003440
n f i d a P
n
32
32
00003444
00003448
k C o a n a
32
32
i a T e o r B
M e d F
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e
00003500
00003504
f i d
PMCR_P5
PMEEECR_P5
n a P i 32
32
00003508
00003510
C o
PMSR_P5
n
PINT_EN_P5
a n 32
32
00003514
T e
00003518
k r B a
PINT_STS_P5
P5_DBG_CNT
32
32
PORT 5 DEBUG COUNT
d i a
00003520
00003524
F o P5_WOL
P5_PFC_STS
32
32
PORT 5 WOL
PORT 5 PFC STATUS
Me
00003530 P5_PFC_RX_PSON_CNT_L 32 Port 5 RX PFC pause on counter for low priority
00003538 P5_PFC_RX_PSOFF_CNT_L 32 Port 5 RX PFC pause off counter for low priority
0000353C P5_PFC_RX_PSOFF_CNT_H 32 Port 5 RX PFC pause off counter for high priority
00003540
00003544
32
32
f o r
se
a
00003600
00003604
00003608
PMCR_P6
PMEEECR_P6
PMSR_P6
R e l e 32
32
32
00003610
00003614
PINT_EN_P6
PINT_STS_P6
t i a l 32
32
00003618
00003620
i
P6_WOL
d e
P6_DBG_CNT
n P i
32
32
PORT 6 DEBUG COUNT
PORT 6 WOL
00003624
00003630
o n f
P6_PFC_STS
a n a
32
32
PORT 6 PFC STATUS
00003634
e
00003638
k C B n
a
32
32
d i a T
0000363C
00003640
F o r
32
32
Me
o r
a s ef
l R ele
00003000 PMCR_P0
n t i a PORT 0 MAC Control Register 00056330

Bit 31 30
f i d e 29
P i
28
FORCE FORCE FORCE FORCE FORCE FORCE FORCE
a
27 26 25 24 23 22 21 20 19 18 17 16
n
MAC_
n
_MOD _MODE _MODE _MODE _MODE _MODE _MODE EXT_PH
o
Name IPG_CFG_P0 MODE
a
E_LNK_ _SPD_P _DPX_ _RX_FC _TX_FC _EEE10 _EEE1G Y_P0
C
_P0
Type
P0
e k
RW
0
RW
B
P0
a n _P0
RW
_P0
RW
0_P0
RW
_P0
RW RW RW RW RW
d i a T F o r

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MT7531

Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 1 0 1
Bit 15 14
n f i d
MAC_T MAC_R
13
a P i
12 11 10 9 8 7 6
BACKP FORCE FORCE FORCE FORCE
5 4 3
FORCE FORCE
2 1 0
n
MAC_P BKOFF_
o
Name X_EN_ X_EN_ R_EN_ _EEE1G _EEE10 _RX_FC _TX_FC FORCE_SPD_P0 _DPX_ _LNK_
a
RE_P0 EN_P0
C n
P0 P0 P0 _P0 0_P0 _P0 _P0 P0 P0
Type
Reset
T e k
RW
1
r B a RW
1
RW
0
RW
1
RW
1
RW
0
RW
0
RW
1
RW
1 0
RW
0
RW
0
RW
0
d i a F o
Me Bit(s)
31
Name
FORCE_MODE_LNK_P0
Description
PORT 0 link status force Mode.
0: Force mode is off.(Mac link status is determined by phy auto-polling
module)
1: Force mode is on. (Mac link status is determined by force_link_P0
f o r
se
register)
30 FORCE_MODE_SPD_P0 PORT 0 speed force Mode.
e l e a 0: Force mode is off.(Mac speed is determined by phy auto-polling

module)
1: Force mode is on. (Mac speed is determined by force_spd_P0 register)
29 FORCE_MODE_DPX_P0
i a l R PORT 0 duplex force Mode.

0: Force mode is off.(Mac duplex mode is determined by phy auto-polling
e n t i
module)
1: Force mode is on. (Mac duplex mode is determined by force_dpx_P0
d
register)
28
o n f i
FORCE_MODE_RX_FC_P0
n a P PORT 0 RX FC force Mode.

0: Force mode is off.(Mac RX FC ability is determined by phy auto-polling
k C a n a module)
1: Force mode is on. (Mac RX FC ability is determined by force_rx_fc_P0
e
register)
27
i a T o r B
FORCE_MODE_TX_FC_P0 PORT 0 TX FC force Mode.
0: Force mode is off.(Mac TX FC ability is determined by phy auto-polling
Me d
26
F
FORCE_MODE_EEE100_P0
module)
1: Force mode is on. (Mac TX FC ability is determined by force_tx_fc_P0
register)
PORT 0 100M EEE force Mode.
0: Force mode is off.(Mac 100M EEE ability is determined by phy auto-
polling module)
r
1: Force mode is on. (Mac 100M EEE ability is determined by
25 FORCE_MODE_EEE1G_P0
force_eee100_P0 register)
PORT 0 1G EEE force Mode.
ef o
s
0: Force mode is off.(Mac 1G EEE ability is determined by phy auto-
polling module)
ele a
1: Force mode is on. (Mac 1G EEE ability is determined by
force_eee1g_P0 register)
19:18 IPG_CFG_P0
i a l R PORT 0 Inter-Frame+ Gap Shrink

00: Normal 96-bits IFG
t
01: Transmit 96-bits IFG with short IFG in random behavior
17 EXT_PHY_P0
i d e n P i
10: Shrink 64-bits IFG
PORT 0 External PHY. Port 0 connects with external PHY.
o n f a n a
0: PORT 0 DOES NOT connect with external PHY
1: PORT 0 connects with external PHY
C
16 MAC_MODE_P0 PORT 0 MAC Mode. PORT 0 operates in MAC mode
e k B a n 0: PORT 0 operates in PHY mode.
d i a T F o r

f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
14
f
MAC_TX_EN_P0
i d e a P i 1: PORT 0 operates in MAC mode.
Port 0 TX MAC Enable (Note: This bit only has impact on MAC function,
C o n n a n and it has no impact on the link status or Queue manager.)

0: TX MAC function is disabled
k a
1: TX MAC function is enabled
13
i a T e o r B
MAC_RX_EN_P0 PORT 0 RX MAC Enable. (Note: This bit only has impact on MAC
function, it has no impact on the link status or Queue manager.)
0: RX MAC function is disabled
Me d
11
F
MAC_PRE_P0
1: RX MAC function is enabled
TX short preamble mode
0: TX short preamble length is disabled
1: TX short preamble is enabled.
9 BKOFF_EN_P0 PORT 0 Backoff Enable
r
0: Disabled
1: Let the MAC of PORT 0 follow the back-off mechanism when collision
happens.
f o
se
8 BACKPR_EN_P0 PORT 0 Backpressure Enable
e l e a 0: Disabled
1: Enable back pressure mechanism when operating in half-duplex mode
with low internal free memory page count.
7 FORCE_EEE1G_P0
i a l R PORT 0 Force LPI Mode For 1000Mbps. When (force_mode_P0 = 1), this
bit is used to control the 1000Base-T EEE ability of PORT 0.
t
0: Do not have the ability of entering EEE Low Power Idle mode for
i d e n P i
1000Mbps.
1: Have the ability of entering EEE Low Power Idle mode for 1000Mbps.
f
6 FORCE_EEE100_P0 PORT 0 Force LPI Mode For 100Mbps. When (force_mode_P0 = 1), this
C o n a n a bit is used to control the 100Base-TX EEE ability of PORT 0.

e k B a n 100Mbps.
T r
5 FORCE_RX_FC_P0 PORT 0 Force RX FC. When (force_mode_P0 = 1), this bit is used to
d i a F o
control the RX FC ability of PORT 0.
0: Disabled
Me
1: Let the MAC of PORT 0 accept a pause frame when operating in full-
duplex mode.
4 FORCE_TX_FC_P0 PORT 0 Force TX FC. When (force_mode_P0 = 1), this bit is used to
control the TX FC ability of PORT 0.
0: Disabled
1: Let the MAC of PORT 0 transmit a pause frame when operating in full-
o r
ef
duplex mode with low internal free memory page count.
3:2 FORCE_SPD_P0 PORT 0 Force Speed [1:0]. When (force_mode_P0 = 1), these bits are
used to control MAC speed of PORT 0.
00: 10Mbps
a s
ele
01: 100Mbps
R
10: 1000Mbps
l
11: Reserved
1 FORCE_DPX_P0
n t i a PORT 0 Force duplex. When (force_mode_P0 = 1), this bit is used to

control MAC duplex of PORT 0.
e
0: Half Duplex
n f i
FORCE_LNK_P0
d a P i 1: Full Duplex
PORT 0 Force MAC Link Up. When (force_mode_P0 = 1), this bit is used
C o n a n to control link status of PORT 0.

0: Link Down
T e k r B a 1: Link Up
e d i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00003004
T e k B a
PMEEECR_P0
r
PORT 0 MAC EEE Control Register 111E01E0
a o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d
Name
i F WAKEUP_TIME_1000_P0 WAKEUP_TIME_100_P0
Me
Type RW RW
Reset 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPI_M
Name
r
LPI_THRESH_P0 ODE_E
o
N_P0
Type
Reset 0 0 0 0 0 0
RW
0 1 1 1 1 0
se f RW
0
e l e a
Bit(s) Name
i a l R Description
31:24 WAKEUP_TIME_1000_P0
e n t i
PORT 0 Wake Up Time for 1000Mbps LPI Mode.
n f i d n a P
The minimum allowed time needed to wait for PHY to be fully functional,
and TXMAC can transmit packet after wakeup.
23:16
k C o a n
WAKEUP_TIME_100_P0
a Time unit: 1 micro second
PORT 0 Wake Up Time for 100Mbps LPI Mode.
i a T e o r B The minimum allowed time needed to wait for PHY to be fully functional,
Me d
15:4
F
LPI_THRESH_P0
Time unit: 1 micro second

PORT 0 LPI Threshold.
When there is no packet to be transmitted, and the idle time is greater

than P0_LPI_THRESHOLD, the TXMAC will automatically enter LPI (Low
o r
ef
Power Idle) mode and send EEE LPI frame to the link partner.
0 LPI_MODE_EN_P0 PORT 0 Enter LPI Mode.
a s
ele
R
t i a l 0: LPI mode depends on the P0_LPI_THRESHOLD.

1: Let the system enter LPI mode immediately and send EEE LPI frame to
n
the link partner.
f i d e a P i
C o n n a n
00003008
T e k r B a
PMSR_P0 PORT 0 MAC Status Register 00000000
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
Type
n f i d a P i
Reset
C o n a n
a
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
k
Bit
e B
EEE100 MAC_D MAC_L
T
EEE1G_ RX_FC_ TX_FC_ MAC_SPD_STS
r
Name _STS_P PX_STS NK_ST
a o
STS_P0 STS_P0 STS_P0 _P0
i
0 _P0 S_P0
Me d
Type
Reset F RO
0
RO
0
RO
0
RO
0 0
RO
0
RO
0
RO
0
Bit(s)
7
Name
EEE1G_STS_P0
Description
PORT 0 LPI Mode Status For 1000Mbps
f o r
se
0: Not capable of entering EEE Low Power Idle mode for 1000Mbps.
6 EEE100_STS_P0
e l e a 1: Capable of entering EEE Low Power Idle mode for 1000Mbps.

PORT 0 LPI Status Mode For 100Mbps
5 RX_FC_STS_P0
i a l R 1: Capable of entering EEE Low Power Idle mode for 100Mbps.

PORT 0 RX XFC Status. Port 0 Rx flow control status.
e n t i
0: Disabled
f
TX_FC_STS_P0
n i d n a P
duplex mode.
PORT 0 TX XFC Status. PORT 0 TX flow control status.
o
0: Disabled
k C a n a 1: Let the MAC of PORT 0 transmit a pause frame when operating in full-
3:2
i a T e o r B
MAC_SPD_STS_P0 PORT 0 Speed [1:0] Status. Current speed of PORT 0 after PHY links up.
00: 10 Mbps
F
01: 100 Mbps
Me d1 MAC_DPX_STS_P0
10: 1000 Mbps
11: Reserved
PORT 0 duplex Status. Current duplex mode of PORT 0 after PHY links
up.
0: Half Duplex
r
1: Full Duplex
0 MAC_LNK_STS_P0 Port 6 Link Up Status. Link up status of PORT 0.
0: Link Down
ef o
s
1: Link Up
ele a
i a l R
00003010
Bit 31
PINT_EN_P0
30
e n t
29
i
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
n f i d n a P
o
Type
Reset
Bit
k C
15 14
a n a13 12 11 10 9 8 7 6 5 4 3 2 1 0
i a T e o r B
M e d F
Page 414 of 830
f o r
l e a se
MT7531

Confidential A
n t
TX_TFF TX_MIS TX_MIS TX_RP
i a TX_RP TX_GP TX_RD TX_DE RX_AR RX_WR RX_GP
Name
f d e
_UNDR VLAN_ PAGE_ AGE_E
i
_INT_E ERR_IN ERR_IN RR_INT
a P i AGE_T
OUT_I
AGE_T PB_TO Q_TOU
OUT_I UT_INT T_INT_
RX_AFF
_FULL_
L_TOU PB_TO AGE_T
T_INT_ UT_INT OUT_I
n
INT_EN
n
N T_EN T_EN _EN NT_EN NT_EN _EN EN EN _EN NT_EN
Type
Reset
RW
0
k C o
RW
0
a
RW
n0
a RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
i a T e o r B
Me d
Bit(s)
15
Name
F
TX_TFF_UNDR_INT_EN
Description
TXMAC TXFIFO Under run Interrupt Enable
0: Disabled
1: Enabled
r
14 TX_MISVLAN_ERR_INT_EN TX_CTRL PKT INFO VLAN Mismatch Error Interrupt Enable
0: Disabled
1: Enabled
f o
se
13 TX_MISPAGE_ERR_INT_EN TX_CTRL PKT INFO Page Mismatch Error Interrupt Enable
12 TX_RPAGE_ERR_INT_EN
e l e a 0: Disabled
1: Enabled
TX_CTRL Release Page Count Error Interrupt Enable
i a l R 0: Disabled
1: Enabled
11 TX_RPAGE_TOUT_INT_EN
e n t i
TX_CTRL Release Page Timeout Interrupt Enable
0: Disabled
10
n f i d
TX_GPAGE_TOUT_INT_EN
n a P
1: Enabled
TX_CTRL Get Page Timeout Interrupt Enable
o
0: Disabled
k C a n a
TX_RDPB_TOUT_INT_EN
1: Enabled
TX_CTRL RD_PB Timeout Interrupt Enable
i a T e o r B 0: Disabled
1: Enabled
Me d
8
3
F
TX_DEQ_TOUT_INT_EN
RX_AFF_FULL_INT_EN
TX_CTRL DEQ Timeout Interrupt Enable
0: Disabled
1: Enabled
RX_CTRL Agent FIFO Full Interrupt Enable
0: Disabled
1: Enabled
2 RX_ARL_TOUT_INT_EN RX_CTRL ARL Timeout Interrupt Enable
o r
ef
0: Disabled
1: Enabled
1 RX_WRPB_TOUT_INT_EN RX_CTRL WR_PB Timeout Interrupt Enable
a s
ele
0: Disabled
1: Enabled
R
0 RX_GPAGE_TOUT_INT_EN RX_CTRL Get Page Timeout Interrupt Enable
t i a l 0: Disabled
1: Enabled
i d e n P i
o n f a n a
00003014
e k C B a n
PINT_STS_P0 PORT 0 Interrupt Status Register 00000000
d i a T F o r

f o r
l e a se MT7531

Confidential A
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
Type
n f i d a P i
Reset
C o n a n
a
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
k
Bit
e B
TX_MIS TX_MIS TX_RP TX_GP RX_GP
T
TX_TFF TX_RP TX_RD TX_DE RX_AFF RX_AR RX_WR
r
VLAN_ PAGE_ AGE_T AGE_T AGE_T
a o
Name _UNDR AGE_E PB_TO Q_TOU _FULL_ L_TOU PB_TO
i
ERR_IN ERR_IN OUT_I OUT_I OUT_I
F
_INT RR_INT UT_INT T_INT INT T_INT UT_INT
Me d
Type
Reset
RC
0
T
RC
0
T
RC
0
NT
RC
0
NT
RC
0
RC
0
RC
0
RC
0
RC
0
RC
0
RC
0
NT
RC
0
f o r
se
15 TX_TFF_UNDR_INT TXMAC TXFIFO Under run Interrupt
14 TX_MISVLAN_ERR_INT
e l e a 0: False
1: True
TX_CTRL PKT INFO VLAN Mismatch Error Interrupt
i a l R 0: False
1: True
13 TX_MISPAGE_ERR_INT
e n t i
TX_CTRL PKT INFO Page Mismatch Error Interrupt
0: False
12
f i d
TX_RPAGE_ERR_INT
n n a P
1: True
TX_CTRL Release Page Count Error Interrupt
o
0: False
11
k C a n
TX_RPAGE_TOUT_INT
a 1: True
TX_CTRL Release Page Timeout Interrupt
i a T e o r B 0: False
1: True
d F
10 TX_GPAGE_TOUT_INT TX_CTRL Get Page Timeout Interrupt
Me
0: False
1: True
9 TX_RDPB_TOUT_INT TX_CTRL RD_PB Timeout Interrupt
0: False
1: True
8 TX_DEQ_TOUT_INT TX_CTRL DEQ Timeout Interrupt
o r
ef
0: False
1: True
3 RX_AFF_FULL_INT RX_CTRL Agent FIFO Full Interrupt
a s
ele
0: False
1: True
R
2 RX_ARL_TOUT_INT RX_CTRL ARL Timeout Interrupt
t i a l 0: False
1: True
n
1 RX_WRPB_TOUT_INT RX_CTRL WR_PB Timeout Interrupt
f i d e a P i
0: False
1: True
n
0 RX_GPAGE_TOUT_INT RX_CTRL Get Page Timeout Interrupt
C o n a n 0: False
1: True
T e k r B a
e d i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00003018
T e k B a
P0_DBG_CNT
r
PORT 0 DEBUG COUNT 00000000
a o
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
d
Name
i F
Me
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_FIFO_URUN RX_FIFO_OV
Type
Reset 0 0
RO
0 0 0
f o r
RO
0 0
l e a se
Bit(s) Name
l R e Description
a
7:4 TX_FIFO_URUN Underrun count of TX fifo. The field is increased when TX fifo underrun
2:0 RX_FIFO_OV
e n t i occurs.
Overflow count of RX fifo. The field is increased when RX fifo overflow
n f i d a P i occurs.
C o n a n
00003020
T e k r B
P0_WOL a PORT 0 WOL 00000000
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
WOL_I WOL_S
Name WOL_DBG
NT_STS TS
Type RO W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
o r
SNP_P CRC_DI WOL_I WOL_E
ef
KT S NT_EN N
Type RW RW RW RW
Reset
a s 0 0 0 0
l R ele
Bit(s)
31:18
Name
WOL_DBG
n t i a Description
Port0 Wake-up On Lan Debug Signals
17
16
WOL_INT_STS
WOL_STS
f i d e a P i
Port0 Wake-up On Lan Interrupt Status
Port0 Wake-up On Lan Status
C o n n a n If enable WOL_EN, this bit will change from 0 to 1 when GMAC RX state
machine enter IDLE state. It indicates GMAC will drop all packets and
T e k r B a detect magic packet.
e d i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
3 SNP_PKT
f i d e a P i Port0 Wake-up On Lan with snoopy packet

0: Disable
C o
CRC_DIS
n n a n 1: Enable
Port0 Wake-up On Lan with CRC Check Disable
k a
0: CRC check enable
i a T e r
WOL_INT_EN
o B 1: CRC check disable

Port0 Wake-up On Lan Interrupt Enable
F
0: Disable
Me d0 WOL_EN
1: Enable
Port0 Wake-up On Lan Function Enable
0: Disable
1: Enable
f o r
00003024 P0_PFC_STS PORT 0 PFC STATUS
l e a se 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
i a l R
Reset
Bit 15 14
e n t 13
i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
n f i d n a P TX_PFC_STS
RO
RX_PFC_STS
RO
Reset
k
0
C o 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a T e o r B
M e dBit(s)
15:8
7:0 F
Name
TX_PFC_STS
RX_PFC_STS
Description
Port0 PFC TX pause on status of 8 priorities 1: pause on 0: pause off
Port0 PFC RX pause on status of 8 priorities 1: pause on 0: pause off
o r
00003030
Bit 31
30 29 28 27 26
25 24 23 22 21 20
a s 19 18
ef00000000
17 16
ele
Name Q3_RX_PSON_CNT Q2_RX_PSON_CNT
R
Type RC RC
Reset
Bit
0
15
0
14
t i
0
13
a l 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
i d e n P
Q1_RX_PSON_CNT
i RC
Q0_RX_PSON_CNT
RC
Reset 0
o n f 0
a n
0
a
0 0 0 0 0 0 0 0 0 0 0 0 0
e k C B a n
d i a T F o r

f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
31:24
23:16
Q3_RX_PSON_CNT
f i
Q2_RX_PSON_CNT
d e a P i PFC RX pause on count for port0 priority 3
PFC RX pause on count for port0 priority 2
15:8
7:0
C n
Q1_RX_PSON_CNT
o
Q0_RX_PSON_CNT
n a n
T e k r B a
d i a F o
Me
00003034 P0_PFC_RX_PSON_CNT_H Port 0 RX PFC pause on counter for high priority 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RC RC
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
f o
0
1
r 0
0
se
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
e l0
e aRC
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
d
31:24 Q7_RX_PSON_CNT PFC RX pause on count for port0 priority 7
23:16
15:8
n f i
Q6_RX_PSON_CNT
Q5_RX_PSON_CNT
o n a P PFC RX pause on count for port0 priority 6

7:0
k C
Q4_RX_PSON_CNT
a n a PFC RX pause on count for port0 priority 4
i a T e o r B
M e d
00003038
Bit
Name
F
31
30 29 28
Q3_RX_PSOFF_CNT
27 26
25 24 23 22 21 20
Q2_RX_PSOFF_CNT
19 18
00000000
17 16
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Name Q1_RX_PSOFF_CNT Q0_RX_PSOFF_CNT
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
ele
0
a RC
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
d
31:24 Q3_RX_PSOFF_CNT PFC RX pause off count for port0 priority 3
23:16
15:8
n f i
Q2_RX_PSOFF_CNT
Q1_RX_PSOFF_CNT
o n a P PFC RX pause off count for port0 priority 2

PFC RX pause off count for port0 priority 1
7:0
k C
Q0_RX_PSOFF_CNT
a n a PFC RX pause off count for port0 priority 0
i a T e o r B
M e d F
Page 419 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
0000303C P0_PFC_RX_PSOFF_CNT_H Port 0 RX PFC pause off counter for high priority 00000000
Bit
Name
31
C o30
n a
29
n 28
Q7_RX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q6_RX_PSOFF_CNT
19 18 17 16
Type
Reset
T e0
k 0
r B a 0 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
d i a 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
23:16
15:8
7:0
Q6_RX_PSOFF_CNT
Q5_RX_PSOFF_CNT
Q4_RX_PSOFF_CNT
e l e a PFC RX pause off count for port0 priority 6

i a l R
e n t i
00003040
n f i d a
n P Port 0 TX PFC pause on counter for low priority 00000000

Bit
Name
31
k C o30
a n a
29 28
Q3_TX_PSON_CNT
27 26 25 24 23 22 21 20
Q2_TX_PSON_CNT
19 18 17 16
e B
Type RC RC
Reset
Bit
d i a T 0
15
F o
0
r
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Me
Name Q1_TX_PSON_CNT Q0_TX_PSON_CNT
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
31:24 Q3_TX_PSON_CNT PFC TX pause on count for port0 priority 3
a s
ele
i a l R
e n t i
00003044
n f i d a P
n
Port 0 TX PFC pause on counter for high priority 00000000
Bit
Name
k
31
C o 30
a n a
29 28
Q7_TX_PSON_CNT
27 26 25 24 23 22 21 20
Q6_TX_PSON_CNT
19 18 17 16
i a T e o r B
M e d F
Page 420 of 830
f o r
l e a se MT7531

Confidential A
n t i a
e
Type RC RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
C o n a n Q5_TX_PSON_CNT
RC
Q4_TX_PSON_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q7_TX_PSON_CNT
Q6_TX_PSON_CNT
Q5_TX_PSON_CNT
Description
PFC TX pause on count for port0 priority 7
f o r
l e a se
00003048 P0_PFC_TX_PSOFF_CNT_L
l R e Port 0 TX PFC pause off counter for low priority 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e n t i
Q3_TX_PSOFF_CNT
RC
Q2_TX_PSOFF_CNT
RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
C o n a n Q1_TX_PSOFF_CNT
RC
Q0_TX_PSOFF_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q3_TX_PSOFF_CNT
Q2_TX_PSOFF_CNT
Q1_TX_PSOFF_CNT
Description
PFC TX pause off count for port0 priority 3
7:0 Q0_TX_PSOFF_CNT PFC TX pause off count for port0 priority 0
o r
a s ef
0000304C
R
l
ele 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e n t i Q7_TX_PSOFF_CNT
RC
Q6_TX_PSOFF_CNT
RC
Reset
Bit
0
15
n f i
0
14
d 0
13
a P i 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q4_TX_PSOFF_CNT
RC
Reset
T e k 0
r B
0
a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ed i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
31:24
23:16
C o
Q7_TX_PSOFF_CNT
Q6_TX_PSOFF_CNT
n a n PFC TX pause off count for port0 priority 7

15:8
7:0
T k r B a
Q5_TX_PSOFF_CNT
e
Q4_TX_PSOFF_CNT
d i a F o
Me 000030B0
Bit 31
PFC_CTRL
30 29 28 27 26
PFC CONTROL REGISTER
25 24 23 22 21 20 19 18
00000000
17 16
Name
f o r
PFC_A PFC_A PFC_A PFC_A PFC_A
UTO_E UTO_E UTO_E UTO_E UTO_E
se
N6 N5 N4 N3 N2
a
Type RO RO RO RO RO
Reset
Bit 15 14 13 12
R e l e 11 10 9 8 7 6 5
0
4
0
3
0
2
0
1
0
0
l
PFC_A PFC_A PFC_SY PFC_SY PFC_SY PFC_SY PFC_SY PFC_SY PFC_SY
PFC_EN PFC_EN PFC_EN PFC_EN PFC_EN PFC_EN PFC_E
Name
i a
UTO_E UTO_E NC_EN NC_EN NC_EN NC_EN NC_EN NC_EN NC_EN
6 5 4 3 2 1 N0
Type
N1
RO
N0
RO
6
e n
RW
t5 4
RW
i
3
RW
2
RW
1 0
RW RW RW RW RW RW RW RW RW RW
Reset 0
n
0
f i d 0
n a P
0 0 0 0 0 0 0 0 0 0 0 0 0
k C o a n a
Bit(s)
20
i a T e
Name
o r B
PFC_AUTO_EN6
Description
PFC auto enable status of user port 6.
F
0: Disabled
Me d
19 PFC_AUTO_EN5
1: Enabled
0: Disabled
1: Enabled
18 PFC_AUTO_EN4 PFC auto enable status of user port 4.
r
0: Disabled
17 PFC_AUTO_EN3
1: Enabled
ef o
s
0: Disabled
16 PFC_AUTO_EN2
1: Enabled
0: Disabled
ele a
15 PFC_AUTO_EN1
i a l R 1: Enabled
e n t i
0: Disabled
1: Enabled
14
n f i
PFC_AUTO_EN0
d n a P
0: Disabled
13
C o
PFC_SYNC_EN6
k a n a
1: Enabled
Enable the PFC auto-sync ability of user port 6.
0: Disable
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
12
f
PFC_SYNC_EN5
i d e a P i 1: Enable
C o n n a n 0: Disable
1: Enable
k a
11 PFC_SYNC_EN4 Enable the PFC auto-sync ability of user port 4.
i a T e o r B 0: Disable
1: Enable
F
Me d9 PFC_SYNC_EN2
0: Disable
1: Enable
0: Disable
1: Enable
r
0: Disable
f o
se
1: Enable
e l e a 0: Disable
1: Enable
R
6 PFC_EN6 Enable the PFC ability of user port 6.
l
0: Disable
5 PFC_EN5
n t i a 1: Enable
Enable the PFC ability of user port 5.
f i d e a P i
0: Disable
1: Enable
n
1: Enable
3
T e k
PFC_EN3
r B a Enable the PFC ability of user port 3.

0: Disable
d
2
i a F o
PFC_EN2
1: Enable
Enable the PFC ability of user port 2.
Me
0: Disable
1: Enable
0: Disable
1: Enable
o r
ef
0: Disable
1: Enable
a s
l R ele
000030B4
t i a
PFC_AUTO_SYNC_DLY_SEL
n
PFC AUTO SYNC DELAY SELECION 00000000
e
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
n f i d a P i
Reset
C o n a n
k a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
i a T e o r B
M e d F
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MT7531

Confidential A
n t i a
PFC_AUTO_SY PFC_AUTO_SY PFC_AUTO_SY PFC_AUTO_SY PFC_AUTO_SY PFC_AUTO_SY PFC_AUTO_SY
Name
Type
f i d e RW
a i
NC_DLY_SEL6 NC_DLY_SEL5 NC_DLY_SEL4 NC_DLY_SEL3 NC_DLY_SEL2 NC_DLY_SEL1 NC_DLY_SEL0
P RW RW RW RW RW RW
Reset
C o n n
0
a n 0 0 0 0 0 0 0 0 0 0 0 0 0
T e k r B a
i a
Bit(s)
d
Name
F o Description
Me
13:12 PFC_AUTO_SYNC_DLY_SEL6 Select the delay of sending PFC auto sync packet of user port 6
0: Delay 0s
1: Delay 0.5s
2: Delay 1s
3: Delay 2s
0: Delay 0s
f o r
se
1: Delay 0.5s
2: Delay 1s
9:8 PFC_AUTO_SYNC_DLY_SEL4
e l e a 3: Delay 2s
Select the delay of sending PFC auto sync packet of user port 4
R
0: Delay 0s
t i a l 1: Delay 0.5s
2: Delay 1s
n
3: Delay 2s
7:6
f i d e
PFC_AUTO_SYNC_DLY_SEL3
a P i
0: Delay 0s
C o n n a n
1: Delay 0.5s
2: Delay 1s
3: Delay 2s
5:4
T e k B a
PFC_AUTO_SYNC_DLY_SEL2
r
0: Delay 0s
d i a F o 1: Delay 0.5s
2: Delay 1s
Me
3: Delay 2s
0: Delay 0s
1: Delay 0.5s
r
2: Delay 1s
1:0 PFC_AUTO_SYNC_DLY_SEL0
3: Delay 2s
ef o
s
0: Delay 0s
1: Delay 0.5s
2: Delay 1s
ele a
R
3: Delay 2s
t i a l
i d e n P i
000030B8
Bit 31
o n f
30
a n
29
a
SGMII_2P5G_SPD_CTRL
28 27 26
SGMII SPEED STATUS CONTROL REGISTER
25 24 23 22 21 20 19 18
00000000
17 16
Name
e k C B a n
d i a T F o r

f o r
l e a se MT7531

Confidential A
n t i a
e
Type
Reset
Bit 15
n
14
f i d 13
a P i
12 11 10 9 8 7 6 5 4 3 2 1 0
C o n a n P6_SG P5_SG
FORCE FORCE
FORCE FORCE
_MODE _MOD
k a
_P6_SG _P5_SG
MII_2P MII_2P _P6_SG E_P5_S
e B
Name MII_2P MII_2P
5G_SP 5G_SP MII_2P GMII_2
T r
5G_SP 5G_SP
a
D_STS D_STS 5G_SP P5G_S
i o
D D
F
D PD
Me d
Type
Reset
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
f o r
se
5 P6_SGMII_2P5G_SPD_STS Port 6 SGMII speed status.
0: SGMII is not running at 2.5G
4 P5_SGMII_2P5G_SPD_STS
e l e a 1: SGMII is running at 2.5G

Port 5 SGMII speed status.
R
i
FORCE_P6_SGMII_2P5G_SPD
t a l 1: SGMII is running at 2.5G

Force port 6 SGMII speed status.
n
f i d e
FORCE_P5_SGMII_2P5G_SPD
a P i
1: SGMII is running at 2.5G
Force port 5 SGMII speed status.
n
C o n a n
FORCE_MODE_P6_SGMII_2P5G_SPD
1: SGMII is running at 2.5G
Port 6 SGMII speed force Mode.
T e k r B a 0: Force mode is off

1: Force mode is on
d
0
i a o
FORCE_MODE_P5_SGMII_2P5G_SPD
F
Port 5 SGMII speed force Mode.
0: Force mode is off
Me
1: Force mode is on
o r
ef
000030C0 LPDET_CTRL LOOP DETECTION CONTROL REGISTER 00130000
s
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
LPDET_ LPDET_ LPDET_ LPDET_ LPDET_ LPDET_ LPDET_
EN6 EN5 EN4 EN3 EN2 EN1 EN0
LPDET_ LPDET_
PERIOD ALARM
_EN _EN
LPDET_ LPDET_
PASS PERIOD
LPDET_
LED_R
ATE
ele a LPDET_THRESHOLD
Type
Reset
RW
0
RW
0
i a l RRW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
1
RW
0 0
RW
1 1
Bit 15
LPDET_ LPDET_
14
e n t
13
i
12 11 10 9 8 7 6 5 4 3 2 1
LPDET_ LPDET_ LPDET_ LPDET_ LPDET_ LPDET_ LPDET_
0
Name ST_LO ST_BCS

OP T
n f i d n a P ALARM ALARM ALARM ALARM ALARM ALARM ALARM

6 5 4 3 2 1 0
Type
Reset
k
RO
0
C o RO
0
a n a
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
W1C
0
i a T e o r B
M e d F
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Confidential A
n t i a
f i d e a P i
n
30
o
LPDET_EN6
C n a n Enable the loop detection ability of user port 6.

0: Disable
29
T e k
LPDET_EN5
r B a 1: Enable
Enable the loop detection ability of user port 5.
a o
0: Disable
d i F 1: Enable
Me
28 LPDET_EN4 Enable the loop detection ability of user port 4.
0: Disable
1: Enable
27 LPDET_EN3 Enable the loop detection ability of user port 3.
0: Disable
26 LPDET_EN2
1: Enable
Enable the loop detection ability of user port 2.
f o r
se
0: Disable
a
1: Enable
25 LPDET_EN1
R e l e Enable the loop detection ability of user port 1.

0: Disable
1: Enable
24 LPDET_EN0
t i a l Enable the loop detection ability of user port 0.

0: Disable
23
d
LPDET_PERIOD_EN
i e n P i
1: Enable
The loop detection frame is triggered by a periodical timer or by
f
broadcast storm.
C o n a n a 0: Broadcast mode
1: Periodical mode
22 LPDET_ALARM_EN
e k B a n Enable 2 kHz alarm output and per-port LED when loop is detected.
0: Disable
21
d i a T o r
LPDET_PASS
F
1: Enable
Loop detection frame is blocked or passed to packet memory.
0: Blocked
Me
1: Pass
20 LPDET_PERIOD Interval of transmitting loop detection frame in Periodical mode.
0: 125 us
1: 1000 ms
r
19 LPDET_LED_RATE LED blinking rate of per port when loop is detected.
o
0: LED blinking at 2 Hz
ef
1: LED blinking at 4 Hz
s
18:16 LPDET_THRESHOLD Number of missed loop detection frame before 2 kHz alarm is reset
15 LPDET_ST_LOOP
a
The status of loop detection. In LOOP state, the loop detection frame is
ele
transmitted, and the loop detection frames are received.
0: Not in Loop state
14 LPDET_ST_BCST
i a l R 1: Loop state
The status of loop detection. In BCST state, the loop detection frame is
e n t i
transmitted, but no loop detection frame is received.
0: Not in BCST state
d
1: BCST state
6
f i
LPDET_ALARM6
o n n a P The status of loop detected on port 6. This bit is cleared when

LPDET_ALARM0 is written as 1.
k C a n a 0: Not detected
1: Detected
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
5 LPDET_ALARM5
f i d e a P i The status of loop detected on port 5. This bit is cleared when

C o n n a n
0: Not detected
1: Detected
k a
4 LPDET_ALARM4 The status of loop detected on port 4. This bit is cleared when
e B
d i a T F o r 0: Not detected
1: Detected
Me
0: Not detected
1: Detected
r
o
0: Not detected
1 LPDET_ALARM1
1: Detected
The status of loop detected on port 1. This bit is cleared when
se f
e l e a LPDET_ALARM0 is written as 1.
0: Not detected
1: Detected
0 LPDET_ALARM0
i a l R The status of loop detected on port 0. This bit is cleared when it is

written as 1.
e n t i
0: Not detected
1: Detected
n f i d n a P
k C o a n a
000030C8
Bit
i a T e31
o r
30
B
LPDET_SA_MSB
29 28 27 26
LOOP DETECTION SA MSB
25 24 23 22 21 20 19 18
88740180
17 16
Me d
Name
Type
Reset
Bit
1
15
F 0
14
0
13
0
12
1
11
0
10
0
9
LPDET_TYPE
0
8
RW
0
7
1
6
1
5
1
4
0
3
1
2
0
1
0
0
Name LPDET_SA_MSB
r
Type RW
Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0
ef
0
o 0
a s
Bit(s)
31:16
Name
LPDET_TYPE
l R
Description
Loop detection frame type
ele
15:0 LPDET_SA_MSB
n t i a Bits [47:32] of loop detection frame SA
f i d e a P i
000030CC
C o n n a
LPDET_SA_LSB
n LOOP DETECTION SA LSB C2000001
Bit
T e k31
r
30
B a 29 28 27 26 25 24 23 22 21 20 19 18 17 16
e d i a F o
M
f o r
l e a seMT7531

Confidential A
n t i a
e
Name LPDET_SA_LSB
Type
Reset 1 1
n f i d 0
a P i
0 0 0 1 0
RW
0 0 0 0 0 0 0 0
Bit
Name
15
C o
14
n a
13
n 12 11 10 9 8
LPDET_SA_LSB
7 6 5 4 3 2 1 0
Type
Reset
T e0
k 0
r B a 0 0 0 0 0 0
RW
0 0 0 0 0 0 0 1
d i a F o
Me Bit(s)
31:0
Name
LPDET_SA_LSB
Description
Bits [31:00] of loop detection frame SA
f o r
000030D0 LPDET_RXSA_MSB
l e a LOOP DETECTION RX SA MSB

se 00000000
Bit
Name
31 30 29
l
28
R e 27 26 25 24 23 22
LPDET_RXPORT
21 20 19 18 17
LPDET_SRCPORT
16
Type
Reset
n t i a 0 0
RO
0 0 0 0
RO
0 0
Bit
Name
15 14
f i d e13
a P i
12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset
C o n n a n
T e k r B a
d i a F o
Me
23:20 LPDET_RXPORT This is the 4-bit port number from which the loop detection frame was
received.
19:16 LPDET_SRCPORT This is the 4-bit source port number in the received loop detection
frame.
o r
a s ef
ele
000030E0 GMACCR Global MAC Control Register 00001E27
Bit 31 30 29
i a l R28 27 26 25 24 23 22 21 20 19 18
TXCRC_ RXCRC
PRMBL
17 16
t
Name _LMT_
EN _EN
Type
i d e n P i
RW RW
EN
RW
Reset
Bit 15
o n f
14
a n
13
a 12 11 10 9 8 7 6 5 4
0
3
0
2
0
1 0
Name
e k C B a n MTCC_LMT MAX_RX_JUMBO
MAX_RX_PKT_
LEN
d i a T F o r

f o r
l e a se MT7531

Confidential A
n t i a
e
Type RW RW RW
Reset
n f i d a P
1
i 1 1 1 1 0 0 1 1 1
C o n a n
Bit(s)
T e k
Name
r B a Description
a o
19 TXCRC_EN TX CRC Enable
d i F
0: TX CRC insertion is enabled.
Me
1: TX CRC insertion is disabled.
18 RXCRC_EN RX CRC Enable
0: RX CRC removal is enabled.
1: RX CRC removal is disabled.
17 PRMBL_LMT_EN Preamble Limit Enable
0: RXMAC can recognize SFD anytime.
1: RXMAC will recognize SFD within 7 Preamble bits, if SFD (0xd5) shows
f o r
se
up after 7 bits preamble; RXMAC will not recognize it and treat it as no
SFD case.
12:9 MTCC_LMT
e l e a MTCC Limit.
R
Maximum transmitted collision count limitation
t i a l 0: Disable TX collision abort function, send packet until the packet is sent
successfully.
15: Maximum transmitted collision count is up to 15.
5:2 MAX_RX_JUMBO
i d e n P i
Maximum length of ingress jumbo frames
0: Reserved.
o n f a n a 1: Reserved.
2: 2K Bytes.
e k C B a n
3: 3K Bytes.
4: 4K Bytes.
T
5: 5K Bytes.
d i a F o r 6: 6K Bytes.
7: 7K Bytes.
Me
8: 8K Bytes.
9: 9K Bytes.
10: 10K Bytes.
11: 11K Bytes.
12: 12K Bytes.
13: 13K Bytes.
o r
ef
14: 14K Bytes.
s
15: 15K Bytes.
1:0 MAX_RX_PKT_LEN Max Receive Packet Length.
ele a
Maximum length of ingress packet including CRC which can be received
i a l R by MAC
0: 1518 bytes for untagged frames; 1522 bytes for tagged frames.
e n t i
1: 1536bytes
2: 1552 bytes
n f i d n a P
3: MAX_RX_JUMBO
k C o a n a
i a T e o r B
M e d F
Page 429 of 830
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Confidential A
000030E4 SMACCR0
n t i a System MAC Control Register 0 0017A501

Bit 31 30
f i d e29
a P i
28 27 26 25 24 23 22 21 20 19 18 17 16
n
Name SMACCR0
Type
Reset 0
C o0
n a
0
n 0 0 0 0 0
RW
0 0 0 1 0 1 1 1
Bit
Name
T e k
15 14
r B a 13 12 11 10 9 8
SMACCR0
7 6 5 4 3 2 1 0
Type
d i
Reset
a F o RW
Me
1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1

31:0 SMACCR0 System MAC Address, sys_mac [31:0]. The first 32-bit of system MAC
address. It is unique and is specified for pause frame.
f o r
l e a se
l R e
000030E8
Bit 31
SMACCR1
30 29
n t i a 28 27 26
System MAC Control Register 1
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
f i d e a P i
Reset
Bit 15
C o n
14
n a
13
n 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
T e k r B a SMACCR1
RW
a o
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i F
Me Bit(s)
15:0
Name
SMACCR1
Description
System MAC Address, sys_mac [47:32]. The second 16-bit of system
MAC address. It is unique and is specified for pause frame.
o r
a s ef
000030F0
31
CKGCR
30 29
l R 28 27 26
Clock Gating Control Register
25 24 23 ele 00001E03
a
Bit 22 21 20 19 18 17 16
Name
Type
e n t i
Reset
Bit 15
n f i
14
d 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
C o n a n LPI_TXIDLE_THD
CKG_T CKG_R
CKG_L CKG_L
NKDN_ NKDN_
k a
XIDLE XLPI
PORT GLB
i a T e o r B
Med F
Page 430 of 830
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Confidential A
n t i a
e
Type RW RW RW RW RW
Reset 0 0
n f i d 0
a P i
1 1 1 1 0 0 0 1 1
C o n a n
Bit(s)
T e k
Name
r B a Description
a o
15:8 LPI_TXIDLE_THD When there is no packet to be transmitted, and the idle time is greater
d i F
than LPI_TXIDLE_THD, the TXMAC will automatically enter LPI (Low
Me
Default: 30ms (unit: 1ms)

5 CKG_TXIDLE 0: Keep the TX port clock ticking.
1: Stop the TX port clock ticking when the corresponding port has no
r
traffic to send, and the idle time is greater than <LPI_TXIDLE_THD> ms.
4 CKG_RXLPI 0: Keep RX port clock ticking.
1: Stop the RX port clock ticking when the corresponding port enters the
f o
se
LPI mode, and the RX FIFO is empty.
1 CKG_LNKDN_PORT
e l e a Port clock gating: Clock of gmac, port_ctrl, sch

0: Keep the RX and TX port clock ticking.
1: Stop both RX and TX port clock ticking when the corresponding port
0 CKG_LNKDN_GLB
i a l R enters the link-down status for 2 seconds.

Global clock gating: Clock of bmu, pb_ctrl, arl
t
0: Keep the global clock ticking.
i d e n P i
1: Stop the global clock ticking when port0~port5 enter the link-down
status for 2 seconds.
o n f a n a
e k C B a n
000030F4
i
Bit
d a T 31
F o r
GPINT_EN
30 29 28 27 26
Global Port Interrupt Enable Register
25 24 23 22 21 20 19 18
00000000
17 16
Me
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
WOL_I LPDET_ PC6_IN PC5_IN PC4_IN PC3_IN PC2_IN PC1_IN PC0_IN
Name
Type
NT_EN INT_EN
RW RW
T_EN T_EN T_EN T_EN T_EN T_EN T_EN
RW RW RW RW RW
ef
RW
o RW
Reset 0 0 0 0 0
a s 0 0 0 0
l R ele
Bit(s)
9
Name
WOL_INT_EN
n t i a Description
Enable interrupt of Wake-On-LAN.
e
0: Disable
n f i
LPDET_INT_EN
d a P i 1: Enable
Enable interrupt when the loop is detected.
1: Enable
6
T e k
PC6_INT_EN
r B a Port Controller 6 Interrupt Enable
e d i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: Disable
1: Enable
5
C o n
PC5_INT_EN
n a n Port Controller 5 Interrupt Enable

0: Disable
k a
1: Enable
4
i a T e
PC4_INT_EN
o r B Port Controller 4 Interrupt Enable

0: Disable
F
1: Enable
Me d3
2
PC3_INT_EN
PC2_INT_EN
Port Controller 3 Interrupt Enable
0: Disable
1: Enable
Port Controller 2 Interrupt Enable
0: Disable
r
1: Enable
1 PC1_INT_EN Port Controller 1 Interrupt Enable
f o
se
0: Disable
1: Enable
0 PC0_INT_EN
e l e a Port Controller 0 Interrupt Enable

0: Disable
R
1: Enable
t i a l
i d e n P i
000030F8
Bit 31
o n f
GPINT_STS
30
a n
29
a 28 27 26
Global Port Interrupt Status Register
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
e k C B a n
Reset
d i
Bit
a T 15
F o r 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
WOL_I LPDET_ PC6_IN PC5_IN PC4_IN PC3_IN PC2_IN PC1_IN PC0_IN
Name
NT INT T T T T T T T
Type W1C W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0
o r
a s ef
ele
9 WOL_INT Wake-On-LAN interrupt status. This bit is cleared when it is written as 1.
0: False
8 LPDET_INT
i a l R 1: True
Loop detection interrupt status. This bit is cleared when it is written as
e n t i
1.
0: False
d
1: True
6 PC6_INT
o n f i n a P Port Controller 6 Interrupt. This bit is cleared when it is written as 1.

0: False
k C
PC5_INT
a n a 1: True
Port Controller 5 Interrupt. This bit is cleared when it is written as 1.
i a T e o r B
M e d F
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MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: False
1: True
4
C o
PC4_INT
n n a n Port Controller 4 Interrupt. This bit is cleared when it is written as 1.

0: False
k a
1: True
3
i a T e
PC3_INT
o r B Port Controller 3 Interrupt. This bit is cleared when it is written as 1.

0: False
F
1: True
Me d2
1
PC2_INT
PC1_INT
0: False
1: True
0: False
r
1: True
0 PC0_INT Port Controller 0 Interrupt. This bit is cleared when it is written as 1.
f o
se
0: False
1: True
e l e a
i a l R
00003100 PMCR_P1
e n t i
PORT 1 MAC Control Register 00056330
d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
o n f i n a P
_MOD _MODE _MODE _MODE _MODE _MODE _MODE
IPG_CFG_P1
EXT_PH
MAC_
MODE
a
C n
_P1
P1 1 P1 _P1 _P1 0_P1 _P1
Type
Reset
T e
RW
0
k RW
r B
0
a RW
0
RW
0
RW
0
RW
0
RW
0 0
RW
1
RW
0
RW
1
i
Bit
d a 15
F o 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
MAC_T MAC_R BACKP FORCE FORCE FORCE FORCE FORCE FORCE
MAC_P BKOFF_
RE_P1 EN_P1
P1 P1 P1 _P1 0_P1 _P1 _P1 P1 P1
Reset 1 1 0 1 1 0 0 1 1 0 0 0 0
o r
a s ef
ele
31 FORCE_MODE_LNK_P1 PORT 1 link status force Mode.
R
l
module)
n t i a 1: Force mode is on. (Mac link status is determined by force_link_P1

register)
e
n f i d a P i 0: Force mode is off.(Mac speed is determined by phy auto-polling

module)
n
29
k C o a n a
FORCE_MODE_DPX_P1 PORT 1 duplex force Mode.
e B
module)
d i a T F o r

f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 1: Force mode is on. (Mac duplex mode is determined by force_dpx_P1

register)
28
C o n
FORCE_MODE_RX_FC_P1
n a n
PORT 1 RX FC force Mode.
module)
T e k r B a 1: Force mode is on. (Mac RX FC ability is determined by force_rx_fc_P1

register)
27
d i a o
FORCE_MODE_TX_FC_P1
F
PORT 1 TX FC force Mode.
Me
module)
register)
26 FORCE_MODE_EEE100_P1 PORT 1 100M EEE force Mode.
r
polling module)
f o
se
25 FORCE_MODE_EEE1G_P1 PORT 1 1G EEE force Mode.
e l e a 0: Force mode is off.(Mac 1G EEE ability is determined by phy auto-

polling module)
19:18 IPG_CFG_P1
i a l R force_eee1g_P1 register)
PORT 1 Inter-Frame+ Gap Shrink.
t
i d e n P i
17 EXT_PHY_P1
o n f a n a
C
16
k
MAC_MODE_P1
e B a n PORT 1 MAC Mode. PORT 1 operates in MAC mode

0: PORT 1 operates in PHY mode
14
d i a T F o r
MAC_TX_EN_P1
1: PORT 1 operates in MAC mode
Port 1 TX MAC Enable (Note: This bit only has impacts on the MAC
Me
13 MAC_RX_EN_P1 PORT 1 RX MAC Enable (Note: This bit only has impacts on MAC
r
o
ef
11 MAC_PRE_P1 TX short preamble mode
s
0: The TX short preamble length is disabled.
9 BKOFF_EN_P1
1: The TX short preamble is enabled.
PORT 1 Backoff Enable
0: Disabled
ele a
i a l R 1: Let the MAC of PORT 1 follow the back-off mechanism when collision
happens.
8 BACKPR_EN_P1
e n t i
PORT 1 Backpressure Enable
0: Disabled
d
n f i
FORCE_EEE1G_P1
o n a P with low internal free memory page count.

PORT 1 Force LPI Mode For 1000Mbps. When (force_mode_P1 = 1), this
k C a n a bit is used to control the 1000Base-T EEE ability of PORT 1.

e B
1000Mbps.
d i a T F o r

f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d
FORCE_EEE100_P1
e a P i 1: Have the ability of entering EEE Low Power Idle mode for 1000Mbps.
C o n n a n bit is used to control the 100Base-TX EEE ability of PORT 1.

a
100Mbps.
T e k r B
FORCE_RX_FC_P1
PORT 1 Force RX FC. When (force_mode_P1 = 1), this bit is used to
d i a F o control the RX FC ability of PORT 1.

0: Disabled
Me
duplex mode.
4 FORCE_TX_FC_P1 PORT 1 Force TX FC. When (force_mode_P1 = 1), this bit is used to
0: Disabled
f o r
se
e l e a 00: 10Mbps
01: 100Mbps
R
10: 1000Mbps
1 FORCE_DPX_P1
t i a l 11: reserved
PORT 1 Force duplex. When (force_mode_P1 = 1), this bit is used to
i d e n P i
control MAC duplex of PORT 1.
0: Half Duplex
f
1: Full Duplex
0
C o n
FORCE_LNK_P1
a n a PORT 1 Force MAC Link Up. When (force_mode_P1 = 1), this bit is used
to control link status of PORT 1.
e k B a n 0: Link Down
1: Link Up
d i a T F o r
Me 00003104
Bit 31
PMEEECR_P1
30 29 28 27 26
25 24 23 22 21 20 19 18
111E01E0
17 16
Name
r
WAKEUP_TIME_1000_P1 WAKEUP_TIME_100_P1
Type
Reset 0 0 0 1
RW
0 0 0 1 0 0 0 1
RW
1 1
ef
1
o 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
a s 3 2 1 0
ele
LPI_M
Name LPI_THRESH_P1 ODE_E
R
N_P1
Type
Reset 0 0
t
0
i a l 0 0 0
RW
0 1 1 1 1 0
RW
0
i d e n P i
o n f a n a
e k C B a n
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
31:24
d e
WAKEUP_TIME_1000_P1
f i a P i PORT 1 Wake Up Time for 1000Mbps LPI Mode.
C o n n a n The minimum allowed time needed to wait for PHY to be fully functional,
T e k r B a Time unit: 1 micro second
a
23:16 WAKEUP_TIME_100_P1 PORT 1 Wake Up Time for 100Mbps LPI Mode.
d i F o
Me

15:4 LPI_THRESH_P1 PORT 1 LPI Threshold.
When there is no packet to be transmittedm, and the idle time is greater
f o r
se
0 LPI_MODE_EN_P1
e l e a PORT 1 Enter LPI Mode.
R
t i a l than P1_LPI_THRESHOLD, the TXMAC will automatically enter LPI (Low

n
0: LPI mode depends on the P1_LPI_THRESHOLD.
f i d e a P i
1: Let the system enter the LPI mode immediately and send EEE LPI frame
to the link partner.
C o n n a n
T e k r B a
d i
Bit
a
00003108
31
F o
PMSR_P1
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Me
Name
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEE100 MAC_D MAC_L
o r
ef
1 _P1 S_P1
Type
Reset
RO
0
RO
0
RO
0
RO
0
le a s
0
RO
0
RO
0
RO
0
l R e
Bit(s) Name
n t i a Description
7
f i d e
EEE1G_STS_P1
a P i PORT 1 LPI Mode Status For 1000Mbps

C o n
EEE100_STS_P1
n a n
1: Capable of entering EEE Low Power Idle mode for 1000Mbps.
T e k r B a
ed i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
f
RX_FC_STS_P1
i d e a P i 1: Capable of entering EEE Low Power Idle mode for 100Mbps.
PORT 1 RX XFC Status. Port 1 Rx flow control status.
C o n n a n 0: Disabled
k a
duplex mode.
e B
4 TX_FC_STS_P1 PORT 1 TX XFC Status. PORT 1 TX flow control status.
d i a T F o r 0: Disabled
Me
3:2 MAC_SPD_STS_P1 PORT 1 Speed [1:0] Status. Current speed of PORT 1 after PHY links up.
00: 10 Mbps
01: 100 Mbps
10: 1000 Mbps
r
11: Reserved
o
1 MAC_DPX_STS_P1 PORT 1 duplex Status. Current duplex mode of PORT 1 after PHY links
up.
0: Half Duplex
se f
0 MAC_LNK_STS_P1
e l e a 1: Full Duplex
Port 1 Link Up Status. Link up status of PORT 1.
0: Link Down
i a l R 1: Link Up
e n t i
n f i d n a P
o
00003110 PINT_EN_P1 PORT 1 Interrupt Enable Register 00000000
Bit 31
k C 30
a n a
29 28 27 26 25 24 23 22 21 20 19 18 17 16
e B
Name
Type
i
Reset
d a T F o r
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TX_TFF TX_MIS TX_MIS TX_RP TX_RP TX_GP TX_RD TX_DE RX_AR RX_WR RX_GP
RX_AFF
_UNDR VLAN_ PAGE_ AGE_E AGE_T AGE_T PB_TO Q_TOU L_TOU PB_TO AGE_T
Name _FULL_
_INT_E ERR_IN ERR_IN RR_INT OUT_I OUT_I UT_INT T_INT_ T_INT_ UT_INT OUT_I
INT_EN
r
Reset 0 0 0 0 0 0 0 0 0 0
ef
0
o 0
a s
Bit(s)
15
Name
TX_TFF_UNDR_INT_EN
l R
Description
ele
n t i a 0: Disabled
1: Enabled
14
f i d e
TX_MISVLAN_ERR_INT_EN
a P i
TX_CTRL PKT INFO VLAN Mismatch Error Interrupt Enable
0: Disabled
n
1: Enabled
13
o a n
TX_MISPAGE_ERR_INT_EN
C n
TX_CTRL PKT INFO Page Mismatch Error Interrupt Enable
0: Disabled
T e k r B a 1: Enabled
e d i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
12
f i d e
TX_RPAGE_ERR_INT_EN
a P i TX_CTRL Release Page Count Error Interrupt Enable

0: Disabled
11
C o n a
TX_RPAGE_TOUT_INT_EN
n n 1: Enabled
k a
0: Disabled
10
i a T e r B
o
1: Enabled
F
0: Disabled
Me d9 TX_RDPB_TOUT_INT_EN
1: Enabled
0: Disabled
1: Enabled
8 TX_DEQ_TOUT_INT_EN TX_CTRL DEQ Timeout Interrupt Enable
r
0: Disabled
1: Enabled
f o
se
3 RX_AFF_FULL_INT_EN RX_CTRL Agent FIFO Full Interrupt Enable
0: Disabled
2 RX_ARL_TOUT_INT_EN
e l e a 1: Enabled
RX_CTRL ARL Timeout Interrupt Enable
R
0: Disabled
l
1: Enabled
1 RX_WRPB_TOUT_INT_EN
n t i a RX_CTRL WR_PB Timeout Interrupt Enable

0: Disabled
i d e
RX_GPAGE_TOUT_INT_EN
f a P i
1: Enabled
RX_CTRL Get Page Timeout Interrupt Enable
n
0: Disabled
C o n a n 1: Enabled
T e k r B a
d i a F o
Me
00003114 PINT_STS_P1 PORT 1 Interrupt Status Register 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Reset
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
a
ele
T T NT NT NT
Type
Reset
RO
0
RO
0
RO
i
0
a l R RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
e n t i
Bit(s)
n
Name
f i d n a P Description
15
k C o a n a
TX_TFF_UNDR_INT TXMAC TXFIFO Under run Interrupt
0: False
i a T e o r B
Med F
Page 438 of 830
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
14
f i d e
TX_MISVLAN_ERR_INT
a P i 1: True
TX_CTRL PKT INFO VLAN Mismatch Error Interrupt
C o n n a n 0: False
1: True
k a
13 TX_MISPAGE_ERR_INT TX_CTRL PKT INFO Page Mismatch Error Interrupt
1: True
F
12 TX_RPAGE_ERR_INT TX_CTRL Release Page Count Error Interrupt
Me d
11 TX_RPAGE_TOUT_INT
0: False
1: True
0: False
1: True
r
0: False
f o
se
1: True
e l e a 0: False
1: True
R
l
0: False
3 RX_AFF_FULL_INT
n t i a 1: True
RX_CTRL Agent FIFO Full Interrupt
f i d e a P i
0: False
1: True
n
C o n a n 0: False
1: True
1
T e k r B a
RX_WRPB_TOUT_INT RX_CTRL WR_PB Timeout Interrupt
0: False
d
0
i a F o
RX_GPAGE_TOUT_INT
1: True
RX_CTRL Get Page Timeout Interrupt
Me
0: False
1: True
o r
00003118
Bit 31
P1_DBG_CNT
30 29 28 27 26
PORT 1 DEBUG COUNT
25 24 23 22 21 20
a s 19 18
ef00000000
17 16
ele
Name
R
Type
Reset
Bit 15 14
t
13
i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i d e n P i
TX_FIFO_URUN
RO
RX_FIFO_OV
RO
Reset
o n f a n a 0 0 0 0 0 0 0
e k C B a n
d i a T F o r

f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
7:4 TX_FIFO_URUN
f i d e a P i Underrun count of TX fifo. The field is increased when TX fifo underrun

occurs.
2:0
C o n
RX_FIFO_OV
n a n
occurs.
T e k r B a
d i a F o
Me
00003120 P1_WOL PORT 1 WOL 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WOL_I WOL_S
Name WOL_DBG
NT_STS TS
Type
r
RO W1C RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Name
e
KT S NT_EN N
Type
Reset
R e l RW
0
RW
0
RW
0
RW
0
t i a l
i d e n P i
f
31:18
17
o n
WOL_DBG
WOL_INT_STS
C a n a Port1 Wake-up On Lan Debug Signals

16
e
WOL_STS
k B a n Port1 Wake-up On Lan Status
d i a T F o r
If enable WOL_EN, this bit will change from 0 to 1 when GMAC RX state
detect magic packet.
M e 3
2
SNP_PKT
CRC_DIS
Port1 Wake-up On Lan with snoopy packet
0: Disable
1: Enable
0: CRC check enable
1: CRC check disable
o r
ef
1 WOL_INT_EN Port1 Wake-up On Lan Interrupt Enable
0: Disable
1: Enable
a s
ele
0 WOL_EN Port1 Wake-up On Lan Function Enable
0: Disable
i a l R 1: Enable
e n t i
n f i d n a P
o
00003124 P1_PFC_STS PORT 1 PFC STATUS 00000000
Bit
Name
k C
31 30
a n a 29 28 27 26 25 24 23 22 21 20 19 18 17 16
i a T e o r B
M e d F
Page 440 of 830
f o r
l e a se MT7531

Confidential A
n t i a
e
Type
Reset
Bit 15
n
14
f i d 13
a P i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
C o n a n TX_PFC_STS
RO
RX_PFC_STS
RO
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
15:8
7:0
Name
TX_PFC_STS
RX_PFC_STS
Description
f o r
00003130 P1_PFC_RX_PSON_CNT_L
l e a Port 1 RX PFC pause on counter for low priority se 00000000

Bit
Name
31 30 29
l
28
R e
Q3_RX_PSON_CNT
27 26 25 24 23 22 21 20
Q2_RX_PSON_CNT
19 18 17 16
Type
Reset 0 0
n
0
t i a 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
Name
15 14
f i d e13
P i
12
Q1_RX_PSON_CNT
a
11 10 9 8 7 6 5 4
Q0_RX_PSON_CNT
3 2 1 0
Type
Reset 0
C o0
n n a
0
n 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
T e k r B a
d i a
Bit(s) Name
F o Description
Me
o r
a s ef
ele
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
i a l R
Q7_RX_PSON_CNT
RC
Q6_RX_PSON_CNT
RC
Reset
Bit
0
15
0
14
e n t
0
13
i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
n f i d n a P
Q5_RX_PSON_CNT
RC
Q4_RX_PSON_CNT
RC
Reset
k
0
C o 0
a n a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a T e o r B
M e d F
Page 441 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
31:24
23:16
C o
Q7_RX_PSON_CNT
Q6_RX_PSON_CNT
n a n PFC RX pause on count for port1 priority 7

15:8
7:0
T k
Q5_RX_PSON_CNT
e r B
Q4_RX_PSON_CNT
a PFC RX pause on count for port1 priority 5
d i a F o
Me 00003138
Bit 31
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Q3_RX_PSOFF_CNT
RC
Q2_RX_PSOFF_CNT
RC
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
l e a
Q1_RX_PSOFF_CNT
e
11 10 9 8 7 6 5 4
Q0_RX_PSOFF_CNT
3 2 1 0
R
Type RC RC
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
i d e n P i
Bit(s)
31:24
Name
o n f
Q3_RX_PSOFF_CNT
a n a Description
23:16
15:8
7:0 C
Q2_RX_PSOFF_CNT
k a
Q1_RX_PSOFF_CNT
e B
Q0_RX_PSOFF_CNT n
d i a T F o r
Me 0000313C
Bit 31
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
o r
ef
Type RC RC
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
Q5_RX_PSOFF_CNT
11 10 9 8 7 6 5
ele
4
a
Q4_RX_PSOFF_CNT
3 2 1 0
R
Type RC RC
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
i d e n P i
Bit(s)
31:24
Name
o n f
Q7_RX_PSOFF_CNT
a n a Description
23:16
15:8
e k C n
Q6_RX_PSOFF_CNT
a
Q5_RX_PSOFF_CNT
B
d i a T F o r

f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
7:0
f i d
Q4_RX_PSOFF_CNT
e a P i PFC RX pause off count for port1 priority 4
C o n n a n
00003140
T e k r B a
P1_PFC_TX_PSON_CNT_L Port 1 TX PFC pause on counter for low priority 00000000
d i
Bit
a 31
F o30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type RC RC
f o
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e l e a
Bit(s)
31:24
Name
Q3_TX_PSON_CNT
i a l R Description
23:16
15:8
Q2_TX_PSON_CNT
Q1_TX_PSON_CNT
e n t i
d
o n f i n a P
k C a n a
00003144
i a T e r B
o
d F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0 0
RC
0 0
ef
0
o 0
a s
Bit(s) Name
l R Description
ele
31:24
23:16
Q7_TX_PSON_CNT
Q6_TX_PSON_CNT
n t i a PFC TX pause on count for port1 priority 7

e
7:0
n f i d
Q4_TX_PSON_CNT
a P i PFC TX pause on count for port1 priority 4
C o n a n
T e k r B a
e d i a F o
M
f o r
l e a seMT7531

Confidential A
00003148
n t i a
P1_PFC_TX_PSOFF_CNT_L Port 1 TX PFC pause off counter for low priority 00000000
Bit 31 30
f i d e29
a P i
28 27 26 25 24 23 22 21 20 19 18 17 16
n
Name Q3_TX_PSOFF_CNT Q2_TX_PSOFF_CNT
Type
Reset 0
C o0
n a
0
n 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
Name
T e k
15 14
r B a 13 12
Q1_TX_PSOFF_CNT
11 10 9 8 7 6 5 4
Q0_TX_PSOFF_CNT
3 2 1 0
Type
d i
Reset
a F o RC RC
Me
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31:24
23:16
Q3_TX_PSOFF_CNT
Q2_TX_PSOFF_CNT
f o r
se
a
R e l e
t i a l
0000314C
Bit 31 30
i d e n
29
P i
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
o n f a n a
Q7_TX_PSOFF_CNT
RC
Q6_TX_PSOFF_CNT
RC
Reset
Bit
e
0
k
15
C 0
14
B a n 0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
d i a T F o r
Q5_TX_PSOFF_CNT
RC
Q4_TX_PSOFF_CNT
RC
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
o
ef
s
a
l R ele
00003200 PMCR_P2
n t i a PORT 2 MAC Control Register 00056130

Bit 31 30
f i d e 29
a P i28 27 26 25 24 23 22 21 20 19 18 17 16
n
n
MAC_
o
a
C n
_P2
k a
P2 2 P2 _P2 _P2 0_P2 _P2
i a T e o r B
M e d F
Page 444 of 830
f o r
l e a se
MT7531

Confidential A
n t i a
e
Type RW RW RW RW RW RW RW RW RW RW
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9 8 7 6 5 4
0
3
1
2
0
1
1
0
Name
C o
MAC_T MAC_R
n
X_EN_ X_EN_
a n MAC_P
BACKP FORCE FORCE FORCE FORCE FORCE FORCE
R_EN_ _EEE1G _EEE10 _RX_FC _TX_FC FORCE_SPD_P2 _DPX_ _LNK_
k a
RE_P2
P2 P2 P2 _P2 0_P2 _P2 _P2 P2 P2
Type
i
Reset
a T e o
RW
r
1
B RW
1
RW
0
RW
1
RW
0
RW
0
RW
1
RW
1 0
RW
0
RW
0
RW
0
Me d F
module)
f o r
se
register)
30 FORCE_MODE_SPD_P2
e l e a PORT 2 speed force Mode.

0: Force mode is off.(Mac speed is determined by phy auto-polling
R
module)
l
29 FORCE_MODE_DPX_P2
n t i a PORT 2 duplex force Mode.

e
module)
n f i d a P i 1: Force mode is on. (Mac duplex mode is determined by force_dpx_P2

register)
28
C o
FORCE_MODE_RX_FC_P2
n a n PORT 2 RX FC force Mode.

k a
module)
e B
27
d i a T o r
FORCE_MODE_TX_FC_P2
F
register)
Me
module)
register)
polling module)
o r
ef
a s
ele
polling module)
19:18 IPG_CFG_P2
i a l R force_eee1g_P2 register)
PORT 2 Inter-Frame+ Gap Shrink
e n t i
17
f
EXT_PHY_P2
n i d n a P
o
16
k C
MAC_MODE_P2
a n a 1: PORT 2 connects with external PHY

PORT 2 MAC Mode. PORT 2 operates in MAC mode
i a T e o r B
M e d F
Page 445 of 830
f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: PORT 2 operates in PHY mode

14
C o n
MAC_TX_EN_P2
n a n Port 2 TX MAC Enable (Note: This bit only has impacts on MAC function,
it has no impact on the link status or Queue manager.)
k a
13
i a T e r B
MAC_RX_EN_P2
o
PORT 2 RX MAC Enable (Note: This bit only has impacts on MAC
F
Me d
11 MAC_PRE_P2
r
0: Disabled
f o
se
with low internal free memory page count.
7 FORCE_EEE1G_P2
e l e a PORT 2 Force LPI Mode For 1000Mbps. When (force_mode_pn = 1), this
bit is used to control the 1000Base-T EEE ability of PORT 2.
i a l R 1000Mbps.
6 FORCE_EEE100_P2
e n t i
PORT 2 Force LPI Mode For 100Mbps. When (force_mode_pn = 1), this
bit is used to control the 100Base-TX EEE ability of PORT 2.
d
o n f i n a P 100Mbps.
5 FORCE_RX_FC_P2
k C a n a PORT 2 Force RX FC. When (force_mode_P2 = 1), this bit is used to

0: Disabled.
i a T e o r B 1: Let the MAC of PORT 2 accept a pause frame when operating in full-
duplex mode.
Me d
4
F
FORCE_TX_FC_P2 PORT 2 Force TX FC. When (force_mode_P2 = 1), this bit is used to
0: Disabled.
o r
ef
00: 10Mbps
01: 100Mbps
10: 1000Mbps
a s
ele
11: Reserved
1 FORCE_DPX_P2 PORT 2 Force duplex. When (force_mode_P2 = 1), this bit is used to
R
control the MAC duplex of PORT 2.
t i a l 0: Half Duplex
1: Full Duplex
n
0 FORCE_LNK_P2 PORT 2 Force MAC Link Up. When (force_mode_P2 = 1), this bit is used
f i d e a P i
to control the link status of PORT 2.
0: Link Down
n
1: Link Up
C o n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
00003204 PMEEECR_P2 PORT 2 MAC EEE Control Register 111E01E0
Bit
Name
31
C o30
n a
29
n 28
WAKEUP_TIME_1000_P2
27 26 25 24 23 22 21 20
WAKEUP_TIME_100_P2
19 18 17 16
Type
Reset
T e0
k 0
r B a 0 1
RW
0 0 0 1 0 0 0 1
RW
1 1 1 0
i
Bit
d a 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
LPI_M
Name LPI_THRESH_P2 ODE_E
N_P2
Type RW RW
Reset 0 0 0 0 0 0 0 1 1 1 1 0 0
f o r
Bit(s)
31:24
Name
WAKEUP_TIME_1000_P2
l e a Description
PORT 2 Wake Up Time for 1000Mbps LPI Mode se
l R e The minimum allowed time needed to wait for PHY to be fully functional,
n t i a and TXMAC can transmit packet after wakeup.
23:16
i d e
WAKEUP_TIME_100_P2
f a P i
PORT 2 Wake Up Time for 100Mbps LPI Mode
C o n n a n The minimum allowed time needed to wait for PHY to be fully functional,
T e k r B a Time unit: 1 micro second
i
15:4
d a o
LPI_THRESH_P2
F
Me
o r
ef
a s
ele
1: Let the system enter the LPI mode immediately and send EEE LPI frame
to the link partner.
i a l R
e n t i
00003208
31
n f
30
i d
PMSR_P2
n
29
a P 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
o
Bit
Name
Type
k C a n a
i a T e o r B
M e d F
Page 447 of 830
f o r
l e a se
MT7531

Confidential A
n t i a
e
Reset
Bit 15 14
n f i d 13
a P i
12 11 10 9 8 7
EEE100
6 5 4 3
MAC_D MAC_L
2 1 0
n
o
a
C n
2 _P2 S_P2
Type
Reset
T e k r B a RO
0
RO
0
RO
0
RO
0 0
RO
0
RO
0
RO
0
d i a F o
Me Bit(s)
7
Name
EEE1G_STS_P2
Description
PORT 2 LPI Mode Status For 1000Mbps
0: Not capable of entering EEE Low Power Idle mode for 1000Mbps
6 EEE100_STS_P2
1: Capable of entering EEE Low Power Idle mode for 1000Mbps
f o r
se
5 RX_FC_STS_P2
e l e a PORT 2 RX XFC Status. Port 2 Rx flow control status

0: Disabled.
4 TX_FC_STS_P2
i a l R 1: Let the MAC of PORT 2 accept a pause frame when operating in full-
duplex mode.
PORT 2 TX XFC Status
e n t i
PORT 2 TX flow control status
n f i d n a P 0: Disabled.
3:2
C o
MAC_SPD_STS_P2
k a n a
PORT 2 Speed [1:0] Status
i a T e o r B Current speed of PORT 2 after PHY links up

00: 10 Mbps
Me d1
F
MAC_DPX_STS_P2
01: 100 Mbps
10: 1000 Mbps
11: Reserved
PORT 2 duplex Status
r
Current duplex mode of PORT 2 after PHY links up
o
0: Half Duplex
ef
1: Full Duplex
s
0 MAC_LNK_STS_P2 Port 2 Link Up Status
Link up status of PORT 2

0: Link Down
ele a
i a l R 1: Link Up
e n t i
n f i d n a P
00003210
Bit
k C
31
o PINT_EN_P2
30
a n a29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
i a T e o r B
M e d F
Page 448 of 830
f o r
l e a se MT7531

Confidential A
n t i a
e
Name
Type
Reset
n f i d a P i
Bit 15
C o14
n a
13
n
12 11
TX_RP
10 9
TX_GP TX_RD TX_DE
8 7 6 5 4 3 2 1
RX_AR RX_WR RX_GP
0
Name
T e k r B a
_INT_E ERR_IN ERR_IN RR_INT
AGE_T
OUT_I
AGE_T PB_TO Q_TOU
OUT_I UT_INT T_INT_
RX_AFF
_FULL_
INT_EN
L_TOU PB_TO AGE_T
T_INT_ UT_INT OUT_I
a o
d i
Type RW
F RW RW RW RW RW RW RW RW RW RW RW
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
15
Name
TX_TFF_UNDR_INT_EN
Description
f o r
se
0: Disabled
a
1: Enabled
14 TX_MISVLAN_ERR_INT_EN
R e l e TX_CTRL PKT INFO VLAN Mismatch Error Interrupt Enable

0: Disabled
1: Enabled
13 TX_MISPAGE_ERR_INT_EN
t i a l TX_CTRL PKT INFO Page Mismatch Error Interrupt Enable

0: Disabled
12
d e n
TX_RPAGE_ERR_INT_EN
i P i
1: Enabled
o n f a n a
0: Disabled
1: Enabled
C
11 TX_RPAGE_TOUT_INT_EN TX_CTRL Release Page Timeout Interrupt Enable
e k B a n 0: Disabled
1: Enabled
10
d i a T F o r
TX_GPAGE_TOUT_INT_EN TX_CTRL Get Page Timeout Interrupt Enable
0: Disabled
Me
1: Enabled
9 TX_RDPB_TOUT_INT_EN TX_CTRL RD_PB Timeout Interrupt Enable
0: Disabled
1: Enabled
r
0: Disabled
3 RX_AFF_FULL_INT_EN
1: Enabled
ef o
0: Disabled
1: Enabled
a s
ele
0: Disabled
i a l R 1: Enabled
RX_CTRL WR_PB Timeout Interrupt Enable
e n t i
0: Disabled
1: Enabled
0
n f i d
n a P
0: Disabled
k C o a n a
1: Enabled
i a T e o r B
M e d F
Page 449 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
Bit
Name
31
C o30
n a
29
n 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
T e k r B a
a
Reset
d i
Bit 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
T T NT NT NT
Type RO RO RO RO RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0 0 0
f o
0
r 0
l e a se
e
R
t i a l 0: False
1: True
n
14 TX_MISVLAN_ERR_INT TX_CTRL PKT INFO VLAN Mismatch Error Interrupt
f i d e a P i
0: False
1: True
13
C o n
TX_MISPAGE_ERR_INT
n a n
0: False
1: True
12
T e k r B a
TX_RPAGE_ERR_INT TX_CTRL Release Page Count Error Interrupt
0: False
d
11
i a F o
TX_RPAGE_TOUT_INT
1: True
Me
0: False
1: True
0: False
1: True
o r
ef
0: False
1: True
a s
ele
0: False
1: True
3 RX_AFF_FULL_INT
i a l R RX_CTRL Agent FIFO Full Interrupt

0: False
2 RX_ARL_TOUT_INT
e n t i
1: True
RX_CTRL ARL Timeout Interrupt
d
0: False
o n f i
RX_WRPB_TOUT_INT
n a P 1: True
RX_CTRL WR_PB Timeout Interrupt
k C a n a 0: False
1: True
i a T e o r B
M e d F
Page 450 of 830
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
0
f i d e
RX_GPAGE_TOUT_INT
a P i RX_CTRL Get Page Timeout Interrupt

0: False
C o n n a n 1: True
T e k r B a
d i a F o
Me
00003218 P2_DBG_CNT PORT 2 DEBUG COUNT 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
r
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o 1 0
se
a
Type RO RO
Reset
R e l e 0 0 0 0 0 0 0
t i a l
Bit(s)
7:4
Name
TX_FIFO_URUN
i d e n P i
Description
Underrun count of TX fifo. The field is increased when TX fifo underrun
2:0
n
RX_FIFO_OV
o f a n a
occurs.
occurs.
e k C B a n
d i a T F o r
Me
00003220 P2_WOL PORT 2 WOL 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WOL_I WOL_S
Name WOL_DBG
NT_STS TS
r
Type RO W1C RO
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
ef
0
1
o 0
0
Name
a s SNP_P CRC_DI WOL_I WOL_E
ele
KT S NT_EN N
Type RW RW RW RW
Reset
i a l R 0 0 0 0
e n t i
Bit(s)
31:18
Name
n
WOL_DBG
17
k C o
WOL_INT_STS
a n a Port2 Wake-up On Lan Interrupt Status
i a T e o r B
M e d F
Page 451 of 830
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
16 WOL_STS
f i d e a P i Port2 Wake-up On Lan Status
k a
e B
3 SNP_PKT Port2 Wake-up On Lan with snoopy packet
d i a T F o r 0: Disable
1: Enable
Me
2 CRC_DIS Port2 Wake-up On Lan with CRC Check Disable
0: CRC check enable
0: Disable
r
1: Enable
0 WOL_EN Port2 Wake-up On Lan Function Enable
0: Disable
f o
se
1: Enable
e l e a
i a l R
00003224
Bit 31
P2_PFC_STS
30
e n t
29
i
28 27 26
PORT 2 PFC STATUS
25 24 23 22 21 20 19 18
00000000
17 16
Name
n f i d n a P
o
Type
Reset
Bit
k
15
C 14
a n a 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i a T e o r B TX_PFC_STS
RO
RX_PFC_STS
RO
Me d
Reset 0
F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15:8 TX_PFC_STS Port2 PFC TX pause on status of 8 priorities 1: pause on 0: pause off
o r
ef
7:0 RX_PFC_STS Port2 PFC RX pause on status of 8 priorities 1: pause on 0: pause off
a s
l R ele
a
00003230 P2_PFC_RX_PSON_CNT_L Port 2 RX PFC pause on counter for low priority 00000000
Bit
Name
31 30
e n t i 29 28
Q3_RX_PSON_CNT
27 26 25 24 23 22 21 20
Q2_RX_PSON_CNT
19 18 17 16
Type
Reset 0
n f i d0
a P
0
i 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
Name
C o
15 14
n a n 13 12
Q1_RX_PSON_CNT
11 10 9 8 7 6 5 4
Q0_RX_PSON_CNT
3 2 1 0
Type
T e k r B a RC RC
ed i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
C o n a n
k a
e B
23:16
i
15:8
d
7:0
a T o r
Q2_RX_PSON_CNT
Q1_RX_PSON_CNT
F
Q0_RX_PSON_CNT
Me
00003234
31
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17r
00000000
16
se
Bit
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
e l0
e aRC
0 0 0 0
Bit
Name
15 14 13
i a l R12
Q5_RX_PSON_CNT
11 10 9 8 7 6 5 4
Q4_RX_PSON_CNT
3 2 1 0
Type
Reset 0 0
e n t
0
i
0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
n f i d n a P
Bit(s)
k C
Name
o a n a Description
31:24
23:16
i a
15:8
T e r B
Q7_RX_PSON_CNT
Q6_RX_PSON_CNT
o
Q5_RX_PSON_CNT
M e d 7:0
F
Q4_RX_PSON_CNT PFC RX pause on count for port2 priority 4
00003238 P2_PFC_RX_PSOFF_CNT_L Port 2 RX PFC pause off counter for low priority
o r
00000000
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Q3_RX_PSOFF_CNT
s
Q2_RX_PSOFF_CNT
a
ele
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13
i a l R12
Q1_RX_PSOFF_CNT
11 10 9 8 7 6 5 4
Q0_RX_PSOFF_CNT
3 2 1 0
Type
Reset 0 0
e n t
0
i
0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
n f i d n a P
k C o a n a
i a T e o r B
M e d F
Page 453 of 830
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
31:24
23:16
f i d
Q3_RX_PSOFF_CNT
Q2_RX_PSOFF_CNT
15:8
7:0
C n
Q1_RX_PSOFF_CNT
o
Q0_RX_PSOFF_CNT
n a n
T e k r B a
d i a F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RC RC
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
f o
0
1
r 0
0
se
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
e l0
e aRC
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
d
23:16
15:8
n f i
Q6_RX_PSOFF_CNT
Q5_RX_PSOFF_CNT

7:0
k C
Q4_RX_PSOFF_CNT
i a T e o r B
M e d
00003240
Bit
Name
F
31
30 29 28
Q3_TX_PSON_CNT
27 26
25 24 23 22 21 20
Q2_TX_PSON_CNT
19 18
00000000
17 16
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
ele
0
a RC
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
d
23:16
15:8
n f i
Q2_TX_PSON_CNT
Q1_TX_PSON_CNT
o n a P PFC TX pause on count for port2 priority 2

7:0
k C
Q0_TX_PSON_CNT
a n a PFC TX pause on count for port2 priority 0
i a T e o r B
M e d F
Page 454 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
00003244 P2_PFC_TX_PSON_CNT_H Port 2 TX PFC pause on counter for high priority 00000000
Bit
Name
31
C o30
n a
29
n 28
Q7_TX_PSON_CNT
27 26 25 24 23 22 21 20
Q6_TX_PSON_CNT
19 18 17 16
Type
Reset
T e0
k 0
r B a 0 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
d i a 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
23:16
15:8
7:0
Q6_TX_PSON_CNT
Q5_TX_PSON_CNT
Q4_TX_PSON_CNT
e l e a PFC TX pause on count for port2 priority 6

i a l R
e n t i
00003248
n f i d a P
n
Port 2 TX PFC pause off counter for low priority 00000000
Bit
Name
31
k C o30
a n a
29 28
Q3_TX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q2_TX_PSOFF_CNT
19 18 17 16
e B
Type RC RC
Reset
Bit
d i a T 0
15
F o
0
r
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
a s
ele
i a l R
e n t i
0000324C
n f i d a P
n
Port 2 TX PFC pause off counter for high priority 00000000
Bit
Name
k
31
C o 30
a n a
29 28
Q7_TX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q6_TX_PSOFF_CNT
19 18 17 16
i a T e o r B
M e d F
Page 455 of 830
f o r
l e a se
MT7531

Confidential A
n t i a
e
Type RC RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q4_TX_PSOFF_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q7_TX_PSOFF_CNT
Q6_TX_PSOFF_CNT
Q5_TX_PSOFF_CNT
Description
f o r
l e a se
00003300 PMCR_P3
l R e PORT 3 MAC Control Register 00056330
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
t i
n
e
IPG_CFG_P3
EXT_PH
MAC_
MODE
i
Type
P3
RW
3
n
RW
f i
P3
d _P3
RW
n P
_P3
a RW
0_P3 _P3
RW RW RW RW RW
_P3
RW
Reset
Bit
0
k
15
C o 0
14
a n a
0
13
0
12
0
11
0
10
0
9 8 7 6 5 4
0
3
1
2
0
1
1
0
Name
i a T e r B
MAC_T MAC_R
X_EN_ X_EN_
o
MAC_P
RE_P3
BKOFF_
EN_P3
F
P3 P3 P3 _P3 0_P3 _P3 _P3 P3 P3
Me d
Type
Reset
RW
1
RW
1
RW
0
RW
1
RW
1
RW
0
RW
0
RW
1
RW
1 0
RW
0
RW
0
RW
0
o r
ef
module)
a s
ele
register)
i a l R PORT 3 speed force Mode.

e n t i
module)
d
29 FORCE_MODE_DPX_P3 PORT 3 duplex force Mode.
o n f i n a P 0: Force mode is off.(Mac duplex mode is determined by phy auto-polling

module)
k C a n a 1: Force mode is on. (Mac duplex mode is determined by force_dpx_P3

register)
e B
28 FORCE_MODE_RX_FC_P3 PORT 3 RX FC force Mode.
d i a T F o r

f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: Force mode is off.(Mac RX FC ability is determined by phy auto-polling

module)
27
C o n n a
FORCE_MODE_TX_FC_P3 n
register)
T e k r B a 0: Force mode is off.(Mac TX FC ability is determined by phy auto-polling

module)
d i a F o 1: Force mode is on. (Mac TX FC ability is determined by force_tx_fc_P3

register)
Me
polling module)
r
polling module)
f o
se
19:18 IPG_CFG_P3
e l e a force_eee1g_P3 register)
i a l R 01: Transmit 96-bits IFG with short IFG in random behavior

17 EXT_PHY_P3
e n t i
PORT 3 External PHY
n f i d n a P
Port 3 connects with external PHY.
o
16
C
MAC_MODE_P3
k a n a PORT 3 MAC Mode
i a T e o r B PORT 3 operates in MAC mode.

Me d
14
F
MAC_TX_EN_P3
it has no impact on the link status or Queue manager.)
13 MAC_RX_EN_P3 PORT 3 RX MAC Enable (Note: This bit only has impact on MAC function,
and it has no impact on the link status or Queue manager.)
o r
ef
a s
ele
R
t i a l 0: Disabled
1: Let the MAC of PORT 3 to follow the back-off mechanism when
n
collision happens.
8 BACKPR_EN_P3
f i d e a P i
0: Disabled
n
1: Enable the back pressure mechanism when operating in half-duplex
C o
FORCE_EEE1G_P3
n a n mode with low internal free memory page count .

PORT 3 Force LPI Mode For 1000Mbps
T e k r B a
e d i a F o
M
f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i When (force_mode_P3 = 1), this bit is used to control the 1000Base-T EEE
ability of PORT 3.
C o n n a n 0: Do not have the ability of entering EEE Low Power Idle mode for
1000Mbps.
a
6
T e k B
FORCE_EEE100_P3
r
d i a F o When (force_mode_P3 = 1), this bit is used to control the 100Base-TX EEE
Me
ability of PORT 3.
100Mbps.
5 FORCE_RX_FC_P3 PORT 3 Force RX FC
f
When (force_mode_P3 = 1), this bit is used to control the RX FC ability of
PORT 3.
o r
se
0: Disabled.
4 FORCE_TX_FC_P3
e l e a 1: Let the MAC of PORT 3 accept a pause frame when operating in full-
duplex mode.
PORT 3 Force TX FC
i a l R When (force_mode_P3 = 1), this bit is used to control the TX FC ability of
e n t i
PORT 3.
0: Disabled.
d
3:2
n f
FORCE_SPD_P3
o i n a P duplex mode with low internal free memory page count.

PORT 3 Force Speed [1:0]
k C a n a When (force_mode_P3 = 1), these bits are used to control the MAC
i a T e o r B
speed of PORT 3.
00: 10Mbps
F
01: 100Mbps
Me d1 FORCE_DPX_P3
10: 1000Mbps
11: Reserved
PORT 3 Force duplex.
When (force_mode_P3 = 1), this bit is used to control the MAC duplex of
r
PORT 3.
0: Half Duplex
1: Full Duplex
ef o
0 FORCE_LNK_P3 PORT 3 Force MAC Link Up
a s
ele
When (force_mode_P3 = 1), this bit is used to control the link status of
R
PORT 3.
t i a l 0: Link Down
1: Link Up
i d e n P i
o n f a n a
00003304
e k C B a n
PMEEECR_P3 PORT 3 MAC EEE Control Register 111E01E0
d i a T F o r

f o r
l e a se MT7531

Confidential A
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
Type
n f i d a P i
WAKEUP_TIME_1000_P3
RW
WAKEUP_TIME_100_P3
RW
Reset
Bit
0
15
C o0
14
n a
0
13
n 1
12
0
11
0
10
0
9
1
8
0
7
0
6
0
5
1
4
1
3
1
2
1
1
0
0
Name
T e k r B a LPI_THRESH_P3
LPI_M
ODE_E
a o
N_P3
d i
Type
F RW RW
Me
Reset 0 0 0 0 0 0 0 1 1 1 1 0 0
Bit(s)
31:24
Name
WAKEUP_TIME_1000_P3
Description
f o r
l e a and TXMAC can transmit packet after wakeup.
se
l R e Time unit: 1 micro second
a
e n t i The minimum allowed time needed to wait for PHY to be fully functional,
n f i d a P i and TXMAC can transmit packet after wakeup.
15:4
C o
LPI_THRESH_P3
n a n Time unit: 1 micro second

PORT 3 LPI Threshold
T e k r B a When there is no packet to be transmitted, and the idle time is greater
a
d i F o Power Idle) mode and send EEE LPI frame to the link partner.
Me

r
the link partner.
ef o
a s
l R ele
00003308
Bit 31
PMSR_P3
30
n t i
29
a 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
f i d e a P i
Reset
Bit
C o
15
n 14
n a n 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T e k r B a
ed i a F o
M
f o r
l e a se
MT7531

Confidential A
n t i a EEE100 MAC_D MAC_L

Name
f i d e a P i
EEE1G_
STS_P3
_STS_P
3
RX_FC_ TX_FC_ MAC_SPD_STS
STS_P3 STS_P3 _P3
PX_STS NK_ST
_P3 S_P3
Type
Reset
C o n n a n
RO
0
RO
0
RO
0
RO
0 0
RO
0
RO
0
RO
0
T e k r B a
d i a F o
Me
7 EEE1G_STS_P3 PORT 3 LPI Mode Status For 1000Mbps
6 EEE100_STS_P3 PORT 3 LPI Status Mode For 100Mbps
r
f o
se
5 RX_FC_STS_P3 PORT 3 RX XFC Status
e l e a Port 3 Rx flow control status

0: Disabled.
R
l
duplex mode.
4 TX_FC_STS_P3
n t i a PORT 3 TX XFC Status
f i d e a P i
0: Disabled.
n
3:2
C o
MAC_SPD_STS_P3
n a n duplex mode with low internal free memory page count.

T e k r B a Current speed of PORT 3 after PHY links up
a o
00: 10 Mbps
d i F 01: 100 Mbps
Me
10: 1000 Mbps
11: Reserved
1 MAC_DPX_STS_P3 PORT 3 duplex Status
Current duplex mode of port 3 after PHY links up

0: Half Duplex
o r
ef
1: Full Duplex
0 MAC_LNK_STS_P3 Port 3 Link Up Status
a s
ele
0: Link Down
i a l R 1: Link Up
e n t i
n f i d n a P
o
Bit
Name
k C
31 30
a n a29 28 27 26 25 24 23 22 21 20 19 18 17 16
i a T e o r B
M e d F
Page 460 of 830
f o r
l e a se MT7531

Confidential A
n t i a
e
Type
Reset
Bit 15
n
14
f i d 13
a P i
12 11 10 9 8 7 6 5 4 3 2 1 0
C o n a
n
TX_TFF TX_MIS TX_MIS TX_RP TX_RP
AGE_T
TX_GP TX_RD TX_DE
AGE_T PB_TO Q_TOU
RX_AFF
RX_AR RX_WR RX_GP
L_TOU PB_TO AGE_T
a
Name
k
_FULL_
e B
INT_EN
Type
d i
Reset
a T RW
0
F o
RW
0
r RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Me Bit(s) Name Description

15 TX_TFF_UNDR_INT_EN TXMAC TXFIFO Under run Interrupt Enable
0: Disabled
f o r
se
1: Enabled
a
e
0: Disabled
13 TX_MISPAGE_ERR_INT_EN
R e l 1: Enabled
t i a l 0: Disabled
1: Enabled
12
i d n
TX_RPAGE_ERR_INT_EN
e P i
0: Disabled
f
1: Enabled
11
C o n
TX_RPAGE_TOUT_INT_EN
a n a TX_CTRL Release Page Timeout Interrupt Enable

0: Disabled
10
e k B a n
1: Enabled
d9
i a T F o r
TX_RDPB_TOUT_INT_EN
0: Disabled
1: Enabled
Me
0: Disabled
1: Enabled
0: Disabled
r
1: Enabled
0: Disabled
ef o
s
1: Enabled
0: Disabled
1: Enabled
ele a
i a l R RX_CTRL WR_PB Timeout Interrupt Enable

0: Disabled
e n t
i
1: Enabled
n f i d n a P
0: Disabled
1: Enabled
k C o a n a
i a T e o r B
M e d F
Page 461 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
Bit
Name
31
C o30
n a
29
n 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
T e k r B a
a
Reset
d i
Bit 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
T T NT NT NT
Reset 0 0 0 0 0 0 0 0 0 0
f o
0
r 0
l e a se
e
R
t i a l 0: False
1: True
n
f i d e a P i
0: False
1: True
13
C o n
TX_MISPAGE_ERR_INT
n a n
0: False
1: True
12
T e k r B a
TX_RPAGE_ERR_INT TX_CTRL Release Page Count Error Interrupt
0: False
d
11
i a F o
TX_RPAGE_TOUT_INT
1: True
Me
0: False
1: True
0: False
1: True
o r
ef
0: False
1: True
a s
ele
0: False
1: True
3 RX_AFF_FULL_INT
i a l R RX_CTRL Agent FIFO Full Interrupt

0: False
2 RX_ARL_TOUT_INT
e n t i
1: True
RX_CTRL ARL Timeout Interrupt
d
0: False
o n f i
RX_WRPB_TOUT_INT
n a P 1: True
RX_CTRL WR_PB Timeout Interrupt
k C a n a 0: False
1: True
i a T e o r B
M e d F
Page 462 of 830
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
0
f i d e
RX_GPAGE_TOUT_INT
a P i RX_CTRL Get Page Timeout Interrupt

0: False
C o n n a n 1: True
T e k r B a
d i a F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
r
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o 1 0
se
a
Type RO RO
Reset
R e l e 0 0 0 0 0 0 0
t i a l
Bit(s)
7:4
Name
TX_FIFO_URUN
i d e n P i
Description
Underrun count of TX fifo
o n f a n a The field is increased when TX fifo underrun occurs.
C
2:0 RX_FIFO_OV Overflow count of RX fifo
e k B a n The field is increased when RX fifo overflow occurs.
d i a T F o r
Me 00003320
Bit 31
P3_WOL
30 29 28 27 26
PORT 3 WOL
25 24 23 22 21 20 19 18
00000000
17 16
o r
WOL_I WOL_S
ef
Name WOL_DBG
NT_STS TS
Type RO W1C RO
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
le a s
0
3
0
2
0
1
0
0
Name
l R e SNP_P CRC_DI WOL_I WOL_E

KT S NT_EN N
a
Type RW RW RW RW
Reset
e n t i 0 0 0 0
n f i d a P i
Bit(s)
C o
Name
n a n Description
31:18
T e k
WOL_DBG
r B a Port3 Wake-up On Lan Debug Signals
ed i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
17
16
WOL_INT_STS
WOL_STS
f i d e a P i Port3 Wake-up On Lan Interrupt Status

k a
e B
d
3
i a T SNP_PKT
F o r Port3 Wake-up On Lan with snoopy packet

0: Disable
1: Enable
Me
2 CRC_DIS Port3 Wake-up On Lan with CRC Check Disable
0: CRC check enable
r
0: Disable
0 WOL_EN
1: Enable
f o
se
0: Disable
e l e a 1: Enable
i a l R
00003324 P3_PFC_STS
e n t i
PORT 3 PFC STATUS 00000000
Bit
Name
31
n f
30
i d 29
n a P
28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
k C o a n a
Bit
Name
i a T e15
o r B
14 13 12
TX_PFC_STS
11 10 9 8 7 6 5 4
RX_PFC_STS
3 2 1 0
Me d
Type
Reset 0
F 0 0 0
RO
0 0 0 0 0 0 0 0
RO
0 0 0 0
o r
ef
15:8 TX_PFC_STS Port3 PFC TX pause on status of 8 priorities 1: pause on 0: pause off
a s
l R ele
00003330
31 30
n t i
29a
28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
e
Bit
Name
Type
n f i d a P i
Q3_RX_PSON_CNT
RC
Q2_RX_PSON_CNT
RC
Reset
Bit
0
C
15
o 0
14
n a n 0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
T e k r B a Q1_RX_PSON_CNT Q0_RX_PSON_CNT
e d i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
e
Type RC RC
Reset 0 0
n f i d 0
a P i
0 0 0 0 0 0 0 0 0 0 0 0 0
C o n a n
Bit(s)
31:24
T e k
Name
r B
Q3_RX_PSON_CNTa Description
d i
23:16
15:8
a F o
Q2_RX_PSON_CNT
Q1_RX_PSON_CNT
Me
00003334 P3_PFC_RX_PSON_CNT_H Port 3 RX PFC pause on counter for high priority

f o r
00000000
Bit
Name
31 30 29 28
e
Q7_RX_PSON_CNT
l a
27 26 25 24 23 22 21 20
Q6_RX_PSON_CNT
19
se
18 17 16
e
Type RC RC
Reset
Bit
0
15
0
14
0
13
i a l R
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
e n t Q5_RX_PSON_CNT
i
RC
Q4_RX_PSON_CNT
RC
Reset 0 0
n f i d 0
n a P
0 0 0 0 0 0 0 0 0 0 0 0 0
k C o a n a
Bit(s)
31:24
i a T e
Name
o r B
Q7_RX_PSON_CNT
Description
F
Me d
15:8
7:0
Q5_RX_PSON_CNT
Q4_RX_PSON_CNT
o r
ef
00003338 P3_PFC_RX_PSOFF_CNT_L Port 3 RX PFC pause off counter for low priority 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Type RC RC
Reset
Bit
0
15
0
14
0
13
i a l R 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
e n t Q1_RX_PSOFF_CNT
i
RC
Q0_RX_PSOFF_CNT
RC
Reset 0
n f i
0
d n
0
a P
0 0 0 0 0 0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 465 of 830
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
31:24
23:16
f i d
Q3_RX_PSOFF_CNT
Q2_RX_PSOFF_CNT
15:8
7:0
C n
Q1_RX_PSOFF_CNT
o
Q0_RX_PSOFF_CNT
n a n
T e k r B a
d i a F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RC RC
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
f o
0
1
r 0
0
se
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
e l0
e aRC
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
d
23:16
15:8
n f i
Q6_RX_PSOFF_CNT
Q5_RX_PSOFF_CNT

7:0
k C
Q4_RX_PSOFF_CNT
i a T e o r B
M e d
00003340
Bit
Name
F
31
30 29 28
Q3_TX_PSON_CNT
27 26
25 24 23 22 21 20
Q2_TX_PSON_CNT
19 18
00000000
17 16
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
ele
0
a RC
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
d
23:16
15:8
n f i
Q2_TX_PSON_CNT
Q1_TX_PSON_CNT
o n a P PFC TX pause on count for port3 priority 2

7:0
k C
Q0_TX_PSON_CNT
a n a PFC TX pause on count for port3 priority 0
i a T e o r B
M e d F
Page 466 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
00003344 P3_PFC_TX_PSON_CNT_H Port 3 TX PFC pause on counter for high priority 00000000
Bit
Name
31
C o30
n a
29
n 28
Q7_TX_PSON_CNT
27 26 25 24 23 22 21 20
Q6_TX_PSON_CNT
19 18 17 16
Type
Reset
T e0
k 0
r B a 0 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
d i a 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
23:16
15:8
7:0
Q6_TX_PSON_CNT
Q5_TX_PSON_CNT
Q4_TX_PSON_CNT
e l e a PFC TX pause on count for port3 priority 6

i a l R
e n t i
00003348
n f i d a P
n
Port 3 TX PFC pause off counter for low priority 00000000
Bit
Name
31
k C o30
a n a
29 28
Q3_TX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q2_TX_PSOFF_CNT
19 18 17 16
e B
Type RC RC
Reset
Bit
d i a T 0
15
F o
0
r
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
a s
ele
i a l R
e n t i
0000334C
n f i d a P
n
Port 3 TX PFC pause off counter for high priority 00000000
Bit
Name
k
31
C o 30
a n a
29 28
Q7_TX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q6_TX_PSOFF_CNT
19 18 17 16
i a T e o r B
M e d F
Page 467 of 830
f o r
l e a se
MT7531

Confidential A
n t i a
e
Type RC RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q4_TX_PSOFF_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q7_TX_PSOFF_CNT
Q6_TX_PSOFF_CNT
Q5_TX_PSOFF_CNT
Description
f o r
l e a se
00003400 PMCR_P4
l R e PORT 4 MAC Control Register 00056330
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
t i
n
e
IPG_CFG_P4
EXT_PH
MAC_
MODE
i
Type
P4
RW
4
n
RW
f i
P4
d _P4
RW
n P
_P4
a RW
0_P4 _P4
RW RW RW RW RW
_P4
RW
Reset
Bit
0
k
15
C o 0
14
a n a
0
13
0
12
0
11
0
10
0
9 8 7 6 5 4
0
3
1
2
0
1
1
0
Name
i a T e r B
MAC_T MAC_R
X_EN_ X_EN_
o
MAC_P
RE_P4
BKOFF_
EN_P4
F
P4 P4 P4 _P4 0_P4 _P4 _P4 P4 P4
Me d
Type
Reset
RW
1
RW
1
RW
0
RW
1
RW
1
RW
0
RW
0
RW
1
RW
1 0
RW
0
RW
0
RW
0
o r
ef
module)
a s
ele
register)
i a l R PORT 4 speed force Mode.

e n t i
module)
d
o n f i n a P 0: Force mode is off.(Mac duplex mode is determined by phy auto-polling

module)
k C a n a 1: Force mode is on. (Mac duplex mode is determined by force_dpx_P4

register)
e B
d i a T F o r

f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: Force mode is off.(Mac RX FC ability is determined by phy auto-polling

module)
27
C o n n a
FORCE_MODE_TX_FC_P4 n
register)
T e k r B a 0: Force mode is off.(Mac TX FC ability is determined by phy auto-polling

module)
d i a F o 1: Force mode is on. (Mac TX FC ability is determined by force_tx_fc_P4

register)
Me
polling module)
r
polling module)
f o
se
19:18 IPG_CFG_P4
e l e a force_eee1g_P4 register)
i a l R 01: Transmit 96-bits IFG with short IFG in random behavior

10: shrink 64-bits IFG
17 EXT_PHY_P4
e n t i
PORT 4 External PHY
n f i d n a P
Port 4 connects with external PHY.
o
16
C
MAC_MODE_P4
k a n a PORT 4 MAC Mode
i a T e o r B PORT 4 operates in MAC mode.

Me d
14
F
MAC_TX_EN_P4
0: TX MAC function is disabled.
1: TX MAC function is enabled.
13 MAC_RX_EN_P4 PORT 4 RX MAC Enable (Note: This bit only has impact on MAC function,
o r
ef
0: RX MAC function is disabled.
1: RX MAC function is enabled.
a s
ele
0: TX short preamble length is disabled.
R
t i a l 0: Disabled
n
happens.
8 BACKPR_EN_P4
f i d e a P i
0: Disabled
n
C o
FORCE_EEE1G_P4
n a n with low internal free memory page count.

T e k r B a bit is used to control the 1000Base-T EEE ability of PORT 4.
e d i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 0: Do not have the ability of entering EEE Low Power Idle mode for
1000Mbps.
C o n
FORCE_EEE100_P4
n a n
a
bit is used to control the 100Base-TX EEE ability of PORT 4.
T e k r B
100Mbps.
d5
i a F o
FORCE_RX_FC_P4
PORT 4 Force RX FC
Me When (force_mode_P4 = 1), this bit is used to control the RX FC ability of

PORT 4.
0: Disabled.
4 FORCE_TX_FC_P4
duplex mode.
PORT 4 Force TX FC
f o r
l e a PORT 4.
se
When (force_mode_P4 = 1), this bit is used to control the TX FC ability of
l R e 0: Disabled.
a
3:2 FORCE_SPD_P4
e n t i PORT 4 Force Speed [1:0]
n f i d a P i When (force_mode_P4 = 1), these bits are used to control MAC speed of
PORT 4.
n
00: 10Mbps
k C o a n a 01: 100Mbps
10: 1000Mbps
e B
11: Reserved
d
1
i a T F o r
FORCE_DPX_P4 PORT 4 Force duplex
Me
When (force_mode_P4 = 1), this bit is used to control MAC duplex of
PORT 4.
0: Half Duplex
1: Full Duplex
0 FORCE_LNK_P4 PORT 4 Force MAC Link Up
o r
ef
When (force_mode_P4 = 1), this bit is used to control link status of PORT
4.
0: Link Down
1: Link Up
a s
l R ele
n t i a
00003404
Bit 31
f
30
i e
PMEEECR_P4
d 29
a P i 28 27 26
25 24 23 22 21 20 19 18
111E01E0
17 16
Name
Type
C o n n a n
WAKEUP_TIME_1000_P4
RW
WAKEUP_TIME_100_P4
RW
k a
Reset 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 0
i a T e o r B
M e d F
Page 470 of 830
f o r
l e a se
MT7531

Confidential A
15 14
n
13
t i a 12 11 10 9 8 7 6 5 4 3 2 1 0
e
Bit
Name
n f i d a P i LPI_THRESH_P4
LPI_M
ODE_E
n
N_P4
Type
Reset 0
k C o0
a n a
0 0 0 0
RW
0 1 1 1 1 0
RW
0
i a T e o r B
Me d
Bit(s)
31:24
NameF
WAKEUP_TIME_1000_P4
Description
f o r
se
23:16 WAKEUP_TIME_100_P4 PORT 4 Wake Up Time for 100Mbps LPI Mode
e l e a The minimum allowed time needed to wait for PHY to be fully functional,
R
t i a l Time unit: 1 micro second
n
15:4 LPI_THRESH_P4 PORT 4 LPI Threshold
f i d e a P i When there is no packet to be transmitted, and the idle time is greater
C o n
LPI_MODE_EN_P4
n a n
PORT 4 Enter LPI Mode.
T e k r B a When there is no packet to be transmitted, and the idle time is greater
d i a F o than P4_LPI_THRESHOLD, the TXMAC will automatically enter LPI (Low

Me
the link partner.
o r
00003408 PMSR_P4 PORT 4 MAC Status Register
a s ef00000000
le
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
l R e
Reset
Bit 15 14
n t i
13
a 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
f i d e a P i EEE1G_
STS_P4
EEE100
_STS_P
STS_P4 STS_P4 _P4
MAC_D MAC_L
PX_STS NK_ST
Type
C o n n a n RO
4
RO RO RO
_P4 S_P4
RO RO RO
k a
Reset 0 0 0 0 0 0 0 0
i a T e o r B
Med F
Page 471 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
7
o
EEE1G_STS_P4
C n a n PORT 4 LPI Mode Status For 1000Mbps

T e k B
EEE100_STS_P4
r a 1: Capable of entering EEE Low Power Idle mode for 1000Mbps.

a o
d i F 1: Capable of entering EEE Low Power Idle mode for 100Mbps.
Me
5 RX_FC_STS_P4 PORT 4 RX XFC Status
Port 4 Rx flow control status

0: Disabled.
4 TX_FC_STS_P4
duplex mode
f o r
l e a
0: Disabled.
se
e
3:2 MAC_SPD_STS_P4
i a l R duplex mode with low internal free memory page count.

e n t i
Current speed of PORT 4 after PHY links up
00: 10 Mbps
n f i d n a P 01: 100 Mbps

10: 1000 Mbps
1
C o
MAC_DPX_STS_P4
k a n a 11: Reserved
i a T e o r B Current duplex mode of PORT 4 after PHY links up
F
0: Half Duplex
Me d0 MAC_LNK_STS_P4
1: Full Duplex
Port 4 Link Up Status

0: Link Down
r
1: Link Up
ef o
a s
00003410
31
PINT_EN_P4
30 29
l R 28 27 26
25 24 23 ele 00000000
a
Bit 22 21 20 19 18 17 16
Name
Type
e n t i
Reset
Bit 15
n f i d
14
a
13
P i 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
C o n a n
TX_TFF TX_MIS TX_MIS TX_RP TX_RP TX_GP TX_RD TX_DE
RX_AFF
_FULL_
RX_AR RX_WR RX_GP
k a
_UNDR VLAN_ PAGE_ AGE_E AGE_T AGE_T PB_TO Q_TOU L_TOU PB_TO AGE_T
INT_EN
i a T e o r B
Med F
Page 472 of 830
f o r
l e a seMT7531

Confidential A
n t i a
Type RW
N
RW
f i d e RW
a P i
T_EN T_EN _EN NT_EN NT_EN _EN
RW RW RW
EN
RW RW RW
EN
RW
_EN NT_EN
RW RW
Reset 0
C o n0
n a
0
n 0 0 0 0 0 0 0 0 0
T e k r B a
i a
Bit(s)
d
Name
F o Description
Me
15 TX_TFF_UNDR_INT_EN TXMAC TXFIFO Under run Interrupt Enable
0: Disabled
1: Enabled
0: Disabled
r
1: Enabled
f o
se
0: Disabled
1: Enabled
e l e a TX_CTRL Release Page Count Error Interrupt Enable

0: Disabled
R
1: Enabled
t i a l TX_CTRL Release Page Timeout Interrupt Enable

0: Disabled
n
1: Enabled
10
f i d e
a P i
0: Disabled
n
1: Enabled
9
o a
TX_RDPB_TOUT_INT_EN
C n n TX_CTRL RD_PB Timeout Interrupt Enable

0: Disabled
T e k r B a
TX_DEQ_TOUT_INT_EN
1: Enabled
d i a F o
0: Disabled
1: Enabled
Me
0: Disabled
1: Enabled
0: Disabled
1: Enabled
o r
ef
0: Disabled
1: Enabled
a s
ele
0: Disabled
i a l R 1: Enabled
e n t i
n f i d n a P
o
Bit
Name
k C
31 30
a n a 29 28 27 26 25 24 23 22 21 20 19 18 17 16
i a T e o r B
M e d F
Page 473 of 830
f o r
l e a se MT7531

Confidential A
n t i a
e
Type
Reset
Bit 15
n
14
f i d 13
a P i
12 11 10 9 8 7 6 5 4 3 2 1 0
TX_TFF
o
TX_MIS TX_MIS
C
VLAN_ PAGE_
n a n
TX_RP
TX_RP TX_GP
AGE_T AGE_T
TX_RD TX_DE RX_AFF RX_AR RX_WR
RX_GP
AGE_T
a
Name _UNDR
k
AGE_E PB_TO Q_TOU _FULL_ L_TOU PB_TO
e B
T T NT NT NT
Type
d i
Reset
a T RO
0
F o0
r
RO RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Me Bit(s) Name Description

0: False
f o r
se
1: True
a
e
0: False
13 TX_MISPAGE_ERR_INT
R e l 1: True
t i a l 0: False
1: True
12 TX_RPAGE_ERR_INT
i d e n P i
0: False
f
1: True
11
C o n
TX_RPAGE_TOUT_INT
a n a TX_CTRL Release Page Timeout Interrupt

0: False
10
e k B a n
TX_GPAGE_TOUT_INT
1: True
TX_CTRL Get Page Timeout Interrupt
d9
i a T F o r
TX_RDPB_TOUT_INT
0: False
1: True
TX_CTRL RD_PB Timeout Interrupt
Me
0: False
1: True
0: False
r
1: True
3 RX_AFF_FULL_INT RX_CTRL Agent FIFO Full Interrupt
0: False
ef o
s
1: True
0: False
1: True
ele a
1 RX_WRPB_TOUT_INT
i a l R RX_CTRL WR_PB Timeout Interrupt

0: False
e
RX_GPAGE_TOUT_INT
n t i
1: True
RX_CTRL Get Page Timeout Interrupt
n f i d n a P
0: False
1: True
k C o a n a
i a T e o r B
M e d F
Page 474 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
Bit
Name
31
C o30
n a n
29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
T e k r B a
a
Reset
d i
Bit 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
Type RO RO
Reset 0 0 0 0 0 0 0
f o r
se
7:4 TX_FIFO_URUN
e l e a Underrun count of TX fifo
The field is increased when TX fifo underrun occurs.

2:0 RX_FIFO_OV
i a l R Overflow count of RX fifo
e n t i
The field is increased when RX fifo overflow occurs.
n f i d n a P
00003420
k C o
P4_WOL
a n a PORT 4 WOL 00000000

Bit
i a T e31
o r
30
B 29 28 27 26 25 24 23 22 21 20 19 18 17
WOL_I WOL_S
16
F
Name WOL_DBG
Me d
Type
Reset
Bit
0
15 14
0 0
13
0
12
0
11
0
10
0
9
RO
0
8
0
7
0
6
0
5
0
4
0
3
0
2
NT_STS TS
W1C
0
1
RO
0
0
Name
r
KT S NT_EN N
Type
Reset
RW
0
RW
0
RW
ef
0
o RW
0
a s
Bit(s) Name
l R Description
ele
31:18
17
WOL_DBG
WOL_INT_STS
n t i a Port4 Wake-up On Lan Debug Signals

e
16 WOL_STS Port4 Wake-up On Lan Status
n f i d a P i If enable WOL_EN, this bit will change from 0 to 1 when GMAC RX state
C o n a n machine enter IDLE state. It indicates GMAC will drop all packets and
k a
3 SNP_PKT Port4 Wake-up On Lan with snoopy packet
i a T e o r B
M e d F
Page 475 of 830
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
1: Enable
2
C o
CRC_DIS
n n a n Port4 Wake-up On Lan with CRC Check Disable

0: CRC check enable
k a
1
i a T e
WOL_INT_EN
o r B Port4 Wake-up On Lan Interrupt Enable

0: Disable
F
1: Enable
Me d0 WOL_EN Port4 Wake-up On Lan Function Enable

0: Disable
1: Enable
f o r
00003424
Bit 31
P4_PFC_STS
30 29 28
l e a 27 26
PORT 4 PFC STATUS
25 24 23 22 21 20 19
se
18
00000000
17 16
Name
Type
l R e
Reset
Bit 15 14
n t
13
i a 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
f i d e a P i
TX_PFC_STS
RO
RX_PFC_STS
RO
Reset 0
C o n 0
n a n
0 0 0 0 0 0 0 0 0 0 0 0 0 0
T e k r B a
d i
15:8
a
Bit(s) Name
F o
TX_PFC_STS
Description
Me
o r
ef
00003430 P4_PFC_RX_PSON_CNT_L Port 4 RX PFC pause on counter for low priority 00000000
s
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
Q3_RX_PSON_CNT
RC
ele a
Q2_RX_PSON_CNT
RC
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14
t
13
i a l 12
Q1_RX_PSON_CNT
11 10 9 8 7 6 5 4
Q0_RX_PSON_CNT
3 2 1 0
Type
Reset 0 0
i d e n 0
P i 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
o n f a n a
e k C B a n
d i a T F o r

f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
31:24
23:16
Q3_RX_PSON_CNT
f i
Q2_RX_PSON_CNT
d e a P i PFC RX pause on count for port4 priority 3
15:8
7:0
C n
Q1_RX_PSON_CNT
o
Q0_RX_PSON_CNT
n a n
T e k r B a
d i a F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RC RC
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
f o
0
1
r 0
0
se
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
e l0
e aRC
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
d
23:16
15:8
n f i
Q6_RX_PSON_CNT
Q5_RX_PSON_CNT
o n a P PFC RX pause on count for port4 priority 6

7:0
k C
Q4_RX_PSON_CNT
a n a PFC RX pause on count for port4 priority 4
i a T e o r B
M e d
00003438
Bit
Name
F
31
30 29 28
Q3_RX_PSOFF_CNT
27 26
25 24 23 22 21 20
Q2_RX_PSOFF_CNT
19 18
00000000
17 16
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
s
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0
ele
0
a RC
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
d
23:16
15:8
n f i
Q2_RX_PSOFF_CNT
Q1_RX_PSOFF_CNT

7:0
k C
Q0_RX_PSOFF_CNT
i a T e o r B
M e d F
Page 477 of 830
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
Bit
Name
31
C o30
n a
29
n 28
Q7_RX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q6_RX_PSOFF_CNT
19 18 17 16
Type
Reset
T e0
k 0
r B a 0 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
d i a 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
23:16
15:8
7:0
Q6_RX_PSOFF_CNT
Q5_RX_PSOFF_CNT
Q4_RX_PSOFF_CNT
e l e a PFC RX pause off count for port4 priority 6

i a l R
e n t i
00003440
n f i d a
n P Port 4 TX PFC pause on counter for low priority 00000000

Bit
Name
31
k C o30
a n a
29 28
Q3_TX_PSON_CNT
27 26 25 24 23 22 21 20
Q2_TX_PSON_CNT
19 18 17 16
e B
Type RC RC
Reset
Bit
d i a T 0
15
F o
0
r
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
a s
ele
i a l R
e n t i
00003444
n f i d a P
n
Bit
Name
k
31
C o 30
a n a
29 28
Q7_TX_PSON_CNT
27 26 25 24 23 22 21 20
Q6_TX_PSON_CNT
19 18 17 16
i a T e o r B
M e d F
Page 478 of 830
f o r
l e a se MT7531

Confidential A
n t i a
e
Type RC RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q4_TX_PSON_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q7_TX_PSON_CNT
Q6_TX_PSON_CNT
Q5_TX_PSON_CNT
Description
f o r
l e a se
00003448 P4_PFC_TX_PSOFF_CNT_L
l R e Port 4 TX PFC pause off counter for low priority 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e n t i
Q3_TX_PSOFF_CNT
RC
Q2_TX_PSOFF_CNT
RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q0_TX_PSOFF_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q3_TX_PSOFF_CNT
Q2_TX_PSOFF_CNT
Q1_TX_PSOFF_CNT
Description
o r
a s ef
0000344C
R
l
ele 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e n t i Q7_TX_PSOFF_CNT
RC
Q6_TX_PSOFF_CNT
RC
Reset
Bit
0
15
n f i
0
14
d 0
13
a P i 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q4_TX_PSOFF_CNT
RC
Reset
T e k 0
r B
0
a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ed i a F o
M
f o r
l e a se
MT7531

Confidential A
n t i a
f i d e a P i
n
31:24
23:16
C o
Q7_TX_PSOFF_CNT
Q6_TX_PSOFF_CNT
n a n PFC TX pause off count for port4 priority 7

15:8
7:0
T k r B a
Q5_TX_PSOFF_CNT
e
Q4_TX_PSOFF_CNT
d i a F o
Me 00003500
Bit 31
PMCR_P5
30 29 28 27 26
25 24 23 22 21 20 19 18
00056330
17 16
Name
IPG_CFG_P5
f o r
EXT_PH
MAC_
MODE
se
_P5
P5 5 P5 _P5 _P5 0_P5 _P5
Type
Reset
RW
0
RW
0
RW
0
RW
0
e l e a
RW
0
RW
0
RW
0 0
RW
1
RW
0
RW
1
Bit 15 14
MAC_T MAC_R
13
i a l R
12 11
MAC_P
10 9
BKOFF_
8 7 6
BACKP FORCE FORCE FORCE FORCE
5 4 3
FORCE FORCE
2 1 0
Name X_EN_ X_EN_

P5 P5
e n t i
RE_P5 EN_P5
P5 _P5 0_P5 _P5 _P5 P5 P5
d
Reset
o
1
n f i 1
n a P 0 1 1 0 0 1 1 0 0 0 0
k C a n a
Bit(s)
i a T e
Name
o r B Description
F
Me d 0: Force mode is off.(Mac link status is determined by phy auto-polling

module)
register)
module)
o r
ef
a s
ele
module)
28 FORCE_MODE_RX_FC_P5
i a l R register)
PORT 5 RX FC force Mode.
e n t i
module)
27
n f i d
FORCE_MODE_TX_FC_P5
n a P
register)
o
k C a n a module)
i a T e o r B
M e d F
Page 480 of 830
f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 1: Force mode is on. (Mac TX FC ability is determined by force_tx_fc_P5

register)
26
C o n
n a n
PORT 5 100M EEE force Mode.
polling module)
T e k r B a 1: Force mode is on. (Mac 100M EEE ability is determined by

25
d i a o
FORCE_MODE_EEE1G_P5
F
PORT 5 1G EEE force Mode.
Me
polling module)
19:18 IPG_CFG_P5 PORT 5 Inter-Frame+ Gap Shrink
f o r
se
17 EXT_PHY_P5 PORT 5 External PHY
e l e a Port 5 connects with external PHY.

0: PORT 5 DOES NOT connect with external PHY.
16 MAC_MODE_P5
i a l R 1: PORT 5 connects with external PHY.

PORT 5 MAC Mode
e n t i
PORT 5 operates in MAC mode.
d
0: PORT 5 operates in PHY mode.
14
n f
MAC_TX_EN_P5
o i n a P 1: PORT 5 operates in MAC mode.

k C a n a and it has no impact on the link status or Queue manager.)

e B
1: TX MAC function is enabled.
13
d i a T F o r
MAC_RX_EN_P5 PORT 5 RX MAC Enable (Note: This bit only has impact on MAC function,
0: RX MAC function is disabled.
Me
0: Disabled
o r
ef
s
happens.
a
ele
0: Disabled
7 FORCE_EEE1G_P5
i a l R with low internal free memory page count.

e n t i
When (force_mode_P5 = 1), this bit is used to control the 1000Base-T EEE
d
ability of PORT 5.
o n f i n a P 0: Do not have the ability of entering EEE Low Power Idle mode for
1000Mbps
a
1: Have the ability of entering EEE Low Power Idle mode for 1000Mbps
e k C B a n
d i a T F o r

f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
6
d
FORCE_EEE100_P5
f i e a P i PORT 5 Force LPI Mode For 100Mbps
C o n n a n When (force_mode_P5 = 1), this bit is used to control the 100Base-TX EEE
ability of PORT 5.
k a
e B
100Mbps
d
5
i a T o r
FORCE_RX_FC_P5
F
1: Have the ability of entering EEE Low Power Idle mode for 100Mbps
PORT 5 Force RX FC
Me
When (force_mode_P5 = 1), this bit is used to control the RX FC ability of
PORT 5.
0: Disabled.
r
duplex mode.
o
4 FORCE_TX_FC_P5 PORT 5 Force TX FC
se f
When (force_mode_P5 = 1), this bit is used to control the TX FC ability of
e l e a PORT 5.
0: Disabled.
3:2 FORCE_SPD_P5
i a l R duplex mode with low internal free memory page count.

e n t i
When (force_mode_P5 = 1), these bits are used to control MAC speed of
d
PORT 5.
o n f i n a P 00: 10Mbps
01: 100Mbps
k C a n a 10: 1000Mbps
11: Reserved
1
i a T e o r B
FORCE_DPX_P5 PORT 5 Force duplex
Me d0
F
FORCE_LNK_P5
When (force_mode_P5 = 1), this bit is used to control MAC duplex of
PORT 5.
0: Half Duplex
1: Full Duplex
PORT 5 Force MAC Link Up
o r
ef
5.
0: Link Down
1: Link Up
a s
l R ele
00003504 PMEEECR_P5
n t i a PORT 5 MAC EEE Control Register 111E01E0

Bit
Name
31 30
f i d e 29
a P i28
WAKEUP_TIME_1000_P5
27 26 25 24 23 22 21 20
WAKEUP_TIME_100_P5
19 18 17 16
Type
Reset 0
C o n0
n a n
0 1
RW
0 0 0 1 0 0 0 1
RW
1 1 1 0
Bit
T e k15
r
14
B a 13 12 11 10 9 8 7 6 5 4 3 2 1 0
e d i a F o
M
f o r
l e a se
MT7531

Confidential A
n t i a LPI_M
Name
f i d e a P i LPI_THRESH_P5 ODE_E
N_P5
Type
Reset 0
C o0
n n a
0
n 0 0 0
RW
0 1 1 1 1 0
RW
0
T e k r B a
d i a F o
Me
f o r
se
e l e a The minimum allowed time needed to wait for PHY to be fully functional,
15:4 LPI_THRESH_P5
i a l R Time unit: 1 micro second

e n t i
n f i d n a P than P5_LPI_THRESHOLD, the TXMAC will automatically enter LPI (Low

0
k C o
LPI_MODE_EN_P5
a n a
PORT 5 Enter LPI Mode
i a T e o r B than P5_LPI_THRESHOLD, the TXMAC will automatically enter LPI (Low

Me d F 0: LPI mode depends on the P5_LPI_THRESHOLD.

the link partner.
o r
00003508
Bit 31
PMSR_P5
30 29 28 27 26
25 24 23 22 21 20
a s 19 18
ef00000000
17 16
ele
Name
R
Type
Reset
Bit 15 14
t
13
i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
EEE1G_
STS_P5
EEE100
_STS_P
STS_P5 STS_P5 _P5
MAC_D MAC_L
PX_STS NK_ST
f
5 _P5 S_P5
Type
Reset
C o n a n a RO
0
RO
0
RO
0
RO
0 0
RO
0
RO
0
RO
0
e k B a n
d i a T F o r

f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
7
o
EEE1G_STS_P5
C n a n PORT 5 LPI Mode Status For 1000Mbps

T e k B
EEE100_STS_P5
r a 1: Capable of entering EEE Low Power Idle mode for 1000Mbps

a o
d i F 1: Capable of entering EEE Low Power Idle mode for 100Mbps
Me
5 RX_FC_STS_P5 PORT 5 RX XFC Status. Port 5 Rx flow control status
0: Disabled.
duplex mode.
4 TX_FC_STS_P5 PORT 5 TX XFC Status
f o r
se
0: Disabled.
a
1: Let the MAC of PORT 5 to transmit a pause frame when operating in
e
full-duplex mode with low internal free memory page count.
3:2 MAC_SPD_STS_P5
R e l PORT 5 Speed [1:0] Status
t i a l Current speed of PORT 5 after PHY links up.

00: 10 Mbps
n
01: 100 Mbps
f i d e a P i
10: 1000 Mbps
11: Reserved
1
n
MAC_DPX_STS_P5
C o n a n
a
Current duplex mode of port 5 after PHY links up
T e k r B
0: Half Duplex
1: Full Duplex
d
0
i a o
MAC_LNK_STS_P5
F
Port 5 Link Up Status. Link up status of PORT 5.
0: Link Down
Me
1: Link Up
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Name
Type
Reset
Bit 15 14
i
13
a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
e n t
i
TX_RP
AGE_T
TX_GP TX_RD TX_DE
AGE_T PB_TO Q_TOU
RX_AFF
RX_AR RX_WR RX_GP
L_TOU PB_TO AGE_T
d
Name _FULL_
i P
f
INT_EN
a
Type
Reset
C o
RW
0
n RW
0
n a n RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
T e k r B a
ed i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
15
o
TX_TFF_UNDR_INT_EN
C n a n TXMAC TXFIFO Under run Interrupt Enable

0: Disabled
14
T e k B a
r
1: Enabled
a o
0: Disabled
d i F 1: Enabled
Me
0: Disabled
1: Enabled
12 TX_RPAGE_ERR_INT_EN TX_CTRL Release Page Count Error Interrupt Enable
0: Disabled
1: Enabled
f o r
se
0: Disabled
a
1: Enabled
10 TX_GPAGE_TOUT_INT_EN
R e l e TX_CTRL Get Page Timeout Interrupt Enable

0: Disabled
1: Enabled
9 TX_RDPB_TOUT_INT_EN
t i a l TX_CTRL RD_PB Timeout Interrupt Enable

0: Disabled
d e
TX_DEQ_TOUT_INT_EN
i n P i
1: Enabled
f
0: Disabled
C o n
RX_AFF_FULL_INT_EN
a n a 1: Enabled
e k B a n 0: Disabled
1: Enabled
d
2
i a T F o r
RX_ARL_TOUT_INT_EN RX_CTRL ARL Timeout Interrupt Enable
0: Disabled
1: Enabled
Me
0: Disabled
1: Enabled
r
0: Disabled
1: Enabled
ef o
a s
00003514 PINT_STS_P5
l R PORT 5 Interrupt Status Register

ele 00000000
Bit
Name
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
f i d e a P i
Bit 15
C o n14
n a n
13 12 11 10 9 8 7 6 5 4 3 2 1 0
T e k r B a
e d i a F o
M
f o r
l e a seMT7531

Confidential A
TX_MIS TX_MIS
n t i a
TX_RP TX_GP RX_GP
TX_TFF
Name _UNDR
_INT
VLAN_ PAGE_
f i d
ERR_IN ERR_IN
e
TX_RP
AGE_E
RR_INT
P i
AGE_T AGE_T
OUT_I OUT_I
a
TX_RD TX_DE
PB_TO Q_TOU
RX_AFF RX_AR RX_WR
_FULL_ L_TOU PB_TO
AGE_T
OUT_I
n
UT_INT T_INT INT T_INT UT_INT
n
T T NT NT NT
Type
Reset
RO
0
k C oRO
0
a n a
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
i a T e o r B
Me d
Bit(s)
15
Name
F
TX_TFF_UNDR_INT
Description
TXMAC TXFIFO Under run Interrupt
0: False
1: True
r
0: False
1: True
f o
se
12 TX_RPAGE_ERR_INT
e l e a 0: False
1: True
i a l R 0: False
1: True
e n t i
0: False
10
n f i d
TX_GPAGE_TOUT_INT
n a P
1: True
o
0: False
k C a
TX_RDPB_TOUT_INT
n a 1: True
1: True
Me d
8
3
F
TX_DEQ_TOUT_INT
RX_AFF_FULL_INT
TX_CTRL DEQ Timeout Interrupt
0: False
1: True
0: False
1: True
o r
ef
0: False
1: True
a s
ele
0: False
1: True
R
t i a l 0: False
1: True
i d e n P i
o n f a n a
00003518
e k C B a n
P5_DBG_CNT PORT 5 DEBUG COUNT 00000000
d i a T F o r

f o r
l e a se MT7531

Confidential A
31 30
n t
29
i a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
Type
n f i d a P i
Reset
C o n a n
a
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
k
Bit
Name
Type
i a T e o r B TX_FIFO_URUN
RO
RX_FIFO_OV
RO
Me d
Reset
F 0 0 0 0 0 0 0

7:4 TX_FIFO_URUN Underrun count of TX fifo. The field is increased when TX fifo underrun
occurs.
f o r
se
2:0 RX_FIFO_OV Overflow count of RX fifo. The field is increased when RX fifo overflow
occurs.
e l e a
i a l R
00003520
Bit 31
P5_WOL
30
e n t
29
i
28 27 26
PORT 5 WOL
25 24 23 22 21 20 19 18
00000000
17 16
Name
n f i d n a P WOL_DBG
WOL_I WOL_S
NT_STS TS
Type
Reset 0
k C o 0
a n a 0 0 0 0 0
RO
0 0 0 0 0 0 0
W1C
0
RO
0
Bit
Name
i a T e15
o r B
14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
F
KT S NT_EN N
Me d
Type
Reset
RW
0
RW
0
RW
0
RW
0
o r
ef
31:18 WOL_DBG Port5 Wake-up On Lan Debug Signals
17
16
WOL_INT_STS
WOL_STS
a s
l R ele
3 SNP_PKT
n t i a detect magic packet.

e
0: Disable
n
CRC_DIS
f i d a P i 1: Enable
C o n a n 0: CRC check enable

1
T e k
WOL_INT_EN
r B a Port5 Wake-up On Lan Interrupt Enable
e d i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
1: Enable
0 WOL_EN
C o n n a n Port5 Wake-up On Lan Function Enable

0: Disable
k a
1: Enable
i a T e o r B
Me d
00003524
Bit 31
F P5_PFC_STS
30 29 28 27 26
PORT 5 PFC STATUS
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
f o r
se
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e l e
RO
a
TX_PFC_STS RX_PFC_STS
RO
Reset 0 0 0
i a l R0 0 0 0 0 0 0 0 0 0 0 0 0
e n t i
Bit(s)
15:8
Name
n
TX_PFC_STS
7:0
k C o
RX_PFC_STS
a n a
i a T e o r B
Me d
00003530
Bit
Name
31
F P5_PFC_RX_PSON_CNT_L
30 29 28
Q3_RX_PSON_CNT
27 26
25 24 23 22 21 20
Q2_RX_PSON_CNT
19 18
00000000
17 16
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Type
Reset 0 0 0 0
RC
0 0 0 0 0 0 0 0
RC
le a s
0 0 0 0
l R e
Bit(s) Name
n t i a Description
31:24
23:16
f i d e
Q3_RX_PSON_CNT
Q2_RX_PSON_CNT
a P i PFC RX pause on count for port5 priority 3

15:8
7:0
C n
Q1_RX_PSON_CNT
o n a
Q0_RX_PSON_CNT
n
T e k r B a
ed i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
Bit
Name
31
C o30
n a
29
n 28
Q7_RX_PSON_CNT
27 26 25 24 23 22 21 20
Q6_RX_PSON_CNT
19 18 17 16
Type
Reset
T e0
k 0
r B a 0 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
d i a 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
23:16
15:8
7:0
Q6_RX_PSON_CNT
Q5_RX_PSON_CNT
Q4_RX_PSON_CNT
e l e a PFC RX pause on count for port5 priority 6

i a l R
e n t i
00003538
n f i d a P
n
Port 5 RX PFC pause off counter for low priority 00000000
Bit
Name
31
k C o30
a n a
29 28
Q3_RX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q2_RX_PSOFF_CNT
19 18 17 16
e B
Type RC RC
Reset
Bit
d i a T 0
15
F o
0
r
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
a s
ele
i a l R
e n t i
0000353C
n f i d a P
n
Port 5 RX PFC pause off counter for high priority 00000000
Bit
Name
k
31
C o 30
a n a
29 28
Q7_RX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q6_RX_PSOFF_CNT
19 18 17 16
i a T e o r B
M e d F
Page 489 of 830
f o r
l e a se MT7531

Confidential A
n t i a
e
Type RC RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
C o n a n Q5_RX_PSOFF_CNT
RC
Q4_RX_PSOFF_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q7_RX_PSOFF_CNT
Q6_RX_PSOFF_CNT
Q5_RX_PSOFF_CNT
Description
f o r
l e a se
00003540 P5_PFC_TX_PSON_CNT_L
l R e Port 5 TX PFC pause on counter for low priority 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e n t i
Q3_TX_PSON_CNT
RC
Q2_TX_PSON_CNT
RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q0_TX_PSON_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q3_TX_PSON_CNT
Q2_TX_PSON_CNT
Q1_TX_PSON_CNT
Description
o r
a s ef
00003544
R
l
ele 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e n t i Q7_TX_PSON_CNT
RC
Q6_TX_PSON_CNT
RC
Reset
Bit
0
15
n f i
0
14
d 0
13
a P i 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q4_TX_PSON_CNT
RC
Reset
T e k 0
r B
0
a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ed i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
31:24
23:16
C o
Q7_TX_PSON_CNT
Q6_TX_PSON_CNT
n a n PFC TX pause on count for port5 priority 7

15:8
7:0
T k
Q5_TX_PSON_CNT
e r B
Q4_TX_PSON_CNT
a PFC TX pause on count for port5 priority 5
d i a F o
Me 00003548
Bit 31
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Q3_TX_PSOFF_CNT
RC
Q2_TX_PSOFF_CNT
RC
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
l e a
Q1_TX_PSOFF_CNT
e
11 10 9 8 7 6 5 4
Q0_TX_PSOFF_CNT
3 2 1 0
R
Type RC RC
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
i d e n P i
Bit(s)
31:24
Name
o n f
Q3_TX_PSOFF_CNT
a n a Description
23:16
15:8
7:0 C
Q2_TX_PSOFF_CNT
k a
Q1_TX_PSOFF_CNT
e B
Q0_TX_PSOFF_CNT n
d i a T F o r
Me 0000354C
Bit 31
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
o r
ef
Type RC RC
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
Q5_TX_PSOFF_CNT
11 10 9 8 7 6 5
ele
4
a
Q4_TX_PSOFF_CNT
3 2 1 0
R
Type RC RC
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
i d e n P i
Bit(s)
31:24
Name
o n f
Q7_TX_PSOFF_CNT
a n a Description
23:16
15:8
e k C n
Q6_TX_PSOFF_CNT
a
Q5_TX_PSOFF_CNT
B
d i a T F o r

f o r
l e a se
MT7531

Confidential A
Bit(s) Name
n t i a Description
7:0
f i d
Q4_TX_PSOFF_CNT
e a P i PFC TX pause off count for port5 priority 4
C o n n a n
00003600
T e k r B
PMCR_P6 a PORT 6 MAC Control Register 00056330
d i
Bit
a 31
F o30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
MAC_
_P6
P6 6 P6 _P6 _P6 0_P6 _P6
Type RW RW RW RW RW RW RW RW RW RW
Reset
Bit
0
15
0
14
0
13
0
12
0
11
0
10
0
9 8 7 6 5 4
0
3
1
2
f o
0
1
r 1
0
se
MAC_T MAC_R BACKP FORCE FORCE FORCE FORCE FORCE FORCE
MAC_P BKOFF_
a
RE_P6 EN_P6
e
P6 P6 P6 _P6 0_P6 _P6 _P6 P6 P6
Type
Reset
RW
1
RW
1
R e l RW
0
RW
1
RW
1
RW
0
RW
0
RW
1
RW
1 0
RW
0
RW
0
RW
0
t i a l
i d e n P i
Bit(s)
31
Name
n f
FORCE_MODE_LNK_P6
o a n a
Description
PORT 6 link status force Mode.
C
e k B a n module)
T r
register)
30
d i a o
FORCE_MODE_SPD_P6
F
PORT 6 speed force Mode.
Me
module)
module)
o r
ef
register)
module)
a s
ele
register)
27 FORCE_MODE_TX_FC_P6
i a l R PORT 6 TX FC force Mode.

e n t i
module)
d
register)
26
o n f i
n a P PORT 6 100M EEE force Mode.

a
polling module)
e k C B a n 1: Force mode is on. (Mac 100M EEE ability is determined by

d i a T F o r

f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
25
f i d e
FORCE_MODE_EEE1G_P6
a P i PORT 6 1G EEE force Mode.

C o n n a n
polling module)
19:18
T e k
IPG_CFG_P6
r B a PORT 6 Inter-Frame+ Gap Shrink

d i a F o 01: Transmit 96-bits IFG with short IFG in random behavior

Me
17 EXT_PHY_P6 PORT 6 External PHY. Port 6 connects with external PHY.
0: PORT 6 DOES NOT connect with external PHY.
1: PORT 6 connects with external PHY.
16 MAC_MODE_P6 PORT 6 MAC Mode. PORT 6 operates in MAC mode
0: PORT 6 operates in PHY mode.
14 MAC_TX_EN_P6
1: PORT 6 operates in MAC mode.
f o r
se
a
13 MAC_RX_EN_P6
R e l e 1: TX MAC function is enabled.

PORT 6 RX MAC Enable (Note: This bit only has impact on MAC function,
t i a l 0: RX MAC function is disabled.

11 MAC_PRE_P6
i d e n P i
o n f
BKOFF_EN_P6
a n a
PORT 6 Backoff Enable
C
0: Disabled
e k B a n 1: Let the MAC of PORT 6 to follow the back-off mechanism when

collision happens.
d
8
i a T F o r
BACKPR_EN_P6 PORT 6 Backpressure Enable
0: Disabled
1: Enable back pressure mechanism when operating in half-duplex with
Me
low internal free memory page count.
7 FORCE_EEE1G_P6 PORT 6 Force LPI Mode For 1000Mbps
When (force_mode_P6 = 1), this bit is used to control the 1000Base-T EEE
ability of PORT 6.
o r
ef
1000Mbps.
6 FORCE_EEE100_P6 PORT 6 Force LPI Mode For 100Mbps
a s
l R ability of PORT 6.
ele
When (force_mode_P6 = 1), this bit is used to control the 100Base-TX EEE
a
e n t i 100Mbps.
5
n f i d
FORCE_RX_FC_P6
a P i PORT 6 Force RX FC. When (force_mode_P6 = 1), this bit is used to

n
0: Disabled.
k C o a n a
duplex mode.
i a T e o r B
M e d F
Page 493 of 830
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
4 FORCE_TX_FC_P6
f i d e a P i PORT 6 Force TX FC
C o n n a n When (force_mode_P6 = 1), this bit is used to control the TX FC ability of

PORT 6.
k a
0: Disabled.
i
3:2
a T e o r B
FORCE_SPD_P6
Me d F When (force_mode_P6 = 1), these bits are used to control MAC speed of
PORT 6.
00: 10Mbps
01: 100Mbps
r
10: 1000Mbps
11: Reserved
f o
se
1 FORCE_DPX_P6 PORT 6 Force duplex
e l e a When (force_mode_P6 = 1), this bit is used to control MAC duplex of

PORT 6.
R
0: Half Duplex
0 FORCE_LNK_P6
t i a l 1: Full Duplex
PORT 6 Force MAC Link Up
i d e n P i
6.
o n f a n a 0: Link Down
1: Link Up
e k C B a n
d i a T F o r
Me
00003604 PMEEECR_P6 PORT 6 MAC EEE Control Register 111E01E0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name WAKEUP_TIME_1000_P6 WAKEUP_TIME_100_P6
Type RW RW
Reset 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1
o r 0
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPI_M
Name LPI_THRESH_P6
a s ODE_E
ele
N_P6
Type RW RW
Reset 0 0 0
i a l R 0 0 0 0 1 1 1 1 0 0
e n t i
Bit(s)
31:24
Name
n f i d n
WAKEUP_TIME_1000_P6
a P Description
k C o a n a
i a T e o r B
M e d F
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MT7531

Confidential A
Bit(s) Name
n t i a Description
f i d e a P i The minimum allowed time needed to wait for PHY to be fully functional,
C o n n a n Time unit: 1 micro second
k a
i a T e o r B The minimum allowed time needed to wait for PHY to be fully functional,
F
Me d
15:4 LPI_THRESH_P6
PORT 6 LPI Threshold

f o r
se
0 LPI_MODE_EN_P6 PORT 6 Enter LPI Mode
e l e a When there is no packet to be transmitted, and the idle time is greater

R
t i a l 0: LPI mode depends on the P6_LPI_THRESHOLD.

n
the link partner.
f i d e a P i
C o n n a n
00003608
Bit
T e k
31
PMSR_P6
r
30
B a 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
d i a F o
Me
Type
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EEE100 MAC_D MAC_L
r
6 _P6 S_P6
Type
Reset
RO
0
RO
0
RO
0
RO
0 0
RO
0
ef
RO
0
o RO
0
a s
l R ele
a
7 EEE1G_STS_P6
e n t i PORT 6 LPI Mode Status For 1000Mbps

n f i d
EEE100_STS_P6
a P i 1: Capable of entering EEE Low Power Idle mode for 1000Mbps.

n
k C o a n a 1: Capable of entering EEE Low Power Idle mode for 100Mbps.
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
5 RX_FC_STS_P6
f i d e a P i PORT 6 RX XFC Status
C o n n a n Port 6 Rx flow control status

0: Disabled.
k a
i a T e r B
TX_FC_STS_P6
o
duplex mode
Me d F PORT 6 TX flow control status

0: Disabled.
3:2 MAC_SPD_STS_P6 PORT 6 Speed [1:0] Status
Current speed of PORT 6 after PHY links up

00: 10 Mbps
f o r
l e a
01: 100 Mbps
10: 1000 Mbps
11: Reserved se
1 MAC_DPX_STS_P6
l R e PORT 6 duplex Status
n t i a Current duplex mode of PORT 6 after PHY links up

0: Half Duplex
f i
MAC_LNK_STS_P6
d e a P i
1: Full Duplex
Port 6 Link Up Status
C o n n a n Link up status of PORT 6

0: Link Down
T e k r B a 1: Link Up
d i a F o
Me 00003610
Bit 31
PINT_EN_P6
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
o r
ef
Type
s
Reset
Bit 15 14 13
12 11
TX_RP
AGE_T
10 9
TX_GP TX_RD TX_DE
AGE_T PB_TO Q_TOU
8 7 6 5
ele
4
a 3
RX_AFF
2 1
RX_AR RX_WR RX_GP
L_TOU PB_TO AGE_T
0
R
Name _FULL_
_INT_E ERR_IN ERR_IN RR_INT OUT_I OUT_I UT_INT T_INT_
l
T_INT_ UT_INT OUT_I
INT_EN
a
Type
Reset
RW
0
RW
0
e n t
RW
0
i RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
n f i d a P i
C o n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531

Confidential A
Bit(s) Name
n t i a Description
15
f i d e
TX_TFF_UNDR_INT_EN
a P i TXMAC TXFIFO Under run Interrupt Enable

0: Disabled
14
C o n a n
n
1: Enabled
k a
0: Disabled
13
i a T e r B
TX_MISPAGE_ERR_INT_EN
o
1: Enabled
F
0: Disabled
Me d
1: Enabled
0: Disabled
1: Enabled
11 TX_RPAGE_TOUT_INT_EN TX_CTRL Release Page Timeout Interrupt Enable
r
0: Disabled
1: Enabled
f o
se
10 TX_GPAGE_TOUT_INT_EN TX_CTRL Get Page Timeout Interrupt Enable
0: Disabled
9 TX_RDPB_TOUT_INT_EN
e l e a 1: Enabled
R
0: Disabled
8 TX_DEQ_TOUT_INT_EN
t i a l 1: Enabled
n
0: Disabled
i d e
RX_AFF_FULL_INT_EN
f a P i
1: Enabled
n
0: Disabled
C o n
RX_ARL_TOUT_INT_EN
a n 1: Enabled
RX_CTRL ARL Timeout Interrupt Enable
T e k r B a 0: Disabled
1: Enabled
d
1
i a o
RX_WRPB_TOUT_INT_EN
F
RX_CTRL WR_PB Timeout Interrupt Enable
0: Disabled
Me
1: Enabled
0: Disabled
1: Enabled
o r
a s ef
le
Bit
Name
31 30 29
l R e 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
Reset
n t i a
Bit 15
f
14
i d e
TX_MIS TX_MIS
13
a P i 12
TX_RP TX_GP
11 10 9 8 7 6 5 4 3 2 1
RX_GP
0
n
n
Name _UNDR
C
_INT
k o T
a
T
a
ERR_IN ERR_IN
n
AGE_E
RR_INT
OUT_I OUT_I
NT NT
PB_TO Q_TOU
UT_INT T_INT
_FULL_ L_TOU PB_TO
INT T_INT UT_INT
OUT_I
NT
i a T e o r B
Med F
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Confidential A
n t i a
e
Reset 0 0
n f i d 0
a P i
0 0 0 0 0 0 0 0 0
C o n a n
Bit(s)
T e k
Name
r B a Description
a o
d i F
0: False
Me
1: True
0: False
1: True
0: False
1: True
f o r
se
12 TX_RPAGE_ERR_INT TX_CTRL Release Page Count Error Interrupt
0: False
e l e a 1: True
R
0: False
10 TX_GPAGE_TOUT_INT
t i a l 1: True
n
0: False
f i d
TX_RDPB_TOUT_INT
e a P i
1: True
n
0: False
C o
TX_DEQ_TOUT_INT
n a n 1: True
TX_CTRL DEQ Timeout Interrupt
T e k r B a 0: False
1: True
d
3
i a o
RX_AFF_FULL_INT
F
0: False
Me
1: True
0: False
1: True
0: False
o r
ef
1: True
s
a
0: False
ele
1: True
i a l R
e n t i
00003618
Bit 31
n f
30
i d
P6_DBG_CNT
29
n a P 28 27 26
PORT 6 DEBUG COUNT
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
k C o a n a
i a T e o r B
M e d F
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Confidential A
n t i a
e
Reset
Bit
Name
15
n
14
f i d 13
a P i 12 11 10 9 8 7 6
TX_FIFO_URUN
5 4 3 2 1
RX_FIFO_OV
0
Type
C o n a n RO RO
a
Reset
k
0 0 0 0 0 0 0
i a T e o r B
Me d
Bit(s)
7:4
Name
F
TX_FIFO_URUN
Description
Underrun count of TX fifo.
The field is increased when TX fifo underrun occurs.
r
2:0 RX_FIFO_OV Overflow count of RX fifo
The field is increased when RX fifo overflow occurs.

f o
l e a se
l R e
00003620
Bit 31
P6_WOL
30
n t
29
i a 28 27 26
PORT 6 WOL
25 24 23 22 21 20 19 18
00000000
17 16
Name
f i d e a P i WOL_DBG
WOL_I WOL_S
NT_STS TS
n
Type RO W1C RO
Reset 0
C o 0
n a n0 0 0 0 0 0 0 0 0 0 0 0 0 0
a
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
T e k r B
KT S NT_EN N
d i
Type
a F o RW RW RW RW
Me
Reset 0 0 0 0
r
31:18
17
WOL_DBG
WOL_INT_STS
ef o
s
16 WOL_STS Port6 Wake-up On Lan Status
ele a
3 SNP_PKT
i a l R detect magic packet.

e n t i
0: Disable
1: Enable
2 CRC_DIS
n f i d n a P
0: CRC check enable
o
1
C
WOL_INT_EN
k a n a Port6 Wake-up On Lan Interrupt Enable

0: Disable
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
0 WOL_EN
f i d e a P i 1: Enable
C o n n a n 0: Disable
1: Enable
T e k r B a
d i a F o
Me
00003624 P6_PFC_STS PORT 6 PFC STATUS 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
r
Type
Reset
f o
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PFC_STS RX_PFC_STS
Type
Reset 0 0 0 0
e l e
RO
a 0 0 0 0 0 0 0 0
RO
0 0 0 0
i a l R
Bit(s) Name
e n t i
Description
15:8
7:0
TX_PFC_STS
n
RX_PFC_STS
f i d n a P Port6 PFC TX pause on status of 8 priorities 1: pause on 0: pause off
k C o a n a
i a T e o r B
Me d
00003630
Bit
Name
Type
31
F P6_PFC_RX_PSON_CNT_L
30 29 28
Q3_RX_PSON_CNT
RC
27 26
25 24 23 22 21 20
Q2_RX_PSON_CNT
RC
19 18
00000000
17 16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r 0
ef
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0
a s 0 0 0 0
l R ele
Bit(s)
31:24
Name
Q3_RX_PSON_CNT
n t i a Description
23:16
15:8
f i d
Q2_RX_PSON_CNT
Q1_RX_PSON_CNT
e a P i PFC RX pause on count for port6 priority 2
7:0
C o n
Q0_RX_PSON_CNT
n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
Bit
Name
31
C o30
n a
29
n 28
Q7_RX_PSON_CNT
27 26 25 24 23 22 21 20
Q6_RX_PSON_CNT
19 18 17 16
Type
Reset
T e0
k 0
r B a 0 0
RC
0 0 0 0 0 0 0 0
RC
0 0 0 0
Bit
d i a 15
F o14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
23:16
15:8
7:0
Q6_RX_PSON_CNT
Q5_RX_PSON_CNT
Q4_RX_PSON_CNT
e l e a PFC RX pause on count for port6 priority 6

i a l R
e n t i
00003638
n f i d a P
n
Port 6 RX PFC pause off counter for low priority 00000000
Bit
Name
31
k C o30
a n a
29 28
Q3_RX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q2_RX_PSOFF_CNT
19 18 17 16
e B
Type RC RC
Reset
Bit
d i a T 0
15
F o
0
r
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Me
Type RC RC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
a s
ele
i a l R
e n t i
0000363C
n f i d a P
n
Port 6 RX PFC pause off counter for high priority 00000000
Bit
Name
k
31
C o 30
a n a
29 28
Q7_RX_PSOFF_CNT
27 26 25 24 23 22 21 20
Q6_RX_PSOFF_CNT
19 18 17 16
i a T e o r B
M e d F
Page 501 of 830
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Confidential A
n t i a
e
Type RC RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
C o n a n Q5_RX_PSOFF_CNT
RC
Q4_RX_PSOFF_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q7_RX_PSOFF_CNT
Q6_RX_PSOFF_CNT
Q5_RX_PSOFF_CNT
Description
f o r
l e a se
00003640 P6_PFC_TX_PSON_CNT_L
l R e Port 6 TX PFC pause on counter for low priority 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e n t i
Q3_TX_PSON_CNT
RC
Q2_TX_PSON_CNT
RC
Reset
Bit
0
15
0
n
14
f i d 0
13
a P i
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q0_TX_PSON_CNT
RC
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me Bit(s)
31:24
23:16
15:8
Name
Q3_TX_PSON_CNT
Q2_TX_PSON_CNT
Q1_TX_PSON_CNT
Description
o r
a s ef
00003644
R
l
ele 00000000
a
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Type
e n t i Q7_TX_PSON_CNT
RC
Q6_TX_PSON_CNT
RC
Reset
Bit
0
15
n f i
0
14
d 0
13
a P i 0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Name
Type
RC
Q4_TX_PSON_CNT
RC
Reset
T e k 0
r B
0
a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ed i a F o
M
f o r
l e a se MT7531

Confidential A
n t i a
f i d e a P i
n
31:24
23:16
C o
Q7_TX_PSON_CNT
Q6_TX_PSON_CNT
n a n PFC TX pause on count for port6 priority 7

15:8
7:0
T k
Q5_TX_PSON_CNT
e r B
Q4_TX_PSON_CNT
a PFC TX pause on count for port6 priority 5
d i a F o
Me 00003648
Bit 31
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
Type
Q3_TX_PSOFF_CNT
RC
Q2_TX_PSOFF_CNT
RC
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
l e a
Q1_TX_PSOFF_CNT
e
11 10 9 8 7 6 5 4
Q0_TX_PSOFF_CNT
3 2 1 0
R
Type RC RC
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
i d e n P i
Bit(s)
31:24
Name
o n f
Q3_TX_PSOFF_CNT
a n a Description
23:16
15:8
7:0 C
Q2_TX_PSOFF_CNT
k a
Q1_TX_PSOFF_CNT
e B
Q0_TX_PSOFF_CNT n
d i a T F o r
Me 0000364C
Bit 31
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
o r
ef
Type RC RC
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
Name
15 14 13 12
Q5_TX_PSOFF_CNT
11 10 9 8 7 6 5
ele
4
a
Q4_TX_PSOFF_CNT
3 2 1 0
R
Type RC RC
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
i d e n P i
Bit(s)
31:24
Name
o n f
Q7_TX_PSOFF_CNT
a n a Description
23:16
15:8
e k C n
Q6_TX_PSOFF_CNT
a
Q5_TX_PSOFF_CNT
B
d i a T F o r

f o r
l e a seMT7531

Confidential A
Bit(s) Name
n t i a Description
7:0
f i d
Q4_TX_PSOFF_CNT
e a P i PFC TX pause off count for port6 priority 4
C o n n a n
T e k r B a
d i a F o
Me
f o r
l e a se
l R e
n t i a
f i d e a P i
C o n n a n
T e k r B a
d i a F o
Me
o r
a s ef
l R ele
n t i a
f i d e a P i
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
6
f i d e a P i
Management information base (MIB)
C o n
Introduction
n a n
a
6.1
T e k r B
a o
MIB counter module supports Ethernet standard MIB counters of 7 Giga ports. Each Port MIB counter
d i F
is implemented with 32x32 Single-port SRAM and registers. ARL MIB counters are implemented with
Me registers.
MIB counter can be read/write accessed by three interfaces.

1. Port MAC MIB interface: When a packet is received or transmitted from a Port MAC, MIB will
f o r
se
update the Enable signal which will be asserted with new information events to update Port MIB
2.
counter (SRAM).
e l e a
ARL MIB interface: When ARL MIB events are received, ARL MIB counters will be increased by
one.
i a l R
t
3. P-Bus interface: The CPU host uses P-Bus to read/write Port MIB counters and ARLMIB
counters.
i d e n P i
o n f n a
The Port MAC module has higher priority for accessing Port MIB counters than P-Bus in order to
a
e k C B n
update TX/RX MIB counters at 1000M line speed. Therefore, when Port MAC module and CPU
a
module access Port MIB counters at the same time, the P-Bus access of CPU will be postponed till
d i a T o r
the Port MAC module updating process is completed. As for ARL MIB update module and CPU P-Bus
F
Me
module, the ARL update module has higher priority than the CPU P-Bus interface.
6.2 Features

o r
ef
Support 7 Giga port Ethernet Switch MIB Counters
 Support MIB events for GMAC TX port
 Support MIB events for GMAC RX port
a s
ele
 Support MIB events for ARL module
 Support 32-bit P-Bus interface to read/write access MIB 32/64-bit registers

l R
Support 7 sets of 32x32 single port SRAM for MIB events memory
i a
e n t i
d
6.2.1 Overview of MIB Counters
o n f i n a P
The MIB module supports MIB counters for GMAC TX/RX ports and ARL module. All MIB counters
C
are listed below.
k a n a
i a T e o r B
M e d F
Page 505 of 830
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Confidential A
n t i a
f i d e a P iTable 6-1. Overview of MIB Counters
C o n Module
n a
Port 0 ~ 6
n MIB Name
TX Drop Packet
Bit width
32
T e k r B a TX CRC Packet
TX Unicast Packet
32
32
d i a F o TX Multicast Packet 32
Me
TX Broadcast Packet 32
TX Collision Event Count 32
TX Single Collision Event Count 32
TX Multiple Collision Event Count 32
TX Deferred Event Count
TX Late Collision Event Count
32
32
f o r
TX Excessive Collision Event Count
e a
TX Pause Packet
l
32
32
se
l R e
TX Packet Length 64 bytes
TX Packet Length 65 ~ 127 bytes
32
32
n t i a TX Packet Length 128 ~ 255 bytes

TX Packet Length 256 ~ 511 bytes
32
32
f i d e a P iTX Packet Length 512 ~ 1023 bytes

TX/RX Packet Length 1024 ~ Max bytes
32
32
C o n n a n TX Octets
RX Drop Packet
64
32
T e k r B a RX Filtering Packet 32
32
a
RX Unicast Packet
d i F o RX Multicast Packet 32
Me
RX Broadcast Packet 32
RX Alignment Error Packet 32
RX CRC Packet 32
RX Undersize Packet 32
RX Fragment Error Packet 32
o r
ef
RX Oversize Packet 32
RX Jabber Error Packet 32
a s
ele
RX Pause Packet 32
RX Packet Length 64 bytes 32
i a l R RX Packet Length 65 ~ 127 bytes

RX Packet Length 128 ~ 255 bytes
32
32
e n t i
RX Packet Length 256 ~ 511 bytes 32
d
RX Packet Length 512 ~ 1023 bytes 32
o n f i n a P RX Packet Length 1024 ~ Max bytes 32
a
RX Octets 64
e k C B a n RX CTRL Drop Packet 32
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a RX Ingress Drop Packet 32
f i d e a P iRX ARL Drop Packet 32
n
ARL ARL Event 0 32
C o n a n ARL Event 1 32
a
32
k
ARL Event 2
i a T e o r B ARL Event 3
ARL Event 4
32
32
Me d F ARL Event 5
ARL Event 6
ARL Event 7
32
32
32
f o r
se
6.3 Register Definition
Module name: MIB Base address: (+0x4000)
e l e a
Address
i
Name
a l R Width Register Function
00004000
TDPC_P0
e n t i
32
TX Drop Packet Counter of Port 0
d
00004004 32
i P
TCRC_P0 TX CRC Packet Counter of Port 0
00004008
o n f
TUPC_P0
a n a 32
TX Unicast Packet Counter of Port 0
0000400C
e k C a
TMPC_P0
B n 32
TX Multicast Packet Counter of Port 0
T r
00004010 32
TBPC_P0 TX Broadcast Packet Counter of Port 0
d i a
00004014
F o 32
Me
TCEC_P0 TX Collision Event Counter of Port 0
00004018 32
TSCEC_P0 TX Single Collision Event Counter of Port 0
0000401C 32
TMCEC_P0 TX Multiple Collision Event Counter of Port 0
00004020
TDEC_P0
32
TX Deferred Event Counter of Port 0
o r
ef
00004024 32
s
TLCEC_P0 TX Late Collision Event Counter of Port 0
00004028
TXCEC_P0
32
ele a
TX excessive Collision Event Counter of Port 0
R
0000402C 32
TPPC_P0 TX Pause Packet Counter of Port 0
00004030
TL64PC_P0
t i a l 32 TX packet Length in 64-byte slot Packet Counter of
n
Port 0
00004034
f d e
TL65PC_P0
i a P i
32 TX packet Length in 65-byte slot Packet Counter of
Port 0
00004038
C o n n
TL128PC_P0
n a
Port 0
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
0000403C 32 TX packet Length in 256-byte slot Packet Counter of
i
TL256PC_P0
d
Port 0
00004040
o n f i
TL512PC_P0
n a P 32 TX packet Length in 512-byte slot Packet Counter of

Port 0
00004044
k C n a
TL1024PC_P0
a
Port 0
i a e
00004048
T o r B
TOCL_P0
32
TX Octet Counter Low double word of Port 0
Me d
0000404C
00004060
00004064
F TOCH_P0
RDPC_P0
32
32
32
TX Octet Counter High double word of Port 0
RX Drop Packet Counter of Port 0
RFPC_P0 RX Filtering Packet Counter of Port 0
r
00004068 32
o
RUPC_P0 RX Unicast Packet Counter of Port 0
0000406C
RMPC_P0
32
RX Multicast Packet Counter of Port 0
se f
00004070
00004074
RBPC_P0
e l e a 32
32
RX Broadcast Packet Counter of Port 0
R
RAEPC_P0 RX Alignment Error Packet Counter of Port 0
00004078
RCEPC_P0
t i a l 32
RX CRC(FCS) Error Packet Counter of Port 0
0000407C
RUSPC_P0
i d e n P i
32
RX Undersize Packet Counter of Port 0
00004080
o n f
RFEPC_P0
a n a
32
RX Fragment Error Packet Counter of Port 0
C
00004084 32
n
ROSPC_P0 RX Oversize Packet Counter of Port 0
T e
00004088
k B a
RJEPC_P0
r
32
RX Jabber Error Packet Counter of Port 0
d i a
0000408C
F o RPPC_P0
32
RX Pause Packet Counter of Port 0
Me
00004090 32 RX packet Length in 64-byte slot Packet Counter of
RL64PC_P0
Port 0
RL65PC_P0
Port 0
r
RL128PC_P0
0000409C
RL256PC_P0
32
Port 0
RX packet Length in 256-byte slot Packet Counter of
ef o
Port 0
a s
ele
000040A0 32 RX packet Length in 512-byte slot Packet Counter of
RL512PC_P0
Port 0
R
l
RL1024PC_P0
Port 0
000040A8
ROCL_P0
n t i a 32
RX Octet Counter Low double word of Port 0
000040AC
d
ROCH_P0
f i e a P i
32
Rx Octet Counter High double word of Port 0
n
000040B0 32
n
RDPC_CTRL_P0 RX CTRL Drop Packet Counter of Port 0
000040B4
k C o a n a
RDPC_ING_P0
32
RX Ingress Drop Packet Counter of Port 0
i a T e o r B
M e d F
Page 508 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
000040B8 32
i
RDPC_ARL_P0 RX ARL Drop Packet Counter of Port 0
000040D0
n f i d
TMIB_HF_STS_P0
n a P 32
TX Port MIB Counter Half Full Status of Port 0
000040D4
k C o a n a
RMIB_HF_STS_P0
32
RX Port MIB Counter Half Full Status of Port 0
e B
00004100 32
TDPC_P1 TX Drop Packet Counter of Port 1
d i a T
00004104
F o r
TCRC_P1
32
TX CRC Packet Counter of Port 1
Me
00004108 32
TUPC_P1 TX Unicast Packet Counter of Port 1
0000410C 32
TMPC_P1 TX Multicast Packet Counter of Port 1
00004110 32
r
00004114
TCEC_P1
32
TX Collision Event Counter of Port 1
f o
00004118
TSCEC_P1
l e a
32
TX Single Collision Event Counter of Port 1
se
e
0000411C 32
00004120
TDEC_P1
i a l R 32
00004124
TLCEC_P1
e n t i
32
TX Late Collision Event Counter of Port 1
00004128
n f i d
TXCEC_P1
n a P
32
0000412C
00004130
k C o TPPC_P1
a n a
32
32
TX Pause Packet Counter of Port 1
TX packet Length in 64-byte slot Packet Counter of
e B
TL64PC_P1
Port 1
d i a T
00004134
F o r
TL65PC_P1
Port 1
Me
00004138 32 TX packet Length in 128-byte slot Packet Counter of
TL128PC_P1
Port 1
TL256PC_P1
Port 1
r
00004140
TL512PC_P1
o
Port 1
ef
TL1024PC_P1
s
Port 1
00004148
0000414C
TOCL_P1
32
32
ele a
R
TOCH_P1 TX Octet Counter High double word of Port 1
00004160
RDPC_P1
t i a l 32
00004164
RFPC_P1
i d e n P i
32
RX Filtering Packet Counter of Port 1
00004168
o n f
RUPC_P1
a n a
32
RX Unicast Packet Counter of Port 1
C
0000416C 32
n
RMPC_P1 RX Multicast Packet Counter of Port 1
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
00004170 32
i
RBPC_P1 RX Broadcast Packet Counter of Port 1
00004174
n f i d
RAEPC_P1
n a P 32
RX Alignment Error Packet Counter of Port 1
00004178
k C o RCEPC_P1
a n a 32
e B
0000417C 32
RUSPC_P1 RX Undersize Packet Counter of Port 1
d i a T
00004180
F o r
RFEPC_P1
32
Me
00004184 32
00004188 32
RJEPC_P1 RX Jabber Error Packet Counter of Port 1
0000418C 32
r
RPPC_P1 RX Pause Packet Counter of Port 1
00004190
RL64PC_P1
32 RX packet Length in 64-byte slot Packet Counter of
f o
se
Port 1
a
e
RL65PC_P1
l
Port 1
00004198
RL128PC_P1
l R e 32 RX packet Length in 128-byte slot Packet Counter of

Port 1
0000419C
RL256PC_P1
n t i a 32 RX packet Length in 256-byte slot Packet Counter of

Port 1
e
i
RL512PC_P1
000041A4
n f i d
RL1024PC_P1
n a P 32
Port 1
000041A8
k C o a
ROCL_P1
n a 32
Port 1
i a e
000041AC
T o r B
ROCH_P1
32
Me d
000041B0
000041B4
000041B8
F RDPC_CTRL_P1
RDPC_ING_P1
32
32
32
RX CTRL Drop Packet Counter of Port 1
r
000041D0 32
o
TMIB_HF_STS_P1 TX Port MIB Counter Half Full Status of Port 1
ef
000041D4 32
RMIB_HF_STS_P1 RX Port MIB Counter Half Full Status of Port 1
00004200 32
a s
ele
00004204 32
R
00004208
TUPC_P2
t i a l 32
0000420C
TMPC_P2
i d e n P i
32
00004210
o n f
TBPC_P2
a n a
32
TX Broadcast Packet Counter of Port 2
C
00004214 32
n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
00004218 32
i
0000421C
n f i d
TMCEC_P2
n a P 32
TX Multiple Collision Event Counter of Port 2
00004220
k C o TDEC_P2
a n a 32
e B
00004224 32
d i a T
00004228
F o r
TXCEC_P2
32
Me
0000422C 32

TL64PC_P2
Port 2
r
00004234
TL65PC_P2
o
Port 2
00004238
TL128PC_P2
Port 2
se f
0000423C
TL256PC_P2
e l e a 32 TX packet Length in 256-byte slot Packet Counter of

Port 2
R
TL512PC_P2
l
Port 2
00004244
TL1024PC_P2
n t i a 32 TX packet Length in 1024-byte slot Packet Counter of

Port 2
00004248
d
TOCL_P2
f i e a P i
32
n
0000424C 32
n
00004260
k C o a
RDPC_P2
n a 32
i a e
00004264
T o r B
RFPC_P2
32
Me d
00004268
0000426C
00004270
F RUPC_P2
RMPC_P2
32
32
32
r
00004274 32
o
ef
00004278 32
RCEPC_P2 RX CRC(FCS) Error Packet Counter of Port 2
0000427C 32
a s
ele
00004280 32
R
RFEPC_P2 RX Fragment Error Packet Counter of Port 2
00004284
ROSPC_P2
t i a l 32
RX Oversize Packet Counter of Port 2
00004288
e
RJEPC_P2
i d n P i
32
0000428C
o n f
RPPC_P2
a n a
32
C
n
RL64PC_P2
k a
Port 2
i a T e o r B
M e d F
Page 511 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
i
RL65PC_P2
d
Port 2
00004298
o n f i
RL128PC_P2
n a P 32 RX packet Length in 128-byte slot Packet Counter of

Port 2
0000429C
k C n
RL256PC_P2
a a 32 RX packet Length in 256-byte slot Packet Counter of

Port 2
i a T e
000042A0
o r B
RL512PC_P2
Port 2
Me d000042A4
000042A8 F RL1024PC_P2
ROCL_P2
32
32
Port 2
000042AC 32
ROCH_P2 Rx Octet Counter High double word of Port 2
000042B0
RDPC_CTRL_P2
32
f o r
se
000042B4 32
RDPC_ING_P2 RX Ingress Drop Packet Counter of Port 2
000042B8
RDPC_ARL_P2
e l e a 32
RX ARL Drop Packet Counter of Port 2
R
000042D0 32
000042D4
t
RMIB_HF_STS_P2
i a l 32
00004300
i d
TDPC_P3
e n P i
32
00004304
o n f
TCRC_P3
a n a 32
00004308
e
0000430C
k C TUPC_P3
B a n
32
32
T r
d i a
00004310
F o TBPC_P3
32
Me
00004314 32
00004318 32
r
0000431C 32
00004320
TDEC_P3
32
ef o
00004324 32
a s
ele
00004328 32
R
TXCEC_P3 TX excessive Collision Event Counter of Port 3
0000432C
TPPC_P3
t i a l 32
00004330
e
TL64PC_P3
i d n P i
Port 3
00004334
o n f
TL65PC_P3
a n a
Port 3
C n
TL128PC_P3
k a
Port 3
i a T e o r B
M e d F
Page 512 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
i
TL256PC_P3
d
Port 3
00004340
o n f i
TL512PC_P3

Port 3
00004344
k C n a
TL1024PC_P3
a
Port 3
i a e
00004348
T o r B
TOCL_P3
32
Me d
0000434C
00004360
00004364
F TOCH_P3
RDPC_P3
32
32
32
r
00004368 32
o
0000436C
RMPC_P3
32
se f
00004370
00004374
RBPC_P3
e l e a 32
32
R
00004378
RCEPC_P3
t i a l 32
0000437C
RUSPC_P3
i d e n P i
32
00004380
o n f
RFEPC_P3
a n a
32
C
00004384 32
n
T e
00004388
k B a
RJEPC_P3
r
32
d i a
0000438C
F o RPPC_P3
32
Me
RL64PC_P3
Port 3
RL65PC_P3
Port 3
r
RL128PC_P3
0000439C
RL256PC_P3
32
Port 3
ef o
Port 3
a s
ele
RL512PC_P3
Port 3
R
l
RL1024PC_P3
Port 3
000043A8
ROCL_P3
n t i a 32
000043AC
d
ROCH_P3
f i e a P i
32
n
000043B0 32
n
000043B4
k C o a n a
RDPC_ING_P3
32
i a T e o r B
M e d F
Page 513 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
000043B8 32
i
000043D0
n f i d
TMIB_HF_STS_P3
n a P 32
000043D4
k C o a n a
RMIB_HF_STS_P3
32
e B
00004400 32
d i a T
00004404
F o r
TCRC_P4
32
Me
00004408 32
TUPC_P4 TX Unicast Packet Counter of Port 4
0000440C 32
00004410 32
r
00004414
TCEC_P4
32
f o
00004418
TSCEC_P4
l e a
32
se
e
0000441C 32
00004420
TDEC_P4
i a l R 32
00004424
TLCEC_P4
e n t i
32
00004428
n f i d
TXCEC_P4
n a P
32
0000442C
00004430
k C o TPPC_P4
a n a
32
32
TX packet Length in 64-byte slot Packet Counter of
e B
TL64PC_P4
Port 4
d i a T
00004434
F o r
TL65PC_P4
Port 4
Me
TL128PC_P4
Port 4
TL256PC_P4
Port 4
r
00004440
TL512PC_P4
o
Port 4
ef
TL1024PC_P4
s
Port 4
00004448
0000444C
TOCL_P4
32
32
ele a
R
00004460
RDPC_P4
t i a l 32
00004464
RFPC_P4
i d e n P i
32
00004468
o n f
RUPC_P4
a n a
32
C
0000446C 32
n
RMPC_P4 RX Multicast Packet Counter of Port 4
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
00004470 32
i
00004474
n f i d
RAEPC_P4
n a P 32
RX Alignment Error Packet Counter of Port 4
00004478
k C o RCEPC_P4
a n a 32
e B
0000447C 32
d i a T
00004480
F o r
RFEPC_P4
32
Me
00004484 32
00004488 32
RJEPC_P4 RX Jabber Error Packet Counter of Port 4
0000448C 32
r
RPPC_P4 RX Pause Packet Counter of Port 4
00004490
RL64PC_P4
f o
se
Port 4
a
e
RL65PC_P4
l
Port 4
00004498
RL128PC_P4
l R e 32 RX packet Length in 128-byte slot Packet Counter of

Port 4
0000449C
RL256PC_P4
n t i a 32 RX packet Length in 256-byte slot Packet Counter of

Port 4
e
i
RL512PC_P4
000044A4
n f i d
RL1024PC_P4
n a P 32
Port 4
000044A8
k C o a
ROCL_P4
n a 32
Port 4
i a e
000044AC
T o r B
ROCH_P4
32
Me d
000044B0
000044B4
000044B8
F RDPC_CTRL_P4
RDPC_ING_P4
32
32
32
r
000044D0 32
o
ef
000044D4 32
RMIB_HF_STS_P4 RX Port MIB Counter Half Full Status of Port 4
00004500 32
a s
ele
00004504 32
R
00004508
TUPC_P5
t i a l 32
0000450C
TMPC_P5
i d e n P i
32
00004510
o n f
TBPC_P5
a n a
32
C
00004514 32
n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
00004518 32
i
0000451C
n f i d
TMCEC_P5
n a P 32
00004520
k C o TDEC_P5
a n a 32
e B
00004524 32
d i a T
00004528
F o r
TXCEC_P5
32
Me
0000452C 32

TL64PC_P5
Port 5
r
00004534
TL65PC_P5
o
Port 5
00004538
TL128PC_P5
Port 5
se f
0000453C
TL256PC_P5
e l e a 32 TX packet Length in 256-byte slot Packet Counter of

Port 5
R
TL512PC_P5
l
Port 5
00004544
TL1024PC_P5
n t i a 32 TX packet Length in 1024-byte slot Packet Counter of

Port 5
00004548
d
TOCL_P5
f i e a P i
32
n
0000454C 32
n
00004560
k C o a
RDPC_P5
n a 32
i a e
00004564
T o r B
RFPC_P5
32
Me d
00004568
0000456C
00004570
F RUPC_P5
RMPC_P5
32
32
32
r
00004574 32
o
ef
00004578 32
RCEPC_P5 RX CRC(FCS) Error Packet Counter of Port 5
0000457C 32
a s
ele
00004580 32
R
RFEPC_P5 RX Fragment Error Packet Counter of Port 5
00004584
ROSPC_P5
t i a l 32
00004588
e
RJEPC_P5
i d n P i
32
0000458C
o n f
RPPC_P5
a n a
32
C
n
RL64PC_P5
k a
Port 5
i a T e o r B
M e d F
Page 516 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
i
RL65PC_P5
d
Port 5
00004598
o n f i
RL128PC_P5
n a P 32 RX packet Length in 128-byte slot Packet Counter of

Port 5
0000459C
k C n
RL256PC_P5
a a 32 RX packet Length in 256-byte slot Packet Counter of

Port 5
i a T e
000045A0
o r B
RL512PC_P5
Port 5
Me d000045A4
000045A8 F RL1024PC_P5
ROCL_P5
32
32
Port 5
000045AC 32
ROCH_P5 Rx Octet Counter High double word of Port 5
000045B0
RDPC_CTRL_P5
32
f o r
se
000045B4 32
RDPC_ING_P5 RX Ingress Drop Packet Counter of Port 5
000045B8
RDPC_ARL_P5
e l e a 32
RX ARL Drop Packet Counter of Port 5
R
000045D0 32
000045D4
t
RMIB_HF_STS_P5
i a l 32
00004600
i d
TDPC_P6
e n P i
32
00004604
o n f
TCRC_P6
a n a 32
00004608
e
0000460C
k C TUPC_P6
B a n
32
32
T r
d i a
00004610
F o TBPC_P6
32
Me
00004614 32
00004618 32
r
0000461C 32
00004620
TDEC_P6
32
ef o
00004624 32
a s
ele
00004628 32
R
TXCEC_P6 TX excessive Collision Event Counter of Port 6
0000462C
TPPC_P6
t i a l 32
00004630
e
TL64PC_P6
i d n P i
Port 6
00004634
o n f
TL65PC_P6
a n a
Port 6
C n
TL128PC_P6
k a
Port 6
i a T e o r B
M e d F
Page 517 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
i
TL256PC_P6
d
Port 6
00004640
o n f i
TL512PC_P6

Port 6
00004644
k C n a
TL1024PC_P6
a
Port 6
i a e
00004648
T o r B
TOCL_P6
32
Me d
0000464C
00004660
00004664
F TOCH_P6
RDPC_P6
32
32
32
r
00004668 32
o
0000466C
RMPC_P6
32
se f
00004670
00004674
RBPC_P6
e l e a 32
32
R
00004678
RCEPC_P6
t i a l 32
0000467C
RUSPC_P6
i d e n P i
32
00004680
o n f
RFEPC_P6
a n a
32
C
00004684 32
n
T e
00004688
k B a
RJEPC_P6
r
32
d i a
0000468C
F o RPPC_P6
32
Me
RL64PC_P6
Port 6
RL65PC_P6
Port 6
r
RL128PC_P6
0000469C
RL256PC_P6
32
Port 6
ef o
Port 6
a s
ele
RL512PC_P6
Port 6
R
l
RL1024PC_P6
Port 6
000046A8
ROCL_P6
n t i a 32
000046AC
d
ROCH_P6
f i e a P i
32
n
000046B0 32
n
000046B4
k C o a n a
RDPC_ING_P6
32
i a T e o r B
M e d F
Page 518 of 830
f o r
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l R e Lynx1
Confidential A
n t i a
e
000046B8 32
i
000046D0
n f i d
TMIB_HF_STS_P6
n a P 32
000046D4
k C o a n a
RMIB_HF_STS_P6
32
e B
00004F00 32
AE0CNT ACL Event 0 Counter
d i a T
00004F04
F o r
AE1CNT
32
ACL Event 1 Counter
Me
00004F08 32
00004F0C 32
00004F10 32
r
00004F14
AE5CNT
32
ACL Event 5 Counter
f o
00004F18
AE6CNT
l e a
32
ACL Event 6 Counter
se
e
00004F1C 32
00004FE0
MIBCCR
i a l R 32
MIB Counter Control
00004FE4
AECCR
e n t i
32
ARL Event Counter Control
00004FE8
n f i d
AEMIB_HF_STS
n a P
32
ARL Event MIB Counter Half Full Status
00004FF0
00004FF4
k C o a n a
MIBHF_INT_EN
32
32
Port/ARL MIB Counter Half Full Interrupt Enable
e B
MIBHF_INT_STS Port/ARL MIB Counter Half Full Interrupt Status
d i a T F o r
Me
00004000 TDPC_P0 TX Drop Packet Counter of Port 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_DROP_CNT
Type RO
o r
Reset 0 0 0 0 0 0 0 0 0 0 0 0
a
0
s
0
ef0 0
le
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
l R e TX_DROP_CNT
Type
i a
RO
Reset 0 0
e n t 0
i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
k C o a n a
i a T e o r B
Med F
Page 519 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f
TX_DROP_CNT
i d e a P i The number of event when the frame output should be dropped due to
C o n n a n
the late collision or excessive collision
T e k r B a
d i a
00004004
F oTCRC_P0 TX CRC Packet Counter of Port 0 00000000
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_CRC_CNT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o
0
r 0
se
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e l e a TX_CRC_CNT
R
Type RO
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
o n
TX_CRC_CNT
f a n a The number of event which the frame will output a CRC packet due to
e k C B a n
TX FIFO underrun
d i a T F o r
Me
00004008 TUPC_P0 TX Unicast Packet Counter of Port 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_UCAST_CNT
Type RO
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
le a s
3 2 1 0
Name
l R e TX_UCAST_CNT
a
Type RO
Reset 0 0
e n t i 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
C o n a n
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f
TX_UCAST_CNT
i d e a P i The number of unicast frames transmitted without any error. It
C o n n a n
excludes Pause frame but includes MAC control and successful
retransmission.
T e k r B a
d i a F o
Me
0000400C TMPC_P0 TX Multicast Packet Counter of Port 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_MCAST_CNT
r
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
Bit 15 14 13 12
l e a
11 10 9 8 7 6 5 4 3 2
se 1 0
e
Name TX_MCAST_CNT
Type
i a l R RO
Reset 0 0
e n
0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
C o
TX_MCAST_CNT
k a n a The number of multicast frames transmitted without any error
i a T e o r B
Me d
00004010
Bit 31
F TBPC_P0
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name TX_BCAST_CNT
Type RO
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
le a s
3 2 1 0
Name
l R e TX_BCAST_CNT
a
Type RO
Reset 0 0
e n t i 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31:0
k C o a n
TX_BCAST_CNT
a The number of broadcast frames transmitted without any error
i a T e o r B
Med F
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Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00004014
Bit
T e k
31
TCEC_P0
r
30
B a 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_COL_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_COL_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_COL_CNT
i d e n P i
The total number of collision events occurrence during frame
f
transmission
C o n a n a
e k B a n
d i a
Bit
T
00004018
F
31
o rTSCEC_P0
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
M e Name
Type
TX_SCOL_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_SCOL_CNT
a s
ele
Type RO
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
f i
TX_SCOL_CNT
n d n a P The number of frames transmitted without any error following a single
o
collision
k C a n a
i a T e o r B
M e d F
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Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
0000401C
Bit
T e k
31
r
30
B a
TMCEC_P0
29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_MCOL_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MCOL_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_MCOL_CNT
i d e n P i
The number of frames transmitted without any error following multiple
f
collisions
C o n a n a
e k B a n
d i a
Bit
T
00004020
F
31
o rTDEC_P0
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
M e Name
Type
TX_DEFER_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_DEFER_CNT
a s
ele
Type RO
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
f i
TX_DEFER_CNT
n d n a P The number of frames deferred at the first transmit attempt due to a
o
busy medium in half duplex mode. Frame involved in collision is not
k C a n a counted
i a T e o r B
M e d F
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Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00004024
Bit
T e k
31
r
30
B a
TLCEC_P0
29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_LCOL_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_LCOL_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_LCOL_CNT
i d e n P i
The number of transmission abortion due to a collision occurring after
f
the transmission of the first 64 bytes for that packet
C o n a n a
e k B a n
d i a
Bit
T
00004028
F
31
o rTXCEC_P0
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
M e Name
Type
TX_XCOL_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_XCOL_CNT
a s
ele
Type RO
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
f i
TX_XCOL_CNT
n d n a P The number of frames that have experienced MAX_COL_NUM (default
o
16) consecutive collisions or more, not including late collisions
k C a n a
i a T e o r B
M e d F
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Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
0000402C
Bit
T e k
31
TPPC_P0
r
30
B a 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_PAUSE_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PAUSE_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_PAUSE_CNT
i d e n P i
The number of correct transmitted MAC flow-control frame
o n f a n a
00004030
e k C B a n
TL64PC_P0 TX packet Length in 64-byte slot Packet Counter 00000000
d i a
Bit
T F
31
o r 30 29 28 27 26
of Port 0
25 24 23 22 21 20 19 18 17 16
M e Name
Type
TX_PKT_64_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PKT_64_CNT
a s
ele
Type RO
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
f i d
TX_PKT_64_CNT
n n a P It indicates the total number of packets, including bad packets
o
transmitted equal to 64 octets in length, excluding framing bits but
k C a n a including FCS octets.
i a T e o r B
M e d F
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Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00004034
T e k r B a
TL65PC_P0 TX packet Length in 65-byte slot Packet Counter
of Port 0
00000000
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Name TX_PKT_65TO127_CNT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o1
r 0
se
Type
e l e a RO
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t i a l
Bit(s) Name
i d e n P i
Description
f
31:0 TX_PKT_65TO127_CNT It indicates the total number of packets, including bad packets
C o n a n a transmitted between 65 and 127 octets in length, excluding framing bits

but including FCS octets.
e k B a n
d i a T F o r
Me
00004038 TL128PC_P0 TX packet Length in 128-byte slot Packet Counter 00000000
of Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
o r
ef
RO
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
e
12 11 10 9 8 7 6 5 4
le a 3 2 1 0
R
Type
t i a l RO
Reset 0
i
0
d e n 0
P i
0 0 0 0 0 0 0 0 0 0 0 0 0
o n f a n a
e k C B a n
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
TX_PKT_128TO255_CNT
a P i It indicates the total number of packets, including bad packets
C o n n a n
transmitted between 128 and 255 octets in length, excluding framing
bits but including FCS octets.
T e k r B a
d i a F o
Me
0000403C TL256PC_P0 TX packet Length in 256-byte slot Packet Counter 00000000
of Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i a l R TX_PKT_256TO511_CNT
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
TX_PKT_256TO511_CNT
Description
It indicates the total number of packets, including bad packets
i a T e o r B transmitted between 256 and 511 octets in length, excluding framing

Me d F
of Port 0
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type RO
ele a
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
t i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
TX_PKT_512TO1023_CNT
Type
Reset
o n f a n a
RO
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
C o n n a n
T e k r B a
d i a F o
Me
00004044 TL1024PC_P0 TX packet Length in 1024-byte slot Packet 00000000
Counter of Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_PKT_1024TOMAX_CNT
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i a l R TX_PKT_1024TOMAX_CNT
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
TX_PKT_1024TOMAX_CNT
Description
i a T e o r B transmitted between 1024 and MAX_FRAME_SIZE octets in length,

excluding framing bits but including FCS octets.
Me d F
00004048 TOCL_P0 TX Octet Counter Low double word of Port 0 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_OCT_CNT_L
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
TX_OCT_CNT_L
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
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Bit(s) Name
n t i a Description
31:0
f
TX_OCT_CNT_L
i d e a P i {TX_OCT_CNT_H, TX_OCT_CNT_L} represents the number of bytes
C o n n a n
transmitted in good or bad frames, excluding preamble bits but
including FCS octets.
TX_OCT_CNT_GOOD bit = 1 (enabled), good packet bytes counted.
T e k r B a TX_OCT_CNT_GOOD bit = 0 (disabled), good packet bytes not counted.
d i a F o TX_OCT_CNT_BAD bit = 1 (enabled), bad packet bytes counted.
Me
TX_OCT_CNT_BAD bit = 0 (disabled), bad packet bytes not counted.
0000404C TOCH_P0 TX Octet Counter High double word of Port 0
f o r
00000000
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e l e a TX_OCT_CNT_H
R
Type RO
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
i d e n
13
P
12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
o n f a n a
TX_OCT_CNT_H
RO
Reset
e
0
k C 0
B a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) T Name
F o r Description
Me 31:0 TX_OCT_CNT_H Refer to TX_OCT_CNT_L (above).
o r
ef
00004060 RDPC_P0 RX Drop Packet Counter of Port 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Name RX_DROP_CNT
Type
i a l R RO
t
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
i d e n 13
P i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
o n f a n a RX_DROP_CNT
Type
e k C B a n
RO
d i a T F o r

f o r
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Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
Bit(s) Name
k a
31:0 RX_DROP_CNT The number of event which the frame should be dropped due to
i a T e o r B 1. an internal buffer shortage by RX_CTRL
Me d F 2. ingress rate limit by Ingress rate limiter
3. broadcast Storm Control, trTCM or ACL Rate Limit .
00004064 RFPC_P0 RX Filtering Packet Counter of Port 0

f o r
00000000
Bit
Name
31 30 29 28
l e a
27 26 25 24
RX_FILTER_CNT
23 22 21 20 19
se
18 17 16
Type
l R e RO
Reset 0 0
n
0
t i a 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
f i d e 13
a P i
12 11 10 9 8 7 6 5 4 3 2 1 0
n
Name RX_FILTER_CNT
Type
C o n a n RO
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me
31:0 RX_FILTER_CNT The number of frames which is filtered by ARL module due to ARL
security, length error, control frame, or port map is equal to zero.
o r
00004068 RUPC_P0 RX Unicast Packet Counter of Port 0
a s ef00000000
le
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
l R e RX_UCAST_CNT
Type
n t i a RO
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15
n f i d
14
a
13
P i 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
C o n a n RX_UCAST_CNT
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
Type RO
Reset 0 0
n f i d 0
a P i0 0 0 0 0 0 0 0 0 0 0 0 0
C o n a n
k a
31:0
i a T e r B
RX_UCAST_CNT
o
The number of unicast frames with length between 64 bytes and the
maximum frame size, received without any error, including MAC control
Me d F frames
0000406C
Bit 31
RMPC_P0
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17
r
00000000
16
Name
Type
l e a
RX_MCAST_CNT
RO se
Reset 0 0 0
l R0
e 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
n t i a 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
f i d e a P i
RX_MCAST_CNT
n
Type RO
Reset 0
C o 0
n a0
n 0 0 0 0 0 0 0 0 0 0 0 0 0
T e k r B a
a o
d i F
Me
31:0 RX_MCAST_CNT The number of multicast frames with length between 64 bytes and the
frames
o r
00004070
Bit 31
RBPC_P0
30 29 28 27 26
25 24 23 22 21 20
a s 19 18
ef00000000
17 16
Name
Type
l R
RX_BCAST_CNT
ele
a
RO
Reset 0 0
e n t0
i 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15
n
14
f i d 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
C o n a n RX_BCAST_CNT
a
Type
k
RO
i a T e o r B
M e d F
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n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
Bit(s) Name
k a
31:0 RX_BCAST_CNT The number of broadcast frames with length between 64 bytes and the
i a T e o r B maximum frame size, received without any error, including MAC control
frames
Me d
00004074
F RAEPC_P0 RX Alignment Error Packet Counter of Port 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_ALIGN_ERR_CNT
f o r
Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0
l0
e a 0 0se 0 0
Bit 15 14 13
l R 12 11 10 9 8 7 6 5
e 4 3 2 1 0
Name
n t i a RX_ALIGN_ERR_CNT
Type
f i d e a P i
RO
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C o n a n
Bit(s)
T e kName
r B a Description
e d i a
31:0
F o
RX_ALIGN_ERR_CNT The number of frames with length between 64 bytes and the maximum
frame size, received with a non-integral number of bytes and a CRC
error or RX_ER asserted.
M
00004078 RCEPC_P0 RX CRC(FCS) Error Packet Counter of Port 0
o r
00000000
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_FCS_ERR_CNT
a s
Type
Reset
l R
RO
ele
a
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
e n t i
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
n f i d a P i RX_FCS_ERR_CNT
Type
C o n a n RO
a
Reset 0 0
k
0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a T e o r B
M ed F
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n t i a
Bit(s) Name
31:0
C o n
RX_FCS_ERR_CNT
n a n The number of frames with length between 64 bytes and the maximum
frame size, received with an integral number of bytes and a CRC error or
k a
RX_ER asserted.
i a T e o r B
Me d
0000407C
Bit 31
F RUSPC_P0
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name RX_UNDERSIZE_CNT
Type RO
f o r
Reset
se
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5
e l
4
e a 3 2 1 0
Name
i a l R RX_UNDERSIZE_CNT
t
Type RO
Reset 0 0
i d e n 0
P i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
e k C a n
RX_UNDERSIZE_CNT
B
The total number of packets received that are less than 64 octets long
T
excluding framing bits, but including FCS octets which are otherwise
d i a F o r well formed.
M e00004080 RFEPC_P0 RX Fragment Error Packet Counter of Port 0 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_FRAG_ERR_CNT
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_FRAG_ERR_CNT
d
Type
i
RO
Reset 0
o n f
0
n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
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Bit(s) Name
n t i a Description
31:0
f i d
RX_FRAG_ERR_CNT
e a P i The total number of packets received that are less than 64 octets in
C o n n a n
length, excluding framing bits but including FCS octets and had either a
bad Frame Check Sequence (FCS) with an integral number of octets (FCS
Error) or a bad FCS with a non-integral number of octets (Alignment
T e k r B a Error).
d i a F o
Me 00004084
Bit 31
ROSPC_P0
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
r
RX_OVERSIZE_CNT
Type RO
f o
Reset 0 0 0 0
l e a
0 0 0 0 0 0 0 0 0 0
se 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a l R RX_OVERSIZE_CNT
Type
e n t i
RO
Reset
i d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o n f n a P
Bit(s) Name
k C a n a Description
31:0
i a T e o r B
RX_OVERSIZE_CNT The number of frames with length larger than the maximum frame size,
received without any error.
Me d F
00004088 RJEPC_P0 RX Jabber Error Packet Counter of Port 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o r
ef
Name RX_JABB_ERR_CNT
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_JABB_ERR_CNT
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 534 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f i d
RX_JABB_ERR_CNT
e a P i The total number of packets received that are longer than 1518 octets
C o n n a n
excluding framing bits, but including FCS octets, and had either a bad
Frame Check Sequence (FCS) with an integral number of octets (FCS
T e k r B a Error).
d i a F o
Me 0000408C
Bit 31
RPPC_P0
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
r
RX_PAUSE_CNT
Type RO
f o
Reset 0 0 0 0
l e a
0 0 0 0 0 0 0 0 0 0
se 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a l R RX_PAUSE_CNT
Type
e n t i
RO
Reset
i d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o n f n a P
Bit(s) Name
31:0
i a T e o r B
RX_PAUSE_CNT The number of correctly received MAC flow-control frame.
Me d
00004090
F RL64PC_P0 RX packet Length in 64-byte slot Packet Counter 00000000
of Port 0
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_PKT_64_CNT
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_PKT_64_CNT
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 535 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f i
RX_PKT_64_CNT
d e a P i It indicates the total number of packets, including bad packets received
C o n n a n
equal to 64 octets in length, excluding framing bits but including FCS
octets.
T e k r B a
d i a F o
Me
00004094 RL65PC_P0 RX packet Length in 65-byte slot Packet Counter 00000000
of Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_PKT_65TO127_CNT
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i a l R RX_PKT_65TO127_CNT
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n
RX_PKT_65TO127_CNT
a
Description
It indicates the total number of packets, including bad packets received
i a T e o r B between 65 and 127 octets in length, excluding framing bits but

Me d F
of Port 0
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type RO
ele a
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
t i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
RX_PKT_128TO255_CNT
Type
Reset
o n f a n a
RO
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
RX_PKT_128TO255_CNT
a P i It indicates the total number of packets, including bad packets received
C o n n a n
T e k r B a
d i a F o
Me
0000409C RL256PC_P0 RX packet Length in 256-byte slot Packet Counter 00000000
of Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
RX_PKT_256TO511_CNT
Description
Me d F
000040A0 RL512PC_P0 RX packet Length in 512-byte slot Packet Counter 00000000
of Port 0
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type RO
ele a
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
t i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
RX_PKT_512TO1023_CNT
Type
Reset
o n f a n a
RO
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
C o n n a n
between 512 and 1023 octets in length, excluding framing bits but
T e k r B a
d i a F o
Me
000040A4 RL1024PC_P0 RX packet Length in 1024-byte slot Packet 00000000
Counter of Port 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_PKT_1024TOMAX_CNT
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i a l R RX_PKT_1024TOMAX_CNT
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
RX_PKT_1024TOMAX_CNT
Description
i a T e o r B between 1024 and MAX_FRAME_SIZE octets in length, excluding

framing bits but including FCS octets.
Me d F
000040A8 ROCL_P0 RX Octet Counter Low double word of Port 0 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_OCT_CNT_L
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_OCT_CNT_L
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 538 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f
RX_OCT_CNT_L
i d e a P i {RX_OCT_CNT_H, RX_OCT_CNT_L} represents the number of bytes
C o n n a n
received in good or bad frames, excluding preamble bits but including
FCS octets.
RX_OCT_CNT_GOOD bit = 1 (enabled), good packet bytes counted.
T e k r B a RX_OCT_CNT_GOOD bit = 0 (disabled), good packet bytes not counted.
d i a F o RX_OCT_CNT_BAD bit = 1 (enabled), bad packet bytes counted.
Me
RX_OCT_CNT_BAD bit = 0 (disabled), bad packet bytes not counted.
000040AC ROCH_P0 Rx Octet Counter High double word of Port 0
f o r
00000000
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e l e a RX_OCT_CNT_H
R
Type RO
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
i d e n
13
P
12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
o n f a n a
RX_OCT_CNT_H
RO
Reset
e
0
k C 0
B a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) T Name
F o r Description
Me 31:0 RX_OCT_CNT_H Refer to RX_OCT_CNT_L (above)
o r
ef
000040B0 RDPC_CTRL_P0 RX CTRL Drop Packet Counter of Port 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Name RX_CTRL_DROP_CNT
Type
i a l R RO
t
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
i d e n 13
P i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
o n f a n a RX_CTRL_DROP_CNT
Type
e k C B a n
RO
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
Bit(s) Name
k a
31:0 RX_CTRL_DROP_CNT The number of event which the frame should be dropped due to error
i a T e o r B interrupt issued by RX_CTRL
Me d
000040B4
F RDPC_ING_P0 RX Ingress Drop Packet Counter of Port 0 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_ING_DROP_CNT
f o r
se
Type RO
Reset
Bit
0
15
0
14
0
13
0
12
e l e a 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Name
i a l R RX_ING_DROP_CNT
Type
e n t i
RO
Reset 0 0
n f i d 0
n a P
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
k C o a n a Description
31:0
i a T e r B
RX_ING_DROP_CNT
o
The number of event which the frame should be dropped according to
the ingress rate limit set by the Ingress rate limiter
Me d F
000040B8 RDPC_ARL_P0 RX ARL Drop Packet Counter of Port 0 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_ARL_DROP_CNT
ef o
Type RO
a s
Reset
Bit
0
15
0
14
0
13
l R
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5 ele0
4
0
3
0
2
0
1
0
Name
n t i a RX_ARL_DROP_CNT
Type
f i d e a P i RO
Reset 0
C o n 0
n a n
0 0 0 0 0 0 0 0 0 0 0 0 0 0
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d
RX_ARL_DROP_CNT
e a P i The number of event which the frame should be dropped due to
C o n n a n
broadcast Storm Control, trTCM or ACL Rate Limit
T e k r B a
d i a
000040D0
F oTMIB_HF_STS_P0 TX Port MIB Counter Half Full Status of Port 0 00000000
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXOCT TXL102 TXL512

Name _HF_ST 4_HF_S _HF_ST
S TS S
Type W1C
f o r
W1C W1C
se
Reset 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
R
TXL256 TXL128 TXPAU TXECOL TXLCOL TXMCO TXSCOL TXBRD TXMUL TXDRO
l
TXL65_ TXL64_ TXDFR_ TXCOL_ TXUNI_ TXCRC_
Name _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST L_HF_S _HF_ST _HF_ST _HF_ST P_HF_S
a
HF_STS HF_STS HF_STS HF_STS HF_STS HF_STS
i
S S S S S TS S S S TS
Type W1C W1C
e n
W1C
t W1C
i
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0
n f i d 0
n a P 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
k
Name
18
i a T e r B
TXOCT_HF_STS
o
TX Octet Counter Half Full Status
Me d
17
F
TXL1024_HF_STS
0: False
1: True
TX Packet Length above 1024 Bytes Counter Half Full Status
0: False
1: True
o r
ef
16 TXL512_HF_STS TX Packet Length 512 ~ 1023 Bytes Counter Half Full Status
0: False
a s
ele
1: True
15 TXL256_HF_STS
i a l R TX Packet Length 256 ~ 511 Bytes Counter Half Full Status
0: False
e n t i
1: True
14
n f i d
TXL128_HF_STS
n a P
TX Packet Length 128 ~ 255 Bytes Counter Half Full Status
o
0: False
k C a n a 1: True
i a T e o r B
M e d F
Page 541 of 830
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Confidential A
Bit(s) Name
n t i a Description
13
f
TXL65_HF_STS
i d e a P i TX Packet Length 65 ~ 127 Bytes Counter Half Full Status
1: True
12
T e k B
TXL64_HF_STS
r a TX Packet Length 64 Bytes Counter Half Full Status
d i a F o 0: False
Me
1: True
11 TXPAU_HF_STS TX Pause Packet Counter Half Full Status
0: False
1: True
10 TXECOL_HF_STS TX Excessive Collision Counter Half Full Status
f o r
l e a
0: False
1: True
se
9 TXLCOL_HF_STS
l R e TX Late Collision Counter Half Full Status
a
0: False
e n t i 1: True
i
8 TXDFR_HF_STS TX Deferred Counter Half Full Status
n f i d n a P 0: False
k C o
TXMCOL_HF_STS
a n a
1: True
TX Multiple Collision Counter Half Full Status
F
1: True
Me d6 TXSCOL_HF_STS TX Single Collision Counter Half Full Status
0: False
1: True
5 TXCOL_HF_STS TX Collision Event Counter Half Full Status
o r
ef
0: False
s
1: True
4 TXBRD_HF_STS TX Broadcast Counter Half Full Status
ele a
i a l R 0: False
1: True
3 TXMUL_HF_STS
e n t i
TX Multicast Counter Half Full Status
n f i d n a P
0: False
1: True
C o
TXUNI_HF_STS
k a n a TX Unicast Counter Half Full Status
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
C o n
TXCRC_HF_STS
n a n
1: True
TX CRC Counter Half Full Status
a o
1: True
d i F
Me
0 TXDROP_HF_STS TX DROP Counter Half Full Status
0: False
1: True
f o r
000040D4
Bit 31
RMIB_HF_STS_P0
30 29 28
l e a 27 26
25 24 23 22 21 20 19
se
18
00000000
17 16
Name
l R e RXARL
_HF_ST
RXING_
RXCTRL RXOCT RXL102 RXL512
_HF_ST _HF_ST 4_HF_S _HF_ST
a
HF_STS
i
S S S TS S
Type
e n t i
W1C W1C W1C W1C W1C W1C
Reset
n f i d n a P 0 0 0 0 0 0
Bit 15
k C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1 0
e B
RXL256 RXL128 RXPAU RXOVR RXFRG RXUND RXCRC RXALG RXBRD RXMUL RXDRO
RXL65_ RXL64_ RXJAB_ RXUNI_ RXFIL_
T r
Name _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST P_HF_S
HF_STS HF_STS HF_STS HF_STS HF_STS
a o
S S S S S S S S S S TS
d i F
Me
Type W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
21 RXARL_HF_STS RX ARL Drop Counter Half Full Status
ef o
0: False
a s
ele
1: True
20 RXING_HF_STS
i a l R RX Ingress Drop Counter Half Full Status
0: False
e n t i
1: True
19
n f i d
RXCTRL_HF_STS
n a P
RX CTRL Drop Counter Half Full Status
o
0: False
k C a n a 1: True
i a T e o r B
M e d F
Page 543 of 830
f o r
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l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
18
f
RXOCT_HF_STS
i d e a P i RX Octet Counter Half Full Status
1: True
17
T e k B
RXL1024_HF_STS
r a RX Packet Length above 1024 Bytes Counter Half Full Status
d i a F o 0: False
Me
1: True
16 RXL512_HF_STS RX Packet Length 512 ~ 1023 Bytes Counter Half Full Status
0: False
1: True
f o r
l e a
0: False
1: True
se
14 RXL128_HF_STS
l R e RX Packet Length 128 ~ 255 Bytes Counter Half Full Status
a
0: False
e n t i 1: True
i
12
k C o
RXL64_HF_STS
a n a
1: True
RX Packet Length 64 Bytes Counter Half Full Status
F
1: True
Me d
11 RXPAU_HF_STS RX Pause Packet Counter Half Full Status
0: False
1: True
10 RXJAB_HF_STS RX Jabber Error Counter Half Full Status
o r
ef
0: False
s
1: True
9 RXOVR_HF_STS RX Oversize Packet Counter Half Full Status
ele a
i a l R 0: False
1: True
8 RXFRG_HF_STS
e n t i
RX Fragment Error Counter Half Full Status
n f i d n a P
0: False
1: True
C o
RXUND_HF_STS
k a n a RX Undersize Packet Counter Half Full Status
i a T e o r B
M e d F
Page 544 of 830
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Confidential A
Bit(s) Name
n t i a Description
C o n
RXCRC_HF_STS
n a n
1: True
RX CRC ERROR Counter Half Full Status
a o
1: True
d i F
Me
5 RXALG_HF_STS RX Alignment Error Counter Half Full Status
0: False
1: True
4 RXBRD_HF_STS RX Broadcast Counter Half Full Status
0: False
f o r
se
1: True
3 RXMUL_HF_STS
e l e a RX Multicast Counter Half Full Status
0: False
i a l R 1: True
2 RXUNI_HF_STS
e n t i
RX Unicast Counter Half Full Status
0: False
n f i d n a P 1: True
k C o
RXFIL_HF_STS
a n a
RX Filtering Counter Half Full Status
0: False
i a T e o r B 1: True
F
0 RXDROP_HF_STS RX DROP Counter Half Full Status
Me d 0: False
1: True
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Name TX_DROP_CNT
Type
i a l R RO
Reset 0 0
e n t0
i
0 0 0 0 0 0 0 0 0 0 0 0 0
d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
o n f i n a P TX_DROP_CNT
Type
k C a n a RO
i a T e o r B
M e d F
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n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
Bit(s) Name
k a
31:0 TX_DROP_CNT The number of event when the frame output should be dropped due to
i a T e o r B the late collision or excessive collision
Me d
00004104
F TCRC_P1 TX CRC Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_CRC_CNT
f o r
se
Type RO
Reset
Bit
0
15
0
14
0
13
0
12
e l e a 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Name
i a l R TX_CRC_CNT
Type
e n t i
RO
Reset 0 0
n f i d 0
n a P
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
i a T e r
TX_CRC_CNT
o B The number of event which the frame will output a CRC packet due to
TX FIFO underrun
Me d F
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_UCAST_CNT
ef o
Type RO
a s
Reset
Bit
0
15
0
14
0
13
l R
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5 ele0
4
0
3
0
2
0
1
0
Name
n t i a TX_UCAST_CNT
Type
f i d e a P i RO
Reset 0
C o n 0
n a n
0 0 0 0 0 0 0 0 0 0 0 0 0 0
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f
TX_UCAST_CNT
i d e a P i The number of unicast frames transmitted without any error. It
C o n n a n
retransmission
T e k r B a
d i a F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_MCAST_CNT
r
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
Bit 15 14 13 12
l e a
11 10 9 8 7 6 5 4 3 2
se 1 0
e
Name TX_MCAST_CNT
Type
i a l R RO
Reset 0 0
e n
0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
C o
TX_MCAST_CNT
i a T e o r B
Me d
00004110
Bit 31
F TBPC_P1
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name TX_BCAST_CNT
Type RO
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
le a s
3 2 1 0
Name
l R e TX_BCAST_CNT
a
Type RO
Reset 0 0
e n t i 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31:0
k C o a n
TX_BCAST_CNT
i a T e o r B
Med F
Page 547 of 830
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Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00004114
Bit
T e k
31
TCEC_P1
r
30
B a 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_COL_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_COL_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_COL_CNT
i d e n P i
The total number of collision events occurred during frame transmission
o n f a n a
00004118
e k C B a n
TSCEC_P1 TX Single Collision Event Counter of Port 1 00000000
d a
Bit
i T 31
F o r 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Name TX_SCOL_CNT
M Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r 0
ef
Name TX_SCOL_CNT
Type RO
a s
Reset 0 0 0
l R
0 0 0 0 0 0 0 0
ele0 0 0 0 0
Bit(s) Name
n t i a Description
31:0
i
TX_SCOL_CNT
f d e a P i The number of frames transmitted without any error following a single

collision
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
0000411C
i d
TMCEC_P1
f e a P i TX Multiple Collision Event Counter of Port 1 00000000
n
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
C o n a n TX_MCOL_CNT
Type
T e k r B a RO
d i
Reset
a 0
F o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MCOL_CNT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0
r 0
Bit(s) Name
l e a Description
se
31:0 TX_MCOL_CNT
l R e The number of frames transmitted without any error following multiple

collisions
n t i a
f i d e a P i
00004120
Bit 31
C o n
TDEC_P1
30
n a
29
n 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
T e k r B a TX_DEFER_CNT
i
Type
d a F o
RO
Me
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_DEFER_CNT
Type RO
o r
Reset 0 0 0 0 0 0 0 0 0 0 0 0
a s
0 0
ef0 0
Bit(s)
31:0
Name
TX_DEFER_CNT
l R
Description
ele
The number of frames deferred at the first transmit attempt due to a
n t i a busy medium in half duplex mode
f i d e a P i
Frame involved in collision is not counted.
C o n n a n
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
00004124 TLCEC_P1
n t i a TX Late Collision Event Counter of Port 1 00000000

Bit 31 30
f i d e 29
a P i
28 27 26 25 24 23 22 21 20 19 18 17 16
Name
C o n n a n TX_LCOL_CNT
a
Type RO
Reset
T e0
k r
0
B 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i
Bit
a 15
F o 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me
Name TX_LCOL_CNT
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
se
31:0 TX_LCOL_CNT
e l e a The number of transmission abortion due to a collision occurring after

i a l R
e n t i
00004128
Bit 31
n
30
f i d
TXCEC_P1
29
n a P 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
k C o a n a TX_XCOL_CNT
Type
i a T e o r B RO
F
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Me d
Bit
Name
15 14 13 12 11 10 9 8
TX_XCOL_CNT
7 6 5 4 3 2 1 0
Type RO
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a s
ele
R
31:0 TX_XCOL_CNT The number of frames that have experienced MAX_COL_NUM (default
t i a l 16) consecutive collisions or more, not including late collisions
i d e n P i
0000412C
o n f
TPPC_P1
a n a TX Pause Packet Counter of Port 1 00000000
C n
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
Name TX_PAUSE_CNT
Type
n f i d a P i RO
Reset 0
C o 0
n a
0
n 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
T e k
15 14
r B a 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Name
o
TX_PAUSE_CNT
d i F
Me
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
31:0 TX_PAUSE_CNT The number of correctly transmitted MAC flow-control frame
f o
l e a se
00004130 TL64PC_P1
l R e TX packet Length in 64-byte slot Packet Counter 00000000
Bit 31 30
n
29
t i a 28 27 26
of Port 1
25 24 23 22 21 20 19 18 17 16
Name
f i d e a P i TX_PKT_64_CNT
Type
C o n n a n RO
Reset
Bit
T e
0
k
15
0
r
14
B a 0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
d
Name
i a F o TX_PKT_64_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
o r
ef
31:0 TX_PKT_64_CNT
s
a
ele
i a l R
e n t i
d
Bit 31
o n f
30
i n
29
a P 28 27 26
of Port 1
25 24 23 22 21 20 19 18 17 16
k C a n a
i a T e o r B
M e d F
Page 551 of 830
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Confidential A
n t i a
e
Type
n f i d a P i RO
Reset 0
C o 0
n a
0
n 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
T e k
15 14
r B a 13 12 11 10 9 8 7 6 5 4 3 2 1 0
a
Name
o
TX_PKT_65TO127_CNT
d i F
Me
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
f o
se
transmitted between 65 and 127 octets in length, excluding framing bits
a
R e l e
t i a l
n
Bit 31 30
f i d e 29
a P i
28 27 26
of Port 1
25 24 23 22 21 20 19 18 17 16
Name
C o n n a n TX_PKT_128TO255_CNT
Type
Reset
T e0k r
0
B a 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
d i
Bit
a 15
F o 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Me Name
Type
TX_PKT_128TO255_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r 0
a s ef
ele
R
t i a l bits but including FCS octets.
i d e n P i
0000413C
o n f
TL256PC_P1
a n a TX packet Length in 256-byte slot Packet Counter 00000000
C
of Port 1
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
n f i d a P i TX_PKT_256TO511_CNT
Type
C o n a n RO
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a o
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
d i F
Me
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
31:0 TX_PKT_256TO511_CNT
l e a
se
e
i a l R
e n t i
00004140
n f i d
TL512PC_P1
n a P
TX packet Length in 512-byte slot Packet Counter
of Port 1
00000000
Bit
Name
31
k C o 30
a n a
29 28 27 26 25 24 23
22 21 20 19 18 17 16
Type
i a T e o r B RO
Me d
Reset
Bit
0
15 F 0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type RO
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a s
ele
31:0 TX_PKT_512TO1023_CNT
i a l R It indicates the total number of packets, including bad packets

e n t i
n f i d n a P
00004144
k C o n a
TL1024PC_P1
a
TX packet Length in 1024-byte slot Packet 00000000
e B
Counter of Port 1
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
31 30
n
29
t i a 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Bit
Name
n f i d a P i TX_PKT_1024TOMAX_CNT
Type
C o n a n RO
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a o
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
d i F
Me
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o r
31:0 TX_PKT_1024TOMAX_CNT
l e a
transmitted between 1024 and MAX_FRAME_SIZE octets in length,
se
e
i a l R
e n t i
00004148
Bit 31
n
30
f i
TOCL_P1
d 29
n a P 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
k C o a n a TX_OCT_CNT_L
Type
i
Reset
a T e0
o r
0 B 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
Me d
Bit
Name
15
F 14 13 12 11 10 9 8
TX_OCT_CNT_L
7 6 5 4 3 2 1 0
Type RO
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
a s
ele
31:0 TX_OCT_CNT_L {TX_OCT_CNT_H, TX_OCT_CNT_L} represents the number of bytes
i a l R transmitted in good or bad frames, excluding preamble bits but

e n t i
d
TX_OCT_CNT_GOOD bit = 0 (disabled), good packet bytes not counted.
o n f i n a P TX_OCT_CNT_BAD bit = 1 (enabled), bad packet bytes counted.
k C a n a TX_OCT_CNT_BAD bit = 0 (disabled), bad packet bytes not counted.
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
0000414C
Bit
T e k
31
TOCH_P1
r
30
B a 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_OCT_CNT_H
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_OCT_CNT_H
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_OCT_CNT_H
i d e n P i
Refer to TX_OCT_CNT_L (above).
o n f a n a
00004160
e k C B a
RDPC_P1
n RX Drop Packet Counter of Port 1 00000000
d a
Bit
i T 31
F o r 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
e
Name RX_DROP_CNT
M Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
o r 0
ef
Name RX_DROP_CNT
Type RO
a s
Reset 0 0 0
l R
0 0 0 0 0 0 0 0
ele0 0 0 0 0
Bit(s) Name
n t i a Description
31:0
i
RX_DROP_CNT
f d e a P i The number of event which the frame should be dropped due to
C o n n a n
1. an internal buffer shortage by RX_CTRL
2. ingress rate limit by Ingress rate limiter
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i 3. broadcast Storm Control, trTCM or ACL Rate Limit
C o n n a n
T e k r B a
d i
Bit
a
00004164
31
F o
RFPC_P1
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Me Name
Type
RX_FILTER_CNT
RO
r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o1 0
Name
l e a
RX_FILTER_CNT
se
e
Type RO
Reset 0 0 0
i a l R0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
n f i
RX_FILTER_CNT
d n a P The number of frames which is filtered by ARL module due to ARL
k C o a n a
security, length error, control frame, or when the port map is equal to
zero
i a T e o r B
Me d
00004168
Bit 31
F RUPC_P1
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name RX_UCAST_CNT
Type RO
o r
Reset 0 0 0 0 0 0 0 0 0 0 0 0
a
0
s
0
ef0 0
le
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
l R e RX_UCAST_CNT
Type
i a
RO
Reset 0 0
e n t 0
i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
k C o a n a
i a T e o r B
Med F
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Confidential A
Bit(s) Name
n t i a Description
31:0
f
RX_UCAST_CNT
i d e a P i The number of unicast frames with length between 64 bytes and the
C o n n a n
frames
T e k r B a
d i a F o
Me
0000416C RMPC_P1 RX Multicast Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_MCAST_CNT
r
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
Bit 15 14 13 12
l e a
11 10 9 8 7 6 5 4 3 2
se 1 0
e
Name RX_MCAST_CNT
Type
i a l R RO
Reset 0 0
e n
0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
C o
RX_MCAST_CNT
k a n a The number of multicast frames with length between 64 bytes and the
i a T e o r B frames
Me d
00004170
F RBPC_P1 RX Broadcast Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_BCAST_CNT
o r
Type RO
a s ef
le
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
l R e 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a
RX_BCAST_CNT
Type
e n t i
RO
Reset 0
n f i0
d n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 557 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f
RX_BCAST_CNT
i d e a P i The number of broadcast frames with length between 64 bytes and the
C o n n a n
frames
T e k r B a
d i a F o
Me
00004174 RAEPC_P1 RX Alignment Error Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
Bit 15 14 13 12
l e a
11 10 9 8 7 6 5 4 3 2
se 1 0
e
Type
i a l R RO
Reset 0 0
e n
0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
C o
RX_ALIGN_ERR_CNT
k a n a The number of frames with length between 64 bytes and the maximum
i a T e o r B error or RX_ER asserted
Me d
00004178
F RCEPC_P1 RX CRC(FCS) Error Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_FCS_ERR_CNT
o r
Type RO
a s ef
le
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
l R e 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a
RX_FCS_ERR_CNT
Type
e n t i
RO
Reset 0
n f i0
d n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 558 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f i
RX_FCS_ERR_CNT
d e a P i The number of frames with length between 64 bytes and the maximum
C o n n a n
RX_ER asserted
T e k r B a
d i a F o
Me
0000417C RUSPC_P1 RX Undersize Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
r
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
Bit 15 14 13 12
l e a
11 10 9 8 7 6 5 4 3 2
se 1 0
e
Type
i a l R RO
Reset 0 0
e n
0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
C o
RX_UNDERSIZE_CNT
k a n a The total number of packets received that are less than 64 octets long
excluding framing bits, but including FCS octets which are otherwise
i a T e o r B well formed
Me d
00004180
F RFEPC_P1 RX Fragment Error Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o r
Type RO
a s ef
le
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
l R e 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i a
RX_FRAG_ERR_CNT
Type
e n t i
RO
Reset 0
n f i0
d n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C o a n a
i a T e o r B
Med F
Page 559 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f i d
RX_FRAG_ERR_CNT
C o n n a n
length, excluding framing bits but including FCS octets and have either a
T e k r B a Error).
d i a F o
Me 00004184
Bit 31
ROSPC_P1
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
r
RX_OVERSIZE_CNT
Type RO
f o
Reset 0 0 0 0
l e a
0 0 0 0 0 0 0 0 0 0
se 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e n t i
RO
Reset
i d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o n f n a P
Bit(s) Name
31:0
i a T e o r B
received without any error
Me d F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o r
ef
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_JABB_ERR_CNT
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
31:0
f i d
RX_JABB_ERR_CNT
e a P i The total number of packets received that are longer than 1518 octets
C o n n a n
excluding framing bits, but including FCS octets and have either a bad
T e k r B a Error)
d i a F o
Me 0000418C
Bit 31
RPPC_P1
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
r
RX_PAUSE_CNT
Type RO
f o
Reset 0 0 0 0
l e a
0 0 0 0 0 0 0 0 0 0
se 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e n t i
RO
Reset
i d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o n f n a P
Bit(s) Name
31:0
i a T e o r B
RX_PAUSE_CNT The number of correctly received MAC flow-control frame
Me d
00004190
of Port 1
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_PKT_64_CNT
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_PKT_64_CNT
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
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Confidential A
Bit(s) Name
n t i a Description
31:0
f i
RX_PKT_64_CNT
C o n n a n
and equal to 64 octets in length, excluding framing bits but including
FCS octets.
T e k r B a
d i a F o
Me
of Port 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n
RX_PKT_65TO127_CNT
a
Description

Me d F
of Port 1
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type RO
ele a
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
t i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
RX_PKT_128TO255_CNT
Type
Reset
o n f a n a
RO
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
RX_PKT_128TO255_CNT
C o n n a n
and transmitted between 128 and 255 octets in length, excluding
T e k r B a
d i a F o
Me
of Port 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
RX_PKT_256TO511_CNT
Description
Me d F
of Port 1
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type RO
ele a
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
t i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
Type
Reset
o n f a n a
RO
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
C o n n a n
T e k r B a
d i a F o
Me
Counter of Port 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
Description

Me d F
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_OCT_CNT_L
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_OCT_CNT_L
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 564 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f
RX_OCT_CNT_L
C o n n a n
FCS octets.
Me
f o r
00000000
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e l e a RX_OCT_CNT_H
R
Type RO
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
i d e n
13
P
12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
o n f a n a
RX_OCT_CNT_H
RO
Reset
e
0
k C 0
B a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) T Name
F o r Description
Me 31:0 RX_OCT_CNT_H Refer to RX_OCT_CNT_L (above)
o r
ef
000041B0 RDPC_CTRL_P1 RX CTRL Drop Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Name RX_CTRL_DROP_CNT
Type
i a l R RO
t
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
i d e n 13
P i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
o n f a n a RX_CTRL_DROP_CNT
Type
e k C B a n
RO
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
Bit(s) Name
k a
31:0 RX_CTRL_DROP_CNT The number of event which the frame should be dropped due to error
i a T e o r B interrupt issued by RX_CTRL
Me d
000041B4
F RDPC_ING_P1 RX Ingress Drop Packet Counter of Port 1 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_ING_DROP_CNT
f o r
se
Type RO
Reset
Bit
0
15
0
14
0
13
0
12
e l e a 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Name
i a l R RX_ING_DROP_CNT
Type
e n t i
RO
Reset 0 0
n f i d 0
n a P
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
i a T e r B
RX_ING_DROP_CNT
o
The number of event which the frame should be dropped due to a
ingress rate limit by Ingress rate limiter
Me d F
000041B8 RDPC_ARL_P1 RX ARL Drop Packet Counter of Port 1 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_ARL_DROP_CNT
ef o
Type RO
a s
Reset
Bit
0
15
0
14
0
13
l R
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5 ele0
4
0
3
0
2
0
1
0
Name
n t i a RX_ARL_DROP_CNT
Type
f i d e a P i RO
Reset 0
C o n 0
n a n
0 0 0 0 0 0 0 0 0 0 0 0 0 0
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d
RX_ARL_DROP_CNT
e a P i The number of event which the frame should be dropped due to
C o n n a n
broadcast Storm Control, trTCM or ACL Rate Limit
T e k r B a
d i a
000041D0
F oTMIB_HF_STS_P1 TX Port MIB Counter Half Full Status of Port 1 00000000
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXOCT TXL102 TXL512

Name _HF_ST 4_HF_S _HF_ST
S TS S
Type W1C
f o r
W1C W1C
se
Reset 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
R
TXL256 TXL128 TXPAU TXECOL TXLCOL TXMCO TXSCOL TXBRD TXMUL TXDRO
l
TXL65_ TXL64_ TXDFR_ TXCOL_ TXUNI_ TXCRC_
Name _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST L_HF_S _HF_ST _HF_ST _HF_ST P_HF_S
a
HF_STS HF_STS HF_STS HF_STS HF_STS HF_STS
i
S S S S S TS S S S TS
Type W1C W1C
e n
W1C
t W1C
i
W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0
n f i d 0
n a P 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s)
k
Name
18
i a T e r B
TXOCT_HF_STS
o
TX Octet Counter Half Full Status
Me d
17
F
TXL1024_HF_STS
0: False
1: True
TX Packet Length above 1024 Bytes Counter Half Full Status
0: False
1: True
o r
ef
16 TXL512_HF_STS TX Packet Length 512 ~ 1023 Bytes Counter Half Full Status
0: False
a s
ele
1: True
15 TXL256_HF_STS
i a l R TX Packet Length 256 ~ 511 Bytes Counter Half Full Status
0: False
e n t i
1: True
14
n f i d
TXL128_HF_STS
n a P
TX Packet Length 128 ~ 255 Bytes Counter Half Full Status
o
0: False
k C a n a 1: True
i a T e o r B
M e d F
Page 567 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
13
f
TXL65_HF_STS
i d e a P i TX Packet Length 65 ~ 127 Bytes Counter Half Full Status
1: True
12
T e k B
TXL64_HF_STS
r a TX Packet Length 64 Bytes Counter Half Full Status
d i a F o 0: False
Me
1: True
11 TXPAU_HF_STS TX Pause Packet Counter Half Full Status
0: False
1: True
10 TXECOL_HF_STS TX Excessive Collision Counter Half Full Status
f o r
l e a
0: False
1: True
se
9 TXLCOL_HF_STS
l R e TX Late Collision Counter Half Full Status
a
0: False
e n t i 1: True
i
8 TXDFR_HF_STS TX Deferred Counter Half Full Status
k C o
TXMCOL_HF_STS
a n a
1: True
TX Multiple Collision Counter Half Full Status
F
1: True
Me d6 TXSCOL_HF_STS TX Single Collision Counter Half Full Status
0: False
1: True
5 TXCOL_HF_STS TX Collision Event Counter Half Full Status
o r
ef
0: False
s
1: True
4 TXBRD_HF_STS TX Broadcast Counter Half Full Status
ele a
i a l R 0: False
1: True
3 TXMUL_HF_STS
e n t i
TX Multicast Counter Half Full Status
n f i d n a P
0: False
1: True
C o
TXUNI_HF_STS
k a n a TX Unicast Counter Half Full Status
i a T e o r B
M e d F
Page 568 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
C o n
TXCRC_HF_STS
n a n
1: True
TX CRC Counter Half Full Status
a o
1: True
d i F
Me
0 TXDROP_HF_STS TX DROP Counter Half Full Status
0: False
1: True
f o r
000041D4
Bit 31
RMIB_HF_STS_P1
30 29 28
l e a 27 26
25 24 23 22 21 20 19
se
18
00000000
17 16
Name
l R e RXARL
_HF_ST
RXING_
RXCTRL RXOCT RXL102 RXL512
_HF_ST _HF_ST 4_HF_S _HF_ST
a
HF_STS
i
S S S TS S
Type
e n t i
W1C W1C W1C W1C W1C W1C
Reset
n f i d n a P 0 0 0 0 0 0
Bit 15
k C o 14
a n a
13 12 11 10 9 8 7 6 5 4 3 2 1 0
e B
RXL256 RXL128 RXPAU RXOVR RXFRG RXUND RXCRC RXALG RXBRD RXMUL RXDRO
RXL65_ RXL64_ RXJAB_ RXUNI_ RXFIL_
T r
Name _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST _HF_ST P_HF_S
HF_STS HF_STS HF_STS HF_STS HF_STS
a o
S S S S S S S S S S TS
d i F
Me
Type W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
r
21 RXARL_HF_STS RX ARL Drop Counter Half Full Status
ef o
0: False
a s
ele
1: True
20 RXING_HF_STS
i a l R RX Ingress Drop Counter Half Full Status
0: False
e n t i
1: True
19
n f i d
RXCTRL_HF_STS
n a P
RX CTRL Drop Counter Half Full Status
o
0: False
k C a n a 1: True
i a T e o r B
M e d F
Page 569 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
18
f
RXOCT_HF_STS
i d e a P i RX Octet Counter Half Full Status
1: True
17
T e k B
RXL1024_HF_STS
r a RX Packet Length above 1024 Bytes Counter Half Full Status
d i a F o 0: False
Me
1: True
0: False
1: True
f o r
l e a
0: False
1: True
se
14 RXL128_HF_STS
l R e RX Packet Length 128 ~ 255 Bytes Counter Half Full Status
a
0: False
e n t i 1: True
i
12
k C o
RXL64_HF_STS
a n a
1: True
RX Packet Length 64 Bytes Counter Half Full Status
F
1: True
Me d
11 RXPAU_HF_STS RX Pause Packet Counter Half Full Status
0: False
1: True
10 RXJAB_HF_STS RX Jabber Error Counter Half Full Status
o r
ef
0: False
s
1: True
9 RXOVR_HF_STS RX Oversize Packet Counter Half Full Status
ele a
i a l R 0: False
1: True
8 RXFRG_HF_STS
e n t i
RX Fragment Error Counter Half Full Status
n f i d n a P
0: False
1: True
C o
RXUND_HF_STS
k a n a RX Undersize Packet Counter Half Full Status
i a T e o r B
M e d F
Page 570 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
C o n
RXCRC_HF_STS
n a n
1: True
RX CRC ERROR Counter Half Full Status
a o
1: True
d i F
Me
5 RXALG_HF_STS RX Alignment Error Counter Half Full Status
0: False
1: True
4 RXBRD_HF_STS RX Broadcast Counter Half Full Status
0: False
f o r
se
1: True
3 RXMUL_HF_STS
e l e a RX Multicast Counter Half Full Status
0: False
i a l R 1: True
2 RXUNI_HF_STS
e n t i
RX Unicast Counter Half Full Status
0: False
n f i d n a P 1: True
k C o
RXFIL_HF_STS
a n a
RX Filtering Counter Half Full Status
0: False
i a T e o r B 1: True
F
0 RXDROP_HF_STS RX DROP Counter Half Full Status
Me d 0: False
1: True
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Name TX_DROP_CNT
Type
i a l R RO
Reset 0 0
e n t0
i
0 0 0 0 0 0 0 0 0 0 0 0 0
d
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
o n f i n a P TX_DROP_CNT
Type
k C a n a RO
i a T e o r B
M e d F
Page 571 of 830
f o r
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l R e Lynx1
Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
Bit(s) Name
k a
31:0 TX_DROP_CNT The number of event which the frame should be dropped on output due
i a T e o r B to the late collision or excessive collision
Me d
00004204
F TCRC_P2 TX CRC Packet Counter of Port 2 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_CRC_CNT
f o r
se
Type RO
Reset
Bit
0
15
0
14
0
13
0
12
e l e a 0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Name
i a l R TX_CRC_CNT
Type
e n t i
RO
Reset 0 0
n f i d 0
n a P
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
i a T e r
TX_CRC_CNT
o B The number of event which the frame will output a CRC packet due to
TX FIFO underrun
Me d F
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_UCAST_CNT
ef o
Type RO
a s
Reset
Bit
0
15
0
14
0
13
l R
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5 ele0
4
0
3
0
2
0
1
0
Name
n t i a TX_UCAST_CNT
Type
f i d e a P i RO
Reset 0
C o n 0
n a n
0 0 0 0 0 0 0 0 0 0 0 0 0 0
T e k r B a
e d i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f
TX_UCAST_CNT
i d e a P i The number of unicast frames transmitted without any error, which
C o n n a n
retransmission
T e k r B a
d i a F o
Me
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_MCAST_CNT
r
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f o0 0
Bit 15 14 13 12
l e a
11 10 9 8 7 6 5 4 3 2
se 1 0
e
Name TX_MCAST_CNT
Type
i a l R RO
Reset 0 0
e n
0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
C o
TX_MCAST_CNT
i a T e o r B
Me d
00004210
Bit 31
F TBPC_P2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name TX_BCAST_CNT
Type RO
o r
ef
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4
le a s
3 2 1 0
Name
l R e TX_BCAST_CNT
a
Type RO
Reset 0 0
e n t i 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
n
31:0
k C o a n
TX_BCAST_CNT
i a T e o r B
Med F
Page 573 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00004214
Bit
T e k
31
TCEC_P2
r
30
B a 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_COL_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_COL_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_COL_CNT
i d e n P i
The total number of collision events occurrence during frame
f
transmission
C o n a n a
e k B a n
d i a
Bit
T
00004218
F
31
o rTSCEC_P2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
M e Name
Type
TX_SCOL_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_SCOL_CNT
a s
ele
Type RO
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
f i
TX_SCOL_CNT
n d n a P The number of frames transmitted without any error following a single
o
collision
k C a n a
i a T e o r B
M e d F
Page 574 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
0000421C
Bit
T e k
31
r
30
B a
TMCEC_P2
29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_MCOL_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_MCOL_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_MCOL_CNT
i d e n P i
The number of frames transmitted without any error following multiple
f
collisions
C o n a n a
e k B a n
d i a
Bit
T
00004220
F
31
o rTDEC_P2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
M e Name
Type
TX_DEFER_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_DEFER_CNT
a s
ele
Type RO
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
f i
TX_DEFER_CNT
n d n a P The number of frames deferred at the first transmit attempt due to a
o
busy medium in half duplex mode. Frame involved in collision is not
k C a n a counted.
i a T e o r B
M e d F
Page 575 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00004224
Bit
T e k
31
r
30
B a
TLCEC_P2
29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_LCOL_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_LCOL_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_LCOL_CNT
i d e n P i
The number of transmission abortion due to a collision occurring after
f
C o n a n a
e k B a n
d i a
Bit
T
00004228
F
31
o rTXCEC_P2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
M e Name
Type
TX_XCOL_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_XCOL_CNT
a s
ele
Type RO
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
f i
TX_XCOL_CNT
n d n a P The number of frames that have experienced MAX_COL_NUM (default
o
16) consecutive collisions or more, not including late collisions
k C a n a
i a T e o r B
M e d F
Page 576 of 830
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
0000422C
Bit
T e k
31
TPPC_P2
r
30
B a 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
d
Name
i a F o TX_PAUSE_CNT
Me Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0 0 0 0 0 0
r
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PAUSE_CNT
f o
Type RO
l e a se
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a l R
t
31:0 TX_PAUSE_CNT
i d e n P i
The number of correctly transmitted MAC flow-control frame
o n f a n a
00004230
e k C B a n
TL64PC_P2 TX packet Length in 64-byte slot Packet Counter 00000000
d i a
Bit
T F
31
o r 30 29 28 27 26
of Port 2
25 24 23 22 21 20 19 18 17 16
M e Name
Type
TX_PKT_64_CNT
RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o r
ef
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TX_PKT_64_CNT
a s
ele
Type RO
Reset 0 0 0
i a l R 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
e n t i
Description
31:0
f i d
TX_PKT_64_CNT
n n a P It indicates the total number of packets, including bad packets
o
k C a n a including FCS octets.
i a T e o r B
M e d F
Page 577 of 830
f o r
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l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
f i d e a P i
C o n n a n
00004234
T e k r B a
TL65PC_P2 TX packet Length in 65-byte slot Packet Counter
of Port 2
00000000
i
Bit
d a 31
F o 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Me
Type RO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2
f o1
r 0
se
Type
e l e a RO
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t i a l
Bit(s) Name
i d e n P i
Description
f
C o n a n a transmitted between 65 and 127 octets in length, excluding framing bits

e k B a n
d i a T F o r
Me
of Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type
o r
ef
RO
s
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
e
12 11 10 9 8 7 6 5 4
le a 3 2 1 0
R
Type
t i a l RO
Reset 0
i
0
d e n 0
P i
0 0 0 0 0 0 0 0 0 0 0 0 0
o n f a n a
e k C B a n
i a T F o r
ed
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
TX_PKT_128TO255_CNT
C o n n a n
T e k r B a
d i a F o
Me
0000423C TL256PC_P2 TX packet Length in 256-byte slot Packet Counter 00000000
of Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i a l R TX_PKT_256TO511_CNT
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
TX_PKT_256TO511_CNT
Description
i a T e o r B transmitted between 256 and 511 octets in length, excluding framing

Me d F
of Port 2
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type RO
ele a
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
t i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
Type
Reset
o n f a n a
RO
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
C o n n a n
T e k r B a
d i a F o
Me
00004244 TL1024PC_P2 TX packet Length in 1024-byte slot Packet 00000000
Counter of Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
i a l R TX_PKT_1024TOMAX_CNT
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
TX_PKT_1024TOMAX_CNT
Description
i a T e o r B transmitted between 1024 and MAX_FRAME_SIZE octets in length,

Me d F
00004248 TOCL_P2 TX Octet Counter Low double word of Port 2 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TX_OCT_CNT_L
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
TX_OCT_CNT_L
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 580 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f
TX_OCT_CNT_L
i d e a P i {TX_OCT_CNT_H, TX_OCT_CNT_L} represents the number of bytes
C o n n a n
transmitted in good or bad frames, excluding preamble bits but
T e k r B a TX_OCT_CNT_GOOD bit = 0 (disabled), good packet bytes not counted.
d i a F o TX_OCT_CNT_BAD bit = 1 (enabled), bad packet bytes counted.
Me
TX_OCT_CNT_BAD bit = 0 (disabled), bad packet bytes not counted.
0000424C TOCH_P2 TX Octet Counter High double word of Port 2
f o r
00000000
se
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
e l e a TX_OCT_CNT_H
R
Type RO
Reset 0 0 0
t i a l 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
i d e n
13
P
12
i
11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
o n f a n a
TX_OCT_CNT_H
RO
Reset
e
0
k C 0
B a n 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a
Bit(s) T Name
F o r Description
Me 31:0 TX_OCT_CNT_H Refer to TX_OCT_CNT_L (above).
o r
ef
00004260 RDPC_P2 RX Drop Packet Counter of Port 2 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20
a s 19 18 17 16
ele
Name RX_DROP_CNT
Type
i a l R RO
t
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
i d e n 13
P i
12 11 10 9 8 7 6 5 4 3 2 1 0
Name
o n f a n a RX_DROP_CNT
Type
e k C B a n
RO
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
Bit(s) Name
k a
31:0 RX_DROP_CNT The number of event which the frame should be dropped due to
i a T e o r B 1. an internal buffer shortage by RX_CTRL
Me d F 2. ingress rate limit by Ingress rate limiter
3. broadcast Storm Control, trTCM or ACL Rate Limit
00004264 RFPC_P2 RX Filtering Packet Counter of Port 2

f o r
00000000
Bit
Name
31 30 29 28
l e a
27 26 25 24
RX_FILTER_CNT
23 22 21 20 19
se
18 17 16
Type
l R e RO
Reset 0 0
n
0
t i a 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
f i d e 13
a P i
12 11 10 9 8 7 6 5 4 3 2 1 0
n
Name RX_FILTER_CNT
Type
C o n a n RO
Reset
T e
0
k 0
r B a 0 0 0 0 0 0 0 0 0 0 0 0 0 0
d i a F o
Me
31:0 RX_FILTER_CNT The number of frames which is filtered by ARL module due to ARL
security, length error, control frame, or port map is equal to zero
o r
00004268 RUPC_P2 RX Unicast Packet Counter of Port 2
a s ef00000000
le
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
l R e RX_UCAST_CNT
Type
n t i a RO
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15
n f i d
14
a
13
P i 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
C o n a n RX_UCAST_CNT
T e k r B a
ed i a F o
M
f o r
l e a se MT7531
l R e Lynx1
Confidential A
n t i a
e
Type RO
Reset 0 0
n f i d 0
a P i0 0 0 0 0 0 0 0 0 0 0 0 0
C o n a n
k a
31:0
i a T e r B
RX_UCAST_CNT
o
The number of unicast frames with length between 64 bytes and the
Me d F frames
0000426C
Bit 31
RMPC_P2
30 29 28 27 26
25 24 23 22 21 20 19 18
f o
17
r
00000000
16
Name
Type
l e a
RX_MCAST_CNT
RO se
Reset 0 0 0
l R0
e 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
n t i a 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
f i d e a P i
RX_MCAST_CNT
n
Type RO
Reset 0
C o 0
n a0
n 0 0 0 0 0 0 0 0 0 0 0 0 0
T e k r B a
a o
d i F
Me
31:0 RX_MCAST_CNT The number of multicast frames with length between 64 bytes and the
frames
o r
00004270
Bit 31
RBPC_P2
30 29 28 27 26
25 24 23 22 21 20
a s 19 18
ef00000000
17 16
Name
Type
l R
RX_BCAST_CNT
ele
a
RO
Reset 0 0
e n t0
i 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15
n
14
f i d 13
a P i 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
C o n a n RX_BCAST_CNT
a
Type
k
RO
i a T e o r B
M e d F
Page 583 of 830
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Confidential A
n t i a
e
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d a P i
Bit(s) Name
k a
31:0 RX_BCAST_CNT The number of broadcast frames with length between 64 bytes and the
i a T e o r B maximum frame size, received without any error, including MAC control
frames
Me d
00004274
F RAEPC_P2 RX Alignment Error Packet Counter of Port 2 00000000
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
f o r
Type
Reset 0 0 0 0 0 0 0 0
RO
0 0 0
l0
e a 0 0se 0 0
Bit 15 14 13
l R 12 11 10 9 8 7 6 5
e 4 3 2 1 0
Name
n t i a RX_ALIGN_ERR_CNT
Type
f i d e a P i
RO
n
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C o n a n
Bit(s)
T e kName
r B a Description
e d i a
31:0
F o
RX_ALIGN_ERR_CNT The number of frames with length between 64 bytes and the maximum
error or RX_ER asserted
M
00004278 RCEPC_P2 RX CRC(FCS) Error Packet Counter of Port 2
o r
00000000
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_FCS_ERR_CNT
a s
Type
Reset
l R
RO
ele
a
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14
e n t i
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
n f i d a P i RX_FCS_ERR_CNT
Type
C o n a n RO
a
Reset 0 0
k
0 0 0 0 0 0 0 0 0 0 0 0 0 0
i a T e o r B
M ed F
Page 584 of 830
f o r
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Confidential A
n t i a
Bit(s) Name
31:0
C o n
RX_FCS_ERR_CNT
n a n The number of frames with length between 64 bytes and the maximum
k a
RX_ER asserted
i a T e o r B
Me d
0000427C
Bit 31
F RUSPC_P2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Type RO
f o r
Reset
se
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5
e l
4
e a 3 2 1 0
Name
i a l R RX_UNDERSIZE_CNT
t
Type RO
Reset 0 0
i d e n 0
P i
0 0 0 0 0 0 0 0 0 0 0 0 0
Bit(s) Name
31:0
e k C a n
RX_UNDERSIZE_CNT
B
The total number of packets received that are less than 64 octets long,
T
excluding framing bits but including FCS octets which are otherwise well
d i a F o r formed
M e00004280 RFEPC_P2 RX Fragment Error Packet Counter of Port 2 00000000
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_FRAG_ERR_CNT
d
Type
i
RO
Reset 0
o n f
0
n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 585 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f i d
RX_FRAG_ERR_CNT
C o n n a n
length, excluding framing bits but including FCS octets and have either a
T e k r B a Error)
d i a F o
Me 00004284
Bit 31
ROSPC_P2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
r
RX_OVERSIZE_CNT
Type RO
f o
Reset 0 0 0 0
l e a
0 0 0 0 0 0 0 0 0 0
se 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e n t i
RO
Reset
i d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o n f n a P
Bit(s) Name
31:0
i a T e o r B
received without any error
Me d F
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
o r
ef
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_JABB_ERR_CNT
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 586 of 830
f o r
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l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d
RX_JABB_ERR_CNT
e a P i The total number of packets received that are longer than 1518 octets,
C o n n a n
excluding framing bits but including FCS octets, and have either a bad
T e k r B a Error)
d i a F o
Me 0000428C
Bit 31
RPPC_P2
30 29 28 27 26
25 24 23 22 21 20 19 18
00000000
17 16
Name
r
RX_PAUSE_CNT
Type RO
f o
Reset 0 0 0 0
l e a
0 0 0 0 0 0 0 0 0 0
se 0 0
e
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
e n t i
RO
Reset
i d
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
o n f n a P
Bit(s) Name
31:0
i a T e o r B
RX_PAUSE_CNT The number of correctly received MAC flow-control frame
Me d
00004290
of Port 2
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_PKT_64_CNT
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_PKT_64_CNT
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 587 of 830
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Confidential A
Bit(s) Name
n t i a Description
31:0
f i
RX_PKT_64_CNT
C o n n a n
equal to 64 octets in length, excluding framing bits but including FCS
octets.
T e k r B a
d i a F o
Me
of Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n
RX_PKT_65TO127_CNT
a
Description

Me d F
of Port 2
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type RO
ele a
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
t i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
RX_PKT_128TO255_CNT
Type
Reset
o n f a n a
RO
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
RX_PKT_128TO255_CNT
C o n n a n
T e k r B a
d i a F o
Me
of Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
RX_PKT_256TO511_CNT
Description
Me d F
of Port 2
o r
ef
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
s
Type RO
ele a
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
t i a l 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
i d e n P i
Type
Reset
o n f a n a
RO
C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
e k B a n
d i a T F o r

f o r
l e a se MT7531
l R e Lynx1
Confidential A
Bit(s) Name
n t i a Description
31:0
f i d e
C o n n a n
T e k r B a
d i a F o
Me
Counter of Port 2
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Type RO
f o r
se
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12
e l e a 11 10 9 8 7 6 5 4 3 2 1 0
Name
Type
RO
Reset 0 0
e n0
t i
0 0 0 0 0 0 0 0 0 0 0 0 0
n f i d n a P
Bit(s)
31:0
Name
k C o a n a
Description

Me d F
r
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name RX_OCT_CNT_L
ef o
Type RO
a s
ele
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13
i a l R 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
e n t i
RX_OCT_CNT_L
d
Type RO
Reset 0
o n f
0
i n
0
a P 0 0 0 0 0 0 0 0 0 0 0 0 0
k C a n a
i a T e o r B
M e d F
Page 590 of 830
f o r
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Confidential A
Bit(s) Name
n t i a Description
31:0
f
RX_OCT_CNT_L
C o n n a n
FCS octets.
Me

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f o r

2 Address Resolution Logic (ARL) ............................................................................................... 7

a n a SCH Register .................................................................................................. 177

M e d F This document contains information that is proprietary to MediaTek Inc.

Features ........................................................................................................................... 406

o r B Overview of MIB Counters .............................................................................. 505

Serial Gigabit Media Independent Interface (SGMII) ............................................................ 712

7.1 Introduction ...................................................................................................................... 712

M e d F This document contains information that is proprietary to MediaTek Inc.

10.2 Features ........................................................................................................................... 760

10.3 Register Definition ........................................................................................................... 760

F o 0x10ff 256 Scheduler registers

l R e 768 I/O registers

1.2 GPHY memory map

entries rule control table.

2.3 Frame Classifications

k C a n a Protocol multicast address

Me 2.3.3 Unicast Frames

MAC Address Table

i a l R Filter ID is learned automatically from VLAN Table. 0 is the default value if

a n a 48-bits MAC Physical Address is searched by Destination MAC Address

11:4 PORT / FILTER

i a l R (Note: Frame dropped by DA Address through PORT=6’b0)

n a P Leaky VLAN Enable

k C o a n a 1’b1: This frame address can pass through VLAN

n t i a (Note: Leaky VLAN can be configured by ARL or Port Control Register

i a l R 3’b101: System Default and CPU Port Included

a n a Programmable age timer. The age duration can be set from 1 to

i a T e o r B AAC.AGE_CNT and counted down by one every AAC.AGE_UNIT seconds.

i a l R occurrence times of no IGMP Report message received before the

M e This document contains information that is proprietary to MediaTek Inc.

i a l R Address Entry Live Status

t i a l 3’b010 ~ 3’b011: Reserved

M e This document contains information that is proprietary to MediaTek Inc.

t i a l 2’b01: DIP Address Entry

a n a 2’b00: Group entry is empty

2.5 Virtual LAN

F o VLAN Entry Valid

i d e nbit[15:14]: Port 5 STAG index

B a n Bit 0: VID Port Member

e n t 1'b0: S_TAG1 shows 12-bit VID

C o n n a n Bit.47 ~ Bit.46 (Port 7)

r B a bit[49:48]: Port 6 STAG index

Me 2.5.2 VLAN Security Mechanism

a 802.1Q function is disabled (VLAN Security and VLAN Filter Table).

2.5.3 VLAN Membership Resolution

ACL PCR.PORT_VLAN VLAN

n n a P Hit Yes Use PORT_MEM in VLAN Table

n a n - - Use EG_TAG in Rule Control Table

a P i Hit - Use EG_TAG in PVC register

k C o a n a Not Hit Use EG_TAG in PCR register

ACL Rule Table

R e l e If CMP_SEL=='b0, this field indicates the 16-bits data pattern.

d i a F o (Note: 0x3F is the reserved and invalid offset value.)

i a l R 3'b110: IPv6 Header (L3 Offset)

M e This document contains information that is proprietary to MediaTek Inc.

F o Bit Name Description

n t i a 3’b0xx: System Default (Disable)

a P i 3’b101: System Default and CPU Port Included

k C o a n a will follow, the system default and CPU are excluded)

o r B MIR_EN Frame Copy to Mirror Port

1 7:0 PORT Destination Port Member / VLAN Port Member

n t i a Multicast MAC Destination Address Swap