Arithmetic and Logic

Chapter 3

Sepehr Naimi
Sarmad Naimi

www.NicerLand.com
 Objectives
• Add, subtract, multiply, and divide
• Carry
• Logic instructions
• Shift and Rotate
• BCD, Packed BCD and ASCII conversion.

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 S Suffix in Arm Instructions

Instructions: OpCode S Operands

Instruction (Flags unchanged) Instruction (Flags updated)

ADD Add ADDS Add and set flags
ADC Add with carry ADCS Add with carry and set flags
SUB SUBS SUBS Subtract and set flags
SBC Subtract with carry SBCS Subtract with carry and set flags
MUL Multiply MULS Multiply and set flags
UMULL Multiply long UMULLS Multiply Long and set flags
RSB Reverse subtract RSBS Reverse subtract and set flags
RSC Reverse subtract with carry RSCS Reverse subtract with carry and set flags
Note: The above instruction affect all the N, Z, C, and V flag bits of CPSR (current program status register)

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 ADD

LDR R2, =0xFFFFFFF5 ; R2 = 0xfffffff5

MOV R3, #0x0B ; R3 = 0x0B
ADDS R1, R2, R3 ; R1 = R2 + R3 and update the flags

0xFFFFFFF5 1111 1111 1111 1111 1111 1111 1111 0101

+ 0x0000000B + 0000 0000 0000 0000 0000 0000 0000 1011
0x100000000 1 0000 0000 0000 0000 0000 0000 0000 0000
All zeros

C=1 Z=1

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Adding 64-bit using ADC (Add with Carry)
LDR R0, =0xf62562fa ; r0 = 0xf62562fa
LDR R1, =0xf412963b ; r1 = 0xf412963b
MOV R2, #0x35 ; r2 = 0x35
MOV R3, #0x21 ; r3 = 0x21
ADDS R5, R1, R0 ; r5 = 0xf62562fa + 0xf412963b
; now c = 1
ADC R6, R2, R3 ; r6 = r2 + r3 + c
; = 0x35 + 21 + 1 = 0x57

00 00 00 35 F6 25 62 FA
+ 00 00 00 21 F4 12 96 3B
00 00 00 57 1 EA 37 F9 35

C=1

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 Some ideas about subtraction
• 100 – 34 = ?
• 99 – 34 = ?
• 100 – 34 = (99-34) + 1

• 34 – 19 = ?
• 34 +100 -19 – 100 = 34 + (99-19)+1 -100

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 Some ideas about subtraction (Cont.)
100000000 – 00101101 = ?
=011111111 – 00101101 + 1 = A
 –00101101 = A - 100000000

010110110 – 00101101 =
010110110 + A – 100000000 =

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 SUB
MOV R2, #0x4F ; r2 = 0x4f
SUBS R4, R2, #0x05 ; r4 = r2 – 0x05

0000004F
0x4F
0x05 – 2’s complement + FFFFFFFB
1 0000004A
0x4A

C=1
(no barrow)

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 Using SUBC (SUB with Carry)
LDR r0, =0xf62562fa ; r0 = 0xf62562fa
LDR r1, =0xf412963b ; r1 = 0xf412963b
MOV r2, #0x21 ; r2 = 0x21
MOV r3, #0x35 ; r3 = 0x35
SUBS r5, r1, r0 ; r5 = r1 – r0
; = 0xf412963b – 0xf62562fa
; = 0xFDED3341, and c = 0
SBC r6, r3, r2 ; r6 = r3 – r2 – 1 + c
; = 0x35 – 0x21 – 1 + 1 = 0x13

00 00 00 35 F4 12 96 3B F4 12 96 3B
– 00 00 00 21 F6 25 62 FA 2’s complement + 09 DA 9D 06
00 00 00 13 FD ED 33 41 0 FD ED 33 41

C=0

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 Multiplication
MUL Rd, Rn, Op2 ; Rd = Rn × Op2
Example:
MOV R1, #0x25 ; R1=0x25
MOV R2, #0x65 ; R2=0x65
MUL R3, R1, R2 ; R3 = R1 × R2 = 0x65 × 0x25

UMULL RdLo, RdHi, Rn, Op2 ; RdHi:RdLo = Rn × Op2

Example:
LDR R1, =0x54000000 ; R1 = 0x54000000
LDR R2, =0x10000002 ; R2 = 0x10000002
UMULL R3, R4, R2, R1 ; 0x54000000 × 0x10000002 = 0x054000000A8000000
; R3 = 0xA8000000, the lower 32 bits
; R4 = 0x05400000, the higher 32 bits

MLA Rd, Rm, Rs, Rn ; Rd = Rm × Rs + Rn

Example:
MOV R1, #100 ; R1 = 100
MOV R2, #5 ; R2 = 5
MOV R3, #40 ; R3 = 40
MLA R4, R1, R2, R3 ; R4 = R1 × R2 + R3 = 100 × 5 + 40 = 540

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 Division
UDIV Rd, Rn, Op2 ; Rd = Rn / Op2
Example:
mov r1, #8 ; r1 = 8
mov r2, #3 ; r2 = 3
udiv r5, r1, r2 ; r5 = 8 / 3 = 2

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 Logic Instructions
AND Rd,Rn,Op2 ; Rd = Rn AND Op2
ORR Rd,Rn,Op2 ; Rd = Rn OR Op2
EOR Rd,Rn,Op2 ; Rd = Rn XOR Op2
MVN Rd,Op2 ; Rd = 1’s Complement of Op2 (11111111 – Rd)

• AND can be used to clear a specific bit(s) of a byte

• OR can be used to set a specific bit(s) of a byte

Show the results of the following.

MOV R2,#0x35 ;R2 = 0x35

ANDS R3,R2,#0x0F ;R3 = R2 AND 0x0F (now R2 = 0x05)

Solution:

35 0011 0101
AND 0F 0000 1111
05 0000 0101 ;35 AND 0F = 05, Z = 0

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 Setting and Clearing bits
• OR can be used to set a specific bit(s) of a byte
• AND can be used to clear a specific bit(s) of a byte
• EOR can be used to toggle a specific bit(s) of a byte

04 0 0 0 0 0 1 0 0 44 0 1 0 0 0 1 0 0
OR 30 0 0 1 1 0 0 0 0 EOR 06 0 0 0 0 0 1 1 0
34 0 0 1 1 0 1 0 0 34 0 1 0 0 0 0 1 0

35 0 0 1 1 0 1 0 1
AND 0F 0 0 0 0 1 1 1 1
05 0 0 0 0 0 1 0 1

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Rotate and Shift
Instructions

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 LSL instruction
MOVS Rd, Rn, LSL #numOfShift
LSL(S) Rd, Rn, #numOfShift ;Logical Shift Left
In LSL, as bits are shifted from right to left,
0 enters the LSB and the MSB exits to the
carry flag. In other words, in LSL 0 is
moved to the LSB, and the
MSB is moved to the C.

this instruction multiplies content of the register by 2 if after

LSL the carry flag is not set.

In the next code you can see what happens to 00100110 after running 3 LSL
instructions.
;Assume C = 0
MOV R2 , #0x26 ;R2 = 0000 0000 0000 0000 0000 0000 0010 0110 (38) C = 0
LSLS R2,R2,#1 ;R2 = 0000 0000 0000 0000 0000 0000 0100 1100 (74) C = 0
LSLS R2,R2,#1 ;R2 = 0000 0000 0000 0000 0000 0000 1001 1000 (148) C = 0
LSLS R2,R2,#1 ;R2 = 0000 0000 0000 0000 0000 0001 0011 0000 (296) C = 0

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 LSR instruction
LSR(S) Rd, Rn, #numOfShift ;Logical Shift Right
MOVS Rd, Rn, LSR #numOfShift
In LSR, as bits are shifted from left to
right, 0 enters the MSB and the LSB exits
to the carry flag. In other words, in LSR
0 is moved to the MSB, and
the LSB is moved to the C.

this instruction divides content of the register by 2 and carry flag contains
the remainder of division.

In the next code you can see what happens to 0010 0110 after running 3 LSR
instructions.

MOV R2, #0x26 ;R2 = 0000 0000 0000 0000 0000 0000 0010 0110 (38)
LSRS R2, R2, #1 ;R2 = 0000 0000 0000 0000 0000 0000 0001 0011 (19) C = 0
LSRS R2, R2, #1 ;R2 = 0000 0000 0000 0000 0000 0000 0000 1001 (9) C = 1
LSRS R2, R2, #1 ;R2 = 0000 0000 0000 0000 0000 0000 0000 0100 (4) C = 1

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 ROR instruction (Rotate Right)
ROR Rd, Rm, #numOfShifts ;Rotate Rm right Rn bit positions
MOVS Rd, Rm, ROR #numOfShifts

In ROR, as bits are rotated from left to right, the LSB goes to the MSB
and to the carry flag.

See what happens to 0010 0110 after running 3 ROR instructions:

;assume C = 0 (carry is 0 )
MOV R2, #0x26 ;R2 = 0000 0000 0000 0000 0000 0000 0010 0110
RORS R2, R2, #1 ;R2 = 0000 0000 0000 0000 0000 0000 0001 0011 C = 0
RORS R2, R2, #1 ;R2 = 1000 0000 0000 0000 0000 0000 0000 1001 C = 1
RORS R2, R2, #1 ;R2 = 1100 0000 0000 0000 0000 0000 0000 0100 C = 1

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RRX instruction (Rotate Right with extend)
RRX(S) Rd, Rm ;Rotate Rm right 1 bit through C flag
MOVS Rd, Rm, RRX

In RRXS, as bits are rotated from left to right, the carry flag enters the MSB
and the LSB exits to the carry flag. In other words, in RRXS the C is moved to
the MSB, and the LSB is moved to the C.

See what happens to 0010 0110 after running 3 ROR instructions:

;assume C = 0 (carry is 0 )
MOV R2, #0x26 ;R2 = 0010 0000 0000 0000 0000 0000 0000 0110
RRXS R2, R2 ;R2 = 0001 0000 0000 0000 0000 0000 0000 0011 C = 0
RRXS R2, R2 ;R2 = 0000 0000 0000 0000 0000 0000 0000 1001 C = 1
RRXS R2, R2 ;R2 = 1000 0000 0000 0000 0000 0000 0000 0100 C = 1

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BCD, Packed BCD and ASCII conversion.
•ASCII
BCD Codes

BCD Codes
Packed BCD

BCD1 BCD0

ASCII and BCD Codes for Digits 0–9

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 Packed BCD to ASCII conversion
To convert packed BCD to ASCII:
• you must first convert it to unpacked BCD.
• Then the unpacked BCD is tagged with 011 0000
(30H).

Packed BCD = 1001 0010

Unpacked BCD = 0000 1001 , 0000 0010

ACSII = 0011 1001 , 0011 0010

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