Data Sheet

APL5331
3A Bus Termination Regulator
Features General Description (Cont.)
• Provide Bi-direction Current On-chip thermal shutdown provides protection against

any combination of overload that would create ex-
- Sourcing or Sinking Current up to 3A
cessive junction temperature. The output voltage of
• 1.25V/0.9V Output for DDR I/II Applications
APL5331 track the voltage at VREF pin. A resistor
• Fast Transient Response divider connected to VIN, GND and VREF pins is
• High Output Accuracy used to provide a half voltage of VIN to VREF pin. In
- ±20mV over Load, VOUT Offset and addition, an external ceramic capacitor and an open-
drain transistor connected to VREF pin provides soft-
Temperature
start and shutdown control respectively. Pulling and
• Adjustable Output Voltage by External Resistors
holding the VREF to GND shuts off the output. The
• Current-Limit Protection
output of APL5331 will be high impedance after be-
• On-Chip Thermal Shutdown ing shut down by VREF or thermal shutdown function.
• Shutdown for Standby or Suspend Mode
• Simple SOP-8, SOP-8-P with thermal pad,
TO-252- 5 and TO-263-5 Packages
Pin Configuration
Applications VOUT
5
VIN 1 8 VC N TL
VREF
4
GND 2 7 VCN TL
VCNTL
3
TAB is VCNTL
VR EF 3 6 VCN TL
• GND
2
DDR I/II SDRAM Termination VO U T 4 5 VCN TL
VIN
1
• SSTL-2/3 Termination Voltage
• Applications Requiring the Regulator with SOP-8 (Top View) TO-252-5 (Top View)
Bi-direction 3A Current Capability
5 VOUT
VIN 1 8 NC
4 VREF
GND 2 7 NC
General Description VREF 3 6 VCNTL

TAB is VCNTL 3
2
VCNTL
GND
VOUT 4 5 NC
1 VIN
The APL5331 linear regulator is designed to provide

a regulated voltage with bi-directional output current SOP-8-P (Top View) TO-263-5 (Top View)
for DDR-SDRAM termination. The APL5331 integrates
NC = No internal connection
two power transistors to source or sink current up to
3A. It also incorporate current-limit, thermal shut- = Thermal Pad
(connected to GND plane for better heat
down and shutdown control functions into a single
dissipation)
chip. Current-limit circuit limits the short-circuit
current.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.8 - Oct., 2003
APL5331
Ordering and Marking Information

Package Code
APL5331 K : S O P -8 K A : S O P -8 -P
U 5 : T O -2 5 2 -5 G 5 : T O -2 6 3 -5
L e a d F re e C o d e Tem p. Range
H a n d lin g C o d e C : 0 to 7 0 o C
H a n d lin g C o d e
Tem p. Range
TR : Tape & Reel
Package Code L e a d F re e C o d e
L : L e a d F re e D e v ic e B la n k : O rg in a l D e v ic e
A P L 5 3 3 1 K C -T R : AP L5331
X X X X X - D a te C o d e
A P L 5 3 3 1 K A C -T R : XXXXX
A P L 5 3 3 1 U 5 C -T R :
AP L5331 X X X X X - D a te C o d e
A P L 5 3 3 1 G 5 C -T R :
XXXXX
Pin Description
PIN NAME I/O DESCRIPTION
Main power input pin. Connect this pin to a voltage source and an input
VIN I capacitor. The APL5331 sources current to VOUT pin by controlling the upper
NPN pass transistor, providing a current path from VIN pin.
Power and signal ground. Connect this pin to system ground plane with shortest
traces. The APL5331 sinks current from VOUT pin by controlling the lower NPN
GND O
pass transistor, providing a current path to GND pin. This pin is also the ground
path for internal control circuitry.
Power input pin for internal control circuitry. Connect this pin to a voltage source,
VCNTL I providing a bias for the internal control circuitry. A bypass capacitor is usually
connected near this pin.
Reference voltage input and active-low shutdown control pin. Apply a voltage to
this pin as a reference voltage for the APL5331. Connect this pin to a resistor
VREF I divider, between VIN and GND, and a capacitor for soft-start and filtering noise
purposes. Applying and holding this pin low by an open-drain transistor to shut
down the output.
Output pin of the regulator. Connect this pin to load. Output capacitors
connected this pin improves stability and transient response. The output voltage
VOUT O
tracks the reference voltage and is capable of sourcing or sinking current up to
3A.

Block Diagram
V C N TL V IN
V o lt a g e Th e rm a l C u rre n t
R e g u la t io n
V OUT
L im it L im it
V RE F
S hutdow n
G ND

Rev. A.8 - Oct., 2003
APL5331
Absolute Maximum Ratings
Symbol Parameter Rating Unit

V CNTL VCNTL Supply Voltage, VCNTL to GND -0.2 ~ 7 V
V IN VIN Supply Voltage, VIN to GND -0.2 ~ 3.9 V
PD Power Dissipation Internally Limited W
o
TJ Junction Temperature 150 C
o
T STG Storage Temperature -65 ~ 150 C
o
T SDR Soldering Temperature, 10 Seconds 300 C
V ESD Minimum ESD Rating (Human Body Mode) ±3 kV

Thermal Characteristics
Symbol Parameter Rating Unit

θJA Thermal Resistance in Free Air
SOP-8 160 °C/W
SOP-8-P 80
TO-252-5 80
TO-263-5 50
Recommended Operating Conditions
Symbol Parameter Range Unit

V CNTL VCNTL Supply Voltage 3.1 ~ 6V V
V IN VIN Supply Voltage 1.6 ~ 3.5 V
V REF VREF Input Voltage 0.8 ~ 1.75 V
IOUT VOUT Output Current (Note1, 2) -3 ~ +3 A
o
TJ Junction Temperature 0 ~ 125 C

Note1 : The symbol “+” means the VOUT sources current to load; the symbol “-“ means the VOUT sinks
current to GND.
Note2 : The max. IOUT varies with the TJ. Please refer to the typical characteristics.

Rev. A.8 - Oct., 2003
APL5331
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over, VCNTL=3.3V, VIN=2.5V/1.8V,
VREF=0.5VIN and TJ= 0 to 125°C, unless otherwise specified. Typical values refer to TJ =25°C.
APL5331
Symbol Parameter Test Conditions Unit
M in Typ M ax
Output Voltage
V OUT VOUT Output Voltage IOUT =0A V REF V
Over tem perature, VOUT offset, and
System Accuracy -20 20 mV
load regulation
VOUT Offset Voltage IOUT =+10m A -14 -9
V OS mV
(V OUT –V REF ) IOUT =-10m A 2 8
IOUT =+10m A to +3A -6 -3
Load Regulation mV
IOUT = -10m A to -3A 7 12
Protection
Sourcing Current T J =25°C +3.3 +3.6

(V IN =2.5V) T J =125°C +3.1
Sinking Current T J =25°C -3.3 -3.6

(V IN =2.5V) T J =125°C -3.1
ILIM Current Lim it A
Sourcing Current T J =25°C +2.9 +3.2

(V IN =1.8V) T J =125°C +2.6
Sinking Current T J =25°C -2.9 -3.2

(V IN =1.8V) T J =125°C -2.6
Therm al Shutdown o
T SD Rising T J 150 C
Tem perature
C
o
Therm al Shutdown Hysteresis 40
Input Current
IOUT =0A 2 4.5 6
IOUT =±3A (Norm al Operation),
ICNTL VCNTL Supply Current 50 110 mA
V CNTL =5V
V REF =GND (Shutdown) 2.6
VREF Bias Current V REF =1.25V/0.9V (Norm al O peration) 150 500 nA
IVREF
(The current flows out of VREF) V REF =GND (Shutdown) 20 40 µA
Shutdow n Control
Shutdown Threshold Voltage 0.2 0.35 0.65 V


Rev. A.8 - Oct., 2003
APL5331
Typical Application Circuit
1. VOUT=1.25V/0.9V Application
VC N TL
+3.3V
VIN
VI N VC N TL
+2.5V/1.8 V
R1 VOU T
1k VR EF GND VO U T +1.25 V/0 .9V
C IN -3~+3 A
4 70 uF VR EF
C C N TL C OU T
Shu tdo w n R2 C SS
0 .1 uF 4 7u F 4 70 uF
Q1 1k
GN D GN D
COUT : 470µF, ESR=25mΩ

R1, R2 : 1kΩ, 1%
Q1 : APM2300 AC
Note : Since R1 and R2 are very small, the voltage offset
caused by the bias current of VREF can be ignore.
2. VOUT=1.4V Application
VCNT L
+5V
VIN VIN VC N TL
+2.8V
R1
VO UT
1k VR E F GN D VOU T +1.4V/
C IN -3~+3 A
470 µ F VRE F
C CNT L C O UT
R2 CSS
0.1 µ F 47 µ F 470 µ F
1k
GND GND

Rev. A.8 - Oct., 2003
APL5331
Typical Characteristics
Sourcing Current-Limit Sinking Current-Limit

vs Junction Temperature vs Junction Temperature
5.0 -2.0
VCNTL=5V,VIN=2.5V
4.5 VCNTL=3.3V,VIN=2.5V -2.5 VCNTL=5V,VIN=1.8V
Current-Limit, ILIM (A)

Current-Limit, ILIM (A)
VCNTL=3.3V,VIN=1.8V
4.0 -3.0
3.5 -3.5
3.0 VCNTL=5V,VIN=1.8V -4.0 VCNTL=3.3V,VIN=2.5V
VCNTL=5V,VIN=2.5V
2.5 VCNTL=3.3V,VIN=1.8V -4.5
2.0 -5.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Junction Temperature (°C) Junction Temperature (°C)
VREF Bias Current VREF Shutdown Threshold

0.40 0.6
VREF=1.25V/0.9V
VREF Bias Current, IVREF (µA)
VREF Shutdown Threshold (V)
0.35
0.5
0.30
VCNTL=5V
0.25
0.4
0.20
0.15 0.3
VCNTL=3.3V
0.10
0.2
0.05
0.00 0.1
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Rev. A.8 - Oct., 2003
APL5331
Typical Characteristics (Cont.)
VOUT Offset Voltage Quiescent VCNTL Current

6 7.0
Quiescent VCNTL Current (mA)

VREF=1.25V/0.9V IOUT=0A
VOUT Offset Voltage, VOS (mV)
4 6.5
2 6.0
VCNTL=5V
0
IOUT=-10mA 5.5
-2
5.0
-4
4.5
-6
4.0
-8
VCNTL=3.3V
-10 3.5
-12 3.0
IOUT=+10mA
-14 2.5
-16 2.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
VREF Bias Current

vs VREF Supply Voltage
22
TJ=25°C
VREF Bias Current, IVREF (µA)
20
18
16
14
12
10
8
6
4
2
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VREF Supply Votage, VREF (V)

Rev. A.8 - Oct., 2003
APL5331
Operating Waveforms
1. Load Transient Response : IOUT = +10mA -> +3A -> +10mA

- VIN = 2.5V, VCNTL = 3.3V
- VREF is 1.250V supplied by a regulator
- COUT = 470µF/10V, ESR = 30mΩ
- IOUT slew rate = ±3A/µS
IOUT = +10mA -> +3A IOUT = +10mA -> +3A -> +10mA IOUT = +3A -> +10mA
Load Regulation = -2.8mV
VOUT VOUT VOUT
IOUT
+3A
IOUT IOUT
+10mA
Ch1 : VOUT, 20mV/Div, DC, Ch1 : VOUT, 20mV/Div, DC, Ch1 : VOUT, 20mV/Div, DC,
Offset = 1.250V Offset = 1.250V Offset = 1.250V
Ax1 : IOUT, 1A/Div Ax1 : IOUT, 1A/Div Ax1 : IOUT, 1A/Div
Time : 1µS/Div Time : 20µS/Div Time : 1µS/Div
2. Load Transient Response : IOUT = -10mA -> -3A -> -10mA

- VIN = 2.5V, VCNTL = 3.3V
IOUT = -10mA -> -3A IOUT = -10mA -> -3A -> -10mA IOUT = -3A -> -10mA
Load Regulation = +6.2mV
VOUT
VOUT VOUT
IOUT IOUT
-10mA
IOUT
-3A

Rev. A.8 - Oct., 2003
APL5331
Operating Waveforms (Cont.)
3. Load Transient Response : IOUT = +3A -> -3A -> +3A

- VIN = 2.5V, VCNTL = 3.3V
IOUT = +3A -> -3A IOUT = +3A -> -3A -> +3A IOUT = -3A -> +3A
VOUT
VOUT VOUT
IOUT IOUT
+3A
IOUT
-3A
4. Short-Circuit Test
- VIN = 2.5V, VCNTL = 3.3V
VOUT is Shorted to GND VOUT is Shorted to VIN (2.5V)
IOUT
VOUT
IOUT
VOUT IOUT
VOUT
Ch1 : VOUT, 500mV/Div, DC, Ch1 : VOUT, 500mV/Div, DC,

Ax1 : IOUT, 2A/Div Ax1 : IOUT, 2A/Div
Time : 5mS/Div Time : 5mS/Div

Rev. A.8 - Oct., 2003
APL5331
Application Information
General Shutdown and Soft-Start

The APL5331 is a linear regulator and is capable of The VREF pin is a dual-function input pin, acting as
sourcing or sinking current up to 3A. The APL5331 reference input and shutdown control input. Apply-
has fast transient response, accurate output voltage ing and holding a voltage below 0.35V(typ.) to VREF
(small voltage offset, load regulation), active-low shut- pin shuts down the output of the regulator. An NPN
down control and fault protections (current-limit, ther- transistor or N-channel MOSFET is used to pull down
mal shutdown). The APL5331 is available in several the VREF while applying a “high” signal to turn on the
packages to meet different of power dissipation in transistor. When shutdown function is active, the
requirement various applications. two pass transistors are turned off and the imped-
ance of the VOUT is about 10MΩ (typ.), sourcing or
Output Voltage Regulation sinking no current. When release the VREF pin, the
The output voltage at VOUT pin tracks the reference current through the resistor divider charges the soft-
voltage applied at VREF pin. Two internal NPN pass start capacitor to initiate a soft-start cycle. The output
transistors controlled by separate high bandwidth er- voltage tracks the rising VREF. The soft start process
ror amplifiers regulate the output voltage by sourcing limits the input surge current.
current from VIN pin or sinking current to GND pin.
The base currents of the pass transistors are pro-
vided by VCNTL pin. An internal kelvin sensing Thermal Shutdown
scheme use at the VOUT pin for perfect load regula- An thermal shutdown circuit limits the junction tem-
tion at various load current. To prevent the two pass perature of the APL5331. When the junction tem-
transistors from shoot-through, a small voltage offset perature exceeds TJ= +150oC, a thermal sensor turns
is created between the positive inputs of the two error off both pass transistors, allowing the device to cool
amplifiers. This results in higher output voltage while down. The regulator starts to regulate again after the
the regulator sinks light or heavy load current. Since junction temperature reduces by 40oC, resulting in a
the APL5331 exhibits very fast load transient pulsed output during continuous thermal overload
response, lesser amount of capacitors can be use. conditions. The thermal limit designed with a 40oC
In addition, capacitors with high ESR can also be hysteresis lowers the average TJ during continuous
use. thermal overload conditions, extend life time of
APL5331.
Current Limit
The APL5331 monitors sourcing and sinking current,
and limits the maximum output current to prevent dam-
ages during overload or short-circuit, To increase
the input voltage of VIN or VCNTL will get higher
current-limit points.

Rev. A.8 - Oct., 2003
APL5331
Application Information
Power Inputs put capacitor should have an ESR less than 1Ω.
Input power sequence are not required for VIN and
VCNTL. However, do not apply a voltage to VOUT
when there is not voltage VCNTL. This is due to the 25
internal parasitic diodes between VOUT to VIN and 20
ESR (mΩ)
VOUT to VCNTL which will be forward bias. The 15 Stable Region
APL5331 can source few current or sinks current up 10
to 3A for load when the input Voltage at VIN is not 5
present. 0
10 100 1000
Capacitance(µF)
Reference Voltage
A reference voltage is applied at the VREF pin by a
resistor divider between VIN and GND pins. Normally Ultra-low-ESR capacitors, such as ceramic chip
the bias current of the VREF pin flows out of the IC capacitors, may promote under-damped transient
and is about 150nA(typ.), creating voltage offset at response, but proper ceramic chip capacitors placed
the resistor divider and affecting the output voltage near loads can be used as decoupling capacitors. A
accuracy. The recommended resistor is <5kΩ to low-ESR solid tantalum and aluminum electrolytic ca-
maintain the accuracy of the output voltage. An ex- pacitor (ESR<1Ω) works extremely well and provides
ternal bypass capacitor is also connected to VREF. good transient response and stability over temperature.
The capacitor and the resistor divider form a low-
pass filter to reduce the inherent reference noise from The output capacitors are also used to reduce the
VIN. A ceramic capacitor can be use and is selected slew rate of load current and help the APL5331 to
to be greater than 0.1µF. Connected the capacitor minimize variations of the output voltage, improving
as close to VREF as possible for optimal effect. More transient response. For this purpose, the low-ESR
capacitance and large resistor divider will increase capacitors are recommended and depend on the step-
the soft-start interval. Do not place any additional load- ping and slew rate of load current.
ing on this reference input pin.
Input Capacitor
Output Capacitor The input capacitors of VCNTL and VIN pins are not
The APL5331 requires a proper output capacitor to required for stability but for supplying surge currents
maintain stability over full temperature and current during large load transients, This will prevent the in-
ranges, and improve transient response. The output put rail from drooping and improve the performance
capacitor selection is dependent upon the ESR of the APL5331. Because of parasitic inductors from
(equivalent series resistance) and capacitance of the voltage sources or other bulk capacitors to the VCNTL
output capacitor over full temperature range. The fol- and VIN pins will limit the slew rate of the surge cur-
lowing chart shows the stable region of the output rents during large load transients, resulting in voltage
capacitor for APL5331. The stable region is above drop at VIN and VCNTL pins.
the curve, indicating minimum required ESR and
capacitance to maintain stability. However, the out

Rev. A.8 - Oct., 2003
APL5331
A capacitor of 1µF (ceramic chip capacitor) or greater plane reduces the resistance ?CA . The relationship
(aluminum electrolytic capacitor) is recommended to between power dissipation and temperatures is the
connect near VCNTL pin. For VIN pin, an aluminum following equation :
electrolytic capacitor (>50µF) is recommended. It is PD = (TJ - TA) / ? JA
not necessary to use low-ESR capacitors. where,
PD : Power dissipation
Layout and Thermal Consideration TJ : Junction Temperature
The input capacitors for VIN and VCNTL pins are TA : Ambient Temperature
normally placed near each pin for good ? JA : Junction-to-Ambient Thermal Resis-
performances. Ceramic decoupling capacitors at tance
output must be placed as close to the load to reduce
102 mil
the parasitic inductors of traces. It is also recom-
mended that the APL5331 and output capacitors are
placed near the load for good load regulation and
load transient response. The negative pins of the in- 118 mil SO P-8-P
put and output capacitors and the GND pin of the

APL5331 should connect to analog ground plane of
the load.
T h e rm a l
See figure 1. The SOP-8-P utilizes a bottom thermal D ie pad Top
g ro u n d
pad to minimize the thermal resistance of the package, pad
making the package suitable for high current

A m b ie n t
applications. The thermal pad is soldered to the top A ir
ground pad and is connected to the internal or bot- V ia s In te rn a l P rin te d

g ro u n d circuit
tom ground plane by several vias. The printed circuit p la n e b o a rd
board (PCB) forms a heat sink and dissipates most Figure 1 Package Top and side view
of the heat into ambient air. The vias are recom-
mended to have proper size to retain solder, helping Figure 2 shows a board layout using the SOP-8-P
heat conduction. package. The demo board is made of FR-4 material
Thermal resistance consists of two main elements, and is a two-layer PCB. The size and thickness are
? JC (junction-to-case thermal resistance) and ? CA 65mm* 65mm and 1.6mm. An area of 140mil*105mil
(case-to-ambient thermal resistance). ? JC is speci- on the top layer is use as a thermal pad for the
fied from the IC junction to the bottom of the thermal APL5331 and this is connected to the bottom layer
pad directly below the die. ?CA is the resistance from by vias. The bottom layer using 2 oz. copper acts as
the bottom of thermal pad to the ambient air and it the ground plane for the system. The PCB and all
includes ? CS (case-to-sink thermal resistance) and components on the board form a heat sink. The ?JA
?SA (sink-to-ambient thermal resistance). The speci- of the APL5331(SOP-8-P) mounted on this demo
fied path for heat flow is the lowest resistance path board is about 37oC/W in free air. Assuming the
and it dissipates majority of the heat to the ambient TA=25oC and the maximum TJ=150oC (typical thermal
air. Typically, ?CA is the dominant thermal resistance. limit temperature), the maximum power dissipation is
Therefore, enlarging the internal or bottom ground calculated as :

Rev. A.8 - Oct., 2003
APL5331
PD (max) = (150 - 25) / 37

= 3.38W
If the TJ is designed to be below 125oC, the calcu-

lated power dissipation should be less than :
PD = (125 - 25) / 37
= 2.70W
APL5331
Figure 2(c) Bottom layer
Figure 2(a) TopOver layer
APL5331
Figure 2(b) Top layer

Rev. A.8 - Oct., 2003
APL5331
Packaging Information
SOP-8 pin ( Reference JEDEC Registration MS-012)
0.015X45
E H
e1 e2
A1
A 1
L
0.004max.
Mi ll im et er s Inche s
Dim
Min . Max . Min. Max .
A 1. 35 1. 75 0. 053 0. 069
A1 0. 10 0. 25 0. 004 0. 010
D 4. 80 5. 00 0. 189 0. 197
E 3. 80 4. 00 0. 150 0. 157
H 5. 80 6. 20 0. 228 0. 244
L 0. 40 1. 27 0. 016 0. 050
e1 0. 33 0. 51 0. 013 0. 020
e2 1. 27B S C 0. 50B S C
φ 1 8° 8°

Rev. A.8 - Oct., 2003
APL5331
SOP-8-P pin ( Reference JEDEC Registration MS-012)
0.015X45
E1 E H
D1
e1 e2
A1
A 1
L
0.004max.
M illimeter s Inc hes

Dim
M in . M ax. M in . M ax.
A 1.3 5 1.7 5 0.0 53 0.0 69
A1 0.1 0 0.2 5 0.0 04 0.0 10
D 4.8 0 5.0 0 0.1 89 0.1 97
D1 3.0 0R EF 0.11 8REF
E 3.8 0 4.0 0 0.1 50 0.1 57
E1 2.6 0R EF 0.1 02R EF
H 5.8 0 6.2 0 0.2 28 0.2 44
L 0.4 0 1.2 7 0.0 16 0.0 50
e1 0.3 3 0.5 1 0.0 13 0.0 20
e2 1.2 7BS C 0.5 0BS C
φ 1 8° 8°

Rev. A.8 - Oct., 2003
APL5331
TO-252-5
E1
A
H
B
J
D1
C
M
S P
K
M illim e te rs In c h e s
D im
M in . M ax. M in . M ax.
A 6 .4 0 6 .8 0 0 .2 5 0 .2 6
B 5 .2 0 5 .5 0 0 .2 0 0 .2 1
C 6 .8 0 7 .2 0 0 .2 6 0 .2 7
D 2 .2 0 2 .8 0 0 .0 8 0 .11
D1 5 .2 R E F 0 .2 0 5 R E F
E1 5 .3 R E F 0 .2 0 9 R E F
P 1 .2 7 R E F 0 .0 5 R E F
S 0 .5 0 0 .8 0 0 .0 2 0 .0 3
H 2 .2 0 2 .4 0 0 .0 8 0 .0 9
J 0 .4 5 0 .5 5 0 .0 1 0 .0 2
K 0 .4 5 0 .6 0 0 .0 1 8 0 .0 2 4
L 0 .9 0 1 .5 0 0 .0 3 0 .0 6
M 5 .4 0 5 .8 0 0 .2 1 0 .2 2


Rev. A.8 - Oct., 2003
APL5331
TO-263-5
A
D
c1
B
v
E
b A1
L2
L1
e1
M ill im et er s Inc h e s
Dim M in . M ax . M in . M ax .
A 4. 0 6 4. 8 3 0. 1 6 0 0. 1 9 0
b 0. 5 0 0. 9 9 0. 0 2 0 0. 0 3 9
b1 1. 5 2 1. 8 3 0. 0 6 0 0. 0 7 2
c 0. 4 5 7 0. 7 3 6 0. 0 1 8 0. 0 2 9
c1 1. 1 4 1. 4 0 0. 0 4 5 0. 0 5 5
D 8. 2 5 9. 6 6 0. 3 2 5 0. 3 8 0
E 9. 6 5 10 . 2 9 0. 3 8 0 0. 4 0 5
L 14 . 6 0 15 . 8 8 0. 5 7 5 0. 6 2 5
L1 2. 2 8 2. 8 0 0. 0 9 0 0. 11 0
L2 1. 4 0 0. 0 5 5

Rev. A.8 - Oct., 2003
APL5331
Physical Specifications
Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)

Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition (IR/Convection or VPR Reflow)

Reference JEDEC Standard J-STD-020A APRIL 1999
temperature
Peak temperature
183°C
Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/ VPR

Convection
Average ramp-up rate(183°C to Peak) 3°C/second max. 10 °C /second max.
Preheat temperature 125 ± 25°C) 120 seconds max
Temperature maintained above 183°C 60 – 150 seconds
Time within 5°C of actual peak temperature 10 –20 seconds 60 seconds
Peak temperature range 220 +5/-0°C or 235 +5/-0°C 215-219°C or 235 +5/-0°C
Ramp-down rate 6 °C /second max. 10 °C /second max.
Time 25°C to peak temperature 6 minutes max.
Package Reflow Conditions
pkg. thickness ≥ 2.5mm pkg. thickness < 2.5mm and pkg. thickness < 2.5mm and pkg.
and all bgas pkg. volume ≥ 350 mm³ volume < 350mm³
Convection 220 +5/-0 °C Convection 235 +5/-0 °C
VPR 215-219 °C VPR 235 +5/-0 °C
IR/Convection 220 +5/-0 °C IR/Convection 235 +5/-0 °C

Rev. A.8 - Oct., 2003
APL5331
R e lia b ilit y te s t p r o g r a m
Te s t ite m M e th o d D e s c rip tio n

S O L D E R A B IL IT Y M IL -S T D -8 8 3 D -2 0 0 3 2 45 °C , 5 S E C
H O LT M IL -S T D -8 8 3 D -1 0 0 5 .7 1 0 0 0 H rs B ia s @ 1 2 5 ° C
PCT J E S D -2 2 - B , A 1 0 2 1 6 8 H rs , 1 0 0 % R H , 1 2 1 ° C
TST M IL -S T D -8 8 3 D -1 0 11 .9 -6 5 °C ~ 1 5 0 °C , 2 0 0 C y c le s
ESD M IL -S T D -8 8 3 D -3 0 1 5 .7 V H B M > 2 K V, V M M > 2 0 0 V
L a tc h -U p JESD 78 1 0 m s , I tr > 1 0 0 m A
Carrier Tape
t
Po P D
E
P1
Bo
F
W
Ko
Ao D1
T2
C
A B
T1

Rev. A.8 - Oct., 2003
APL5331
Application A B C J T1 T2 W P E
330 ± 1 62 +1.5 12.75+ 2 ± 0.5 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75±0.1
0.15
SOP- 8 F D D1 Po P1 Ao Bo Ko t
SOP-8-P
5.5± 1 1.55 +0.1 1.55+ 0.25 4.0 ± 0.1 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 2.1± 0.1 0.3±0.013
330 ±3 100 ± 2 13 ± 0. 5 2 ± 0.5 16.4 + 0.3 2.5± 0.5 16+ 0.3 8 ± 0.1 1.75± 0.1
-0.2 - 0.1
TO-252 F D D1 Po P1 Ao Bo Ko t
7.5 ± 0.1 1.5 +0.1 1.5± 0.25 4.0 ± 0.1 2.0 ± 0.1 6.8 ± 0.1 10.4± 0.1 2.5± 0.1 0.3±0.05
380±3 80 ± 2 13 ± 0. 5 2 ± 0.5 24 ± 4 2± 0.3 24 + 0.3 16 ± 0.1 1.75± 0.1
- 0.1
TO-263 F D D1 Po P1 Ao Bo Ko t
11.5 ± 0.1 1.5 +0.1 1.5± 0.25 4.0 ± 0.1 2.0 ± 0.1 10.8 ± 0.1 16.1± 0.1 5.2± 0.1 0.35±0.013
Cover Tape Dimensions
Application Carrier Width Cover Tape Width Devices Per Reel

SOP- 8 / SOP-8-P 12 9.3 2500
TO- 252 16 13.3 2500
TO- 263 24 21.3 1000
Customer Service
Anpec Electronics Corp.

Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369

Rev. A.8 - Oct., 2003

Data Sheet

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Data Sheet

Uploaded by

Copyright:

Available Formats

APL5331

3A Bus Termination Regulator

Features General Description (Cont.)

• Provide Bi-direction Current On-chip thermal shutdown provides protection against

General Description VREF 3 6 VCNTL

The APL5331 linear regulator is designed to provide

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Ordering and Marking Information

Copyright  ANPEC Electronics Corp. 2 www.anpec.com.tw

Absolute Maximum Ratings

Symbol Parameter Rating Unit

Symbol Parameter Rating Unit

Recommended Operating Conditions

Symbol Parameter Range Unit

Copyright  ANPEC Electronics Corp. 3 www.anpec.com.tw

Copyright  ANPEC Electronics Corp. 4 www.anpec.com.tw

Typical Application Circuit

COUT : 470µF, ESR=25mΩ

Copyright  ANPEC Electronics Corp. 5 www.anpec.com.tw

Sourcing Current-Limit Sinking Current-Limit

4.5 VCNTL=3.3V,VIN=2.5V -2.5 VCNTL=5V,VIN=1.8V

Current-Limit, ILIM (A)

3.0 VCNTL=5V,VIN=1.8V -4.0 VCNTL=3.3V,VIN=2.5V

Junction Temperature (°C) Junction Temperature (°C)

VREF Bias Current VREF Shutdown Threshold

VREF Shutdown Threshold (V)

Junction Temperature (°C) Junction Temperature (°C)

Copyright  ANPEC Electronics Corp. 6 www.anpec.com.tw

Typical Characteristics (Cont.)

VOUT Offset Voltage Quiescent VCNTL Current

Quiescent VCNTL Current (mA)

Junction Temperature (°C) Junction Temperature (°C)

VREF Bias Current

VREF Supply Votage, VREF (V)

Copyright  ANPEC Electronics Corp. 7 www.anpec.com.tw

1. Load Transient Response : IOUT = +10mA -> +3A -> +10mA

VOUT VOUT VOUT

2. Load Transient Response : IOUT = -10mA -> -3A -> -10mA

Copyright  ANPEC Electronics Corp. 8 www.anpec.com.tw

Operating Waveforms (Cont.)

3. Load Transient Response : IOUT = +3A -> -3A -> +3A

VOUT is Shorted to GND VOUT is Shorted to VIN (2.5V)

Ch1 : VOUT, 500mV/Div, DC, Ch1 : VOUT, 500mV/Div, DC,

Copyright  ANPEC Electronics Corp. 9 www.anpec.com.tw

General Shutdown and Soft-Start

Copyright  ANPEC Electronics Corp. 10 www.anpec.com.tw

Copyright  ANPEC Electronics Corp. 11 www.anpec.com.tw

put and output capacitors and the GND pin of the

making the package suitable for high current

ground pad and is connected to the internal or bot- V ia s In te rn a l P rin te d

Copyright  ANPEC Electronics Corp. 12 www.anpec.com.tw

PD (max) = (150 - 25) / 37

If the TJ is designed to be below 125oC, the calcu-

Figure 2(c) Bottom layer

Figure 2(a) TopOver layer

Figure 2(b) Top layer

Copyright  ANPEC Electronics Corp. 13 www.anpec.com.tw

SOP-8 pin ( Reference JEDEC Registration MS-012)

Copyright  ANPEC Electronics Corp. 14 www.anpec.com.tw

SOP-8-P pin ( Reference JEDEC Registration MS-012)

M illimeter s Inc hes

Copyright  ANPEC Electronics Corp. 15 www.anpec.com.tw

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw