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MULTIPROCESSOR INTERCONNECTION NETWORKS

Conference Paper · September 2013

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 13th International Conference
Research and Development in Mechanical Industry
RaDMI 2013
12-15 September 2013, Kopaonik, Serbia

MULTIPROCESSOR INTERCONNECTION NETWORKS

2 3 3
, , Aleksandar Gojkovi
1
University of Belgrade, Technical faculty in Bor, Bor, SERBIA, E-mail: zdamnjanovic@tf.bor.ac.rs
2
SERBIA, E-mail: serifiveis@yahoo.com
3
Univerzitet UNION, Faculty of Business and Industrial Management, Belgrade, SERBIA,
E-mail: agojkovic@gmail.com

Summary: Multiprocessor system consists of multiple processing units connected via some interconnection
network plus the software needed to make the processing units work together. There are two major factors used
to categorize such systems: the processing units themselves, and the interconnection network that ties them
together. A number of communication styles exist for multiprocessing networks. These can be broadly classified
according to the communication model as shared memory (single address space) versus message
passing(multiple address spaces).

Keywords: interconnection, networking, data processing, architecture.

1. INTRODUCTION

Communication in shared memory systems is performed by writing to and reading from the global
memory, while communication in message passing systems is accomplished via send and receive
commands. In both cases, the interconnection network plays a major role in determining the
communication speed. In this chapter, we introduce the different topologies used for interconnecting
multiple processors and memory modules. Two schemes are introduced, namely static and dynamic
interconnection networks. Static networks form all connections when the system is designed rather
than when the connection is needed. In a static network, messages must be routed along established
links. Dynamic interconnection networks establish connections between two or more nodes on the fly
as messages are routed along the links. The hypercube, mesh, and k-ary n-cube topologies are
introduced as examples for static networks. The bus, crossbar, and multistage inter-connection
topologies are introduced as examples for dynamic interconnection net-works. Our coverage in this
chapter will conclude with a section on performance evaluation and analysis of the different
interconnection networks.

2. INTERCONNECTION NETWORKS TAXONOMY

In this section, we discuss a topology-based taxonomy for interconnection networks (INs). An

interconnection network could be either static or dynamic. Connections in a static network are fixed
links, while connections in a dynamic network re established on the fly as needed. Static networks can
be further classified accord-ing to their interconnection pattern as one-dimension (1D), two-dimension
(2D), or hypercube (HC). Dynamic networks, on the other hand, can be classified based on
interconnection scheme as bus-based versus switch-based. Bus-based networks can further be

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classified as single bus or multiple buses. Switch-based dynamic net-works can be classified according
to the structure of the interconnection network as single-stage (SS), multistage (MS), or crossbar
networks. Figure 1 illustrate this taxonomy. In the following discussion, we study the different types
of dynamic and static interconnection networks.

Figure 1: Taxonomy of interconnection networks

3. SINGLE BUS BASED INTERCONNECTION NETWORKS

A single bus is considered the simplest way to connect multiprocessor systems. Figure 2 shows an
illustration of a single bus system. In its general form, such a system consists of N processors, each
having its own cache, connected by a shared bus. The use of local caches reduces the processor
memory traffic. All processors communicate with a single shared memory. The typical size of such a
system varies between 2 and 50 processors. The actual size is determined by the traffic per processor
and the bus bandwidth (defined as the maximum rate at which the bus can propagate data once
transmission has started). The single bus network complexity, measured in terms of the number of
buses used, isO(1), while the time complexity, measured in terms of the amount of input to output
delay isO(N). Although simple and easy to expand, single bus multiprocessors are inherently limited
by the bandwidth of the bus and the fact that only one processor can access the bus, and in turn only
one memory access can take place at any given time.

Figure 2: Single bus system

4. MULTIPLE BUS BASED INTERCONNECTION NETWORKS

The use of multiple buses to connect multiple processors is a natural extension to the single shared bus
system. A multiple bus multiprocessor systemuses several parallel buses to interconnect multiple
processors and multiple memory modules. A number of connection schemes are possible in this case.
Among the possibilities are the multiple bus with full bus memory connection (MBFBMC), multiple
bus with single bus memory connection (MBSBMC), multiple bus with partial bus memory
connection (MBPBMC), and multiple bus with class-based memory connection (MBCBMC).
Il
3.

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The multiple bus with full bus memory connection has all memory modules connected to all buses.
The multiple bus with single bus memory connec-tion has each memory module connected to a
specific bus. The multiple bus with partial bus memory connection has each memory module
connected to a subset of buses. The multiple bus with class-based memory connection has memory
mod-ules grouped into classes whereby each class is connected to a specific subset of buses. A class is
just an arbitrary collection of memory modules.

Figure 3: (a) Multiple bus with full bus memory connection (MBFBMC); (b) multiple bus with single
bus-memory connection (MBSBMC); (c) multiple bus with partial bus memory connection
(MBPBMC); and (d) multiple bus with class-based memory connection (MBCBMC)

5. SWITCH-BASED INTERCONNECTION SINGLE-STAGE NETWORKS

A crossbar network represents the other extreme to the limited single bus network. While the single
bus can provide only a single connection, the crossbar can provide simultaneous connections among

654
all its inputs and all its outputs. The crossbar contains a switching element (SE) at the intersection of
any two lines extended horizontally or vertically inside the switch. Consider, for example the 8x8
crossbar network shown in Figure 4. In this case, an SE (also called a cross-point) is pro-vided at each
of the 64 intersection points (shown as small squares in Fig. 4). The figure illustrates the case of
setting the SEs such that simultaneous connections between Pi and M8-i+1 for 1 8 are made. The two
possible settings of an SE in the crossbar (straight and diagonal) are also shown in the figure.

Figure 4: An 8x8 crossbar network (a) straight switch setting; and (b) diagonal switch setting

6. SWITCH-BASED INTERCONNECTION MULTI-STAGE NETWORKS

Multistage interconnection networks (MINs) were introduced as a means to improve some of the
limitations of the single bus system while keeping the cost within an affordable limit. The most
undesirable single bus limitation that MINs is set to improve is the availability of only one single path
between the processors and the memory modules. Such MINs provide a number of simultaneous paths
between the processors and the memory modules. As shown in Figure 5, a general MIN consists of a
number of stages each con-sisting of a set of 2x2 switching elements. Stages are connected to each
other using Inter-stage Connection (ISC) Pattern. These patterns may follow any of the routing
functions such as Shuffle Exchange, Butterfly, Cube, and so on.

Figure 5: Multistage interconnection network

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Figure 6 shows an example of an 8x8MIN that uses the 2x2 SEs described before. This network is
known in the literature as the Shuffle Exchange network (SEN). The settings of the SEs in the figure
illustrate how a number of paths can be established simultaneously in the network. For example, the
figure shows how three simultaneous paths connecting the 101,
101 011, and 110 010 can be established. It should be noted that the interconnection pattern among
stages follows the shuffle operation.

Figure 6: An example 8x8 Shuffle Exchange network (SEN)

7. CONCLUSION

In this paper, we have overviewed a number of system configurations for multiprocessors. We have
discussed the different topologies used for inter-connecting multiprocessors. Taxonomy for
interconnection networks based on their topology is introduced. Dynamic and static interconnection
schemes have been studied. In the dynamic interconnection scheme, three main mechanisms have
been covered. These are the bus topology, the crossbar topology, and the multistage topology.

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