Registration Number: MT1769

2007 Microchip 16bit Embedded Control Design Contest

dsPIC LCR Meter

Registration Number: MT1769

Eligible Part(s) Used:

dsPIC30F4012 28Pin Motor Control MCU
Bonus Part(s) Used:
MCP6022 10MHz Dual Op-Amp
Additional MICROCHIP Part(s) Used:
MCP23S08 8Bit SPI GPIO
MCP41010 10K SPI Digital Pot
MCP6S91 SPI Binary PGA Op-Amp
MCP1525 2.5V Precision Voltage Reference

Abstract:
The LCR meter is not a tool commonly found in the electronics hobbyist’s workshop. Traditionally these
tools have been limited to professional design labs and production line quality assurance activities. Whilst
high end (and increasingly entry level) millimeters include a capacitance measurement mode, the charge
discharge methodology used is inaccurate and idealizes the component being tested.

A number of current trends in electronics are driving the increasing need for an LCR meter by the
hobbyist. The first situation requiring and LCR meter is the widespread use of SMD topologies and the
increasing desire of hobbyist to take advantage of these components. Typically, SMD chip capacitors are
not marked with their values making identification impossible without some method to measure them,
preferable in circuit. Using a portable LCR meter with tweezer attachments this type of measurement is
quick and accurate.

The second driver for needing an LCR meter is the rapid increase switch mode power supplies being used
to deliver embedded systems with flexible input and output voltage rails. In particular the ‘buck boost’
style of supply system has seen the introduction of inductors into the kit of hobbyists who would otherwise
not have ever had need for this component. One excellent source of inductors is obsolete electronics;
however the parameters are never marked on the device making the inductance and quality factor a
complete mystery.

The design presented utilizes up to date digital methods to analyze the analog performance of the device
under test (DUT). The design uses direct digital synthesis (DDS) techniques to generate the test
waveform and digital signal processing (DSP) methods to condition the resulting voltage and current
signals. Three test frequencies are implemented (100Hz, 1kHz, 10kHz) and both parallel and series
circuit models are evaluated, automatic selection of both frequency and circuit model is available. Basic
accuracy is better than 1%.

The prototype system is built around Microchip’s 16bit 28pin development board. Programming of flash
memory was achieved using Microchip’s USB PICKITII programmer. Firmware code was written in C and
compiled using the competition version of C30, developed in MPLAB v7.50. Coefficients for DSP filtering
were created using Momentum Data Systems dsPIC FD Lite. The analog anti aliasing filters were
designed with Microchip’s Filter Lab v2.0.

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Fig 1 : Complete dsPIC LCR Meter Prototype System.

Theory of Operation:
LCR Meters measure the impedance of a component subjected to an AC voltage source. The measured
impedance consists of both real (current in phase with voltage) and complex (current 90° out of phase with
voltage). These parameters can tell the user a lot of information about the component, how it will perform
at a particular frequency as well as quantifying its non ideal characteristics.

Existing LCR meters use a number of methods to establish the real and complex components of AC
impedance. One method is to mix the voltage and current signals in order to establish an effective power
factor (PF) ratio, therefore determining the phase relationship. Another method is to measure the voltage
and current through the device in separation and compare to a reference waveform of known phase. The
method used in this device is to simultaneously measure the voltage and current waveforms and directly
establish the total impedance and phase angle.

The impedance can be derived from the ratio of voltage amplitude to current amplitude. The phase angle
can be measured as the time lag between zero crossings. Figure 2 illustrates these measurements
graphically. The relationships hold true for either parallel or series circuits.

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Current Voltage
Amplitude Amplitude

Phase Shift

Fig 2 : components defining total impedance.

Figure 3 shows simplified diagram of the circuit used to make the impedance measurements. A sinusoidal
waveform of known frequency is buffered by an op-amp and then applied to the device under test (DUT)
via a source resistance. Current flowing through the DUT is directed to the inverting input of a second op-
amp. The output voltage of this op-amp ensures that the current flowing through the feedback resistor is
equal to that flowing through the DUT. This action induces a voltage across the feedback resistor that is
proportional to the current flow.

DUT DUT
Voltage Current

1K Source
Resistance 1K
-
Device Under Test
(DUT) -
+
+

Fig 3 : Simplified Test Circuit.

Using the circuit shown the two differential voltage signals representing current through and voltage
across the DUT can be measured simultaneously. If this data is bandwidth limited and logged at a rate
that ensures the Nyquist-Shannon criterion is met, the signal can be accurately re-constructed.

In order to ensure that the signal to be analyzed was free from superfluous noise and aliasing effects,
careful attention was paid to signal conditioning. Figure 4 shows the overall flow of data acquisition in
both the analog and digital realms for each test signal frequency.

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 Registration Number: MT1769

Signal + Noise
+

-61dB attenuation
Low Pass
from 10KHz ->
Anti Aliasing Filter
50KHz

6th Order Analogue

(Butterworth) Filter

10bit ADC 100KHz Sample Rate

10KHz Test Freq. 1KHz Test Freq. 100Hz Test Freq.

32 Tap LP FIR + 48 Tap LP FIR +

Decimate x 8 Decimate x 16

8 Tap IIR + 8 Tap IIR + 8 Tap IIR +

Butterworth BP Butterworth BP Butterworth BP

Minimal Noise
Signal

Fig 4 : Data Acquisition and Digital Signal Processing Methodology.

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The first component of the signal conditioning is the anti-aliasing filters. The requirement on these filters is
to reduce the energy of the signal in the bandwidth Fs/2 to represent less than the ADC LSB value. In this
case the sample rate (Fs) is 100 kHz and the ADC is 10bits, therefore this filter stage has to reduce the
signal strength by 61B between 10 KHz (highest frequency of interest) and 50 kHz (Fs/2). This task
requires a 6th order Butterworth filter. Microchips Filter Lab v2.0 was used to generate the passive
component values for this filter.

Once the signal has been suitably band limited it is digitized by the 10bit ADC. The next action is
dependant on the test frequency being generated by the DDS chip. In the case of a 10 kHz test the signal
is passed directly to an IIR band pass filter that limits the bandwidth to only the frequency of interest. With
the 10kHz test frequency the sample rate gives ten samples per sinusoidal cycle, the minimum resolution
of all test frequencies, this is however sufficient to accurately re-construct the signal being measured.

In the case of the 1 kHz and 100 Hz tests, the signal must first be low pass filtered and decimated. The
low pass filter is a FIR type (Gaussian). The rate of decimation is dependent on the test frequency, either
a rate of eight or sixteen. The need to decimate in a multi-rate system comes from the desire to minimize
the size of data needed to represent a single cycle and the need to still meet Nyquist with a single anti-
aliasing filter.

Fig 5 : Typical Waveforms. (Left – Minimal Gain), (Right – Effects of EMI at High Gain).

The need for effective filtering is best illustrated by the right hand image in Figure 5. The noise seen on
the highly amplified current signal is predominantly caused by a florescent magnifying lamp in very close
proximity to the circuit. Whilst a number of approaches will be taken to avoid EMI effects in the final
product (e.g. shielding) the DSP filtering represents a more effective defense against this error source.

Once the signal has been appropriately digitized and filtered it can be reconstructed by accurately finding
the zero crossings. Prior to this the values of each point over an arbitrary cycle are summed and the data
adjusted by this value, essentially negating any offset errors.

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Figure 6 illustrates the methodology used for finding the zero crossing points. Initially a linear regression
of points either side of a crossing is made, this generates a guess value for the actual crossing. Using this
method with sufficiency high sampling rates (minimum five time source frequency) yields errors in the
order of 5°.

a0

g a1

dt
Fig 6 : Methodology for Determining Zero Crossing Point.

Further improvements in accuracy are made by implementing an iterative function in the area either side
of the guess point. This function aims to minimize the error between the calculated and measured values
for a0 & a1. This can be achieved without knowing the amplitude of the waveform because the formula
used (Figure 7) is implemented as a ratio of values that effectively cancels the effect of the amplitude.
This formula attempts to compare the values obtained by using the guessed crossing point with the actual
values measured.

Error = | [ (sin(g) / sin(dt – g)) – ( a0 / a1 ) ] |

Fig 7 : Zero Crossing Error Function.

The amplitude of the waveform is then evaluated using the calculated zero crossing. The actual point
used for this calculation is closer to the waveform peak to minimize error as the gradient here is smaller.

Once the amplitued and relative phase between the voltage and current waveforms is known all of the
device paramaters can be evaluated using standard text book electrical fomulas. The exact formula to be
used is determined by the nature of the component (i.e. leading or laging) and the type of circuit model to
be used (i.e. series or parallel).

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Operating Specification:

Test Frequency 100Hz, 1kHz, 10kHz, (Auto)

Measurement Model Series, Parallel, (Auto)
Drive Signal 1V pp via 1kΩ
Maximum Impedance 10MΩ
Minimum Impedance 100mΩ
Basic Accuracy 1% ( ± 0.1° )
Displayed Parameters Z(Ω), R(Ω), X(Ω), C(F), L(H), Q, D, θ(°)
Supply Voltage 9V
Supply Current 180mA (385mA with LCD Back Light)
Fig 8 : Basic Operation Specifications

System Overview:
Figure 9 shows the overall functional block diagram of the system. The core device is a dsPIC30F4012
clocked from an external crystal operating a 6MHz. The 16x PLL is used to result in 24MIPS Operation.
This oscillator was used to allow exact ADC sample rates.

The system was initially designed around the dsPIC30F2010 supplied in the competition sample pack,
however during development it became clear that this device did not have enough program memory or
variable RAM to implements the functions needed for this product. This family of dsPIC family was
chosen because of the fast 10bit ADC; higher resolution would have required un-realistic anitalising filter
attenuation (e.g. 12bits requires 74dB).

The system consists of analog measurements stages and a user interface stage. Extensive use of the
SPI port was made to maximize functionality from the 28pin device. The Graphic LCD’s 8bit parallel data
port is controlled by a MCP23S08 SPI GPIO and the control switches are interfaced to the ADC port using
a resistor ladder configuration. The Analog stages also consist of several SPI devices, including two
MCP6S91 PGA’s an AD9833 DDS signal generator and a MCP41010 10K Digital Pot used to correct the
driver signal offset. The chip select (CS) signal between the Digital Pot and GPIO were able to be shared
due to the instruction set bit masking used by each device, further reducing the required pins.

The configuration of the Analog input stage gives a total gain range for each channel between G=2 and
G=4096. The binary steps in gain are designed to ensure that the signal will always fall between two well
defined limits, ensuring a suitable minimum resolution. This arrangement effectively adds ten (10)
additional bits of resolution to the internal 10bit ADC.

Hardware:
The prototype system was built around Microchip’s 16bit 28pin development board. In addition to this
three other boards were manufactured. One board carries the user interface components, graphic LCD
and control buttons. The SPI GPIO chip is mounted on this board, close to the LCD header. This was
manufactured on proto board and mounted on an acrylic stand to allow better viewing of the LCD

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 Registration Number: MT1769

dsPIC30F4012
User Interface

GPIO
128x64 GRAPHIC LCD

SPI Module

Control Buttons (x3)

Resistor Ladder
Arrangement
10Bit ADC

Analogue Input Stage

Anti Aliasing Filters
(PGA)

Device Under Test Direct Digital Synthesis

(DUT) Waveform Generator

Fig 9 : System Block Diagram.

Another board supports the analog measurement components. Due to the low noise requirements and
SMD components used, this double sided board was etched rather than using proto board. Whilst most
component packages were able to be directly soldered to this board (SOIC etc) the AD9833 DDS signal
generator is only available is an MSOP package that required a DIP adaptor board due to its fine pitch.

The final board constructed contains the anti aliasing filters. This was built using proto-board and
reserves some space for future development of the battery power supply stage. Signal connections to and
from this board are made with shielded cable to reduce additional noise pick-up.

The device under test is connected via a set of test leads to the analog board. In the prototype the
connectors between the four wire test leads and PCB are two RCA plugs, the cable shielding is connected
to the analog ground plane by a pair of screw terminals. RCA Plugs were used as they are cheap,
reasonably small, and have good performance at the test frequency. In the final design four separate
RCA plugs will be employed, each with the shield connected to the outer terminal, to allow better noise
immunity. The DUT is connected via a pair of ‘Parrot’ clips which allow hands free use for axial
components; a tweezer test lead will be made for SMD parts. The first set of leads constructed utilized a
four core cable; however this proved to introduce a large amount of parallel capacitance; for this reason
the leads were separated.

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Fig 10 : User Interface Board. Fig 11 : Anti Aliasing Filters.

Fig 12 : Analog Stage Board - Top. Fig 13 : Analog Stage Board - Bottom.

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Control Interface –

The user interacts with the device via three control buttons and receives information via a graphic LCD
screen. The interface is intentionally kept a simple a possible; however there is scope to introduce more
features, settings, menus etc. later.

The graphic LCD is a 128 x 64 pixel screen using a Toshiba T6963C chipset. The eight data lines d0
through d7 are driven via a Microchip MCP23S08 SPI GPIO. These lines are driven as outputs for data
write cycles and changed to inputs for status checking. The RD signal is supplied as an inversion of the
WR signal, via a general purpose NPN transistor rather than utilizing an additional GPIO Line for no
additional function. The two remaining control lines, CE and C/D, are driven directly from the
dsPIC30F4012 I/O pins.

The screen contrast is controlled by connection to a PWM pin clocked at 1MHz (required for DDS
operation) and pulse width modulated. The firmware submitted for the contest does not attempt to allow
the user to adjust this contrast, although this functionality will be added in a later revision. Similarly
backlighting control is not implemented in the prototype; however its use needs to be reviewed in terms of
the planned battery powered configuration.

The push buttons are intended to be implemented in the final product as membrane keys, however for the
prototype general purpose PCB mount push buttons were used. There are four buttons pictured, however
only three are operational in the prototype; the red button is intended to switch a low quiescent current flip-
flop that will control an LDO regulator for battery operation to be developed later.

Fig 14 : Example Graphic LCD Screens.

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Each push button links a resistor to ground in a ladder configuration. This system gives the advantage of
only requiring a single ADC line to implement a number of buttons. Additionally, combinations of button
presses can have unique ADC values if resistor values are correctly selected. In this implementation
pressing the two left hand switches in combination enacts a separate function (calibration). Suitable de-
bounce delays have to be implemented in firmware to deal with the slight timing difference that humans
will cause when pushing both buttons together.

Signal Generation –

The AC sinusoidal signal required for device testing is created using an Analog Devices AD9833 DDS
signal generator chip. This device runs as an SPI slave, outputting a square, triangle or sine wave based
on an internal 28bit frequency setting register and an external clock signal. The resulting output is a
common mode output with 10bit resolution.

Whilst it may have been possible to generate a sine wave directly from the PIC chip using a number of
methods, as recently described in Circuit Cellar, the system quickly becomes complex and inflexible
requiring a large number of external components. This is especially true where multiple frequencies are
required.

Utilizing a DDS chip creates waveforms over a wide frequency range with very low distortion and requires
no additional filtering etc. The master clock signal for the DDS chip was created from the dsPIC30F4012
PWM port. The Clock frequency was set at 1MHz in order to deliver both good frequency resolution from
the 28bit control register and minimize noise transfer to the measurements frequencies.

Analog System Stages –

The analog stages were designed with high accuracy and low noise in mind. Considerable amplification is
required for devices at either extreme of the impedance spectrum, making the system susceptible to a
number of error sources. The signal from offset errors at these high amplifications can easily saturate the
output. With this in mind the bipolar sections of the analog circuit were handled via Analog Devices
AD8629 Zero-Drift Op Amps whose 1µV offset and 0.002µV/°C offset drift are orders of magnitude bellow
the expected signal range.

The task of the first analog stage is to condition the test signal. The signal from the DDS chip is ~0.3V PP
and its common mode voltage (CMV) is ~ 0.3V. This signal is fed through a single order low pass RC
filter to further isolate any clock noise. From there it is directed to the inverting input of an Analog Devices
AD8629 Op Amp. This Op Amp is configured to generate a nominal 1vPP signal with 0v CMV. The gain is
set by external resistors and the offset is achieved via a voltage present on the non-inverting input which
is adjusted by the MCP41010 10kΩ Digital Pot.

The resultant signal from the first stage is fed via a 1kΩ source resistor to the DUT. A four wire “Kelvin”
configuration is used to feed the differential voltage signal across the DUT to the next stage. The test
signal voltage passes through the DUT and into the inverting input of a ground referenced AD8629 Op
Amp. The current flowing through the device is then imposed as a voltage across the 1kΩ 0.1% feedback
resistor. This differential voltage signal is also fed to the next stage and represents the current flow in the
DUT.

The differential signals for voltage and current are directed to separate differential instrumentation style
amplifiers constructed of three AD8629 Op Amp sections each. The gain for this stage is selectable via a
Vishay DG418L analog switch, resulting is either G=2 or G=128. The final op-amp in this differential
configuration is referenced to a 2.5V signal provided by a Microchip MCP1525 Precision Voltage
Reference and buffered by a Microchip MCP6022 Op Amp, In order to minimize source impedance.

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Signal gain stages made use of 0.1% resistors. This was done to ensure that the desired accuracy could
be met without special calibration methods, witch themselves usually involve higher accuracy resistors.

The Analog Devices AD8629 Op Amps have had lead compensation added, by way of small capacitance
(47pF) paralleled with the feedback resistor. This is necessary to ensure stability, especially for stages
with minimal gain. The capacitor value was carefully chosen to not attenuate the test frequency. This
value will once again have to be checked in the final design where PCB trace capacitance may affect the
resulting lead compensation.

The previous stage output is centered on 2.5V but still requires additional gain for impedances significantly
greater or smaller than the 1kΩ source resistance. This signal is finally amplified in binary steps (e.g. 2, 4,
8, 16, 32) by a Microchip MCP6S91 SPI PGA. The reference pin for this op-amp is tied to the same 2.5v
reference voltage as the previous stage.

The non ideal realization of this design is caused by the high frequency impedance of the Vishay DG418L
analog switch, a quantity not covered in the specification sheet. At 10 kHz the switch displays
approximately 3db attenuation and also introduces additional phase shift which has to be compensated
for. A more suitable component, with higher cutoff frequency, will be substituted in future revisions.

Anti-Aliasing Filters –

The anti-aliasing filter was designed using the wizard within Microchips Filter Lab v2.0. The result is a 6 th
order Butterworth filter (Figure 15). Each filter requires three op-amps to implement. Future
developments will aim to increase the sample rate in order to reduce the filter order to four or less. The
main constraint on this task is the ability to effectively down sample data between ADC buffer flag events,
the increase in data size and reduction in interrupt period both become limiting factors.

Fig 15 : “Filter Lab” Program used to design the anti-aliasing filters.

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Power Stages –

The final intention for this device is battery operation; however this has not yet been implemented in the
development system. Currently the power source is a 9V mains regulator, attached to the 16pin
development board using the standard 2.5mm DC jack. The 9V is stepped down using the on board
National Semiconductor LM2937IMP +5V LDO Regulator. All further power stages are fed from this
primary +5v regulated power rail.

The analog stages require a negative voltage rail for bipolar operation. This rail was generated from the
+5v rail using a Texas Instruments TPS60403 60mA Charge Pump. This part only required a minimal
number of external Tantalum capacitors for operation. This particular part was chosen due to its high
switching frequency (250KHz) which is would be successfully filtered from the test signal.

The +2.4v and -2.4v rails used by the AD8629 Op Amps are derived from the +5v and -5v rails
respectively using zener diodes.

Firmware:
The code for this device was written in C, compiled with the contest version of C30 and MPLAB was used
as the IDE. DSP filter coefficients were included as assembly files (*.s) generated by Momentum Data
Systems dsPIC FD Lite. Code was compiled without any optimization levels in anticipation of the limited
license period ending.

Code was developed as many small individual functions which could be tested in isolation. Developing
the code in small manageable pieces was a necessary approach because the programming tool being
used (PICKITII) did not support debugging of dsPIC devices.

The design was initially based on the dsPIC30F2010 device included in the contest sample pack.
However, Flash data space was soon exceeded, requiring a device with more program memory space.
Luckily the transition between chips in the same family is simple. The dsPIC30F4012 device represents
two steps up the device tree, giving a four fold increase in memory. It is possible that with optimization the
code could fit into an intermediate device.

The code submitted with the contest consumes 41,466 bytes of program space and 2,526 bytes of RAM.
This result is with no code optimization; tests revealed that using optimization level five reduced the
program code size to 32,775 bytes, although no extensive tests were made of functionality. Coefficients
for DSP filter functions are stored in PSV variable space to reduce RAM consumption. The fractional
arrays holding the measured and filtered voltage and current data were the key users of RAM.

SPI Interface Code –

Code to interface with the SPI module was written first. Rather than using library functions, the interface
code for read and write cycles was written from scratch. This allowed better flexibility and helped the
authors understanding of the modules operation.

The SPI module is configured in master mode and 8 bit data frame size. Some of the devices used
expect 16bit words, this is handled by software where needed.

In total there are five SPI slave devices deployed in this device. Compared to the SPI GPIO used for the
LCD, the clock speed had to be reduced for items on the analog board as slew rates were to low to ensure
robust communications. The decreased slew rates are mostly a function of the prototyping interconnects
used. It is expected that the clock rate can be made common with the graphics module once the final
PCB’s are developed.

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unsigned char READ_SPI_GPIO_INPUT_VALUE()

{
unsigned char READ_VAL;
SET_SPI_GPIO_INPUT_MODE();
int wait;
wait = 0;
while (SPI1STATbits.SPITBF == 1){} //WAIT FOR BUFFER CLEAR
SPI_LCD_CS = 0; //BRING CS LOW
wait++;
wait++;
SPI1BUF= 0x41; //SEND CONTROL BYTE
while (SPI1STATbits.SPITBF == 1){} //WAIT FOR BUFFER CLEAR
SPI1BUF=0x09; //SEND ADDRESS BYTE
wait = 0;
while (wait <= 60){wait++;} //WAIT FOR BUFFER CLEAR
SPI1STATbits.SPIROV = 0; //CLEAR OVERUN FLAG
READ_VAL = SPI1BUF; //READ DATA BYTE
SPI1STATbits.SPIROV = 0; //CLEAR OVERUN FLAG
SPI1BUF=0x00; //SEND EMPTY BYTE
while (SPI1STATbits.SPIRBF == 0){} //WAIT FOR READ BUFFER FULL
READ_VAL = SPI1BUF; //READ DATA BYTE
SPI_LCD_CS = 1; //BRING CS HIGH
wait++;
wait++;
SET_SPI_GPIO_OUTPUT_MODE();

return READ_VAL;
}

Fig 16 : Example Code: Function For Reading Data From SPI GPIO.

Graphic LCD Code –

Once SPI support was available, code was developed to interface with the LCD screen. The screen then
became a rudimentary debugging device, replacing the single LED often used.

Control code was based on the Toshiba T6963C Datasheet. The screen was run in six bit mode in order
to correctly space the text. The disadvantage of using this mode is the associated increase in the amount
of memory used to store graphics.

Fig 17 : FastLCD Program (Free Download: www.FastAVR.com)

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Functions were written for displaying graphics and text strings stored in program memory. A custom
function was written to handle the display of float variables as fixed precision integers, also displaying the
appropriate unit prefix (e.g. p, n, µ, m, K, M). This function was created rather than using a standard c
library functions such as fprintf() because of the large code size and large software stack associated with
those functions.

The graphics displayed on the LCD were created with FastLCD V1.2.0. (Available from FastAVR.com)
This free program (Figure 17) allows the user to quickly create and preview graphics before exporting as a
text file in a number of formats including one suitable for the Toshiba T6963C chipset. Graphics were
stored in program memory as constants, representing a sizable amount of data.

void LoadSymbol (int HOME_ADDRESS, unsigned char SYMBOL[], int SYMBOL_WIDTH, int SYMBOL_LINES) //Loads Screen
{
int Address;
int MemCount;
int Lines;
Lines = SYMBOL_LINES;
Address=0;

while (Lines > 0)

{

while ( (CheckStatus() & 0x03) != 0x03){} //WAIT FOR STATUS BITS

WriteData(LOBYTE(HOME_ADDRESS + ((SYMBOL_LINES - Lines)*22)));
while ( (CheckStatus() & 0x03) != 0x03){} //WAIT FOR STATUS BITS
WriteData(HIBYTE(HOME_ADDRESS + ((SYMBOL_LINES - Lines)*22)));
while ( (CheckStatus() & 0x03) != 0x03){} //WAIT FOR STATUS BITS
WriteCommand(0x24);

// Auto Mode
while ( (CheckStatus() & 0x03) != 0x03){} //WAIT FOR STATUS BITS
WriteCommand(0xB0); //START AUTOMODE

MemCount=(SYMBOL_WIDTH);

while (MemCount!=0)
{
while ( (CheckStatus() & 0x08) != 0x08){} //WAIT FOR STATUS BITS

WriteData(SYMBOL[Address]);
MemCount--;
Address++;
}

while ( (CheckStatus() & 0x08) != 0x08){} //WAIT FOR STATUS BITS

WriteCommand(0xB2); //END AUTOMODE

Lines--;
}
Fig 18 : Example Code: Function for Loading Graphics Stored in Const Array to LCD.

ADC Implementation –

Three ADC channels are implemented in this design AN4, AN3, AN2. Voltage reference signals are
supplied external to the analog module on AN0 and AN1. The external reference signals are probably
unnecessary for this design and may be removed in future to free up more IO lines for other functions
such as battery voltage monitoring.

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Sampling for control buttons is controlled by software, in contrast LCR measurements are automatically
triggered by the ADC module. These measurements are made in simultaneous mode using FSOC as the
timing input. Each channel is sampled at 100 kHz, giving a total ADC load of 200 kS/s. The software
polls the interrupt flag during sampling to decide when to unload the result buffers, no interrupt routine is
used.

DSP Functions –

As outlined in the “Theory of Operation” section, the dsPIC LCR meter implements both IIR and FIR filters.
The filters were designed using Momentum Data Systems dsPIC FD Lite. The resulting assembly files
from this program had to be modified to suit versions of MPLAB C30 v1.30 and higher, as the standard
declarations used are not allowed.

Because the initial value of the data set could lie anywhere within the sinusoid function, the filters have to
be appropriately set-up before implementation. Without doing this correctly, the data could appear to the
filter as a step input which would cause ringing that outlasts the size of the data set. The process for
setting the delay line involves running a set of data, whose length is an exact multiple of the period, many
times through the filter and ignoring the resulting output data.

Fig 19 : Momentum Data Systems dsPIC FD Lite – 8 Tap 100Hz Band pass IIR Filter

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Setting the delay line for IIR filters in the way described presents no problems, however the actual
frequency of the “100 Hz” test was adjusted to 100.80635 Hz in order to present an exact period of data
with an integer sized data set. The FIR filters used for down sampling cannot use recorded data as there
is a strict requirement on the cycles between buffer flags. Instead the initial fifty cycles of the filter use
fresh data to set up the filter and then record only the last few frames for further analysis.

Test Code –

The code that actually performs the LCR measurements is contained within the file LCR METER
FUNCS.C. Each test frequency has a separate function call; this is called from RUN_TEST() depending
on the user settings. The test routines take an argument to set the number of samples to be averaged.
There is no return form this function; instead the result is stored in a global (to that module) variable.

In ‘Auto Frequency’ mode each test routine is called from RUN_TEST() without averaging, the frequency
which produces an impedance closest to that of the source resistance is then chosen as the test
frequency. The chosen frequency is called again with some averaging (5x) to produce the final results.
This method produces the lowest gain measurement; the user can override the auto mode if the chosen
frequency is inappropriate for the component under test.

Figure 20 illustrates a simplified program flow for the function call that performs each test. The detail,
especially that relating to down-sampling, is different for each frequency. The first tasks performed are
setting the ADC module, setting the DDS chip for the desired frequency and setting the gain for both
channels to a minimum value. The function of the initial acquisition loop is to auto range the gain for each
channel. Following offset correction and band-pass filtering the data set is scanned for the maximum
value, if bellow a preset threshold the gain is increased (doubled) and acquisition started again. This
process is continued until either a suitable gain is found or the maximum gain is reached.

The second loop within the test function acquires data in a similar way to the previous loop, correcting the
offset and filtering the resulting array. The main difference with this loop is that additional code is
executed to calculate the crossing point and from this the impedance and phase angle. The number of
times that this loop executes is dependant on the argument passed to the function. Once the appropriate
number of loops has executed the calculated impedance and phase values are divided by the argument to
create an average value which is then stored in a global variable.

Calculations of the parameters other than impedance and phase angle are made within RUN_TEST().
This calculation is dependant on the circuit model under consideration. Auto mode attempts to first check
if the parallel mode is suitable (small capacitance) otherwise the series model is utilized. The resulting
parameter values are recorded to a global structure. A call to functions within the module Graphic LCD.C
displays the resulting values within this structure, as well as displaying the circuit elements graphically.

Main Routine –

The main routine does very little. On reset the main loop calls all of the various initialization routines,
starting with hardware and then peripheral devices such as the DDS chip. Following this the LCD is
initialized; the splash screen displayed briefly before the main screen is loaded.

After initialization the function of the loop within Main() is to monitor the control buttons and call the
appropriate function when a valid button push is detected. Button de-bounce code is contained within this
function.

Page 17 of 25
 Registration Number: MT1769

Initialize ADC

Initialize DDS Output

Initialize Gain (Low Setting)

Aquire Smaples

Correct Offset

Bandpass Filter

Sufficient
Increase Gain
Gain ?
NO

YES

Aquire Smaples

Correct Offset

Bandpass Filter

Calculate Phase & Impedance

Sufficient
Sum Result With Previous
Results ?
NO

YES

Divide Result by Num Samples

Reset DDS Output

Fig 20 : Test Code – Simplified Program Flow.

Page 18 of 25
 Registration Number: MT1769

Performance:
The prototype system’s performance is very pleasing. The user interface is easy to use, the push button
operation has a positive feel and the Graphic LCD is clear and easy to read. Measurements appear to
meet the required accuracy (<1%) and repeatability is excellent. The system is able to automatically
choose the most suitable frequency and circuit type, making basic measurements very easy.

Currently the program implements a five cycle averaging function on the result to improve stability and
accuracy. Whilst this is a useful function it has the disadvantage of increasing the overall test cycle time,
a test on “automatic” will take up to five seconds to finish. A fast test feature is needed in the next
prototype to allow quick sorting of parts at a lower accuracy.

Typically LCR meters implement short circuit and open circuit calibration. Tests on this device have
shown that the use of the four wire method has resulted in a series resistance error that is significantly
less than the lower limit impedance able to be measured. Open circuit tests however have shown that
there is approximately 3.5pF of parallel capacitance in the test leads. At frequencies bellow 10 KHz this
capacitance represents an impedance value significantly above the measurement ceiling.

The Calibration function enacted by holding the “Freq” and “Mode” buttons down together currently only
adjusts the offset voltage via the SPI Digital Pot. Future revisions of this design will include add a
calibration cycle to this function to measure and compensate for the parallel capacitance.

Further Developments:
The initial task for further development is to optimize the current operations. This time consuming task
involves reviewing each data processing function and calculating and evaluating the effect of simplifying
the code. For example, it may be possible to reduce the number of cycles that the filters are run in order
to set their delay line; however the possible impact on accuracy has not been evaluated.

Once the current code is optimized the amount of free memory will dictate what additional functions are
implemented in the final meter. The following is a list of some of the desired features\functions.

 User control of LCD Contrast.

 User control of LCD Backlighting.
 Replace analog switch for device with better bandwidth.
 Add calibration functions.
 Introduction of additional control button for Fast\Slow test.
 Introduction of optional phasor display of complex impedance.
 Use of four shielded cables for leads (reduce noise susceptibility).
 Smart battery power (Auto Shutdown, Low Battery Warning etc.).

In order to correctly measure the impedance, or more importantly equivalent series resistance (ESR), of
electrolytic capacitors a DC bias voltage must be applied. In the next design this is easily added as a
fixed (e.g. 2V) bias that is isolated from the measurement equipment by small value DC blocking series
capacitors. If higher bias voltages are required an external bias terminal set may be added.

Input overload protection is another feature that is especially important for large electrolytic capacitors and
is also easy to add to the design. When the DUT is connected any stored energy in the device will
discharge into the measurement circuit. Effective protection can be provided by varistors or zenners
coupled with forward biased diodes.

The final development of this project will be incorporation into a multi-meter style enclosure and battery
power for portable use.

Page 19 of 25
 Registration Number: MT1769

Conclusion:
The development of the dsPIC LCR Meter has been an excellent introduction for the author to Microchip’s
16bit DSP controllers. The tool chain and development tools supplied by Microchip make coding this type
of controller quick and painless, especially important as I was moving on from years of coding 8bit PIC
processors in assembly. The compiler was easy to use and all of the library files were well documented.
Somewhat surprisingly, the DSP filter functions were the easiest part of the firmware to code, mostly due
to the dsPIC FD Lite program and Microchip documentation.

The SPI communication protocol was a savior in terms of functionality to pin count ratio. This is especially
true for the LCD which if not handled by the SPI GPIO would have consumed half of the microprocessors
available pins.

Once the above listed features are added, the dsPIC LCR Meter will make a welcome addition to tools on
my desk. With some insight into the possibilities of these processors, I am already thinking of the next
project.

Page 20 of 25
 Registration Number: MT1769

D1
1N4148

VR1 +5v +5v

LM2937IMP
1 3
IN OUT

1KΩ 1%
R1
J1 GND GND

+
2 4
D2

10μF

10μF
0.1μF
C1

C3
C2
PWR GRN
ON

+5v

10KΩ 1%
R2
SW1
4 1 R3 +5v
MCLR
3 2 1KΩ 1%
0.1μF REFER NOTE #2

C4
RESET
+5v C10 R6
100nF 0Ω
REFER NOTE #2

+
R4

C11
10μF
R7
MCLR AVDD
10Ω 1% IC1
EMUD3/AN0/VREF+/CN2/RB0 AVSS 0Ω
+
100nF

C5

10μF

C6

EMUD3/AN1/VREF-/CN3/RB1 PWM1L/RE0
LCD_CONT
AN2/SS1/LVDIN/CN4/RB2 PWM1H/RE1
R5 V_SE_SIG LCD_WR
AN3/INDX/CN5/RB3 PWM2L/RE2

dsPIC30F4012
A_SE_SIG PWG_FMCLK
10Ω 1% AN4/QEA/IC7/CN6/RB4 PWM2H/RE3
RES_LADDER LCD_CD +5v
AN5/QEB/IC8/CN7/RB5 PWM3L/RE4
APGA_SPI_CS LCD_CE
VSS PWM3H/RE5
LCDPOT_CS
C7 OSC1/CLKI VDD

20pF OSC2/CLKO/RC15 VSS

6MHz

EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 PGC/EMUC/U1RX/SDI1/SDA/RF2
C8 SPI_SDI
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 PGD/EMUD/U1TX/SDO1/SCL/RF3

+
SPI_SDO

100nF
C12

C13
20pF

1μF
X1 VDD FLTA/INT0/SCK1/OCFA/RE8
SPI_SCK
EMUD2/OC2/IC2/IN2/RD1 EMUC2/OC1/IC1/INT1/RD0
DDS_SPI_CS
100nF

C9

+5v
VPGA_SPI_CS

J2 +5v
VPP MCLR
VDD

VSS

PGD SW_GA
PGC SW_GV
NC

NOTES:

1. UNLESS NOTED, ITEMS ON THIS

PAGE ARE STANDARD SECTIONS OF
THE 16-BIT 28-PIN MICROCHIP
X1 6MHz Crystal
DEVELOPMENT BOARD.
D2 LED Green
D1 1N4148
C13 0.1µF Ceramic 2. ITEMS HIGHLIGHTED ARE NOT
C12 1µF Tantalum STANDARD PARTS OF THE
C11 10µF Tantalum DEVELOPMENT BOARD.
C10 0.1µF Ceramic MODIFICATIONS MADE FOR 1MSPS
C9 0.1µF Ceramic ADC OPERATION AS PER DATA
C8 20pF Ceramic SHEET.
C7 20pF Ceramic
C6 1µF Tantalum
C5 0.1µF MKT J2 ICSP 6-Pin Single Inline RA Male
3. THE FOLLOWING 0Ω RESISTORS
C4 0.1µF Ceramic J1 2.5mm Female DC Jack WERE REMOVED FROM THE
C3 1µF Tantalum IC1 dsPIC30F4012 DEVELOPMENT BOARD: R14, R15,
C2 0.1µF Ceramic VR1 LM2937IMP 5V REG R16, R18
C1 1µF Tantalum SW1 SPST Mom Switch
R7 0R 1% ¼W
2007 Microchip \ Circuit Cellar Design Contest REGISTRATION NO:
R6 0R 1% ¼W
R5 10R 1% ¼W dsPIC LCR METER MT1769
R4 10R 1% ¼W
R3 1K 1% ¼W o
REV N : DATE: PAGE DESCRIPTION: SIZE: PAGE:
R2 10K 1% ¼W
R1 1K 1% ¼W 0 06/10/07 MICROPROCESSOR (28Pin Dev Board) A4 1/5
SYMBOL DESCRIPTION

Page 21 of 25
 Registration Number: MT1769

+5v

+5v Schottky
1N5819 470Ω 1%
15kHz PWM
LCD_CON
D2 R10

C14
10KΩ 1%

1μF

C15
10nF
R9

+
C
1KΩ 1% BC547
B
LCD_WR NPN

R8 Q1 J3
E
FG/Vee 1 +5v
Vss

Vdd
+5v Vo

WR

RD

10KΩ 1%
CE

R11
LCD_CE
C/D +5v
22KΩ 1%

LCD_CD
R26

Reset

DB0

RES_LADDER DB1

0.15μF

C16
DB2
DB3
82KΩ 1%

R27

DB4

10KΩ 1%

R12
DB5
SW2
DB6
4 1 39KΩ 1% DB7

3 2 FS
R28
MODE K
MODE + FREQ = CALIBRATE

A
20
470Ω 1%
470Ω 1%

470Ω 1%

470Ω 1%
R14

R16

R18

R20 +5v
+5v
470Ω 1%

470Ω 1%
470Ω 1%

470Ω 1%
R15

R17

R19

SW3 R21

10KΩ 1%
4 1

R22
18KΩ 1%
470Ω 1%
3 2
R29 R13
FREQ

NC
10KΩ 1%
MCP23S08

LCDPOT_CS
+5v R23
SW4
4 1
2.2KΩ 1%

3 2
R30 SPI_SI 10KΩ 1%
TEST SPI_SO
IC2 SPI_SCK R24
+

C18
C17

0.1µF
1μF

10KΩ 1%

R25

R30 2.2K 1% ¼W NOTES:

R29 18K 1% ¼W
R28 39K 1% ¼W
1. INTERFACE FOR TOSHIBA T6963C
R27 82K 1% ¼W J3 20-Pin Single Inline Female Socket
R26 22K 1% ¼W IC2 MCP23S08 8-BIT SPI GPIO
LCD INTERFACE.
R25 10K 1% ¼W Q1 BC547 NPN
R24 10K 1% ¼W SW4 SPST Mom Switch 2. SCREEN RESOLUTION: 128 x 64.
R23 10K 1% ¼W SW3 SPST Mom Switch
R22 10K 1% ¼W SW2 SPST Mom Switch 3. FONT SELECT BIASED HIGH FOR
R21 470R 1% ¼W C9 1N5819 Schottky 8x6 FONT SET.
R20 470R 1% ¼W D3 0.1µF MKT
R19 470R 1% ¼W C18 0.1µF MKT
4. MCP23S08 ADDRESS: A0 = 0, A1 = 0
R18 470R 1% ¼W C17 1µF Tantalum
R17 470R 1% ¼W C16 0.15µF MKT
R16 470R 1% ¼W C15 0.1µF MKT
R15 470R 1% ¼W C14 1µF Tantalum
R14 470R 1% ¼W
2007 Microchip \ Circuit Cellar Design Contest REGISTRATION NO:
R13 470R 1% ¼W
R12 10K 1% ¼W dsPIC LCR METER MT1769
R11 10K 1% ¼W
R10 470R 1% ¼W o
REV N : DATE: PAGE DESCRIPTION: SIZE: PAGE:
R9 10K 1% ¼W
R8 1K 1% ¼W 0 06/10/07 USER INTERFACE A4 2/5
SYMBOL DESCRIPTION

Page 22 of 25
 Registration Number: MT1769

+5v +2.4v
0.1μF
ANALOG J3

DUT
0.1μF C32 100KΩ 0.1%

C20 R35

1.8KΩ 1%

R34

C30
47pF
IC5
C19
0.1μF

33Ω 1% 220Ω 1% 22Ω 1% 100KΩ 0.1% J4

IC3 -
+

AD9833
R31 R32 R33 - R36
+

C23
0.01uF
AD8629 47pF J5

ANALOG
C31
10μF

0.1μF
+

C21

ANALOG
C22
0.1μF

DUT_V_NEG

ANALOG

ANALOG

OFFSET ADJUST
C33

ANALOG
DUT_V_POS
-2.4v
+2.4v
DDS_SPI_CS
0.1μF
SPI_SCK

ANALOG
SPI_SDO +5v +2.4v C33
IC6
1MHZ PWM 50% DUTY
PWG_FMCLK
-
+ -
IC4 +
LCDPOT_CS 1MΩ 1% 1MΩ 1%
AD8629
SPI_SCK 0.1μF

10KΩ LIN
DUT_V_POS
SPI_SDO
R37 R38
150KΩ 47.5KΩ 953Ω

ANALOG
220KΩ 1% 27KΩ 1%
+2.4v C34 0.1% 0.1% 0.1%
DUT_V_NEG 47pF 47pF
0.1μF R39 R40
MCP41010 R66 R44 R45
-2.4v C24 C25

ANALOG
-2.4v C36
ANALOG

100KΩ 750Ω 24.3Ω 24.3Ω 750Ω 100KΩ

IC8 0.1% 0.1% 0.1% 0.1% 0.1% 0.1%

- R41 R42 R43 R46 R47 R48

+ -
+

100KΩ 0.1%

100KΩ 0.1%
AD8629

R49

R50
150KΩ 47.5KΩ 953Ω
IC7
0.1% 0.1% 0.1% -5v
C37
0.1μF

47pF 47pF

R65 R54 R55

C26 C27

ANALOG
ANALOG

100KΩ 750Ω 24.3Ω 24.3Ω 750Ω 100KΩ V_PRE_G A_PRE_G DG418L

0.1% 0.1% 0.1% 0.1% 0.1% 0.1% +5v +5v

R51 R52 R53 R56 R57 R58

R60

0.1μF
100KΩ 0.1%

SW_GA
100KΩ 0.1%

R59

IC9 47pF C35 47pF

ANALOG

-5v
C29
C28
ANALOG

100KΩ 0.1% 100KΩ 0.1%

IC10
DG418L
+5v R61 R63
-
+ -
+
AD8629
SW_GV
ANALOG

100KΩ 0.1%

R64
100KΩ 0.1%

R62

VREF_A

VREF_V

R56 24.3R 0.1% ¼W C27 47pF Ceramic J3 Gold RCA Socket NOTES:
R55 953R 0.1% ¼W C26 47pF Ceramic IC10 AD8629 Low Offset Op-Amp
R54 47.5K 0.1% ¼W C25 47pF Ceramic IC9 DG418L Analog Switch 1. GROUND CONNECTIONS MARKED
R53 24.3R 0.1% ¼W C24 47pF Ceramic IC8 AD8629 Low Offset Op-Amp
“ANALOG” SHOULD BE PLACED ON A
R52 750R 0.1% ¼W C23 10nF MKT IC7 DG418L Analog Switch
R51 100K 0.1% ¼W C22 0.1µF MKT IC6 AD8629 Low Offset Op-Amp
SEPARATE PLANE AND LINKED TO
R50 100K 0.1% ¼W C21 10µF Tantalum IC5 AD8629 Low Offset Op-Amp DIGITAL\GENERAL GROUND IN ONE
R49 100K 0.1% ¼W C20 0.1µF MKT IC4 MCP41010 10K SPI Digital Pot POINT ONLY.
R48 100K 0.1% ¼W C19 0.1µF MKT IC3 AD9833 DDS Signal Generator
R47 750R 0.1% ¼W R66 150K 0.1% ¼W C37 0.1µF MKT 2. CHIP SELECT (CS) SIGNAL FOR
R46 24.3R 0.1% ¼W R65 150K 0.1% ¼W C36 0.1µF MKT DIGITAL POT (IC4) IS SHARED WITH 8
R45 953R 0.1% ¼W R64 100K 0.1% ¼W C35 0.1µF MKT BIT SPI GPIO (IC2). INSTRUCTION
R44 47.5K 0.1% ¼W R63 100K 0.1% ¼W C34 0.1µF MKT
MASKING ENSURES CORRECT
R43 24.3R 0.1% ¼W R62 100K 0.1% ¼W C33 0.1µF MKT
R42 750R 0.1% ¼W R61 100K 0.1% ¼W C32 0.1µF MKT
INDEPENDENT OPERATION.
R41 100K 0.1% ¼W R60 100K 0.1% ¼W C31 47nF Ceramic
R40 27K 1% ¼W R59 100K 0.1% ¼W C30 47nF Ceramic
R39 220K 1% ¼W R58 100K 0.1% ¼W C29 47pF Ceramic J5 Screw Terminal
R38 1M 1% ¼W R57 750R 0.1% ¼W C28 47nF Ceramic J4 Gold RCA Socket
R37 1M 1% ¼W
2007 Microchip \ Circuit Cellar Design Contest REGISTRATION NO:
R36 100K 0.1% ¼W
R35 100K 0.1% ¼W dsPIC LCR METER MT1769
R34 1.8K 1% ¼W
R33 22R 1% ¼W o
REV N : DATE: PAGE DESCRIPTION: SIZE: PAGE:
R32 220R 1% ¼W
R31 33R 1% ¼W 0 06/10/07 ANALOG STAGE (1/2) A4 3/5
SYMBOL DESCRIPTION

Page 23 of 25
 Registration Number: MT1769

+5v +5v

IC11 IC12

V_PRE_G SPI_SCK A_PRE_G SPI_SCK

VREF_V SPI_SDO VREF_A SPI_SDO
VPGA_SPI_CS APGA_SPI_CS
MCP6S91 MCP6S91

+5v
820pF

820pF
C38 IC13
C39
10KΩ 1% 20KΩ 1% -
+ - 20KΩ 1% 10KΩ 1%
R67 R68 +
MCP6022
R69 R70
ANALOG
C40
680pF

680pF

C41
ANALOG

ANALOG
6.8KΩ 1%
6.8KΩ 1%

R74
R71

200Ω 1%
200Ω 1%

R75
R72

680Ω 1%
680Ω 1%

R76
R73

+5v +5v
13KΩ 1%

13KΩ 1%
C42

C43
1.5nF

1.5nF
R77

R79

430Ω 1% 2KΩ 1% 430Ω 1% 2KΩ 1%

1.3KΩ 1%

1.3KΩ 1%
C44

C45
R82 R81 R83 R84
12nF

12nF
R78

R80

IC14 IC15
3KΩ 1%

R85

3KΩ 1%

R88
- -
+ - + -
2KΩ 1%

+ +
R86

2KΩ 1%

R89
MCP6022 MCP6022
ANALOG

ANALOG
C47
680pF
C46
680pF
620Ω 1%

R87

620Ω 1%

R90
ANALOG
ANALOG
C48
680pF

C49
680pF
ANALOG

V_SE_SIG A_SE_SIG
ANALOG

C39 820pF Ceramic NOTES:

C38 820pF Ceramic
R90 620R 1% ¼W
1. GROUND CONNECTIONS MARKED
R89 2K 1% ¼W
R88 3K 1% ¼W IC14 MCP6022 Dual Op-Amp “ANALOG” SHOULD BE PLACED ON A
R87 620R 1% ¼W IC14 MCP6022 Dual Op-Amp SEPARATE PLANE AND LINKED TO
R86 2K 1% ¼W IC13 MCP6022 Dual Op-Amp DIGITAL\GENERAL GROUND IN ONE
R85 3K 1% ¼W IC12 MCP6S91 SPI PGA POINT ONLY.
R84 430R 1% ¼W IC11 MCP6S91 SPI PGA
R83 2K 1% ¼W C49 680pF Ceramic
R82 430R 1% ¼W C48 680pF Ceramic
R81 2K 1% ¼W C47 680pF Ceramic
R80 1.3K 1% ¼W C46 680pF Ceramic
R79 13K 1% ¼W C45 12nF MKT
R78 1.3K 1% ¼W C44 12nF MKT
R77 13K 1% ¼W C43 1.5nF MKT
R76 680R 1% ¼W C42 1.5nF MKT
R75 200R 1% ¼W C41 680pF Ceramic
R74 6.8K 1% ¼W C40 680pF Ceramic
R73 680R 1% ¼W
2007 Microchip \ Circuit Cellar Design Contest REGISTRATION NO:
R72 200R 1% ¼W
R71 6.8K 1% ¼W dsPIC LCR METER MT1769
R70 10K 1% ¼W
R69 20K 1% ¼W o
REV N : DATE: PAGE DESCRIPTION: SIZE: PAGE:
R68 20K 1% ¼W
R67 10K 1% ¼W 0 06/10/07 ANALOG STAGE (2/2) A4 4/5
SYMBOL DESCRIPTION

Page 24 of 25
 Registration Number: MT1769

+5v -5v

C52
1μF
VR2

TPS60403

C51
1μF
+

C50
1μF

-5v +2.4v

330Ω 1%

R91

10KΩ 1%

R92
D4
2.4 V

+5v +2.4v

330Ω 1%

R93
C53
+
1μF

10KΩ 1%

R94
D5
2.4 V

+5v

IC16
VREF_V
+5v
+2.5v Reference VREF_A
-
+ - +2.5v Reference
+
MCP6022
VR3

MCP1525
+

C54
1μF

C55
1μF

IC16 MCP6022 Dual Op-Amp

VR3 MCP1525 Precision 2.5V Reference
VR2 TPS60403 60mA -5V Charge Pump
D5 2.4V Zener
D4 2.4V Zener
C55 1µF Tantalum
C54 1µF Tantalum
C53 1µF Tantalum
C52 1µF Tantalum
2007 Microchip \ Circuit Cellar Design Contest REGISTRATION NO:
C51 1µF Tantalum
C50 1µF Tantalum dsPIC LCR METER MT1769
R94 10K 1% ¼W
R93 330R 1% ¼W o
REV N : DATE: PAGE DESCRIPTION: SIZE: PAGE:
R92 10K 1% ¼W
R91 330R 1% ¼W 0 06/10/07 POWER CONDITIONING A4 5/5
SYMBOL DESCRIPTION

Page 25 of 25