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SNNIM A 10T-SRAM Based Spiking-Neural-Network-In-Memory Architecture With Capacitance Computation
SNNIM A 10T-SRAM Based Spiking-Neural-Network-In-Memory Architecture With Capacitance Computation
SNNIM A 10T-SRAM Based Spiking-Neural-Network-In-Memory Architecture With Capacitance Computation
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(b) Vref Gen. SRAM I/O Interface (c) VP VN SYBIA(10T) Group#0
t for spike SWL[0] SWL[0]
SWL[0] ... ... WL[0] S WL[0]
W
W/R Excitatory-Path L
WL[0] ... ... C 6T 6T 6T 6T 6T
Inhibitory-Path SWL[1] SWL[1]
Bias-Array WL[1] S
W
WL[1]
Core Ctrl L
...
...
SNNIM SNNIM SNNIM C 6T 6T 6T 6T 6T
&
#Group0 #Group1 #GroupX
WLs
...
...
...
...
...
/R
Driver ... ...
RWL[15] SWL[128] SWL[128]
W/R WL[128] S WL[128]
W
WWL[15] ... ... L
C 6T 6T 6T 6T 6T
SWL[129] SWL[129]
WL[129] S WL[129]
W
...
...
...
...
...
SRAM I/O Interface
(a) RBL_s[3] RBL_s[2] RBL_s[1] RBL_s[0]
8C 4C 3C 2C 1C
Vmem
Comp.
CCA
Group#0 1C 3C 2C 4C 8C
Vmth
8T 8T 8T 8T
Postsynaptic Neuron[j] RWL[1] RWL[1]
WWL[1] WWL[1]
Axon[j] Timing
8T 8T 8T 8T &
Soma
Spike-Output
...
...
...
...
RWL[15]
Ctrl RWL[15]
Presynaptic
WWL[15] #Group0 WWL[15]
Neuron[i] 8T 8T 8T 8T
SMTA(8T) Group#0
Postsynaptic Neuron[j+1]
...
Fig.1 (a) Abstract representation of information interaction between neurons in biology. (b) The Overall structure of the proposed SNNIM macro and
(c) partial detail description for the group0 of SNNIM macro.
control and input driver, reference voltage generator (Vref SRAM in SYBIA is used as a bias array to provide bias
Gen.), SRAM I/O interfaces and spike output mapping value for SNN operations (see Section III). For the 16×4b
control. In this design, a SNNIM macro integrates X 8T-SRAM of SMTA, the original membrane potential
SNNIM groups (X=16). All SNNIM groups in a SNNIM (Vmem0 [3:0]) and the corresponding threshold values
macro share a set of WL drivers and logic control modules. (Vmth0 [3:0]) are stored here.
When a spike-event occurs on SWLs, these SNNIM The CCA is an array of capacitors arranged in a specific
groups work in parallel. The input spikes are preprocessed way to integrate the output of the SYBIA and the SMTA
by Core Ctrl module and the pulse-width on these Word- by RBL_s [3:0] and RBL_m [3:0] respectively. There is
Lines are different. The SWLs transmit the customized only one CCA in each SNNIM group. These configured
spikes among these SYBIA of SNNIM groups, and the neurons share the CCA in one SNNIM group and realize
pulse on RWLs controls the read operation for developing the computing properties of SNN as the generalized
Vmem and Vmth on CCA from SMTA. The assertion of integrated-and-fire (G.I&F) model does.
WLs and WWLs is used to write and read data for 10T-
SRAM and 8T-SRAM respectively when SNNIM macro III. CIRCUIT TECHNIQUES EMPLOYED IN THE
works in SRAM mode. Due to the two types of SRAM
PROPOSED SNNIM
array (10T and 8T) existing in the SNNIM macro, there are
two SRAM I/O interfaces. The Vref Gen module generates A. SYBIA Circuit
the reference voltage named VN and VP that will be used
for clamping in SWLC circuit. The Spike Output Mapping Each row in SYBIA is a synaptic branch which is
Ctrl module can deliver the output spikes from one SNNIM capable of being an excitatory synapse or an inhibitory
group to the next SNNIM macro and can also send them synapse. This attribute of synaptic branch can be controlled
back to the local Core Ctrl module as the new input spikes. by its head-cell consisting of the leftmost SRAM cell (6T-
As shown in Fig. 1(c), each SNNIM group is a small SRAM) with the SWLC module (see Fig.2). If the head-
CIM bank composed of SYBIA that based 136×5b 10T- cell stores low on the node of QS (QS=0) and there is a
SRAM, SMTA that based 16×4b 8T-SRAM and CCA. The spike-event occurrence on the SWL, this synaptic branch
128×5b SRAM in SYBIA acts as the synaptic array, and will behave as an excitatory synapse and convert the SWL
each row is a configurable synaptic branch, which is to SWL_c by clamping its low voltage to VP while SWL_d
composed of 4b 10T-SRAM for synaptic weight and 1b keeps GND. Otherwise (QS=1) the synaptic branch will
SRAM with SWL-converter (SWLC) module for sign-bit behave as an inhibitory synapse and convert the SWL to
processing. If the synaptic array receives a spike-event XI SWL_d by clamping its high voltage to VN while SWL_c
(XI is a set of spikes) and N synaptic branches are activated, keeps VDD. The VP and VN are generated from a biasing
the MAC operation of ∑𝑁 𝐼 𝑖
𝑛=1 ∑𝑖=1 𝑋𝑛 × 𝑊𝑛 [4: 0] will be
circuit in Vref Gen. Therefore, the current (|𝐼𝑐 |) flowing
done between SYBIA and CCA. The remaining 8×5b 10T- through PMOS with VP as its gate voltage will be equal to
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VN VDD
SWL_c
SWL_d
QS QS_B WL
SWL_d SWL_c
discharge
Repolar_Rst MN0 MP0
charge
MN1 MP1
VP Q QB
a single spike on SWL tswl for spike
RBL_s BL BLB
QS=1 Head-cells
SWL
VP VN
Repolar_Rst
SWL[0] S
SWL_c = 1 SWL_c[0]
WL[0] W
VN Working as a L
Excitatory synapse 6T 6T 6T 6T 6T
SWL_d C
QS=0
SWL[1] S SWL_d[1]
QS=0 SWL WL[1] W
Working as a L
Repolar_Rst Inhibitory synapse 6T 6T 6T 6T 6T
C
QS=1
SWL_c
RBL_s[3] RBL_s[2] RBL_s[1] RBL_s[0]
...
...
...
...
...
VP
SWL_d = 0
Fig.2 10T-SRAM bit-cell for SYBIA and the SWLC module with its operation waveform.
(a) Phase (a): Read the Vmem0 (c) Phase (c): Synaptic injection (e) Phase (e): charge-sharing for Vmem and Vmth
8C 4C 3C 2C 1C 8C 4C 3C 2C 1C 8C 4C 3C 2C 1C
Vmem
1C 3C 2C 4C 8C 1C 3C 2C 4C 8C 1C 3C 2C 4C 8C
Vmth
RBL_m[0] RBL_m[1] RBL_m[2] RBL_m[3] RBL_m[0] RBL_m[1] RBL_m[2] RBL_m[3] RBL_m[0] RBL_m[1] RBL_m[2] RBL_m[3]
SMTA
SMTA SMTA
SMTA SMTA
SMTA
(b) Phase (b): Charge-sharing to U0 (d) Phase (d): Injection computing and read Vmth (f) Vmem updating and Muti-spikes output
Comparator clk
SYBIA SYBIA
Input spikes
RBL_s[3] RBL_s[2] RBL_s[1] RBL_s[0] RBL_s[3] RBL_s[2] RBL_s[1] RBL_s[0]
(Assume all
8C 4C 3C 2C 1C 8C 4C 3C 2C 1C on excitatory
U0
synapses )
1C 3C 2C 4C 8C 1C 3C 2C 4C 8C
Vmth
RBL_m[0] RBL_m[1] RBL_m[2] RBL_m[3] RBL_m[0] RBL_m[1] RBL_m[2] RBL_m[3] Vmem
SMTA
SMTA SMTA
SMTA Output spikes
time
Fig.3 The CIM methods in CCA for SNN computing about five phases (a) - (e) and (f) an example for Vmem updating and multi-spikes (MS) output.
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Table I. Comparison table with previous SNN works
TrueNorth[1] Loihi[2] Tianjic[3] ROLLS[4] IMPULSE[5] This work
CCA&SMTA Technology node 28nm 14nm 28nm 180nm 65nm 28nm
SYBIA
Timing &Ctrl CIM CIM
Neuron type Digital Digital Digital Analog
Comparator 29.40% (Digital) (Mix-signal)
Vref Gen
44.15% Basal neuron model G.I&F G.I&F I&F+ANN G.I&F G.I&F G.I&F
Data width 9W-1S 9W-1S 8w-8A/1S N.A. 6W-1S 5W-1S/MS
Area(um2)/Neuron 4.3e6 457.88 360 2.008e5 4.02e3 100.6-201.25
Energy Efficiency
0.4[9] N.A. 0.649 N.A. N.A. 25.18
Fig4. Energy breakdown of the proposed SNNIM group. (TSyOPS/W)
in phase (b) as shown in Fig. 3(b), the charge-sharing will group with one input spike in SNN mode. Owing to the
happen and the 𝑈0 can be expressed as follow: compact design of synaptic and soma array, within the five
3 +4∗𝛿 2 +2∗𝛿 1 +1∗𝛿 0
8∗𝛿𝑚
𝑘 =1
𝑉𝐷𝐷, 𝑄𝑚 phases for SNN computing, the energy of SYBIAs for all
𝑘 = 0 (1)
𝑚 𝑚 𝑚 𝑘 = 𝛿(𝑄 𝑘 ) {
𝑈0 = , 𝛿𝑚 𝑚 groups in SNNIM macro with a spike-event (16*16
36 0, 𝑄𝑚
𝑘
synapses will activate by the single spike) was 0.349 pJ.
𝑄𝑚 is the stored value in 8T-SRAM cell corresponding Due to the sharing of CCA in one SNNIM group, the
to the Vmem0 [k] (k=0,1,2,3). After the charge-sharing, power of initialization and reset for membrane potential
each RBL_s becomes independent and holds the voltage of can be reduced by about 25%. Although the Channel-
𝑈0 as shown in Fig .3(c). In phase (c), the N synaptic Length-Modulation (CLM) for MN0 and MP0 may disturb
branches are activated and the ∆𝑘 will be integrated with the computational linearity of synaptic injection which can
𝑈0 on RBL_s [k]. Now, the accumulated electric charge be observed in Fig. 3(f), this can be greatly improved by
on RBL_s [k] can be expressed as 𝐸0𝑘 : setting the Vmth below the nonlinear interval with the
𝐸0𝑘 = ∆𝑘 + 𝑈0 ∗ 9𝐶0 employment of proposed SMTA bias circuits.
In phase (d), the top set of caps disconnect from the Table I presented the comparison between SNNIM with
bottom caps and accomplish the computing of input existing SNN based works [1-5]. Compared with digital
synaptic injection. Meanwhile, the bottom set of caps type neuron design [3], 38× better energy efficiency can
develop the Vmth0 as phase (a) does. The accumulated achieve owing to the SNNIM structure. Compared with
electric charge on RBL_s [k] is changed as 𝐸1𝑘 : pure analog type neuron design [4], this work
2𝑘 (201.25um2/neuron) can achieve over 997 times better
𝐸1𝑘 = ∗ (∆𝑘 + 𝑈0 ∗ 9𝐶0 )
9 neuron density. The benefits mainly arise from the
In the last phase (e) as shown in Fig. 3(e), the charge- proposed SYBIA and the employment of 10T-SRAM cells,
sharing happens synchronously on the two sets of caps, and which can enable larger data parallelism. By a low-cost
the final Vmem and Vmth can be determined: transition from ANN (only one hidden layer) to SNNIM
structure in simulation, the SNN can achieve an accuracy
1 8∗∆3 4∗∆2 2∗∆1 1∗∆0
𝑉𝑚𝑒𝑚 =
15
∗ ( 9𝐶0
+ 9𝐶0
+ 9𝐶0
+ 9𝐶0
)+𝑈0 (2) of 95.83% on MNIST without on-line training.
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ACKNOWLEDEMENTS
This work was supported in part by the National
Natural Science Foundation of China under Grant
61834002.
REFERENCES
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