10/11/2023

Prototypage des Systèmes Mécatronique

Nexys3 Board : Applications

Pr. A. AIT MADI

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OUTLINE
 Goal
 What is FPGA ?
 Domain applications of FPGAs
 Leading manufacturers of FPGAs
 FPGA XILINX Spartan 6
 Nexys3 Board
 FPGA Design Flow
 Creating a new project
 Adding a new VHDL source
 XST Synthesis
 Functional simulation with Isim
 RTL Schematic (Register Transfert Level)
 Assigning PINS FPGA -File UCF
 Implementation of the project
 Creating the configuration file with Adept
 FPGA programming : JTAG Mode

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Goal
We want to program the decoder in the FPGA using Nexys3 Board

SW[0:2] Led[0:7]
0 1 2 0 1 2 3 4 5 6 7
led(0) 0 0 0 1 0 0 0 0 0 0 0
led(1) 0 0 1 0 1 0 0 0 0 0 0
Sw(0)
led(2)
0 1 0 0 0 1 0 0 0 0 0
Sw(1) Decoder led(3)
38 led(4) 0 1 1 0 0 0 1 0 0 0 0
Sw(2) led(5) 1 0 0 0 0 0 0 1 0 0 0
led(6)
led(7) 1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Decoder True Table

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Goal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder is
Port
(
sw : in STD_LOGIC_VECTOR (2 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin VHDL Code
led <= "00000001" when sw="000" else
"00000010" when sw="001" else
"00000100" when sw="010" else
"00001000" when sw="011" else
"00010000" when sw="100" else
"00100000" when sw="101" else
"01000000" when sw="110" else
"10000000";
end Behavioral;

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Goal

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY decoder_tb IS
END decoder_tb;

ARCHITECTURE behavior OF decoder_tb IS

signal sw : std_logic_vector(2 downto 0) := (others => '0');

signal led : std_logic_vector(7 downto 0); TestBench
COMPONENT Decoder
PORT(
sw : IN std_logic_vector(2 downto 0);
led : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;

BEGIN
uut: Decoder PORT MAP (sw => sw, led => led);

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Goal

stim_proc: process

begin

sw <="000"; wait for 50 ns;

sw <="001"; wait for 50 ns;
sw <="010"; wait for 50 ns;
sw <="011"; wait for 50 ns;
TestBench
sw <="100"; wait for 50 ns;
sw <="101"; wait for 50 ns;
sw <="110"; wait for 50 ns;
sw <="111"; wait for 50 ns;

end process;

END;

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What is FPGA ?

FPGA

Field Programmable Gate Array

These are semi-conductor devices electrically programmable only once

(fuses) or repeatedly (reconfigurable)

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What is FPGA ?

Matériel Logiciel

circuits personnalisés circuits existants

microprocesseurs
processeurs DSPs
circuits mémoires
ASICs logiques périphériques
programmables
FPGA
EPLD

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What is FPGA ?

programmation Entrées / Sorties

ou configuration
Plan de programmation :
interconnexion

Entrées / Sorties Entrées / Sorties

Plan actif : cellules logiques

Entrées/Sorties
technologies architectures du plan actif :
de programmation : - PAL hiérarchique (EPLD)
- EEPROM - gate-array (FPGA)
- SRAM - mixtes (CPLD ALTERAs)
- antifusible

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What is FPGA ?
I/O Blocks

Each CLB can be configured to

perform complex combinational
and sequential functions

Multiplexer

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What is FPGA ?

ASIC Placement
spec Code+synth fab
Routage

FPGA
P
spec Code+synth Time to market
R

mP

+
spec Code
temps
logiciel

Temps de conception

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What is FPGA ?

fréquence 80 Matériel : traitement parallèle

de traitement
70

60

F clock 50

40

30
Logiciel : traitement séquentiel

20
fclock
10
f=
nb op/cycle

1 2 3 4 8 12 16 20 24 28 32 36 40 44 48 52

Nb opérations/cycle

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Domain applications of FPGA

Medical

Automotive
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Leading manufacturers of FPGAs

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FPGA XILINX Spartan 6

Xilinx headquarters in the United States

Industry Integrated Circuits

Founded 1984
Jim Barnett
Founder Ross Freeman
Bernie Vonderschmitt
Headquarters San Jose, California, U.S

Products FPGAs, CPLDs

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FPGA XILINX Spartan 6

 The Spartan-6 was marketed in 2009 as a low-cost family solution for

automotive, wireless communications, flat-panel display and video
surveillance applications

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FPGA XILINX Spartan 6

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FPGA XILINX Spartan 6

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FPGA XILINX Spartan 6

Each column of CLBs contain two slice

columns. One column is a SLICEX column, the
other column alternates between SLICEL and
SLICEMs

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FPGA XILINX Spartan 6

 The SLICEMs contain the carry structure and multiplexers, and add
the ability to use the LUTs as 64-bit distributed RAM and as variable-length shift registers
(maximum 32-bit)
A1
A2
A3
A4 LUT =
A5
A6

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FPGA XILINX Spartan 6

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FPGA XILINX Spartan 6

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FPGA XILINX Spartan 6

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Nexys3 Board

Here We want to discover Nexys 3 Board-FPGA XILINX Spartan 6

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Nexys3 Board

Spartan 6
XC6SLX16-3 CSG324

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Features

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Features
 Xilinx Spartan 6 XC6SLX16-3 CSG324

 16Mbyte Micron Cellular RAM

 16Mbyte Micron Parallel PCM

 16Mbyte Micron Quad-mode SPI PCM

 10/100 SMSC LAN8710 PHY

 Digilent Adept USB port for power, programming & data transfers

 USB-UART

 Type-A USB host for mouse, keyboard or memory stick

 8-bit VGA

 100MHz fixed-frequency oscillator

 8 slide switches, 5 push buttons, 4-digit 7seg display, 8 LEDs

 Four double-wide Pmod connectors, one VHDC connector

 Rugged plastic case, USB cable included

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Power Supplies
 The main regulator on the Nexys3 can accommodate input voltages up to 5.5VDC

 Voltage regulator circuits from Linear Technology create the required 3.3V, 2.5V, 1 .8V, and 1.2V
supplies from the main power input

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Configuration sources
 The Spartan-6 FPGA board must be configured (or programmed) in one of four ways By :

• PC using the Adept "USB Prog“ port

• File stored in the non-volatile parallel PCM device

• File stored in the non-volatile serial (SPI) PCM device

• Programming file transferred from a USB memory stick attached to the USB HID port

JTAG Mode can be

accessed at any time
without changing
jumpers

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FPGA Design Flow

Requirements

RTL Model Simulate

Synthesize

Gate-level
Model Simulate Test Bench

ASIC or FPGA Place & Route

programming

Timing
Model Simulate

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FPGA Design Flow

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Creating a new project

We must Create a new project Named decoder

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Creating a new project

 Start Xilinx ISE Design Suite
 Select File => New Project or click on New Project

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Creating a new project

 Enter “Decoder" for the project name (select an appropriate location)

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Creating a new project

 Click Next

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Creating a new project

 Enter the following values in New Project Wizard- Project Settings

• Product Category: All

• Family: Spartan6

• Device: XC6SLX16

• Package: CSG324

• Speed: -3

• Synthesis Tool: XST (VHDL/Verilog)

• Simulator: Isim (VHDL/Verilog)

• Preferred Language: VHDL

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Creating a new project

 Click Next

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Creating a new project

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Creating a new project

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Adding a new VHDL source

Now we want to create a new source VHDL in the decoder Project

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Adding a new VHDL source

 Right Click on decoder Project and select New Source

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Adding a new VHDL source

 Select VHDL Module and enter decoder as File name

 Click Next

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Adding a new VHDL source

 Add sw and led port names, select direction, and bus size

 Click Next

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Adding a new VHDL source

 Click Finish

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Adding a new VHDL source

 A skeleton of your decoder VHDL source file is open for editing

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Adding a new VHDL source

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Adding a new VHDL source

 Add VHDL statements to describe the operation of the 3 to 8 decoder

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XST Synthesis

Now we want to Synthesize a in order to verify design and

create Xilinx-specific netlist file known as NGC file

XST : Xilinx Synthesis Technology

NGC : is a translation of the VHDL design file into gates optimized for the
target architecture

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XST Synthesis

 In the Processes window–double-click on Synthesize XST to verify your design. If

successful you should see a green check mark next to the Synthesize operation

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XST Synthesis

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Functional simulation with Isim

The testing or simulation is done with testbench files

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Functional simulation with Isim

 Create a testbench file
• Right click on the project name decoder
• Click on New source

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Functional simulation with Isim

 Enter decoder_tb for the file name
 Select VHDL Test Bench
 Click Next

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Functional simulation with Isim

 This testbench has been automatically generated

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Functional simulation with Isim

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Functional simulation with Isim

 Simulation :
• Click the Simulation View

• Select the decoder_tb.vhd file. The Isim Simulator displays in the Processes window

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Functional simulation with Isim

 Expand the ISim Simulator if it is not already expanded by clicking the plus sign

 Double click the Simulate Behavioral Model option under the ISim Simulator

 The simulator will start. Once the simulation is complete the ISim application window
will open

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Functional simulation with Isim

 click on the Zoom to Full View icon, then click Zoom In to better view the simulation

Signals and Waveform

Bus List

Wave Window

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RTL Schematic (Register Transfert Level)

The View RTL Schematic tool is an excellent product for visualizing the circuit
that the Hardware Description Language (VHDL) creates

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RTL Schematic (Register Transfert Level)

 Switch to the Implementation view
 Select the decoder– behavioral (decoder.vhd) file in the Design Window
 Expand the Synthesize –XST process in the Processes Window
 Double click the View RTL Schematic option

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RTL Schematic (Register Transfert Level)

The schematic displays in the

workspace. This first image
shows how the overall inputs
(left) and outputs (right) are
developed

Double click the

decoder box in the
workspace. The circuit
will expand to the next
level (result in the
following slide)

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RTL Schematic (Register Transfert Level)

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Assigning PINS FPGA -File UCF

We now need to assign FPGA pins to the switches and leds so they will
be connected to the correct ports on the board. This is done by creating
a UCF file (User Constraints File)

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Assigning PINS FPGA -File UCF

 Expand the User Constraints process in the Processes window and double-click on the
I/O Pin Planning (Plan Ahead) - Post Synthesis.

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Assigning PINS FPGA -File UCF

 Plan Ahead will start and alert you to create a UCF file

 Select Yes

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Assigning PINS FPGA -File UCF

 PlanAhead will now run, eventually a window will open

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Assigning PINS FPGA -File UCF

 Select the I/O ports tab and then expand the led and sw ports

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Assigning PINS FPGA -File UCF

 Select led[0] in the I/O ports window and drag to the package pin location U16
 The Site box in the I/O Port Properties window should be updated (instead of dragging,
you can also type the site location directly)

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Assigning PINS FPGA -File UCF

 With reference to the Nexys3 Reference Manual complete the pin information for the
rest of the led and sw ports
OUTPUTS

led(0)=U16
led(1)=V16
led(2)=U15
led(3)=V15
led(4)=M11
led(5)=N11
led(6)=R11
led(7)=T11

INPUTS

sw(0)=T10
sw(1)=T9
sw(2)=V9

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Assigning PINS FPGA -File UCF

 Select File => Save constraints and exit PlanAhead
 In the ISE Project Navigator Design - Hierarchy window expand the decoder and you
should see the new decoder.ucf file is now added
 To view the UCF file, select the decoder.ucf and then select Edit Constraints (Text)
in the Processes window and the decoder.ucf file will open
You can also just create and edit this
UCF file using a text editor (like
Notepad or wordpad

# PlanAhead Generated physical constraints

NET "led[0]" LOC = U16;

NET "led[1]" LOC = V16;
NET "led[2]" LOC = U15;
NET "led[3]" LOC = V15;
NET "led[4]" LOC = M11;
NET "led[5]" LOC = N11;
NET "led[6]" LOC = R11;
NET "led[7]" LOC = T11;
NET "sw[0]" LOC = T10;
NET "sw[1]" LOC = T9;
NET "sw[2]" LOC = V9;

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Implementation of the project

 The implementation of the project is carried out in three phases

• Translation : merges all of the input netlists and design constraints and create a
Xilinx Native Generic Database (NGD) file

• Mapping : maps the logic defined by an NGD file into FPGA elements and create The
Native Circuit Description (NCD) file

• Placement & Routing : takes a mapped NCD file, places and routes the design, and
produces an NCD file that is used as input for bitstream generation

 ISE Design suite call automatically the appropriate integrated tool for
successively perform each step

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Implementation of the project

 Select Decoder-Bahavioral (Decoder.vhd) in Design Window

If successful you should see a

 Double click on implement Design in process window green check mark next to the
Synthesize operation

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Implementation of the project

We now need to consult the implementation report

Click on the icon Design Summary report

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Implementation of the project

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Implementation of the project

For example the decoder device utilization summary is

Number of Slices LUTS : 1%

Number of used as logic : 1%
Number of occupied Slices : 1%
Number of bonded IOBs: 4%

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Creating the configuration file with Adept

Here we want to generate a programming file with

extension .bit useful to program FPGA

 We need to specify the FPGA Startup Clock. It set to :

• JTAG (Joint Test Action Group) Clock when we load the FPGA through the USB
connector using the Adept Programming Software (recommended here)
• CCLK (Configuration Clock) when we generating configuration file that will be
stored on a a PROM (FLASH)

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Creating the configuration file with Adept

 Right-click on the Generate Programming File in the Processes window and then
select Process Properties

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Creating the configuration file with Adept

 Select Startup Options
 Select Advanced in Property display level
 Select JTAG Clock for FPGA Startup Clock then Click OK

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Creating the configuration file with Adept

 Back in the design window select the decoder-Behavioral (decoder.vhd)

 Double-click on the Generate Programming File in processes window

 If successful you should see a green check mark next to the Generate Programming
File operation

Result : Generation of bit file named decoder.bit

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FPGA programming : JTAG Mode

Here we want to transfer .bin or . svf file ( using decoder. Bit) , to the FPGA
device , through the USB cable using the Digilent Adept software

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FPGA programming : JTAG Mode

 Connect your Nexys3 board to a USB connector on the PC

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FPGA programming : JTAG Mode

 Open Digilent Adept by selecting Start All Programs Digilent Adept Adept

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FPGA programming : JTAG Mode

 Choose Nexys3 from the
Connect Product drop 1
down menu

 Click the Browse button.

The Open dialog box
displays
3 2 4
 Navigate to the folder of
the decoder project and
select the decoder. Bit file
 Click the Open button. The
file is displayed in the
dropdown list next to the
FPGA icon

 Click the Program button.

The bit file, decoder. Bit, is 5
programmed to the FPGA
board
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Problème
 Pour la version du système d’exploitation
64 bits , il fallait procéder comme suit pour
lancer la simulation à base du logiciel Isim:
 Ouvrir le logiciel ISE14.3 à partir du
chemin suivant :
C:\xilinx\14,3\ise_ds\ise\bin\nt64\

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