Fpga Based System Design Lab Lab 7, 8 & 9 Task

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FPGA BASED SYSTEM DESIGN LAB

LAB 7 ,8 & 9 TASK

LAB 7:
1. Write the Verilog Code for 8 bit ALU which can perform the following operations on the
inputs.
• Shift Left
• Shift Right
• Greater than
• Less than
• Negation
• Concatenation
• Modulus
• Logical Equality

Code:
module aluu(opcode, operand1, operand2, result1, result2, flagc, flagz);
input [2:0] opcode;
input [7:0] operand1, operand2; output
reg [7:0] result1;
output reg [7:0] result2;
output reg flagc;
output reg flagz;
parameter [2:0] RSHIFT =3'b000;
parameter [2:0] LSHIFT =3'b001;
parameter [2:0] GREATER =3'b010;
parameter [2:0] LESS =3'b011;
parameter [2:0] NEGATE =3'b100;
parameter [2:0] CONC =3'b101;
parameter [2:0] MODULUS =3'b110;
parameter [2:0] LEQUALITY
=3'b111;
always @ (opcode or operand1 or operand2)
begin
result1=8'b0;
result2=8'b0;
flagc=1'b0;
flagz=1'b0;
case(opcode)
RSHIFT: begin
result1=operand1<<1;
result2=operand2<<1;
flagz=(result1==8'b0);
end
LSHIFT: begin
result1=operand1>>1;
result2=operand2>>1;
flagz=(result1==8'b0);
end
GREATER: begin
if(operand1>operand2)
begin result1=8'b1; result2=8'b1; end else
begin result1=8'b0; result2=8'b0; end
flagz=(result1==8'b0);

end
LESS: begin
if(operand1<operand2)
begin result1=8'b1; result2=8'b1; end else
begin result1=8'b0; result2=8'b0; end
flagz=(result1==8'b0);
end
NEGATE: begin
result1=!operand1;
result2=!operand2;
flagz=(result1==8'b0);
end
CONC: begin
result1={operand1,operand2};
result2=8'b0;
flagz=(result1==8'b0);
end
MODULUS: begin
result1 = operand1 & (operand2 - 1);
result2=8'b0;
flagz=(result1==8'b0);
end
LEQUALITY: begin
if(operand1==operand2)
begin result1=8'b1; result2=8'b1; end else
begin result1=8'b0; result2=8'b0; end
flagz=(result1==8'b0);
end
endcase
end
endmodule
Test Bench:

Timing Diagram:
LAB 8:
1. Design the JK Flipflop through Behavioral Modelling in Verilog. The function table of JK
Flipflop is as Table Ex. 1. Verify the functionality through Test Bench / Timing Diagram.

TABLE EX. 1: TRUTH TABLE OF JK FLIPFLOP

Q _ Bar
Clock J K Q

↑ 0 0 No Change

1
↑ 0 1 0

0
↑ 1 0 1

↑ 1 1 Toggling

Code:
Test Bench:

Timing Diagram:
2. Design Down Counter through Behavioral Modeling in Verilog. Verify functionality
through Test Bench / Timing Diagram.

Code:

Test Bench:
Timing Diagram:
LAB 9:
Write Verilog code to determine sequence of 1011 using Mealy and Moore Finite State
Machines.
Code:
module MealyFSM (input clk, input reset, input wire in, output reg out);
reg [1:0] state, nextstate;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @(posedge clk or posedge reset)
if (reset)
state <= S0;
else
state <= nextstate;
always @(state or in)
case(state)
S0: begin
if (in) begin
out <= 0;
nextstate <= S1;
end else begin
out <= 0;
nextstate <= S0;
end
end
S1: begin
if (in) begin
out <= 0;
nextstate <= S2;
end else begin
out <= 0;
nextstate <= S0;
end
end
S2: begin
if (in) begin
out <= 1;
nextstate <= S3;
end else begin
out <= 0;
nextstate <= S0;
end
end
S3: begin
if (in) begin
out <= 0;
nextstate <= S0;
end else begin
out <= 0;
nextstate <= S0;
end
end
default: nextstate <= S0;
endcase
endmodule
Test Bench:

Timing Diagram:
Code:
module Moorebased(input clk, input reset, input in, output reg out);
reg [1:0] state, nextstate;
parameter S0=0, S1=1,S2=2, S3=3;
always @(posedge clk or posedge reset)
if(reset)
begin
state<=S0;
end
else
state<=nextstate;
always @(state or in)
begin
case(state)
S0:
begin
out<=0;
if(in)
begin
nextstate<=S1;
end
else
begin
nextstate<=S0;
end
end
S1:
begin
out<=0;
if(in)
begin
nextstate<=S0;
end
else
begin
nextstate<=S2;
end
end
S2:
begin
out<=0;
if(in)
begin
nextstate<=S3;
end
else
begin
nextstate<=S0;
end
end
S3:
begin
out<=1;
if(in)
begin
nextstate<=S0;
end
else
begin
nextstate<=S0;
end
end
default:
nextstate<=S0;
endcase
end
endmodule
Test Bench:

Timing Diagram:

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