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Lab 5and 6
Lab 5and 6
TEST BENCH:
TIMING DIAGRAM:
CODE: 1-to-8 Line DE-MUX
TEST BENCH:
TIMING DIAGRAM:
2. Write the Verilog Code (Behavioral Modelling) for 16-to-1 Line MUX and Verilog Code (Using
Conditional Operator) 1-to-16 Line DeMUX. Verify their functionality through Test Bench /
Timing Diagram.
TESH BENCH:
TIMING DIAGRAM:
CODE: 1-to-16 Line DE-MUX
TESH BENCH:
TIMING DIAGRAM:
3. Write the Verilog Code for 64-to-1 Line MUX by using 8-to-1 MUX. Verify their functionality
through Test Bench / Timing Diagram.
CODE:
TESTBENCH:
TIMING DIARGAM:
LAB 6:
1. Write the Verilog Code (Behavioral Modelling) for 16 into 4 Line Encoder. Verify their
functionality through Test Bench / Timing Diagram.
TRUTHTABLE:
CODE:
module encoder(d,Q);
input [15:0]d;
output reg [3:0]Q;
always @(d)
begin
if(d[15]==1) Q=4'b1111;
else if(d[14]==1) Q=4'b1110;
else if(d[13]==1) Q=4'b1101;
else if(d[12]==1) Q=4'b1100;
else if(d[11]==1) Q=4'b1011;
else if(d[10]==1) Q=4'b1010;
else if(d[9]==1) Q=4'b1001;
else if(d[8]==1) Q=4'b1000;
else if(d[7]==1) Q=4'b0111;
else if(d[6]==1) Q=4'b0110;
else if(d[5]==1) Q=4'b0101;
else if(d[4]==1) Q=4'b0100;
else if(d[3]==1) Q=4'b0011;
else if(d[2]==1) Q=4'b0010;
else if(d[1]==1) Q=4'b0001;
else
Q=4'b0000;
end
endmodule
TESTBENCH:
TIMING DIAGRAM:
2. Write the Verilog Code (Behavioral Modelling) for 4 into 16 Line Encoder. Verify their
functionality through Test Bench / Timing Diagram.
TRUTH TABLE:
CODE:
module DECODER(d0,d1,d2,d3,Q);
input d0,d1,d2,d3;
output reg [15:0]Q;
always @(d0,d1,d2,d3)
begin
if(d3==1'b0 & d2==1'b0 & d1==1'b0 & d0==1'b0 ) Q=16'b0000000000000001;
else if(d3==1'b0 & d2==1'b0 & d1==1'b0 & d0==1'b1 ) Q=16'b0000000000000010;
else if(d3==1'b0 & d2==1'b0 & d1==1'b1 & d0==1'b0 ) Q=16'b0000000000000100;
else if(d3==1'b0 & d2==1'b0 & d1==1'b1 & d0==1'b1 ) Q=16'b0000000000001000;
else if(d3==1'b0 & d2==1'b1 & d1==1'b0 & d0==1'b0 ) Q=16'b0000000000010000;
else if(d3==1'b0 & d2==1'b1 & d1==1'b0 & d0==1'b1 ) Q=16'b0000000000100000;
else if(d3==1'b0 & d2==1'b1 & d1==1'b1 & d0==1'b0 ) Q=16'b0000000001000000;
else if(d3==1'b0 & d2==1'b1 & d1==1'b1 & d0==1'b1 ) Q=16'b0000000010000000;
else if(d3==1'b1 & d2==1'b0 & d1==1'b0 & d0==1'b0 ) Q=16'b0000000100000000;
else if(d3==1'b1 & d2==1'b0 & d1==1'b0 & d0==1'b1 ) Q=16'b0000001000000000;
else if(d3==1'b1 & d2==1'b0 & d1==1'b1 & d0==1'b0 ) Q=16'b0000010000000000;
else if(d3==1'b1 & d2==1'b0 & d1==1'b1 & d0==1'b1 ) Q=16'b0000100000000000;
else if(d3==1'b1 & d2==1'b1 & d1==1'b0 & d0==1'b0 ) Q=16'b0001000000000000;
else if(d3==1'b1 & d2==1'b1 & d1==1'b0 & d0==1'b1 ) Q=16'b0010000000000000;
else if(d3==1'b1 & d2==1'b1 & d1==1'b1 & d0==1'b0 ) Q=16'b0100000000000000;
else if(d3==1'b1 & d2==1'b1 & d1==1'b1 & d0==1'b1 ) Q=16'b1000000000000000;
else Q=16'bxxxxxxxxxxxxxxxx;
end
endmodule
TESTBENCH:
TIMING DIAGRAM:
3. Write the Verilog Code for converting 4 bit gray code to binary code. Verify their
functionality through Test Bench / Timing Diagram.
TRUTH TABLE:
CIRCUIT:
CODE:
module graytobinary( G0,G1,G2,G3,B0,B1,B2,B3);
input G0,G1,G2,G3;
output B0,B1,B2,B3;
TESTBENCH:
TIMING DIAGRAM:
4. Write the Verilog Code for 2 bit magnitude comparator. Verify their functionality through
Test Bench / Timing Diagram.
TRUTH TABLE:
A greater than B:
A=B:
A less than B:
CODE:
module COMPARATOR(input [1:0] A,B, output A_less_B, A_equal_B, A_greater_B);
wire a,b,c,d,e,f,g,h;
// A = B output
xnor (a,A[1],B[1]);
xnor (b,A[0],B[0]);
and u3(A_equal_B,a,b);
TIMING DIAGRAM: