Sradha M

Phone: +91 6238539029, sradhamurali12@gmail.com LinkedIn/sradha Kasargod, Kerala, India - 671314

Educational Qualifications:
Academics Institution University Year CGPA/%
Bachelor of Technology, Electrical College of Engineering Trivandrum, APJ Abdul Kalam Kerala
2019-2023 9.23
and Electronics Engineering Thiruvananthapuram Technological University, Kerala
Relevant Courses:
Microprocessors and Microcontrollers, Digital Electronics, Electronic Circuits, Analog Electronics, Signals and Systems,
B. Tech Analog and Digital Communication Theory, Communication Systems, Electromagnetic Theory, Advanced Control Systems,
Courses Linear Systems and network Analysis, Non-Linear Systems.

“Computer Architecture and Organization”, IIT Kharagpur, Prof. Indranil Sengupta & Prof. Kamalika Das
NPTEL “VLSI Design Flow: RTL to GDS”, IIT Delhi, Prof. Sneh Saurabh
Courses “Digital IC Design”, IIT Madras, Prof. Janakiraman
“Hardware modeling using Verilog”, IIT Kharagpur, Prof. Indranil
Sengupta

Berkeley.edu “Digital Integrated Circuits”, Dr. Jan M. Rabaey

Skills and Tools:

Hardware Modeling, RTL Design and synthesis, Computer Architecture- Pipeline Hazards, Memory hierarchy design, Basics of MIPS32, x86
Architecture, FSM optimization, static timing analysis, verification concepts, RTOS- real-time task/thread scheduling algorithms and resource
sharing, POSIX-RT, Protocols- UART, SPI, I2C, experience in using Vector signal analyzer(VSA), Oscilloscope.
Hardware Languages: Verilog, System Verilog, C Scripting Languages: Tcl, Python Tools: Eagle CAD, Xilinx Vivado, Altera Quartus Prime,
Autodesk Fusion 360, Modelsim, MATLAB, Xilinx Vitis, FreeRTOS, Xilinx SDK, QuestaSim.
Undergraduate Thesis:
➢ Verilog implementation of Level Set Algorithm
❖ The accelerator is implemented based on Zedboard having a Zynq-7000 FPGA chip (100 MHz).
❖ Designed hardware accelerator for image (256 x 256 pixels) segmentation using pipelining, and parallel processing. Used Gaussian & Sobel
Filters for noise reduction, and edge smoothing in the preprocessing stage, and achieved 20x acceleration in 500 iterations to execute Level
Set Algorithm in the iterative stage, Utilized BRAM to store initial contour.
❖ The iteration stage executes the algorithm to the image pixels. An initial contour is set and force function corresponding to image pixels is
formed. The curve is evolved in the first step of the algorithm and then minimized to get the contour output .
➢ FPGA-Based Line Follower Bot
❖ The bot’s brain is powered by Altera Cyclone IV-E FPGA and implemented on a De0-Nano board. Designed a 3-Channel ADC Control module to
communicate with Line sensor connected to each ADC input.
❖ Development board contains an ADC128S022 low power, eight-channel CMOS 12-bit analog-to-digital converter. A 3-channel ADC Control
module which will send channel addresses to on-board ADC128S022 and fetch digital data of analog value present on that corresponding channel
is designed. It will be communicating with the ADC128S022 using the SPI Protocol. Three Line sensors are connected to each ADC input of the
De0-Nano board. An entire map of the arena is loaded in the FPGA. The position of the bot is identified using nodes provided in the arena
❖ Utilized 3-channel IR sensor output to control N20 motors with L9110sMotor driver for proper navigation.
➢ Automatic Component Extractor
❖ Built portable extractor for substrate-like PCB (SLP Board) with ATmega250, controlling a 240V AC heating coil and TB6600 motor
driver to drive 2 stepper motors.
❖ Temperature for separation was determined by the trial-and-error method.
Experiences:
Pre-Doctoral Fellow at Electrical Communication Engineering Department, Indian Institute of Science (IISc) (Sept 2023- Present)
➢ Implementing the control unit for the mixer and synthesizer for a 5G/MMW Gatelink Antenna using Zedboard having a Zynq- 7000 FPGA chip while
conducting experiments to validate the accuracy of the current transceiver setup under Prof. K. J. Vinoy.
Embedded Engineer Intern at Toboids Automata (Mar 2022 - Aug 2022)
➢ Implemented manual routing techniques while designing Arduino Giga Board (4-layer design) using Eagle CAD.
➢ Improved ESP32 WROOM board design with avalanche transient voltage suppression diodes (TVS Diodes) for robust electrostatic discharge ESD
protection, ensuring signal quality integrity, and used manual routing in Eagle CAD for the board layout optimization.
TCS Rapid Labs (Aug 2021 - Oct2021)
➢ Created customizable bedridden patient laptop stand, increasing satisfaction by 20% through user-driven design by cooperating 2 types of joints
-rotary joint and swivel joint.
➢ Partnered with diverse teams to generate interactive humanoid low-fidelity models, facilitating realistic user scenarios, and obtaining valuable
feedback.
Achievements:
➢ Selected to represent India in the Singapore Autonomous Underwater Vehicle Challenge 2022 (SAUVC’22) leveraging expertise in AUV
navigation, visual identification, acoustic localization, and robotic manipulation.
➢ 1st Place in State Robotics Quiz by IEEE Kerala Chapter, 2021.