Functional and Formal

Verification of Digital Designs

Sudeendra kumar K
Department of Electronics and Communication
Engineering

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FUNCTIONAL AND FORMAL
VERIFICATION OF DIGITAL DESIGNS
Concurrent Assertions

Unit-II Session -III

Sudeendra kumar K
Department of Electronics and Communication Engineering
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 Functional and Formal Verification of Digital Designs
Review of Introduction to System Verilog Assertions:

• Immediate Assertions
• Introduction to Concurrent Assertions

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 Functional and Formal Verification of Digital Designs
Contents

• Sampled Value Functions

• Clock and Concurrent Assertions
• Reset and Concurrent Assertions
• Setting clock and reset

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 Functional and Formal Verification of Digital Designs
Samples Value Functions

• SVA also a set of sampled value functions, built-in

functions that operate on sampled values in the same
way as concurrent assertions.
• For example, suppose we want to make sure that
whenever there is no grant, there was no request on the
previous cycle.

• Both the req and gnt values are sampled just before the
positive edge of clk, and the $past function examines
the value of its argument one cycle earlier.

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Courtesy: - Erik Seligman Formal Verification
Functional and Formal Verification of Digital Designs
List of Sampled Value Functions

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Courtesy: - Erik Seligman, Formal Verification
Functional and Formal Verification of Digital Designs
Sampled Value Functions

• According to the LRM, a transition from X to 1 counts as a

rise for $rose, and from X to 0 counts as a fall for $fell.

• The design/validation environment do not want

transitions from X/Z to count as a rise or fall, you should
probably be using sequence notation, rather than these
shorthand functions.

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 Functional and Formal Verification of Digital Designs
Concurrent Assertions and clock edges
• clock is expressed with a clock specifier such as @(posedge
clk1). A common mistake is to omit an edge and use an
expression like @(clk1): this makes an assertion act on
positive and negative clock edges, effectively examining each
phase rather than each cycle.

• For a latch-based design, this may sometimes be the true

user intent, but more commonly, a posedge is really needed.

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 Functional and Formal Verification of Digital Designs
Sampling behavior with different clocks

• check_posedge: assert property (@(posedge clk1) !sig1);

• check_anyedge: assert property (@(clk1) !sig1);

• check_posedge4: assert property (@(posedge clk4) !sig1);

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Functional and Formal Verification of Digital Designs
Sampling Behaviour with different Clocks

• At phase 4, the check_posedge and check_anyedge

assertions have detected the zero value of sig1, but the
check_posedge4 assertion has not, since we do not yet
have a positive edge of clk4.
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Functional and Formal Verification of Digital Designs
Sampling Behaviour with different Clocks

• At phase 7, the check_anyedge assertion has

detected the one-phase glitch of sig1, but neither
of the other two detects it, since this pulse does
not persist until any positive clock edge.
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 Functional and Formal Verification of Digital Designs
Sampling Behaviour with different Clocks

• At phase 14, we see that all three assertions are passing,

since sig1 had a value of 0 before positive edges of both
clocks.
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Courtesy: System Verilog Assertions, Erik Seligman
 Functional and Formal Verification of Digital Designs
Reset and Concurrent Assertions
• In addition to clocks, concurrent assertions also allow you
to specify reset conditions using disable iff.

• The main goal here is to shut off assertion checking during

reset: on most modern designs, you can expect some level
of arbitrary “garbage” values in your design at reset, and
you probably do not want to deal with the noise of invalid
assertion failures due to these arbitrary values.

• So an assertion is considered to be trivially passing

whenever its disable condition is true.

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Courtesy: Formal Verification, Erik Seligman
Functional and Formal Verification of Digital Designs
Reset and Concurrent Assertions
• Assertion reset is asynchronous, with an assertion being
shut off immediately any time its disable condition is met.
• For example, consider the following two assertions, both
trying to state that outside of reset, if you have at least
one grant, you should have a request:

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 Functional and Formal Verification of Digital Designs
Setting default Clock and Reset
• Fortunately, SVA offers a way to set a global clock and reset
for the concurrent assertions in a module, so they can be
written once and cover multiple assertions.

• We declare a default clock with a default clocking statement

and a default reset with a default disable iff statement.

• If these defaults are declared, they apply to all assertion

statements in the current module, except those that
explicitly include a different clock or reset.

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Courtesy: System Verilog Assertions, Erik Seligman
Functional and Formal Verification of Digital Designs
Setting default Clocking and Reset

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Functional and Formal Verification of Digital Designs
Summary

• Sampled Value Functions

• Clock and Concurrent Assertions
• Reset and Concurrent Assertions
• Setting clock and reset

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Functional and Formal Verification of Digital Designs
Next Session

• Sequences
• Properties

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THANK YOU

Sudeendra kumar K
Department of Electronics and Communication
Engineering
sudeendrakumark@pes.edu

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