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    YUWEI LIN
    This document provides a mid-term progress report on an Internet of Things data filtering project. It summarizes the current progress, including finishing RTL code writing and circuit synthesis while unfinished tasks remain optimizing the circuit and designing an automatic testbench. It also outlines the project schedule, lists potential issues like area being too large or timing violations, and expected solutions. The document concludes by thanking the audience.

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    Digital

    Uploaded by

    YUWEI LIN
    4 views17 pages
    This document provides a mid-term progress report on an Internet of Things data filtering project. It summarizes the current progress, including finishing RTL code writing and circuit synthesis while unfinished tasks remain optimizing the circuit and designing an automatic testbench. It also outlines the project schedule, lists potential issues like area being too large or timing violations, and expected solutions. The document concludes by thanking the audience.

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    DIGITAL PRESENTATION

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    This document provides a mid-term progress report on an Internet of Things data filtering project. It summarizes the current progress, including finishing RTL code writing and circuit synthesis while unfinished tasks remain optimizing the circuit and designing an automatic testbench. It also outlines the project schedule, lists potential issues like area being too large or timing violations, and expected solutions. The document concludes by thanking the audience.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    4 views17 pages

    Digital

    Uploaded by

    YUWEI LIN
    This document provides a mid-term progress report on an Internet of Things data filtering project. It summarizes the current progress, including finishing RTL code writing and circuit synthesis while unfinished tasks remain optimizing the circuit and designing an automatic testbench. It also outlines the project schedule, lists potential issues like area being too large or timing violations, and expected solutions. The document concludes by thanking the audience.

    Copyright:

    © All Rights Reserved
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    of 17

    Progress

    Presentation
    Internet of Things (IoT) Data Filtering
    Specification

    Area=93121.060875
    Specification

    Max

    Gate Delay =
    49.91
    Specification

    Time = 16350 NS
    Algorithm
    F1 & F2
    Max & Min

    1 Round

    F6 & F7
    Peak Max &
    Peak Min

    2 Round
    F3
    Average

    Shift right 3 bits


    Extract

    F4 & F5
    Exclude
    Structure
    System
    Architecture
    Known and
    to-be-learned issues

    01
    Researching how to pass more tests with automatic testbench

    02
    Using spyglass to ensure my design

    03
    Reducing the delay of the circuit
    Current
    Progress

    Finished Unfinished
    RTLcode writing Optimize Circuit

    Circuit Synthesis Design testbench by myself

    Pass the TA’s testbench Design automatic


    testbench
    Mid-term Progress Report
    ouputs valid , iot_out
    8*128 bits reg

    Logic Synthesis Result

    Decoder

    7 functions module
    CC
    My team

    Lem
    on
    林祐葳
    Project Designer
    林祐葳
    PPT Designer
    林祐葳
    Report Speaker
    Schedule
    Finished

    Unfinished

    12/15~12/22 12/23~12/29 12/29~1/5 1/5~1/8

    RTL_code type
    Preliminary Circuit Running Score
    Circuit Synthesis
    Synthesized Circuit Running Score
    Midterm Progress Report Production
    Circuit Optimization
    Trying to design an automated validation file
    Final Report Production
    Possible Issiues and
    Expected Solutions

    01 Area too large


    Reduce the use of adders by extrapolating the boolean function of counter+1
    with a logic gateway. Then check if the conditional clause can be simplified.

    02 Can’t get a better performance

    02 Set-up time or
    Hold- time violation
    Thank you

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