UNIT- III

Semiconductor memories interfacing (RAM, ROM), Intel 8255 programmable peripheral interface,
Interfacing switches and LEDS, Interfacing seven segment displays, software and hardware interrupt
applications, Intel 8251 USART architecture and interfacing, Intel 8257a DMA controller, stepper motor,
A/D and D/A converters, Need for 8259 programmable interrupt controllers.

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1. 8086 Memory Interface

Memory Devices
Simple or complex, every microprocessor-based system has a memory system.
Almost all systems contain four common types of memory:
 Read only memory (ROM)
 Flash memory (EEPROM)
 Static Random access memory (SARAM)
 Dynamic Random access memory (DRAM).
Before attempting to interface memory to the microprocessor, it is essential to
understand the operation of memory components.

Memory Pin Connections

Figure (1) shows a general form diagram of ROM and RAM pins. Pin connections common to
all memory devices are:
 Address connections
 Data connections
 Selection connections
 Control connections

Address connections: All memory devices have address inputs that select a memory location
within the memory device. Address inputs are labeled from A0 to An

Data connections: All memory devices have a set of data outputs or input/outputs. Today many of
them have bi-directional common I/O pins.

Selection connections: Each memory device has an input that selects or enables the memory
device. This kind of input is most often called a chip select ( CS ), chip enable ( CE ) or simply
select ( S ) input.
 RAM memory generally has at least one CS or S input and ROM at least one CE .
 If the CE , CS , S input is active the memory device perform the read or write.
 If it is inactive the memory device cannot perform read or write operation.
 If more than one CS connection is present, all most be active to perform read or write
data.

Control connections:
 A ROM usually has only one control input, while a RAM often has one or two control inputs.
 The control input most often found on the ROM is the output enable ( OE ) or gate ( G ),
 this allows data to flow out of the output data pins of the ROM.
 A RAM memory device has either one or two control inputs. If there is one control input it
is often called R W .
 This pin selects a read operation or a write operation only if the device is selected by the
selection input ( CS )

Read-only memory (ROM)

Read-only memory (ROM) permanently stores programs/data resident to the system, and must not
change when power disconnected

Often called nonvolatile memory, because its contents do not change even if power is
disconnected.

A device we call a ROM is purchased in mass quantities from a manufacturer. programmed

during fabrication at the factory

The EPROM (erasable programmable read-only memory) is programmed in the field on a device
called an EPROM programmer.

Also erasable if exposed to high-intensity ultraviolet light, depending on the type of EPROM.

The PROM (programmable read-only memory) is also programmed in the field by burning open
tiny NIchrome or silicon oxide fuses. Once it is programmed, it cannot be erased.

A newer type of read-mostly memory (RMM) is called the flash memory.

Flash memory is also often called an EEPROM (electrically erasable programmable ROM) or
EAROM (electrically alterable ROM) or a NOVRAM (nonvolatile RAM)

Electrically erasable in the system, but they require more time to erase than normal RAM.
 The flash memory device is used to store setup information for systems such as the video card in
the computer.

Static Random Access Memory (SRAM)

A Static RAM is a volatile memory device which means that the contents of the memory array
will be lost if power is removed.

Unlike a dynamic memory device, the static memory does not require a periodical refresh cycle
and generally runs much faster than a dynamic memory device.

Static RAM is used when the size of the read/write memory is relatively small, today, a small
memory is less than 1M byte.

The main difference between ROM and RAM is that RAM is written under normal operation,
whereas ROM is programmed outside the computer and normally is only read.

Dynamic Random Access Memory (DRAM)

Available up to 256M X 8 (2G bits).

DRAM is essentially the same as SRAM, except that it retains data for only 2 or 4 ms on an
integrated capacitor.

After 2 or 4 ms, the contents of the DRAM must be completely rewritten (refreshed), because the
capacitors, which store a logic 1 or logic 0, lose their charges.

8086 Memory Interface

The memory address space of the 8086-based microcomputers has different logical and physical
organizations (see Fig. 2).
Fig. 2: (a) Logical memory organization, and (b) Physical memory organization (high and low memory
banks) of the 8086 microprocessor.

Logically, memory is implemented as a single 1M × 8 memory chunk. The byte-wide

storage locations are assigned consecutive addresses over the range from 00000H through
FFFFFH
Physically, memory is implemented as two independent 512 Kbyte banks: the low (even)
bank and the high (odd) bank. Data bytes associated with an even address (00000H

00002H, etc.) reside in the low bank, and those with odd addresses (00001H, 00003H,
etc.) reside in the high bank.
Address bits A1 through A19 select the storage location that is to be accessed. They are
applied to both banks in parallel. A0 and bank high enable ( BHE ) are used as bank-select
signals.
The memory locations 00000-FFFFF are designed as odd and even bytes. To distinguish
between odd and even bytes, the CPU provides a signal called BHE (bus high enable).
BHE and A0 are used to select the odd and even byte, as shown in the table below.

A0 Functio
BH n
E
0 0 Choose both odd and even memory bank
0 1 Choose only odd memory bank
1 0 Choose only even memory bank
1 1 None is chosen

Minimum mode Memory Interface

Figure (3) show block diagram of minimum mode 8086 memory interface.

ALE

AD0-AD15

8086
WR
MPU RD
Memory
M/IO
Subsystem
and bus
DT/R interface
Vcc DEN
Circuit
BHE
MN/MX

Fig. 3: Minimum mode memory interface

 The control signals provided to support the interface to the memory subsystem are
ALE , M IO , DT R , RD , WR , DEN and BHE

When Address latch enable (ALE) is logic 1 it signals that a valid address is on the
bus.

This address can be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
M IO (memory/IO) and DT R tells external circuitry whether a memory or I/O transfer is
taking place over the bus, and whether the 8086 will transmit or receive data over the bus.
❖ The bank high enable ( BHE ) signal is used as a memory enable signal for the
most

significant byte half of the data bus, D8 through D15.

The signals WR (write) and RD (read) identify that a write or read bus cycleis in
progress.
DEN (data enable), is also supplied. It enables external devices to supply data to the
microprocessor.

Maximum mode Memory Interface

Figure (4) show block diagram of maximum mode memory interface.
In maximum mode the 8086 not directly provides all control signal to support the memory
interface.
Instead, an external Bus Controller (8288) provides memory commands and control
signals as shown in table (5) in lecture (8)

8086
 2. Programmable Peripheral Interface 8255

The 8255 is a general purpose programmable I/O device designed to transfer the data from I/O to interrupt I/O
under certain conditions as required. It can be used with almost any microprocessor.

It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per the requirement.

Ports of 8255

8255 has three ports, i.e., PORT A, PORT B, and PORT C.

• Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.

• Port B is similar to PORT A.

• Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by the
control word.

These three ports are further divided into two groups, i.e. Group A includes PORT A and upper PORT C.
Group B includes PORT B and lower PORT C. These two groups can be programmed in three different
modes, i.e. the first mode is named as mode 0, the second mode is named as Mode 1 and the third mode is
named as Mode 2.

Operating Modes

8255A has three different operating modes −

• Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports. Each port
can be programmed in either input mode or output mode where outputs are latched and inputs are not
latched. Ports do not have interrupt capability.

• Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as either input
or output ports. Each port uses three lines from port C as handshake signals. Inputs and outputs are
latched.

• Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B either in Mode 0
or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining
three signals from Port C can be used either as simple I/O or as handshake for port B.

Features of 8255A

The prominent features of 8255A are as follows −

• It consists of 3 8-bit IO ports i.e. PA, PB, and PC.

• Address/data bus must be externally demux'd.

• It is TTL compatible.

• It has improved DC driving capability.

8255 Architecture

The following figure shows the architecture of 8255A −

 3. Programmable Interrupt Controller 8259

The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085 and 8086 there
are five hardware interrupts and two hardware interrupts respectively. Bu adding 8259, we can increase the
interrupt handling capability. This chip combines the multi-interrupt input source to single interrupt output.
This provides 8-interrupts from IR0 to IR7. Let us see some features of this microprocessor.

• This chip is designed for 8085 and 8086.

• It can be programmed either in edge triggered, or in level triggered mode

• We can mask individual bits of Interrupt Request Register.

• By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines

• Clock cycle is not needed.

The pin level diagram and functional pin diagram is like below -
The block diagram is like below -

Block Description

Data Bus Buffer This block is used to communicate between 8259 and 8085/8086 by
acting as buffer. It takes the control word from 8085/8086 and send it
to the 8259. It transfers the opcode of the selected interrupts and
address of ISR to the other connected microprocessor. It can send
maximum 8-bit at a time.

R/W Control Logic This block works when the value of pin CS is 0. This block is used to
flow the data depending upon the inputs of RD and WR. These are
active low pins for read and write.

Control Logic It controls the functionality of each block. It has pin called INTR. This
is connected to other microprocessors for taking the interrupt request.
The INT pin is used to give the output. If 8259 is enabled, and also the
interrupt flags of other microprocessors are high then this causes the
value of the output INT pin high, and in this way this chip can responds
requests made by other microprocessors.
Block Description

Interrupt Request It stores all interrupt level that are requesting for interrupt service.
Register

Interrupt Service It stores interrupt level that are currently being execute.
Register

Interrupt Mask It stores interrupt level that will be masked, by storing the masking bits
Register of interrupt level.

Priority Resolver It checks all three registers, and set the priority of the interrupts.
Interrupt with the highest priority is set in the ISR register. It also reset
the interrupt level which is already been serviced in the IRR.

Cascade Buffer To increase number of interrupt pin, we can cascade more number of
pins, by using cascade buffer. When we are going to increase the
interrupt capability, CSA lines are used to control multiple interrupts.
 4. Programmable Communication Interface 8251 USART

8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator between
microprocessor and peripheral to transmit serial data into parallel form and vice versa.

1. It takes data serially from peripheral (outside devices) and converts into parallel data.

2. After converting the data into parallel form, it transmits it to the CPU.

3. Similarly, it receives parallel data from microprocessor and converts it into serial form.

4. After converting data into serial form, it transmits it to outside device (peripheral).

Block Diagram of 8251 USART –

It contains the following blocks:

1. Data bus buffer –

This block helps in interfacing the internal data bus of 8251 to the system data bus. The data
transmission is possible between 8251 and CPU by the data bus buffer block.

2. Read/Write control logic –

It is a control block for overall device. It controls the overall working by selecting the operation to be
done. The operation selection depends upon input signals as:
In this way, this unit selects one of the three registers- data buffer register, control register, status register.

3. Modem control (modulator/demodulator) –

A device converts analog signals to digital signals and vice-versa and helps the computers to
communicate over telephone lines or cable wires. The following are active-low pins of Modem.

• DSR: Data Set Ready signal is an input signal.

• DTR: Data terminal Ready is an output signal.

• CTS: It is an input signal which controls the data transmit circuit.

RTS: It is an output signal which is used to set the status RTS.

4. Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for conversion into serial
signal and further transmission onto the common channel.

• TXD: It is an output signal, if its value is one, means transmitter will transmit the data.

5. Transmit control –
This block is used to control the data transmission with the help of following pins:

• TXRDY: It means transmitter is ready to transmit data character.

• TXEMPTY: An output signal which indicates that TXEMPTY pin has transmitted all the data
characters and transmitter is empty now.

• TXC: An active-low input pin which controls the data transmission rate of transmitted data.

6. Receive buffer –
This block acts as a buffer for the received data.

• RXD: An input signal which receives the data.

7. Receive control –
This block controls the receiving data.

• RXRDY: An input signal indicates that it is ready to receive the data.

• RXC: An active-low input signal which controls the data transmission rate of received data.

• SYNDET/BD: An input or output terminal. External synchronous mode-input terminal and

asynchronous mode-output terminal.
 5. DMA Controller 8257

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It allows the
device to transfer the data directly to/from memory without any interference of the CPU.

Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so the device is
free to transfer data directly to/from the memory. The DMA data transfer is initiated only after receiving
HLDA signal from the CPU.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −

• Initially, when any device has to send data between the device and the memory, the device has to send
DMA request (DRQ) to DMA controller.

• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA.

• Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the
control over bus and acknowledges the HOLD request through HLDA signal.

• Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses
between the CPU, memory, and I/O devices.

Features of 8257

Here is a list of some of the prominent features of 8257 −

• It has four channels which can be used over four I/O devices.

• Each channel has 16-bit address and 14-bit counter.

• Each channel can transfer data up to 64kb.

• Each channel can be programmed independently.

• Each channel can perform read transfer, write transfer and verify transfer operations.

• It generates MARK signal to the peripheral device that 128 bytes have been transferred.

• It requires a single phase clock.

• Its frequency ranges from 250Hz to 3MHz.

• It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture

The following image shows the architecture of 8257 −

8257 Pin Description

The following image shows the pin diagram of a 8257 DMA controller −

DRQ0−DRQ3

These are the four individual channel DMA request inputs, which are used by the peripheral devices for using
DMA services. When the fixed priority mode is selected, then DRQ0 has the highest priority and DRQ3 has the
lowest priority among them.

DACKo − DACK3

These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the status of
their request by the CPU. These lines can also act as strobe lines for the requesting devices.

Do − D7

These are bidirectional, data lines which are used to interface the system bus with the internal data bus of
DMA controller. In the Slave mode, it carries command words to 8257 and status word from 8257. In the
master mode, these lines are used to send higher byte of the generated address to the latch. This address is
further latched using ADSTB signal.
IOR

It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal registers of 8257
in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a memory
write cycle.

IOW

It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the 8-bit mode
register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, it
is used to load the data to the peripheral devices during DMA memory read cycle.

CLK

It is a clock frequency signal which is required for the internal operation of 8257.

RESET

This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3

These are the four least significant address lines. In the slave mode, they act as an input, which selects one of
the registers to be read or written. In the master mode, they are the four least significant memory address
output lines generated by 8257.

CS

It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from 8257. In the
master mode, it disables the read/write operations to/from 8257.

A4 - A7

These are the higher nibble of the lower byte address generated by DMA in the master mode.

READY

It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.

HRQ

This signal is used to receive the hold request signal from the output device. In the slave mode, it is connected
with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.

HLDA

It is the hold acknowledgement signal which indicates the DMA controller that the bus has been granted to the
requesting peripheral by the CPU when it is set to 1.

MEMR

It is the low memory read signal, which is used to read the data from the addressed memory locations during
DMA read cycles.

MEMW
It is the active-low three state signal which is used to write the data to the addressed memory location during
DMA write operation.

ADST

This signal is used to convert the higher byte of the memory address generated by the DMA controller into the
latches.

AEN

This signal is used to disable the address bus/data bus.

TC

It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral devices.

MARK

The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It indicates the
current DMA cycle is the 128th cycle since the previous MARK output to the selected peripheral device.

Vcc

It is the power signal which is required for the operation of the circuit.
 6. Interfacing DAC with 8086 Using 8255
It can convert an 8 bit digital data input into an analog voltage output. Reference voltage for conversion is
provided using +Vref and –Vref. The output can be amplified (optional) using an op-amp.

Features:

➢ Low power consumption

➢ Easy interface to all microprocessors
➢ Wide power supply range +/- 4.5 to +/- 18V
➢ Fast setting output current 100nS

Types of DAC
There are two types of D/A converters: Weighted Resistor or Resistive Divider type. R-2R Ladder type.
Interfacing DAC0830 with 8086 Using 8255:

The DAC0830 Digital to Analog Converter is connected to 8086 microprocessor, as shown in the Fig. 14.118.
Here, I/O port address is decoded using_ OR gate. The digital data is loaded into DAC0830 when A 0-A7 lines,
WR and IO/M signals are low. This gives us the address for DAC0830 as 00H and the data can be loaded in
the DAC0830 by OUT 00H,AL instruction, where AL register contains the digital data to be sent to DAC0830.
The IC 741, the operational amplifier is used to convert current output of DAC0830 to voltage output. The
voltage output of the operational amplifier is used to drive the DC motor after increasing the driving capacity.
The driving capacity is increased by using the darlington transistor.
 7. Stepper motor interfacing with 8086
A stepper motor is an electric motor whose main feature is that its shaft rotates by performing steps, that is, by
moving by a fixed amount of degrees. This feature is obtained thanks to the internal structure of the motor, and
allows to know the exact angular position of the shaft by simply counting how may steps have been performed,
with no need for a sensor. This feature also makes it fit for a wide range of applications.

There are three main types of stepper motors:

• Permanent Magnet Stepper. PM steppers have rotors that are constructed with permanent magnets,
which interact with the electromagnets of the stator to create rotation and torque. ...

• Variable Reluctance Stepper. ...

• Hybrid Syncronous Stepper.

Working principle

The basic working principle of the stepper motor is the following: By energizing one or more of the stator
phases, a magnetic field is generated by the current flowing in the coil and the rotor aligns with this field.

Uses of stepper motors

Commercially, stepper motors are used in floppy disk drives, flatbed scanners, computer printers, plotters, slot
machines, image scanners, compact disc drives, intelligent lighting, camera lenses, CNC machines, and 3D
printers.

8086 8255 Stepper

motor
 8.LED DISPLAY AND LCD DISPLAY

INTERFACING LIGHT EMITTING DIODE (LED) WITH 8086

Anode is connected through a resistor to GND & the Cathode isconnected to the
Microprocessor pin as shown in Fig.9.1. When the Port Pin is HIGH, the LED is OFF &
whenthe Port Pin is LOW the LED is turned ON.

Figure 3.10.1 LED interfacing diagram

We now want to flash a LED. It works by turning ON a LED & then turning it OFF
& then looping back to START. A delay is generated between the flashing of LEDs.

Point 8255 Lines LED Selection

LD1 PA.0
LD2 PA.1

LD3 PA.2

LD4 PA.3
DIGITAL OUTPUTS

LD5 PA.4

LD6 PA.5

LD7 PA.6

LD8 PA.7

Table 3.10.1 Port Pin Assignment for LEDs

 Figure 3.10.2 LEDs connected to port pins of 8255

ASSEMBLY PROGRAM TO TURN ON AND OFF LEDS USING 8086

MOV AL, 80

MOV DX, Ctrl Reg OUT

DX, AL

BEGIN: MOV AL, 00

MOV DX, Port addr

OUT DX, AL CALL

DELAY MOV AL, FF

OUT DX, AL

CALL DELAY

JMP BEGIN
.

DELAY: MOV

CX, FFFF P0:

DEC CX

JNZ PO

RET
INTERFACING LIQUID CRYSTAL DISPLAY (LCD) WITH 8086

Liquid Crystal displays (LCD) are created by sandwiching a thin 10-12 µm

layer of a liquid-crystal fluid between two glass plates. A transparent, electrically
conductive film or backplane is put on the rear glass sheet. Transparent sections of
conductive film in the shape of the desired characters are coated on the front glass plate.
When a voltage is applied between a segment and the backplane, an electric field is
created in the region under the segment. This electric field changes the transmission of
light through the region under the segment film.
There are two commonly available types of LCD: dynamic scattering and field-
effect. The Dynamic scattering types of LCD: It scrambles the molecules where the field
is present. This produces an etched-glass-looking light character on a dark
background.Field-effect types use polarization to absorb light where the electric field is
present. This produces dark characters on a silver- gray background.

Most LCDs require a voltage of 2 or 3 V between the backplane and a segment to

turn on the segment. We cannot just connect the backplane to ground and drive the
segment with the outputs of a TTL decoder. The reason for this is a steady dc voltage of
more than about 50mV is applied between a segment and the backplane. To prevent a dc
buildup on the segments, the segment drive signals for LCD must be square waves with
a frequency of 30 to 150 Hz.

Intersil ICM7211M can be connected to drive a 4-digit, nonmultiplexed, 7- segment

LCD display through port pins or directly to microcomputer bus. Here, the CS inputs are
connected to the Y2 output of the 74LS138 port decoder. The device can be addressed as
ports say with a base address of FF10H. 8086 system address lines A2 is connected to
.

the digit-select input (DS2) and system address lines A1 is connected to the DS1 input.

the 8086 system data bus. The oscillator input is left open.

To display a character on one of the digits, the 4-bit hex code for that digit is in the
lower 4 bits of the AL register and output it to the system address for that digit. The
ICM7211M converts the 4-bit hex code to the required 7- segment code. The rising edge
of the CS input signal causes the 7-segment code to be latched in the output latches for
the address digit. An internal oscillator automatically generates the segment and
backplane drive waveforms.
.

9. Software and hardware interrupt applications

The different types of interrupts present in the 8086 microprocessor are given by:

1. Hardware Interrupts – Hardware interrupts are those interrupts that are caused by any
peripheral device by sending a signal through a specified pin to the microprocessor.
There are two hardware interrupts in the 8086 microprocessor. They are:

• NMI (Non-Maskable Interrupt): It is a single pin non-maskable hardware interrupt

that cannot be disabled. It is the highest priority interrupt in the 8086
microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt.
IP is loaded from word location 00008 H, and CS is loaded from the word
location 0000A H.

• INTR (Interrupt Request): It provides a single interrupt request and is activated by

the I/O port. This interrupt can be masked or delayed. It is a level-triggered
interrupt. It can receive any interrupt type, so the value of IP and CS will change
on the interrupt type received.

2. Software Interrupts – These are instructions inserted within the program to generate
interrupts. There are 256 software interrupts in the 8086 microprocessor. The instructions
are of the format INT type, where the type ranges from 00 to FF. The starting address
ranges from 00000 H to 003FF H. These are 2-byte instructions. IP is loaded from type *
04 H, and CS is loaded from the following address given by (type * 04) + 02 H. Some
important software interrupts are:

• TYPE 0 corresponds to division by zero(0).

• TYPE 1 is used for single-step execution for debugging the program.

• TYPE 2 represents NMI and is used in power failure conditions.

• TYPE 3 represents a break-point interrupt.

• TYPE 4 is the overflow interrupt.

.

Applications of interrupts:

1. Applications of interrupts include the following: system timers, disk I/O, power-off
signals, and traps.

2. Other interrupts exist to transfer data bytes using UARTs or Ethernet; sense key-presses;
or anything else the equipment must do.

3. Another typical use is to generate periodic interrupts by dividing the output of a crystal
oscillator and having an interrupt handler count the interrupts in order for a processor to
keep time.

4. These periodic interrupts are often used by the OS's task scheduler to reschedule the
priorities of running processes.

5. Some older computers generated periodic interrupts from the power line frequency
because it was controlled by the utilities to eliminate long-term drift of electric clocks.

6. For example, a disk interrupt signals the completion of a data transfer from or to the disk
peripheral; a process waiting to read or write a file starts up again.

7. As another example, a power-off interrupt predicts or requests a loss of power, allowing

the computer equipment to perform an orderly shut-down.

8. Also, interrupts are used in type ahead features for buffering events like keystrokes.