Ch4 Modular Design of

Digital Circuits
Lecture 1: Introduction of Levels of Integration and Modular Circuit
Design for Arithmetical and Logical Operations

Content Reference: M. Morris Mano, and Michael D. Ciletti, “Digital Design with an introduction to Verilog HDL, VHDL, and
System Verilog”, Sixth Edition, Pearson, 2017
Note: Reference to images may be found as hyperlinks or in slide notes
What is in this chapter?
• Introduction of Levels of Integration
• Combinational Circuit Modules
• Adders, Subtractors, Multipliers and Comparators
• Encoders and Decoders
• Multiplexers, Demultiplexers and Dividers
• Memory and Programmable Logic
• Read only Memory (ROM)
• Programmable Logic Arrays
• Arithmetic and Logic Unit (ALU)
Lecture Hours Laboratory Hours Assignment Hours
6 3 3
 Chapter Objectives?
• Know the different levels of integration available • Know how to write an HDL description of a memory.
• Understand the functionality of a half adder and a full-adder. • Know how to interpret memory cycle timing waveforms.
• Understand the concepts of overflow and underflow. • Given the capacity and word size of a memory, know how to specify
the number of its address and data lines.
• Understand the implementation of a binary adder.
• Be able to write a truth table for a ROM.
• Understand the implementation of a binary coded decimal (BCD) adder.
• Be able to write a programming table for a PLA.
• Understand the implementation of a binary multiplier.
• Be able to write a programming table for a PAL.
• Understand fundamental combinational logic circuits: decoder, encoder,
priority encoder, multiplexer, and three-state gate. • Be able to write an HDL model of a RAM.
• Know how to implement a Boolean function with a multiplexer. • Understand the implementation of an Arithmetic and Logic Unit
(ALU)
• Know how to write an HDL description of decoder, encoder and
multiplexer. • Be able to write an HDL model of an ALU
• Know the organizational structure and functionality of programmable
logic devices (PLDs).
• Know how array logic diagrams differ from conventional logic diagrams.
• Know the letters that are used to refer to the number of words in a
memory.
What is in this lecture?
• Integrated circuits
• Levels of Integration
• Modular Design of Digital Systems
• Modular Circuit Design for Arithmetical and Logical Operations
• Adders
• Subtractors
• Multipliers
• Comparators
Outline
Integrated circuits
Integrated Circuits
• An integrated circuit (IC) is fabricated on a die
of a silicon semiconductor crystal
• The various gates are interconnected inside the This Photo by Unknown Author is licensed under CC BY-SA
chip to form the required circuit
• Chip is mounted in a ceramic or plastic
container
• Connections are welded to external pins to
form the integrated circuit

This Photo by Unknown Author is licensed under CC BY-SA

Levels of Integration
Levels of Integration
• Digital ICs are classified according to the complicity of the circuit.
• Types of ICs
• Small-Scale Integration (SSI) devices: less than 10 gates in a package
• Medium-Scale Integration (MSI) devices: 10 to 1000 gates in a package
• Large-Scale Integration (LSI) devices: thousands of gates in a package
• Very Large-Scale integration (VLSI) and Ultra Large-Scale Integration (ULSI)
devices: contain millions of gates within a single package

This Photo by Unknown Author is licensed

under CC BY-SA
Small-scale integration (SSI) devices
• Less than 10 gates in a package
• Usually contain several independent gates in a single package
Examples: 7404 (NOT gate IC), 7400 (NAND Gate IC), 7432 (OR Gate IC)

This Photo by Unknown Author is licensed under CC BY-SA This Photo by Unknown Author is licensed under CC BY-SA This Photo by Unknown Author is licensed under CC BY-SA
Medium-Scale Integration (MSI) devices
• 10 to 1000 gates in a package
• They usually perform specific elementary digital operations.
Examples use cases: decoders, adders, multiplexers, registers and
counters

74LS48 BCD to 7-Segment

decoder
Large-Scale Integration (LSI) devices
• Thousands of gates in a package
• They include digital systems such as processors, memory chips, and
programmable logic devices
Programmable Logic IC

Memory Chips

This Photo by Unknown Author is licensed under CC BY This Photo by Unknown Author is licensed under CC BY This Photo by Unknown Author is licensed under CC BY-SA
Very Large-Scale integration (VLSI) devices
• Contain millions of gates within a single package
• Examples are large memory arrays and complex microcomputer chips.

"VLSI VL82C594AFC2 chipset and Pentium-75" by htomari is licensed under CC BY-SA 2.0
Ultra Large-Scale Integration (ULSI) devices
• Contain millions of gates within a single package
• Circuits having over one-million transistors

"ULSI_AMC_DX_DLC_40MHz_DSC10256" by FritzchensFritz is marked

with CC0 1.0
Modular Design of Digital
Systems
🧩 🧩
🧩
Modular Design of Digital Systems
• “A digital system is a sequential logic system constructed with
flip‐flops and gates.”
• Sequential circuits can be specified by means of state tables
• However, for a large system number of states can be enormous

📚 😓
Modular Design of Digital Systems cont…
Solution:
• The system is partitioned into subsystems

📚 📕📘📗📙
Modular Design of Digital Systems cont…
Solution:
• The system is partitioned into subsystems
• Each of which performs some function
• modules are constructed from such digital devices as,
• registers, decoders, multiplexers, arithmetic elements, and control logic
• Various modules are interconnected with datapaths and control signals
Combinational Circuit Modules
Adders, Subtractors, Multipliers and Comparators
Combinational Circuits
Combinational circuits:
“A logic circuit is combinational if outputs at any time are a function of
only the present inputs”

-The logic diagram of a combinational circuit has logic gates with no

feedback paths or memory elements
-In sequential circuits due to storage elements outputs depend not only
the present values of inputs but also on past inputs
Standard components
• Several combinational circuits that are employed extensively
• These circuits are available in integrated circuits
• Examples: adders, subtractors, comparators, decoders, encoders, and
multiplexers
• Use cases
• In integrated circuits as MSI
• As standard cells in complex VLSI such as application-specific integrated
circuits (ASICs)
Binary Adder
• The most basic operation is addition
• Simple addition contains 4 possible elementary operations

Operation Result
0+0 0
0+1 1
1+0 1
1+1 10
Binary Adder
• The most basic operation is addition
• Simple addition contains 4 possible elementary operations

Operation Result
0+0 0
0+1 1 Single digit output
1+0 1
1+1 10 Two digit output
The carry

Operation Result
1+1 1 0

The carry

The higher significant bit of this result (with two bits) is called a carry
N-bit addition

0 1 0 1 0 1 0

0 0 1 1 1 1 1
N-bit addition cont…

0 1 0 1 0 1 0

+ + + + + + +

0 0 1 1 1 1 1

To add N-bit numbers we add each pair of bits at the same level of
significance
N-bit addition cont...

0 1 0 1 0 1 0
Operation Result

+ + + + + + + 0+0 0
0+1 1
0 0 1 1 1 1 1 1+0 1
1+1 10

To add N-bit numbers we add each pair of bits at the same level of
significance
N-bit addition cont…

0 1 0 1 0 1 0
Operation Result

+ + + + + + + 0+0 0
0+1 1
0 0 1 1 1 1 1 1+0 1
1+1 10

10 1

However, when there is a carry, …

N-bit addition cont... 1

0 1 0 1 0 1 0

+ + + + + + +

0 0 1 1 1 1 1

0 1

However, when there is a carry, it should be added with the next set of
bits
N-bit addition cont… 1

+
0 1 0 1 0 1 0

+ + + + + + +

0 0 1 1 1 1 1

0 1

Now, to get the next bit of the result there has to be 2 additions
N-bit addition cont... 1
Operation
0+0
Result
0
0+1 1
+ 1+0 1
0 1 0 1 0 1 0 1+1 10

+ + + + + + +

0 0 1 1 1 1 1

0 1

Now, to get the next bit of the result there has to be 2 additions, these
additions can be done one after other.
N-bit addition cont… 1
Operation
0+0
Result
0
1
+ 1+0 1
0 1 0 1 1 0 1+1 10

+ + + + 1 + +

0 0 1 1 1 1

1 0 0 1

Now, to get the next bit of the result there has to be 2 additions, these additions
can be done one after other.
AGAIN! there is an addition with a carry
N-bit addition cont…

Operation Result
0+0 00
0+1 01
1+0 01
1+1 10

In general all additions can be considered as an addition with a carry.

Just in some cases the carry is 0.
 Operation Result
0+0 00

N-bit addition cont… 0+1

1+0
01
01
1+1 10

Carry 0 1 1 1 1 1 0

+ + + + + +

Augend 0 1 0 1 0 1 0

+ + + + + + +

Addend 0 0 1 1 1 1 1

0 1 0 0 1 0 0 1
N-bit addition cont…

Operation Result
0+0 00
0+1 01
1+0 01
1+1 10

Thus, to successfully do a n-bit addition it each bit requires 2 additions.

A single addition can be done according to the table above.
Half-Adder and Full-Adder The names of the circuits stem from the fact that
two half adders can be employed to implement a
full adder

• A combinational circuit that performs the addition of two bits is called

a half-adder
• One that performs the addition of three bits (two significant bits and
a previous carry) is a full-adder

Full-Adder

Half-adder
Half-Adder

Operation Result
0+0 00
0+1 01
Outputs
1+0 01
1+1 10

• To design the combinational circuit, we

need to assign inputs and outputs
• Inputs: x (augend), y (addend)
Inputs
• Outputs: S (sum), C (carry)
Half-Adder cont…
Truth table for half-adder

Operation Result x y C S
0+0 00 0 0 0 0
0+1 01 0 1 0 1
1+0 01 1 0 0 1
1+1 10 1 1 1 0
Half-Adder cont…
Truth table for half-adder

Operation Result x y C S
0+0 00 0 0 0 0
0+1 01 0 1 0 1
1+0 01 1 0 0 1
1+1 10 1 1 1 0

Same as AND Same as XOR

x C x S
y y
Alternatively, K-maps or
minterms can be used, to find
C and S
Half-Adder cont…
Truth table for half-adder

Operation Result x y C S x S
0+0 00 0 0 0 0 y
0+1 01 0 1 0 1
1+0 01 1 0 0 1 C
1+1 10 1 1 1 0
The Half-adder
Full-Adder
• To design the combinational circuit, we
need to assign inputs and outputs
• Inputs: x (augend), y (addend), z (carry-in)
• Outputs: S (sum), C (carry) Outputs

Inputs
Full-Adder cont…
We can create a truth table as before (shown below right) to derive the
circuit
Operation Result x y z C S
0+0+0 00 0 0 0 0 0
0+1+1 01 0 0 1 0 1
0+0+0 01 0 1 0 0 1
0+1+1 10 0 1 1 1 0
1+0+0 01 1 0 0 0 1
1+1+1 10 1 0 1 1 0
1+0+0 10 1 1 0 1 0
1+1+1 11 1 1 1 1 1
Full-Adder cont…
But by the logic we used here…

We can S and C as, z+(x+y) ! “+” denotes ADDITION not to be confused with OR

Half-adders
Full-Adder cont…
But by the logic we used here…

We can S and C as, z+(x+y) ! “+” denotes ADDITION not to be confused with OR

x x plus y
y

Half-Adder
Full-Adder cont…
But by the logic we used here…

We can S and C as, z+(x+y) ! “+” denotes ADDITION not to be confused with OR

z
x S
y x plus y

C
C
Half-Adder
Half-Adder
Full-Adder cont…
But now there are two Carry (C) what is to be done about that?
• We know both are valid cases of Carry
• In other words there is a carry if C1 or C2

z
x S
y

C
C
C2
C1
Full-Adder cont…
There is a carry if C1 or C2
Thus, the circuit is as below.
z
x S
y
C2
C1
C

The Full-adder
Full-Adder cont…
Note x, y, z can be interchanged as they the process of addition is
commutative
z
x S
y

x
y S This or any permutation of x, y, z is
z a valid circuit for the full-adder

C
N-Bit Binary Adder
• Binary Adder: “A digital circuit that produces the arithmetic sum of
two binary numbers”
Carry 0 1 1 1

+ + +

Augend 0 1 0 1

+ + + +

Addend 0 0 1 1

0 1 0 0 1
4-Bit Binary Adder

C3 C2 C1 C0
Carry 0 1 1 1
Again we can begin by assigning
+ + + variables for inputs and outputs.
A3 A2 A1 A0 • A0 to A3 for the Augend
• B0 to B3 for the Addend
Augend 0 1 0 1
• C0 for input carry (there is
not one here)
+ + + + • C4 for result carry
B3 B2 B1 B0 • S0 to S3 for result
Addend 0 0 1 1 • C1 to C3 for intermediate
carries
C4 S3 S2 S1 S0
0 1 0 0 1
4-Bit Binary Adder cont…

C3 C2 C1 C0
Carry 0 1 1 1
We can see each bit addition is
+ + + requires a full-adder
A3 A2 A1 A0
Augend 0 1 0 1

+ + + +
B3 B2 B1 B0
Addend 0 0 1 1

C4 S3 S2 S1 S0
0 1 0 0 1
4-Bit Binary Adder cont…

C3 C2 C1 C0
Carry 0 1 1 1
However, the first addition can
+ + + be a half-adder
A3 A2 A1 A0
Augend 0 1 0 1

+ + + +
B3 B2 B1 B0
Addend 0 0 1 1

C4 S3 S2 S1 S0
0 1 0 0 1
4-Bit Binary Adder cont…
But for now let's use all full-adders
C3 C2 C1 C0
Carry 0 1 1 1

+ + +
A3 A2 A1 A0
Augend 0 1 0 1

+ + + +
B3 B2 B1 B0
Addend 0 0 1 1

C4 S3 S2 S1 S0
0 1 0 0 1
 B3 A3
4-Bit Binary Adder cont…
Now, let’s see how a full-adder module connects C4
FA C3
C3 C2 C1 C0
Carry 0 1 1 1
S3
+ + +
A3 A2 A1 A0
Augend 0 1 0 1

We are using modular

+ + + + design the full adder
B3 B2 B1 B0 module is being used
Addend 0 0 1 1 to make the 4-bit adder

C4 S3 S2 S1 S0
0 1 0 0 1
 B3 A3
4-Bit Binary Adder cont…
Considering next adder, C4
FA C3
C3 C2 C1 C0
Carry 0 1 1 1
S3
+ + +
A3 A2 A1 A0 B2 A2
Augend 0 1 0 1

+ + + +
B3 B2 B1 B0 C3
FA C2
Addend 0 0 1 1

C4 S3 S2 S1 S0
0 1 0 0 1 S2
 4-Bit Binary Adder cont…
Seeing the pattern, the 4-bit binary adder will
be as below

B3 A3 B2 A2 B1 A1 B0 A0

C4
FA C3 FA C2 FA C1 FA C0

S3 S2 S1 S0
 4-Bit Binary Adder cont…
Considering the fact…

B3 A3 B2 A2 B1 A1 B0 A0

C4
FA C3 FA C2 FA C1 HA

Half-adder
S3 S2 S1 S0 module

! However, you should be cautious as some times the input carry is necessary
BCD (Binary Coded Decimal) Adder
• This is an example use case of the
Binary Adder as a module
• BCD is basically a 4 bit Binary number,
but the difference is that 4-bit binary
exists until 15 vs a maximum value of
9 in BCD.
• Thus, to map 9 to 15 we add 6 if there
is a carry (i.e. addition >9)
 Carry Propagation https://www.youtube.com/watch?
v=WfhWsAWXsFM&list=PLAoF4o7zqskSKR4JG_MZ67EnqTS6khWmE&index=101

• Longest propagation delay time in an adder is the time it takes the carry to
propagate
• Only after the carry propagates and ripples through all stages will the last
output S3 and carry C4 settle to their final correct value

B3 A3 B2 A2 B1 A1 B0 A0

C4
FA C3 FA C2 FA C1 FA C0

S3 S2 S1 S0
Carry Propagation cont…
• Each carry propagates through two gates
• In a n-bitt adder, there are 2n gate levels for the carry to propagate
• Carry propagation time is an important attribute
• It limits the speed with which two numbers are added

Ci
Ai S
Bi

Ci+1

The Full-adder
 Carry Lookahead Logic https://www.youtube.com/watch?
v=sfBOI2lnmvI&list=PLAoF4o7zqskSKR4JG_MZ67EnqTS6khWmE&index=102

• At intermediate stages (independent of carry),

• 𝑷𝒊 = 𝑨𝒊 ⊕ 𝑩𝒊
• 𝑮𝒊 = 𝑨𝒊 𝑩𝒊
• Output sum and Carry can be represented as,
• 𝑺𝒊 = 𝑷𝒊 ⨁𝑪𝒊
• 𝑪𝒊+𝟏 = 𝑮𝒊 + 𝑷𝒊 𝑪𝒊

Carry generate Ci
Ai Si
Bi Pi
Carry propagate

Ci+1
Gi

The Full-adder
Carry Lookahead Logic cont…
• If we write Ci (carry at ith stage) in terms of previous stages,
• 𝐶0 = 𝑖𝑛𝑝𝑢𝑡 𝑐𝑎𝑟𝑟𝑦
𝑪𝒊+𝟏 = 𝑮𝒊 + 𝑷𝒊 𝑪𝒊
• 𝑪𝟏 = 𝑮𝟎 + 𝑷𝟎 𝑪𝟎
• 𝐶2 = 𝐺1 + 𝑃1 𝑪𝟏 = 𝑮𝟏 + 𝑷𝟏 𝑮𝟎 + 𝑷𝟏 𝑷𝟎 𝑪𝟎
• 𝐶3 = 𝐺2 + 𝑃2 𝑪𝟐 = 𝑮𝟐 + 𝑷𝟐 𝑮𝟏 + 𝑷𝟐 𝑷𝟏 𝑮𝟎 + 𝑷𝟐 𝑷𝟏 𝑷𝟎 𝑪𝟎
• Each output carry is expressed in sum-of-product
• C3 cab be propagated at the same time as C1 and C2
Carry Lookahead Generator

𝑪𝟑 = 𝑮𝟐 + 𝑷𝟐 𝑮𝟏 + 𝑷𝟐 𝑷𝟏 𝑮𝟎 + 𝑷𝟐 𝑷𝟏 𝑷𝟎 𝑪𝟎

𝑪𝟐 = 𝑮𝟏 + 𝑷𝟏 𝑮𝟎 + 𝑷𝟏 𝑷𝟎 𝑪𝟎

𝑪𝟏 = 𝑮𝟎 + 𝑷𝟎 𝑪𝟎
 Four-bit adder with carry lookahead
𝑷𝒊 = 𝑨𝒊 ⊕ 𝑩𝒊 𝑺𝒊 = 𝑷𝒊 ⨁𝑪𝒊
𝑮𝒊 = 𝑨𝒊 𝑩𝒊
Binary Subtractor
• Substruction is done with 2’s complement
• To find A – B, we need 2’s complement of B, then add to A
• 2’s complement of B is,
• 1’s complement
• Add 1 to least significant bit
• 1-+ve
• 0-ve
• Tk 2s comp of result
4 Bit Binary Adder-Subtractor
• A XOR can be used to demine if B should be 2’s complemented
• 𝐵𝑖 ⨁ 1 = 𝐵ഥ𝑖 , 𝐵𝑖 ⨁ 0 = 𝐵𝑖
• Thus, at M=0 we have 𝑩𝒊 , Cin=0, that is addition
• Thus, at M=1 we have 𝑩𝒊 , Cin=1, that is subtraction
Overflow
• “When two numbers with n digits each are added and the sum is a
number occupying n + 1 digits, we say that an overflow occurred”
• If unsigned: overflow is detected from the end carry out
• Signed numbers:
• An overflow may occur if the two numbers added are both positive or both
negative
• Carry into the sign bit position and the carry out of the sign bit position are
not equal
Carries: 0 1 Carries: 1 0
+70 0 1000110 -70 1 0111010 The range of numbers that each
register can accommodate is from
+80 0 1010000 -80 1 0110000
binary +127 to binary -128
+150 1 0010110 -150 0 1101010
Overflow
• Signed numbers:
• An overflow may occur if the two numbers added are both positive or both
negative
• Carry into the sign bit position and the carry out of the sign bit position are
not equal Positive overflow Non-negative result
• 𝐶3 ⨁ 𝐶4= =0 no overflow
given a non-negative

Carries: 0 1 Carries: 1 0
+70 0 1000110 -70 1 0111010 The range of numbers that each
register can accommodate is from
+80 0 1010000 -80 1 0110000
binary +127 to binary -128
+150 1 0010110 -150 0 1101010
both not negative both negative
4 Bit Binary Adder-Subtractor with overflow
detection
Binary Multiplier
• Similar to multiplication of decimal numbers

Partial Products Partial Products

 Binary Multiplier cont…
• Usually, there are more bits in the partial products and it is necessary to
use full adders

B3 B2 B1 B0
A2 A1 A0
0 A0B3 A0B2 A0B1 A0B0
A1B3 A1B2 A1B1 A1B0
A2B3 A2B2 A2B1 A2B0
C6 C5 C4 C3 C2 C1 C0
Two-bit by two-bit binary multiplier
 Binary Multiplier cont…
• For J multiplier (A) bits and K multiplicand (B) bits,
• Need 𝐽 × 𝐾 AND gates for partial products
• Need (J-1) K-bit Adders

B3 B2 B1 B0 K=4
A2 A1 A0 J=3

0 A0B3 A0B2 A0B1 A0B0

A1B3 A1B2 A1B1 A1B0
A2B3 A2B2 A2B1 A2B0
C6 C5 C4 C3 C2 C1 C0
Two-bit by two-bit binary multiplier
Magnitude Comparator

Types of Magnitude Comparator

There are basically four types of magnitude comparators which we study
in digital electronics which are listed below:

1-bit magnitude comparator

2-bit magnitude comparator
4-bit magnitude comparator
8-bit magnitude comparator
Magnitude Comparator
• Comparison of two numbers to determine whether one number is
greater than, less than, or equal to the other
• Exclusive NOR can be used for equality
A
(𝐴⨁𝐵)′
B A B (𝐴⨁𝐵)′
0 0 1
0 1 0
A 1 0 0
(𝐴⨁𝐵)′ 1 1 1
B Truth Table for XNOR
Applications of Magnitude Comparators
• They are used in the Central Processing Unit (CPUs) and Microcontrollers (MCUs).
• They are used for authorization purposes (such as password management) and biometric
applications.
• They are used to implement controllers and also in servo motors.
• They are used to address the decoding security of the computers.
• They are also used in data comparison of variables like temperature, pressure, etc.

• 1-Bit Magnitude Comparator

• A comparator used to compare two bits is called a single-bit comparator. It
consists of two inputs each for two single-bit numbers and three outputs to
generate less than, equal to, and greater than between two binary
numbers
1-Bit Magnitude Comparator cont…

A>B: AB'
A<B: A'B
A=B: A'B' + AB
Four-bit Magnitude Comparator
• A = A3 A2 A1 A0
• B = B3 B2 B1 B0
• The two numbers are equal if all pairs of significant digits are equal: A3 = B3, A2 =
B2, A1 = B1, and A0 = B0
• (A = B) = x3x2x1
• in a 4-bit comparator, the condition of A>B can be possible in the following four
cases.
• If A3 = 1 and B3 = 0
• If A3 = B3 and A2 = 1 and B2 = 0
• If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
• If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
(A>B)=A3b3’+x3A2B2’+X3X2A1B1’+X3X2X1A0B0’
• Similarly, the condition for A<B can be possible in the following four
cases.
• If A3 = 0 and B3 = 1
• If A3 = B3 and A2 = 0 and B2 = 1
• If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
• If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

• (A<B)=A3’b3+x3A2’B2+X3X2A1’B1+X3X2X1A0’B0
Equality
• For equality all bits should be equal
• For any pair of bits, Xi=(𝐴i⨁𝐵i)′
• For all bits, (A=B) implies,
Xn ⋅Xn-1 … ⋅ Xk ⋅ …X2 ⋅ X1 is high
Greater Than
• Compare from MSB to LSB
A3 A2 A1 A0
B3 B2 B1 B0
• Check for Ai>Bi, that is AiBi’
Greater Than cont…
• If equal check next bit

A3 A2 A1 A0
=

B3 B2 B1 B0

i.e. X3
Greater Than cont…
• Likewise compare all pairs until a one
is not equal
Less Than
• Compare from MSB to LSB
A3 A2 A1 A0
B3 B2 B1 B0
• Check for Ai<Bi, that is Ai’Bi
• If equal check next bit
A3 A2 A1 A0
=

B3 B2 B1 B0

i.e. X3
• Likewise compare all pairs until a one
is not equal
Four-bit Magnitude Comparator

𝐴 < 𝐵 = 𝐴′3 𝐵3 + 𝑥2 𝐴′2 𝐵2 + 𝑥3 𝑥2 𝐴1′ 𝐵1 + 𝑥3 𝑥2 𝑥1 𝐴′0 𝐵0

𝐴 > 𝐵 = 𝐴3 𝐵3′ + 𝑥2 𝐴2 𝐵2′ + 𝑥3 𝑥2 𝐴1 𝐵1′ + 𝑥3 𝑥2 𝑥1 𝐴0 𝐵0′

𝐴 = 𝐵 = 𝑥4 𝑥3 𝑥2 𝑥1
References
[1] M. Morris Mano, and Michael D. Ciletti, “Digital Design with an
introduction to Verilog HDL, VHDL, and System Verilog”, Sixth Edition,
Pearson, 2017 – Chapter 2.9, 4.5