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  • Lecture29 - Sequential CKT - Latch Based System - 24nov

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    Nivedita Acharyya 2035
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    This document is a lecture on digital VLSI CMOS sequential circuits. It discusses two-phase latch based systems and provides equations for calculating the maximum and minimum delay. The maximum delay equation is TC ≥ tpdq1 + tpd1 + tpdq2 + tpd2. The minimum delay equations are thold ≤ tnonoverlap + tccq1 + tcd1 and tcd1 , tcd2 ≥ thold - tnonoverlap − tccq1.

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    Lecture29_sequential ckt_latch based system_24Nov (1)

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    This document is a lecture on digital VLSI CMOS sequential circuits. It discusses two-phase latch based systems and provides equations for calculating the maximum and minimum delay. The maximum delay equation is TC ≥ tpdq1 + tpd1 + tpdq2 + tpd2. The minimum delay equations are thold ≤ tnonoverlap + tccq1 + tcd1 and tcd1 , tcd2 ≥ thold - tnonoverlap − tccq1.

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    13 views5 pages

    Lecture29 - Sequential CKT - Latch Based System - 24nov

    Uploaded by

    Nivedita Acharyya 2035
    This document is a lecture on digital VLSI CMOS sequential circuits. It discusses two-phase latch based systems and provides equations for calculating the maximum and minimum delay. The maximum delay equation is TC ≥ tpdq1 + tpd1 + tpdq2 + tpd2. The minimum delay equations are thold ≤ tnonoverlap + tccq1 + tcd1 and tcd1 , tcd2 ≥ thold - tnonoverlap − tccq1.

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    © All Rights Reserved
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    of 5

    VLSI Design (MEL G621)

    Lecture 29
    (Digital VlSI(CMOS sequential Circuit)

    Instructor

    Dr. Apurba Chakraborty


    Assistant Professor
    Department of Electrical and Electronics Engineering
    BITS Pilani, K K Birla Goa Campus

    Date: 24/11/2022
    Two phase latch based system: Max Delay
    𝑻𝑪 ≥ 𝒕𝒑𝒅𝒒𝟏 + 𝒕𝒑𝒅𝟏 + 𝒕𝒑𝒅𝒒𝟐 + 𝒕𝒑𝒅𝟐
    Two phase latch based system: Max Delay

    𝑻𝑪 ≥ 𝒕𝒑𝒅𝒒𝟏 + 𝒕𝒑𝒅𝟏 + 𝒕𝒑𝒅𝒒𝟐 + 𝒕𝒑𝒅𝟐


    Two phase latch based system: Min Delay

    𝒕𝒉𝒐𝒍𝒅 ≤ 𝒕𝒏𝒐𝒏𝒐𝒗𝒆𝒓𝒍𝒂𝒑 + 𝒕𝒄𝒄𝒒𝟏 + 𝒕𝒄𝒅𝟏


    𝒕𝒄𝒅𝟏 , 𝒕𝒄𝒅𝟐 ≥ 𝒕𝒉𝒐𝒍𝒅 - 𝒕𝒏𝒐𝒏𝒐𝒗𝒆𝒓𝒍𝒂𝒑 − 𝒕𝒄𝒄𝒒𝟏

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