Earlier known as

B. V. B. College of Engineering & Technology

School of Computer Science and Engineering
ISA EXAM II

1.a With neat diagram explain data flow for interrupt cycle.
(3 marks)
• The current contents of the PC must be saved so that the
processor can resume normal activity after the interrupt.
• Thus, the contents of the PC are transferred to the MBR to
be written into memory.
• The special memory location reserved for this purpose is
loaded into the MAR from the control unit.
• It might, for example, be a stack pointer.
• The PC is loaded with the address of the interrupt routine.
• As a result, the next instruction cycle will begin by fetching
the appropriate instruction. (2 marks)

b Assume a superscalar pipeline capable of fetching and decoding two instructions at a time, having three 5
separate functional units and having two instances of the write-back pipeline stage.
i. I1 requires three cycles to execute
ii. I3 and I4 compete for the same execution unit
iii. I5 requires two cycles to execute
iv. I5 and I6 compete for the same execution unit
Show the issue and completion policies for out-of-order issue and out-of-order completion

c What is cache coherence? Explain the software method to deal with the same. 5

Cache Coherence • Design complexity transferred from hardware to

• Multiple copies of same data in different caches software
• Can result in an inconsistent view of memory • However, software tends to make conservative decisions
• Write back policy can lead to inconsistency • Inefficient cache utilization
• Write through can also give problems unless caches • Analyze code to determine safe periods for caching
monitor memory traffic
shared variables
Software methods
• Compiler and operating system deal with problem
• Overhead transferred to compile time

d Explain various multicore organization alternatives. (4x1 mark for each figure + 1 mark explanation) 5
 Earlier known as
B. V. B. College of Engineering & Technology
School of Computer Science and Engineering
ISA EXAM II

2.a Consider the following assembly language program: 5

I1: Move R3, R7
I2: Load R8, (R3)
I3: Add R3, R3, 4
I4: Load R9, (R3)
I5: BLE R8, R9, L3
Identify and justify the dependencies occurring in the same.

I1 & I2: RAW I1 & I3: WAW I2 & I3: WAR I3 & I4: RAW I4 & I5: RAW (1 mark each)

b Compare and contrast various branch prediction techniques 5

• Predict never taken (5 x 1 mark for each)

• Predict always taken
• Predict by opcode
• Taken/not taken switch
• Branch history table

c Compare and contrast Multiprogramming, Multiprocessing and Multicore organization 5

Multiprocessing Multiprogramming Multicore Organization

• The availability of more than one
processor per system, that can
execute several set of instructions in
parallel is known as multiprocessing.
• The number of CPU is more than one.
• It takes less time for job processing.
• In this, more than one process can be
executed at a time.
• It is economical.
• The number of users is can be one or
more than one.
• Throughput is maximum.
• Its efficiency is maximum.
d Explain Hierarchical cluster model and its advantages
• The concurrent application of more than
one program in the main memory is
known as multiprogramming.
• The number of CPU is one.
• It takes more time to process the jobs.
• In this, one process can be executed at a
time.
• It is economical.
• The number of users is one at a time.
• Throughput is less.
• Its efficiency is Less.
• Number of core processors on chip
• Number of levels of cache on chip
• Amount of shared cache
• Homogeneous multicore systems have
more than one core and share the same
architecture and microarchitecture.
• Heterogeneous multicore systems have
two or more cores that differ in
architecture or microarchitecture
5
 Earlier known as
B. V. B. College of Engineering & Technology
School of Computer Science and Engineering
ISA EXAM II

Cluster computing provides a number of benefits: high availability

through fault tolerance and resilience, load balancing and scaling
capabilities, and performance improvements (3 marks)

(2 marks)

3.a Consider the following assembly language program: 5

I1: Move R3,R7
I2: Load R8, (R3)
I3: Add R3, R3,4
I4: Load R9, (R3)
I5: BLE R8, R9, L3
Draw the timing diagram for a 5-stage pipelined architecture. Identify the hazards w.r.t pipelined
architecture and suggest ways to handle them.

(5 marks)
b A microprocessor provides an instruction capable of moving a set of ASCII values from one area of memory to another. 5
The fetching takes 6 clock cycles and decoding of the instruction takes 2 clock cycles. Thereafter, it takes 10 clock cycles
to transfer each ASCII value. The microprocessor is clocked at a rate of 8GHz.
a. Determine the length of the instruction cycle for the case of 32 ASCII characters.
b. What is the worst-case delay for acknowledging an interrupt if the instruction is non-interruptible?
c. Repeat part (b) assuming the instruction can be interrupted at the beginning of each transfer.

a. The length of the clock cycle is 0.125ns. The length of the instruction cycle for this case is
[8+(10 x 32)] x 0.125 = 41ns……..(1 mark)

b. The worst case delay is when the interrupt occurs just after the start of the instruction, which is 41ns. ……..(1 mark)

c. In this case, the instruction can be interrupted after the instruction fetch, which takes 6 clock cycles, so the delay is
(6 x 0.125 = 0.75ns), the instruction can be interrupted after the instruction decode, which takes 2 clock cycles, so
the delay is (2 x 0.125 = 0.25ns). The instruction can be interrupted between byte transfers, which results in a delay
of no more than 10 clock cycles = 1.25 ns. Hence worst case delay is 1.25ns. ……..(3 marks)

c Consider a situation in which there are 5 SMPs P1, P2, P3, P4 and P5. All of them have a cache and use the MESI protocol. 5
Initially, P1 and P3 have a copy of ‘x’. With a neat state diagram and relevant signals explain transitions that take place for
the following sequence of events:
i. P4 intends to modify x.
ii. P5 intends to modify x
iii. P1 and P2 wants to read x
 Earlier known as
B. V. B. College of Engineering & Technology
School of Computer Science and Engineering
ISA EXAM II

iv. P3 intends to write to x

(5 marks)

d Compare and contrast Directory and Snoopy protocols 5