Electronics- I

Lab 7: DC Biasing Schemes of a BJT Transistor

Names Abdul Wahab

Muhammad Rehan Tabassum

Registration
FA20-BEE-010
Number
FA19-BEE-139

Class BEE-3A

Instructor’s Name Ma’am Riffat Shaista

Lab Assessment
Post Lab Total
Pre-Lab In-Lab
Data Presentation Data Analysis Writing Style
Objectives:
1: To understand DC biasing schemes of a BJT transistor
2: To verify the voltages and currents in an emitter-biased circuit as well as to construct its
dc load line.

Equipment:
Breadboard
Digital Multimeter
DC Voltage Source: VDC: 15V
Resistor: 1KΩ, 560kΩ, 4.7kΩ
Transistor: 2N3904, 2N3906

In-Lab I: Emitter Bias

Experiment with NPN Transistor: 2N3904

Section 1 > Table 1 > Emitter Biased > NPN

Measured 2N3904 Calculated

Parameters
IC 6.26mA 6.42mA
IB 14.5µA 14.212µA
BDC 431 451
VB 1.465V 1.42V
VC 8.86V 8.645V
VE 1.045V 1.112V
VCE 7.78V 7.83V
Section 1 > Table 2 > Emitter Biased > NPN > Cut-Off and Saturation region
Parameter Value
VCE Off 20.5V
IC Sat 7.5mA

NPN Emitter Bias 2N3904

7

4
IC (mA)

0
0 1 2 3 4 5 6 7 8
VCE (V)

Load Line

For the NPN transistor 2N3904 we got a Collector current of 6.2mA and a Base current of 14.5µA
which gives us a Gain of 431 times.
Experiment with PNP Transistor: 2N3906
Section 1 > Table 3 > Emitter Biased > PNP

Measured 2N3904 Calculated

Parameters
IC -10.9mA 8.56mA
IB -1.7mA 2.31mA
BDC 6.41176 3.70
VB -6.82V -6.21V
VC -6.10V -5.876V
VE -6.06V -6.1V
VCE -0.72V -0.79V

Section 1 > Table 4 > Emitter Biased > PNP > Cut-Off and Saturation region
Parameter Value
VCE Off -20.3V
IC Sat 7.5mA

PNP Emitter Bias 2N3906

12

10

8
IC (mA)

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VCC (V)

Load Line

For the PNP transistor 2N3906 we got a Collector current of -10.9mA and a Base current of -
1.7mA which gives us a Gain of 6.4 times. However, the value of Beta must be between 50 and
500. The BJT 2N3906 has the minimum amplification of 30. Therefore, this experiment was a
failure. The failure can be attributed to either faulty BJTs or wrong circuit parameters.
In-Lab II: Voltage Divider Bias
Experiment with NPN Transistor: 2N3904

Section 2 > Table 5 > Voltage Divider Biased > NPN

Measured 2N3904 Calculated

Parameters
IC 9.72mA 8.23mA
IB 0.64mA 2.231mA
BDC 15.18 3.68
VB 6.15V 7.5V
VC 5.48V 6.5V
VE 5.45V 6.78V
VCE 37.2mV 67.833mV

Section 2 > Table 6 > Voltage Divider Biased > NPN > Cut-Off and Saturation region
Parameter Value
VCE Off -20.3V
IC Sat 7.5mA
 NPN Emitter Bias 2N3904
12

10

8
IC (mA)

0
0 0.1 0.2 0.3 0.4
Vcc (V)

Load Line

For the NPN transistor 2N3904 in Voltage Divider Configuration we got a Collector current of
9.72mA and a Base current of 0.64mA which gives us a Gain of 15.18 times. Which again is a
failure as the minimum value of Beta is 50. The error maybe because of faulty BJT or poor circuit
design.

Experiment with PNP Transistor: 2N3906

Section 1 > Table 7 > Voltage Divider Biased > PNP

Measured 2N3904 Calculated

Parameters
IC -5.24mA -5.2mA
IB -27µA -28.5µA
BDC 194 182.456
VB -6.13V -6.8V
VC -272mV -215mV
VE -6.82V -6.525V
VCE -6.55V -6.895V

Section 1 > Table 8 > Voltage Divider Biased > PNP > Cut-Off and Saturation region
Parameter Value
VCE Off -20.3V
IC Sat 7.5mA

Load Line
6

4
Ic (mA)

0
0 1 2 3 4 5 5.5 7
Vcc (V)

Load Line

For the PNP transistor 2N3906 we got a Collector current of -5.24mA and a Base current
of 27µA which gives us a Gain of 194 times.
Critical Analysis:
In this lab we examined the characteristics of different transistor configurations, such as
Emitter Bias and Voltage Divider Bias.
In the experiments we ran into problems where BJT circuit failed to achieve amplification
of 50 which is the minimum value of Beta, as such 2 of the 4 experiments yielded incorrect
numbers.
This is likely caused by errors in the circuit diagram or faulty BJTs, however it is more likely
the former as experiments by different groups also yielded similar results.