VLSI Digital Design using VHDL &

H/W implementation on FPGA

(Targeting Xilinx Virtex-5 FPGA Kit)

Dr. Mervat Mahmoud, mervat-m@eri.sci.eg

Dr. Nahla Elazab, nahlaelazab@eri.sci.eg

Table of content
• Difference between Digital design and
Analog design
• Introduction to VLSI Design
• VHDL
▪ VHDL Basic Structure
• Implementation of projects in FPGA

© MervatMahmoudERI

1
 What is the difference between Digital design and
Analog design?
Analog design
Transistor level, Design is not necessarily
a CMOS design, and it can include
resistors, capacitors, inductors, …..etc.
Designer needs knowledge about:
semiconductor technology, semiconductor
physics, electrical circuit theory, control
and feedback.
Designer needs to be familiar with:
EDA tools such as: SPICE for circuit
simulation, schematic and layout tools.
Digital design
Gate level,
Design is mostly CMOS
Designer needs knowledge about:
Boolean algebra, linear algebra, digital
signal processing, synchronous and
asynchronous system.
Designer needs to be able to:
use HDL languages, simulate netlists,
perform synthesis, run timing analysis.

Designs amplifiers, oscillators, analog Designs logic gates, latches, counters,

filters, mixers, power supply regulators, adders, multipliers, digital filters, micro-
A/D and D/A converters controllers.
© MervatMahmoudERI

Introduction to VLSI
Design

© MervatMahmoudERI

2
Digital Design Implementation
❑ Printed Circuit Board (PCB)
■ Using Orcad/PSpice tool
■ For laboratory experiment

❑ Microcontroller
■ Small processor
■ For control circuits
■ Programmed with high level language (MicroC /
MicroBasic/MicroPython)

❑ FPGA
❑ ASIC
© MervatMahmoudERI

Digital Design Implementation

❑ Printed Circuit Board (PCB)

© MervatMahmoudERI

3
Digital Design Implementation
❑ MicroController

© MervatMahmoudERI

Digital Design Implementation

❑ FPGA (Field-programmable Gate Array)

© MervatMahmoudERI

4
Digital Design Implementation
❑ FPGA
▪ Logic Cell

© MervatMahmoudERI

❑ FPGA

Digital design can be written in

• Behavioural Level ( Design algorithm/ function )

• Structural/Data path Level (building blocks )

• Logic (RTL) Level (Gate Wirelist, Netlist)

© MervatMahmoudERI

5
 Digital Design Implementation
❑ ASIC (Application Specific Integrated Circuit)

• All logic cells are customized and all mask layers.

• Example: microprocessor
• Customizing all of the IC features in this way allows
designers to include analog circuits, optimized memory
cells, or mechanical structures on an IC.
• The manufacturing lead time (the time it takes just to
make an IC—not including design time) is typically eight
weeks for a full-custom IC.
• Full-custom ICs are the most expensive to manufacture
and design but have the best performance.
© MervatMahmoudERI

❑ Full-Custom ASIC

Digital design written in

• Behavioural design Level ( Design algorithm/ function )
or
• Structural design/Data path Level (building blocks )
or
• Logic design (RTL) Level (Gate Wirelist, Netlist)

Then
• Layout design

Then
• Send to Manufactory -> Chip

6
 VLSI Design Process

© MervatMahmoudERI

VLSI Design Process

 Idea
High Level of
abstraction
 Behavioural design ( Design algorithm/ function )

 Structural design/Data path ( Design building blocks )

 Logic design (RTL) (Gate Wirelist, Netlist)

Low Level of  Physical design (Transistor List, Layout)

abstraction
 Manufacturing -> Chip

7
 Behavioural design

 Structural Design

© MervatMahmoudERI

8
For simulation

Called (post synthesis simulation)

Called (post layout simulation)

© MervatMahmoudERI

IC design

• From Sand to Silicon: the Making of a

Chip

https://www.youtube.com/watch?v=Q5
paWn7bFg4

© MervatMahmoudERI

9
 IC design

https://www.youtube.com/watch?v=Uvl
uuAIiA50

© MervatMahmoudERI

IC layers fabrication

• The Fabrication of Integrated

Circuits

https://www.youtube.com/watch?v=35j
WSQXku74

© MervatMahmoudERI

10
 IC Design

© MervatMahmoudERI

IC Design Flow
Requirements

Design Schematic Simulate

or VHDL code

Synthesis

Timing Extraction

Simulate

Timing
FPGA Place&route (FPGA)
Simulate
ASIC Layout (ASIC)

11
EDA (Electronic Design Automation)
• Electronic design automation (EDA) is a category
of software tools for designing electronic
systems such as printed circuit boards and
integrated circuits.

• The tools work together in a design flow that chip

designers use to design and analyze entire
semiconductor chips.

• Software focuses on Design, Simulation, Analysis

and verification, and Manufacturing preparation
for all levels of abstraction (Behavioural,
Structural, Logic, and Physical design).

EDA Top Companies (ASIC)

Cadence: The company is

Synopsys: The company is headquartered in San Jose,
headquartered in Mountain California, US.
View, California, US.

Mentor: The company is

headquartered in Wilsonville,
Oregon, US.

12
Semiconductor Industry (IDMs)
❖ Originally, microelectronic devices were
manufactured by companies that both design and
produce the devices, which achieve efficient vertical
integration. “Integrated Device Manufacturers
(IDMs)”

❖ However, Integrated circuit production facilities are

expensive to build and maintain.

IDM Companies
The top 5 IDM companies (in semiconductor sales)
in 2015 were:
Country of
Rank Company
origin

1 Intel USA
2 Samsung South Korea
3 SK Hynix South Korea
4 Micron USA
5 Texas Instruments USA
Ref: http://www.icinsights.com/news/bulletins/Six-Top-20-1Q15-Semiconductor-Suppliers-Show-20-
Growth-/

13
 Semiconductor Industry
(Foundry Model)
❖ The Foundry Model refers to the separation of a
semiconductor fabrication plant operation
(foundries) from an integrated circuit design
operation (Fabless companies), into separate
companies or business units.

▪ Fabless (without fab) companies focus on the design

of innovative integrated circuits, development and
marketing, while avoiding the high cost of building,
operating, and upgrading a manufacturing facility.
▪ Foundries find work from the worldwide pool of
fabless companies, and by careful scheduling, pricing,
and contracting keep their plants at full utilization.

Foundry Companies
The top 3 foundry companies (in semiconductor sales)
in 2015 were:
Country
Rank Company
of origin

1 TSMC Taiwan
2 GlobalFoundries USA
3 UMC Taiwan

Ref: http://www.icinsights.com/news/bulletins/Six-Top-20-1Q15-Semiconductor-Suppliers-Show-20-
Growth-/

14
 Fabless Companies
The top 5 Fabless companies (in semiconductor sales)
in 2015 were:
Country
Rank Company
of origin

1 Qualcomm/CSR USA
2 Avago/Broadcom USA
3 Mediatek Taiwan
4 Nividia USA
5 AMD USA
Ref: http://www.icinsights.com/news/bulletins/IDMs-Could-Top-Fabless-Semiconductor-Company-
Growth-For-Only-The-Second-Time-In-History/

© MervatMahmoudERI

Fabless Companies in Egypt

Goodix

Si-ware

Si-vision

Mixel

Vidatronic

Analog Devices

15
 Very High Speed Integrated Circuit
Hardware Description Language
(VHDL)

© MervatMahmoudERI

Question on the sidelines

What is the difference between software programming

languages and hardware programming languages ?
Hardware programming Software programming
languages languages

Concurrent in nature and executed a Sequential in nature and executed a

piece of code in parallel piece of code sequentially

model a Digital circuits and the executed as a piece of instructions to

circuits synthesized to a hardware CPU and the code is not synthesizable

Need the knowledge of Digital and Need the knowledge of Algorithm

hardware circuit and Processor

examples of HDL are VHDL, examples of Software Languages are

Verilog, SystemVerilog C, C++, java, matlab

16
 What is VHDL?
➢ VHDL is the VHSIC (Very High Speed Integrated Circuit) HDL
(Hardware Description Language).

➢ VHDL was initiated in 1981 by the USA DoD (Department of

Defense) to address hardware life-cycle design problem.

➢ VHDL describes the behavior, structure, and RTL of electronic

systems.

➢ VHDL is inherently concurrent (parallel) contrary to regular

computer programs which are sequential.

➢ The two most popular hardware description languages are VHDL

and Verilog. © MervatMahmoudERI

 VHDL Basic Structure

- Entity, architecture structure
- Objects
- Components
- Operators
- Attributes, predefined functions

© MervatMahmoudERI

17
 VHDL Basic Structure
• LIBRARY
– A list of all libraries to be used in the design.
• Entity (External View)
– Describes the interface of the module (Input-Output
Port definition )
• Architecture (Internal View)
– Behavioral Description - e.g. functions and processes.
– Structural Description - e.g. Gates and wires

© MervatMahmoudERI

Entity
entity <entity name> is
port (<port names> : <port mode> <port type> );
end <entity name> ;

• Example:
entity test is
port( a, b, c: in bit ; c: out bit);
end test;

© MervatMahmoudERI

18
 Architecture
architecture <architecture name> of <entity name> is
<declaration part> -- for signals, constants,
-- data types, and components
begin
<concurrent statements>
end <architecture name> ;

entity
• Example:
architecture dataflow of test is
Begin architecture-3
architecture-2
c <= a and b; architecture-1

end dataflow;
We can have more than one architecture for same entity
© MervatMahmoudERI

Implementation of projects
in FPGA

© MervatMahmoudERI

19
 FPGA Tools
(depend on FPGA used)
For Xilinx FPGAs

© MervatMahmoudERI

FPGA Tools
(depend on FPGA used)
For Intel FPGAs

© MervatMahmoudERI

20
 ISE
Synthesis: generates a netlist that consists of gates and flip-flops

Translate: takes netlists files and turn it into one big design file.
Map: takes the generic logic gates and flip-flops described in the
design files and turns them into the resources available in the
FPGA you've chosen
Place & route: decides where in the die the resources will be
placed and it will wire them together, to meet the design criteria
you have given the tool (timing, area, etc).

The bit file: which is understood by FPGA, and describes the

final configuration and wiring of the FPGA. Downloading it into
the FPGA will configure it into the circuitry you have mapped,
placed and routed.
© MervatMahmoudERI

2-bit Adder example

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder_2bit is
Port ( clk : in std_logic;
in1, in2 : in std_logic_vector(1 downto 0);
sum : out std_logic_vector(2 downto 0));
end adder_2bit;
architecture Behavioral of adder_2bit is
begin
process(clk)
begin
if(clk'event and clk='1') then
sum <= (‘0’ & in1) + (‘0’ & in2) ;
end if;
end process;
end Behavioral;

21
Counter and Frequency Divider
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity clk200Hz is
Port (
clk_in, reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end clk200Hz;

Counter and Frequency Divider

architecture Behavioral of clk200Hz is
signal counter : std_logic_vector(2 downto 0);
signal temp: std_logic;
begin
process (reset, clk_in)
begin
if (reset = '1') then
counter <= “000”;
temp <= ‘0’;
elsif rising_edge(clk_in) then
if (counter = “111”) then
counter <= 0;
temp <= not (temp);
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temp;
end Behavioral;

22