OPTIMIZED HARDWARE IMPLEMENTATION OF

MEDIAN FILTER FOR IMAGE PROCESSING

H.H.Draz, Nahla Elazab, Mervat M. A. Mahmoud
Microelectronics Department, Electronics Research Institute, Cairo, Egypt

Abstract
The field of digital image processing is widespread in several applications
which are essential in daily life. Different image processing algorithms assist
in clarifying the image and improving the ability to recognize distinct charac-
teristics of the image. The median filter is a widespread image pre-processing
way; it effectively eliminates salt and pepper noise from the image. The main
target of this paper is to investigate efficient median filter units to connect to
a general-purpose processor (GPP) for FPGA-based embedded systems. The
paper exposes two novel median filtering techniques. These techniques focus
on a 3x3 image window filtering in which the median unit of the filter can
produce the required result in high accuracy, short time, and reduced number
of comparisons. These are inspired by the median of median (MOM) algo-
rithm. Besides, the paper illustrates how the concept beyond the proposed
techniques can be used to perform the maximum pooling for convolution
neural networks. Furthermore, the two proposed filtering units are imple-
mented leveraging the advantage of the parallel processing, pipelining, and
the FPGA flexible resources to satisfy the real-time processing constraints.
A comparison between the two proposed techniques and their counterparts
in the literature is included. The comparison reveals the superiority of the
first technique in terms of accuracy with fewer comparators than previously
published techniques.
1

Keywords:

Email address: hdraz@eri.sci.eg (H.H.Draz)

1
All source codes discussed and used in this contribution is freely available from the
authors via the above e-mail.

Preprint submitted to Journal Name April 5, 2021

 Embedded Systems, FPGA, Image de-noising, Median Filter, Median of
Medians, Pipelining

1 1. Introduction
2 Digital images have a significant role in daily life applications and areas
3 of research and technology such as magnetic resonance imaging, satellite
4 television, geographical information systems, and astronomy Raju et al. [1].
5 It acts a vital rule in some medical applications such as diabetic retinopathy
6 diseases Priyanka [2]. Data sets gathered by image sensors, the circuitry of a
7 scanner or digital camera are generally infected by noise. It can originate by
8 the image sensor, in the film grain, or in an ideal photon detector’s obligatory
9 shot noise. In addition to the problems with the data acquisition process and
10 imperfect instruments, transmission errors, interfering natural phenomena,
11 and compression can also be sources for image noise [3]. This noise can
12 be recognized as a fundamental signal distortion that degrades the process
13 of information extraction and image observation. Eliminating image noise
14 (denoising) forms a necessary basis for image processing and analysis. Image
15 denoising has been exhaustively studied in the area of computer science.
16 Therefore, many filtration algorithms exist. Denoising algorithms include
17 transform-domain thresholding, statistical models, random fields, dictionary
18 learning methods, anisotropic diffusion methods, spatial domain filtering,
19 and hybrid methods. [4].
20 Regarding the spatial domain techniques, the similarities between pixels
21 or patches of an image are exploited. Spatial domain methods comprise
22 local and non-local filters. A non-local filter makes use of the correlation
23 between the complete range of image pixels. Local filters are limited by
24 spatial distance. The noise reduction schemes in local filtering are classified
25 into linear filtering and nonlinear filtering techniques. These linear filters
26 depend on convolving the image matrix with a filter mask to produce a
27 linear extension of neighborhood values. This kind of spatial filtering is the
28 most accessible and most primitive form of noise removal, but it frequently
29 causes an undesirable quantity of edges smoothing, loss of details, and poor
30 feature localization [5, 6, 7] . Hereafter, a variety of nonlinear filters have
31 been introduced in order to focus on the aforementioned restrictions in a
32 manner of their innovative and improvisations concepts [8, 9].
33 The median filter is one of the nonlinear filters based on order-statistics
34 theory David and Nagaraja [10]and used for impulse noise removal. Im-

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35 pulse noise for Grayscale images is also expressed as Salt and Pepper noise.
36 This filter substitutes each pixel by the median of the surrounding pixels.
37 The median value must essentially be one of the neighborhood pixels val-
38 ues. As a result, separated noise points will be removed without generating
39 new impracticable pixel values. Therefore, this technology is preferred for
40 eliminating the random additive and the salt-and-pepper noise. It can also
41 keep the high-frequency portion of the image to a great extent, thus en-
42 sures the image visual effect. Consequently, median filters can present good
43 noise reduction facilities, significantly less blurring than smoothing linear
44 filters of equal size. For these reasons, the median filtering approach has
45 become a widespread algorithm of the image repairing field in recent years
46 [1]. Nevertheless, this technique’s methodology comprises too much manipu-
47 lation involving the scan, compare and move operation, making it relatively
48 slow [1]. Standard median filtering can not comply with the real-time re-
49 quirement. Additionally, software implementations of sorting procedures are
50 time-consuming. Thus, optimized sorting techniques should be used for fast
51 median filtering. Also, it is critical to implement the filter in a high-speed
52 environment. Therefore, two filtering techniques are proposed, which do not
53 depend on sorting all the elements but on making some comparisons to ex-
54 clude the nonmedian elements. This concept prevents unnecessary sorting
55 and comparisons from satisfying the real-time processing constraints. On the
56 other hand, the implementation of 3x3 (9 elements window) median filters
57 has been motivated, given that larger filters usually reduce small edges [11].
58 Furthermore, hardware acceleration is utilized in this work using FPGA to
59 improve the performance. Since FPGAs usually offer a substantial speed
60 improvement compared to software-based solutions via adaption to the ap-
61 plication and parallelism features. Hence, the two proposed filtering units
62 benefiting from the merits of the parallel processing, pipelining, and FPGA
63 flexible resources. The rest of the paper is organized as follows: Section
64 2 describes the background of the median filter techniques, including the
65 sorting-based techniques and the selection-based techniques. The two pro-
66 posed algorithms are demonstrated in detail in sections 3, 4, and 5. While,
67 the hardware implementation, and the simulation results are illustrated in
68 section 6, and 7 respectively. Finally, the paper is concluded in section 8.

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 69 2. Background of median filter algorithms
70 The median value is the value in the mid position of an arranged sequence.
71 70 Assume that the window pixel values are put into an array named x, such
72 that its elements are x1 , x2 , x3 , x4 , . . . . . . , xn and it turns into xi1 ≤ xi2 ≤
73 xi3 ≤ xi4 . . . . . . ≤ xin after sorting it in descending order, afterwards its
74 median value is xi(n−1)/2 . There are many techniques to get the median
75 number of an array; some of them depend on sorting the array elements
76 first then selecting the elements of the mid position, and the others are
77 done without sorting. The sorting-based techniques are more popular than
78 the techniques that belong to the other category. Therefore, the literature
79 includes many implementations of the median filter using different sorting
80 algorithms such that the Bubble, Insertion, Selection, Quick, Heap, Shell,
81 Merge, and Tim sort [12]. In these implementations, the effectiveness of these
82 median filters depends mostly on the adopted sorting techniques’ speed and
83 efficiency. However, even with the high-efficiency sorting techniques, there
84 is a waste in the used hardware and the computational time wherein sorting
85 all the elements is not actually required. Additionally, some of the sorting
86 techniques, i.e., merge sorting and odd-even merge-sort, restrict the array
87 length to be a power of 2 which means appending the window array by
88 some zeros (or some other values), and after applying the sort algorithm,
89 those appended zeros should be eliminated [13]. Hence, in the case of 3x3
90 windows, there should be seven appended elements to satisfy this condition
91 which incorporates undesired overhead in the used memory, the required
92 hardware, and processing time. Therefore these techniques are not suitable
93 to be a base for a median filter. Thus, there is a need to get the median
94 without sorting the entire array. Therefore, other techniques with different
95 conceptions have been arisen, which do not wholly sort the array. These
96 techniques are divided into the quick selection algorithm and the median of
97 median algorithm according to their main idea of thinking.

98 2.1. Quick Selection Algorithm

99 quickselect is a selection technique to locate the k th smallest element in
100 an unsorted group. It is interrelated to the quicksort sorting technique. Sim-
101 ilar to quicksort, it was established by Tony Hoare, and as a result is also
102 recognized as Hoare’s selection algorithm [14]. Like quicksort, it is effective
103 in execution and has satisfactory average-case performance, although it has

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104 weak worst-case performance. Quickselect and its versions are the most fre-
105 quently used selection algorithm in productive real-world implementations.
106 It utilizes the same global methodology as quicksort, which considers one
107 element as a pivot, then separating the data into two groups that relied on
108 the pivot, less than the pivot group or greater than it. As a result of com-
109 paring the pivot to all other elements, the rank ‘r’of the pivot is found out.
110 The pivot is then inserted in the rth index of the array. All other elements,
111 equal to or smaller than the pivot, are located into positions before the pivot.
112 Moreover, every larger element is placed after the pivot [1]. However, instead
113 of repeating into both sides, like in quicksort, quickselect only reiterates into
114 one side, which contains the element of interest. Like quicksort algorithm,
115 quickselect is in general realized as an in-place technique, and at the same
116 time as selecting the k th element, it also partially arranges the data. This
117 degrades the order of the average complexity from O(n log n) to O(n). Nev-
118 ertheless, the worst-case situation occurs when choosing the largest or the
119 smallest element as a pivot. Consequently, each step would eliminate just
120 one element from the list, and the complexity will be O(n2 ) rather than O(n).
121 Therefore, this algorithm is a practical randomized linear algorithm for me-
122 dian finding. However, it is insufficient to have only a randomized algorithm
123 where sometimes it may be more critical to be accurate than to be fast. So
124 the median of the median algorithm has been developed, which is a linear
125 worst-case time algorithm.

126 2.1.1. Median of Median (MOM ) Algorithm

127 The median-of-medians is a predictable linear-time selection technique.
128 It was published, for the first time, in [15]], and accordingly is named as
129 "BFPRT" after the last names of the authors. In the initial paper, the algo-
130 rithm was indicated as "PICK," denoting quickselect as "FIND". The MOM
131 algorithm relies on partitioning the list into some sublists and then gets the
132 estimated median place in each sublist. Next, all medians are collected and
133 arranged into a new list, then finding out the list’s median location. It consid-
134 ers the value of the median location as a pivot then utilizes it for comparisons
135 with the other elements of the list. If an element is smaller than the pivot
136 value, the element is placed on the pivot’s left side, but if the element has a
137 value greater than the pivot, it is put to the right. The algorithm is repeated
138 on the list focusing on the value it is searching for. Despite worthy average
139 performance, the algorithm in the worst-case pivot condition is insufficient
140 for assurance exact selection in linear time [16]. Therefore, some modifica-

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141 tions are developed on this algorithm to overcome this problem, like median
142 3, median 4, and median 5. Afterward, an improvement was accomplished
143 on MOM that is recognized as REPEATEDSTEP. However, the number of
144 comparisons for nine elements list is still large, which can be calculated using
145 (1) [16].

C(n) ≤ C(n/5) + C(7n/10) + 2n (1)

146 where n is the length of the list, another modification is applied to the mod-
147 ified version. The new version is known by REPEATEDSTEPIMPROVED,
148 then again it gives a large number of comparisons that can be expressed as
149 in ( 2) [16].

C(n) ≤ C(n/9) + C(7n/9) + n + n/3 + 8n/9 (2)

150 For all modifications above, the number of comparisons for calculating the
151 median of an array with nine numbers is larger than 5n where n=9, which
152 is considered an enormous number that needs relatively massive hardware
153 and long processing time. In this context, the median of median algorithm is
154 selected as a base to the suggested techniques. Afterward, some modifications
155 have been applied on it to ensure getting the median value with the highest
156 accuracy and least number of comparators.
157 Consequently, this paper proposes two novel designs to select the median
158 of 9 elements list, referred to as Median 9, inspired by the MOM algorithm.
159 The proposed techniques are based on a refined explanation of MOM, and
160 it is partly inspired by the Odd-Even Merge Sort [17]. However, they have
161 a lower order of complexity than the Odd-Even Merge Sort technique. The
162 first proposed algorithm (ALG1) guarantees an exact selection in linear time.
163 Moreover, it dramatically reduces the number of comparators. This technique
164 provides an exact median of 9 elements array with only 17 comparators which
165 is less than 2n. Subsequently, it reduces the needed hardware resources for
166 its implementation. Aside from the precise detection, two versions of the
167 first algorithm are proposed and introduced as ALG2 and ALG3 techniques.
168 In these algorithms, the hardware requirements are more released with im-
169 provements in the processing time at the expense of a slight reduction of
170 the accuracy. Thus, they represent two different options, and the preference
171 depends on the application obligations. Besides, all the proposed techniques
172 do not restrict the array length to be of a power of 2.

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173 Furthermore, FPGA is used as a hardware accelerator to implement the
174 proposed techniques for satisfying higher processing speed. Since FPGAs
175 provide inherent parallelism. The proposed algorithms will be illustrated in
176 detail in the following sections.

177 3. The First (Accurate) Algorithm (ALG1)

Figure 1: The Comparisons in each clock cycles with swapping steps for ALG1 algorithm

178 Assuming that the pixels array, p, contains the values for all the pixels
179 in the selected 3X3 window. The pixels are represented by 8-bit numbers

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180 and located in the indices 0,1,2,3,4,5,6,7,8. The proposed algorithm which
181 aims to extract the median pixel, relies on rearranging the array to ensure
182 that the numbers in the last four locations are greater than the numbers
183 in the first five locations. So in the first step, the numbers at locations
184 0,1,2,3 are compared with their counterparts at locations 5,6,7,8 respectively.
185 Swapping processes are performed, if needed, to guarantee that (P[0]<P[5]),
186 (P[1]<P[6]), (P[2]<P[7]), and (P[3]<P[8]). Secondly, the same concept is
187 used with the array tailing half by performing the following comparisons
188 (P[5]<P[7]), (P[6]<P[8]) and doing swapping if these conditions are not ini-
189 tially satisfied. Furthermore, if the swapping between any couple of these
190 locations is done, another swapping should be done to keep the validity of
191 the reached relations. Such that, if swapping between P[6] and P[8]is oc-
192 curred then swapping between P[0] and P[2] should be performed regardless
193 of their arrangement. Similarly, for the case of P[1] and P[3] if P[5] and P[7]
194 are swapped. Thirdly, a comparison between P[7] and P[8] is executed, then
195 P[8]is undoubtedly greater than numbers at locations 0, 1, 2, 3, 5, 6, 7. So
196 P[8] will be excluded from the subsequent comparisons. However, in this
197 step if the condition between P[7] and P[8] is verified, some swapping should
198 be made (0 with 1, 2 with 3, and 5 with 6). These swapping processes are
199 necessary to keep the reached relations between the elements valid whether
200 the condition between P[7] and P[8] is fulfilled or not. In the fourth step,
201 two comparisons would be made. One of them is between elements of in-
202 dices 6 and 7 to throw the element of index 7 from the comparisons after
203 ensure that element number 7 is more significant than 0, 1, 2, 3, 5, 6. The
204 other one is needed to include index 4 in the sequence of comparisons, and it
205 will be between P[3] and P[4]. The following steps are processed to let P[4]
206 larger than its left side elements and less than its correct side elements. The
207 sequence of comparisons for this technique is illustrated in Fig 1.
208 This algorithm includes seventeen comparisons which are executed in ten
209 clock cycles, and it detects the median number of a nine elements array with
210 an accuracy 100%. Some modifications can be applied to this technique in
211 order to reduce the required number of clock cycles. However, in all of these
212 versions, the accuracy will be decreased too. The hardware architecture of
213 this technique is shown in Fig. 2.
214 The results of applying the ALG1 ALGORITHM on two noisy images
215 are portrayed in Fig.3. One can deduce that the salt and pepper noise are
216 significantly eliminated.

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 Figure 2: The hardware implementation of the ALG1 algorithm

217 4. The Second Proposed Algorithm (ALG2)

218 Another technique is suggested in the march towards more reduction of
219 the total required comparisons and the execution clock cycles. This tech-
220 nique is firmly grounded in fulfilling one hypothesis, P[7] and P[8], after the
221 third clock cycle, are greater than the array median number. By running ex-
222 tensive numerical simulations under various examples, the probability of this
223 assumption’s validity is greater than 97%. The Hardware implementation,
224 in addition to the progression of the comparison and swapping steps for this
225 technique, is depicted in Fig. 4.
226 In this technique, the first and second steps are the same as those in
227 the first technique. Depending on the assumption above, the elements at
228 P[7] and P[8] are kept out from the following comparisons. In the third
229 step, a comparison between P[5] and P[6] is made to determine which ele-
230 ment will need only one comparison and then be thrown out of the following
231 comparisons. Also, in the third clock cycle, another comparison between
232 P[2] and P[4] is executed, where one of the advantages of the hardware im-
233 plementation that multi-comparisons between different stores and swapping
234 their values can be performed without any conflict in memory. An extensive
235 numerical simulation has been run under various conditions to the grantee
236 that these assumptions are sufficiently satisfied. In the light of the previous
237 postulations, step four includes a comparison between P[4] and P[6], then
238 a rearranging is made between the elements in the following indices 4, 5,

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 Figure 3: a: The original images, b: The images after adding salt and pepper noise, c:
The noisy images after applying the proposed technique

239 and 6. Where P[5] in place of P[4], P[6] in place of P[5], and finally P[4] in
240 place of P[6]. Afterward, there will be six elements only for the remaining
241 comparisons, and the comparisons will continue until the grantee that P[4]
242 is larger than all elements except P[5]. In step five, a comparison between
243 elements of indices 3 and 5 is executed. Next, in step six, a comparison is
244 made between indices 1 and 3. Accordingly, if the condition is true, swapping
245 will be between indices 1 and 3; otherwise, swapping will be between indices
246 2 and 3. In the seventh step, two comparisons are made: between indices
247 2 and 4, and the other is between indices 3 and 5. The last step includes
248 comparing indices 3 and 4, so if the condition is satisfied, the median is at
249 index four; otherwise, another comparison will be executed between indices
250 4 and 5. As a result, the median is at index 4. The error can occur when the
251 1st assumption does not fulfill.
252 The result of applying this technique on two different graphs is presented
253 in Fig.5. The figure includes the original, noisy, and denoise plots. This
254 technique can deduce the median number after nine clock cycles using only
255 fifteen comparisons with accuracy equals 87%. On the other hand, in ex-
256 ploiting this technique for noisy grayscale images, the accuracy is improved
257 to 96% because of the grayscale pixels convergent scaling.

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 Figure 4: The hardware implementation of the second technique

258 5. The Third Proposed Algorithm (ALG3), for Generating the

259 Maximum of an array of 9 elements
260 In many modern applications, such as max-pooling in convolution neural
261 networks, there is a need to obtain the maximum of nine elements array [18].
262 The same concept can be used but with limiting the swapping processes to
263 the compared elements only. The earliest three steps will be used, and after
264 those, there is a grantee that index 8 is greater than indexes 0,1,2,3,5,6,7 so
265 that the last step will be a comparison between P[4] and P[8]. As a result,
266 the max number of a nine elements array will be determined after four clocks
267 with eight comparisons only. The hardware implementation of the Maximum
268 algorithm is exposed in Fig. 6.

269 6. Simulation and Results

270 The proposed algorithms were implemented using Hardware Description
271 Language, VHDL, and simulated using Xilinx ISE 12.2, Xilinx EDK 12.2, and
272 Modelsim 6.6c tools with hardware experiment’s environment Xilinx Virtex-5
273 LX110T board. The FPGA implementation environment provides an attrac-
274 tive combination of apparent flexibility, high performance, and low-cost prop-
275 erties. The structure of proposed techniques mainly comprises comparator
276 blocks and register after each stage as shown in Fig.2, Fig.4, and Fig. 6 which

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 Figure 5: a:Original, b:noisy, c:denoisy for 2nd technique

277 support the pipelining feature. The suggested architecture for the median
278 filter depends on a sequence of pipeline stages to reduce the computational
279 time. Hence, any algorithm’s hardware architecture is used as a building
280 block, identified as "median 9 block", in the median filter architecture.

Table 1: A comparison among the different algorithms

Proposed ALG1 Proposed ALG2 [1] [19]

Accuracy 100% 87% 93% 93%
Comparators 17 15 19 19
Frequency (MHz) 389.2 400.1 100 N/A∗
Clocks 10 9 3 N/A
Execution time (ns) 25.11 22.47 30 76.21
Throughput (bp/µs) 2866.32 3200 2400 N/A
Number of Slice registers 368 240 N/A 73
Number of Slice LUTs 465 314 N/A 728

281 A detailed comparison between the first proposed design, the second one,
282 and the design published in [1] is illustrated in Table. 1. From the simulation
283 results, it can be deduced that our proposed filter, using the first algorithm,

13
 Figure 6: The hardware implementation of Max technique

284 requires ten clock pulses with 398.2 MHz maximum operating frequency to
285 find out the median value with 100% accuracy. This provides an improvement
286 in the processing time than the filter proposed in [1], although the technique
287 proposed in [1] needs only three clock pulses but with 100 MHz maximum
288 operating frequency. Moreover, the accuracy is enhanced by 7%, and the
289 execution time is reduced by more than 16%. Besides, by comparing the first
290 proposed technique with the designs investigated in [20, 19, 21, 22, 2], more
291 than 10% improves the hardware of each median block because it needs only
292 seventeen compactors instead of nineteen.

293 7. Conclusion
294 The flexibility, high performance, and low-cost features of the FPGA
295 and hardware implementation are utilized to develop the high-speed, low
296 area, and high accuracy median filters. The hardware results showed that
297 these proposed algorithms have enhanced and comprehensive output results
298 compared to standard median techniques as well as the adaptive median

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299 algorithm. Hence, they have suitable applications prospect in real-time image
300 processing and meet the different applications’ requirements.

301 References
302 [1] K. S. Raju, P. Phukan, G. Baurah, An fpga implementation of a fast 2-
303 dimensional median filter, in: National Conference on Recent Advances
304 in Communication, Control and Computing Technology,RACCCT 2012,
305 2012, pp. 144–147.

306 [2] C. Priyanka, Median filter algorithm implementation on fpga for restora-
307 tion of retina images, International Journal of Innovative Science, En-
308 gineering and Technology 3 (2016).

309 [3] L. Liang, S. Deng, L. Gueguen, M. Wei, X. Wu, J. Qin, Convolutional

310 neural network with median layers for denoising salt-and-pepper con-
311 taminations, arXiv preprint arXiv:1908.06452 (2019).

312 [4] H.-Y. Yang, X.-Y. Wang, P.-P. Niu, Y.-C. Liu, Image denoising using
313 nonsubsampled shearlet transform and twin support vector machines,
314 Neural networks 57 (2014) 152–165.

315 [5] M. Lebrun, M. Colom, A. Buades, J.-M. Morel, Secrets of image de-
316 noising cuisine, Acta Numerica 21 (2012) 475.

317 [6] L. Shao, R. Yan, X. Li, Y. Liu, From heuristic optimization to dictionary
318 learning: A review and comprehensive comparison of image denoising
319 algorithms, IEEE transactions on cybernetics 44 (2013) 1001–1013.

320 [7] R. Gonzalez, R. Woods, Image processing. digit, Image Process 2 (2007).

321 [8] B. Goyal, A. Dogra, S. Agrawal, B. Sohi, A. Sharma, Image denois-

322 ing review: From classical to state-of-the-art approaches, Information
323 Fusion 55 (2020) 220–244.

324 [9] J. L. Bentley, M. D. McIlroy, Engineering a sort function, Software:

325 Practice and Experience 23 (1993) 1249–1265.

326 [10] H. A. David, H. N. Nagaraja, Order statistics, Encyclopedia of Statis-

327 tical Sciences (2004).

15
328 [11] A. Rauh, G. R. Arce, A fast weighted median algorithm based on quick-
329 select, in: 2010 IEEE International Conference on Image Processing,
330 2010, pp. 105–108. doi:10.1109/ICIP.2010.5651855.
331 [12] Y. Ben Jmaa, R. Ben Atitallah, D. Duvivier, M. Ben Jemaa, A com-
332 parative study of sorting algorithms with fpga acceleration by high level
333 synthesis, Computación y Sistemas 23 (2019) 213.
334 [13] R. Sedgewick, Algorithms in Java, Parts 1-4, Addison-Wesley Profes-
335 sional, 2002.
336 [14] H.-K. Hwang, T.-H. Tsai, Quickselect and the dickman function, Com-
337 binatorics Probability and Computing 11 (2002) 353–371.
338 [15] M. Blum, R. W. Floyd, V. Pratt, R. L. Rivest, R. E. Tar-
339 jan, Time bounds for selection, J. Comput. Syst. Sci. 7 (1973)
340 448–461. URL: https://doi.org/10.1016/S0022-0000(73)80033-9.
341 doi:10.1016/S0022-0000(73)80033-9.
342 [16] A. Alexandrescu, Fast deterministic selection, arXiv preprint
343 arXiv:1606.00484 (2016).
344 [17] S. Sadangi, P. Priyanka, Fpga implementation of parallel sorting mech-
345 anism for turbo decoding in lte system, in: 2018 Second International
346 Conference on Inventive Communication and Computational Technolo-
347 gies (ICICCT), 2018, pp. 359–362. doi:10.1109/ICICCT.2018.8473025.
348 [18] B. Graham, Fractional max-pooling, arXiv preprint arXiv:1412.6071
349 (2014).
350 [19] A. H. Rasheed, Fpga-based optimized systolic design for median filtering
351 algorithms, International Journal of Applied Engineering Research 12
352 (2017) 16100–16113.
353 [20] M. A. Vega-Rodríguez, J. M. Sánchez-Pérez, J. A. Gómez-Pulido, An
354 fpga-based implementation for median filter meeting the real-time re-
355 quirements of automated visual inspection systems, Proc. 10th Mediter-
356 ranean Conf. Control and Automation (2002).
357 [21] A. Eric, Fpga implementation of median filter using an improved al-
358 gorithm for image processing, International Journal for Innovative Re-
359 search in Science & Technology 1 (2015) 25–30.

16
360 [22] S. Maurya, I. Gupta, Fpga based hardware implementation of median
361 filtering and morphological image processing algorithm, International
362 journal of engineering research and technology 3 (2014).

17