‘ational Logic Circuits coms i 2 pLisa conceptually simple and modul 281 : ) ar logic Style. Its applicabiy; ppli arongly upon the logic funetion tobe Implemented, The al me hs vanes well of the ease ofimplementing Specific gat ‘ aos sn ; € structures makes it ipliers, some qitractive for structures such as adders and multi 9 pOWER DISSIPATION 4 @ static CMOS gates are very power-efficient and ige neatly CMOS desi, Speedand area ofthe chip wasthe major consideration wher wor was only secondary. As the transistor Count an oe id clock frequenc . ‘ ‘ 'y has reduced, th power consumption has increased greatly and is ow a major design constraint ake Instantaneous power P(t) drawn from the power uret ig (t) and the supply voltage Vie PO= tpp © Yop [the energy consumed over some time interval] power. dissipate almost ZeT0 power when Supply is proportional tothe supply is the integral of the instantaneous E=[in Vp dt é ~ The average power over this interval is la, TT h ipp (t) Vpp at Power dissipation in CMOS circuits comes from two components: Pavg = Dynamic dissipation due to 4 Charging and discharging load capacitances as gates switch Short-circuit” current while both pMos and nMOS stacks are partially ON me Static dissipation due to Subthreshold leakage through OFF transistors Gate leakage through gate dielectric Junction leakage from source/drain diffusions S\N NV NAY Contention current in ratioed circuits Putting this together gives the total power ofa circuit P wax P, oat Poatic* PaynamidA LSI AS 2nd Chip Des, 8 ASA Static Dissipation pMos Fri L pMos nMOS ~ nMOS Vv Figure 2.61 CMOS inverter model re $ The above diagram shows a CMOS inverter model for static Power dissipation evaluation. > (Consider input=0, Y nMOS transistor is ON Y — pMOS transistor is OFF Y output vottage is 0V (GNs)’ Note: One of the transistors is always OFF when the gate is in either of the logic States, No current flows through the OFF transistoy the circuit is quiescent, ive. when no transistors are Switching, Zero quiescent power dissipation isa principle advantage Of CMOS over, Competing transistor technologies. However, Secondary effects including sub-threshold conduction, tunneling, and leakage lead to small amounts of; static current flowing through the OFF transistor, Assuming the ‘and average Power are the Same, the static Power dissipation is the product of total Heakage current and the Supply voltage. V, 80 the power, dissipation is zero when Pate “Tyatc DDCombinational Logic Circuits 2.69 2 Dyhamic Dissipation The primary-component of dynamic power dissipation is charging the load capacitance. Suppose a load C is switched between GND and V,,, at an average frequency f.,,, ver any given interval of time T, the load will be charged and discharged ‘Tf,,,times. Current flows from V.,, to the load to charge it. Then current flows from the load to GND to discharge. In one complete charge/discharge cycle, a total charge of Q=CV,,, is thus transferred from V,,, to GND.) “ The average dynamic power dissipation is T. vi inp (0) dt P synamic = ; iipp (© Yop 4 = “pp. b Taking the integral of the current over time interval T as the total charge delivered during that tume, we can simplify to P dynamic = XP ffzy CoD} = CV yy? spe r Because most gets dg not switch every clock cycle, it is of ten more convenient xpress, switching frequency f,. as an activity factor o, times the clock frequency. Now the rewitten as: Paynamic = @CV 2S | Exampl, 0