7/18/23, 8:30 PM Place and Route Design Flow Overview

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Working With the Fusion Compiler Tool > Place and Route Design Flow Overview

Place and Route Design Flow Overview

Figure 1 shows the basic place and route design flow using the Fusion Compiler tool.

Figure 1: Fusion Compiler Place and Route Flow

To run the Fusion Compiler place and route flow,

1. Set up the libraries and prepare the design data, as described in Preparing the Design.

2. Perform design planning and power planning.

When you perform design planning and power planning, you create a floorplan to determine the
size of the design, create the boundary and core area, create site rows for the placement of
standard cells, set up the I/O pads, and create a power plan.

For more information about design planning and power planning, see the Fusion Compiler Design
Planning User Guide.

3. Perform placement and optimization.

To perform placement and optimization, use the place_opt command.

The place_opt command addresses and resolves timing closure for your design. This iterative process
uses enhanced placement and synthesis technologies to generate legalized placement for leaf cells
and an optimized design. You can supplement this functionality by optimizing for power, recovering
area for placement, minimizing congestion, and minimizing timing and design rule violations.

For more information about placement and optimization, see .

4. Perform clock tree synthesis and optimization.

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7/18/23, 8:30 PM Place and Route Design Flow Overview

To perform clock tree synthesis and optimization, use the clock_opt command.

Fusion Compiler clock tree synthesis and embedded optimization solve complicated clock tree
synthesis problems, such as blockage avoidance and the correlation between preroute and
postroute data. Clock tree optimization improves both clock skew and clock insertion delay by
performing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment,
reconfiguration, delay insertion, dummy load insertion, and balancing of interclock delays.

For more information about clock tree synthesis and optimization, see Clock Tree Synthesis.

5. Perform routing and postroute optimization, as described in Routing and Postroute

Optimization.

The Fusion Compiler tool uses Zroute to perform global routing, track assignment, detail routing,
topological optimization, and engineering change order (ECO) routing. To perform postroute
optimization, use the route_opt command. For most designs, the default postroute optimization setup
produces optimal results. If necessary, you can supplement this functionality by optimizing routing
patterns and reducing crosstalk or by customizing the routing and postroute optimization functions
for special needs.

6. Perform chip finishing and design for manufacturing tasks, as described in Chip Finishing and
Design for Manufacturing.

The Fusion Compiler tool provides chip finishing and design for manufacturing and design for yield
capabilities that you can apply throughout the various stages of the design flow to address process
design issues encountered during chip manufacturing.

7. Save the design.

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