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Manual de Instrução Drive DCD - 1
Manual de Instrução Drive DCD - 1
DATA PRODUCTS ~m
DCD-1
DATA CARTRIDGE DRIVE
INSTRUCTION MANUAL
LIST PRICE $7.50
C/N 681-3540-9470-8 ISSUE 2
TABLE OF CONTENTS
APPENDIX
Page
May 1977 ii
LIST OF TABLES
Table Page
May 1977 iv
SECTION I. INTRODUCTION
1-1 SCOPE 1-2 GENERAL DESCRIPTION
This manual describes the OCD-l Data Cartridge Drive The OCD-I Data Cartridge Drive has been designed for use
along with its operation, interface, use, mounting, and with the "Scotch" Brand OCI00A Data Cartridge. The
maintenance. drive and cartridge provide a tape storage system capable of
recording and reading approximately 100,000 eight bit
bytes in a physically small, highly reliable unit.
I nterboard Cable
Read/Write Amplifier
and Servo Electronics
PC Assembly
CA-5 83-0003-0972-0
Customer Interface Cable
Cartridge Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102,400 bytes, average (256 bytes per block, 1 inch IRG)
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .
Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Drive
5-3/4" wide (14.6 cm)
4" high (10.2 cm)
4-1/2" deep (11.4 cm)
Electronics
Two 5" x 12" cards
(12.7 x 30.48 cm)
NOTES:
.468-.. ---4.47---~
1. . . .
~~~~~ltt--·-
b ]0 -rl
1. . . . .
J25 3.98
439
.188
l~-~
2.025 .587
J 1
1.11
L .86 84
--i
~o~~_. 1
3.
01----- --~-- 1.50 MIN.
II.....-_. _ _ _ _ ~~-----~
FRONT VIEW TOP VIEW
~;-d~E·-::5
.15
~ 14------6.307
~l:
-----10.850
f.+.---------------11.15
3-t:·307 • ..
•
II ,-
.15
Figure 2-2. Mounting Dimensions for Encode/Decode and Servo Electronics Read/Write Amplifier PC Assembly
0 0 1=7 -
.375
~
L. Ht>-
.375 O I 3%
2.625
I·
1.187
H~
I
I
....
i. ~~
i
()
- - - - ()
Ii
~- ~
~
~ ~
"-~H
.281
t
I~.----5%-----.,.1
I.I 5.375 .1I
The OCD-l mechanical assembly may be mounted in any input. This prevents any possibility of motor movement
attitude. As shown in Figure 2-1, the unit may be secured during the power up cycle. When removing power, turn off
at the three ears of the top plate casting. Or if desired, the the +5 VDC input first.
shipping bracket, used to protect the motor, may be used
as a mounting frame. Location of holes for mounting in 2-3 INTERF ACE LOGIC
this frame are shown in Figure 2-1 and 2-2. Note that the
top plate casting can be secured to the mounting frame in All inputs and outputs of the DeD-l are TTL compatible
two different positions as shown in Figure· 2-3. In the for- with 0 to +0.8 VDC = logic 1 =low and +2.5 VDe to +5.0
ward position, the frame can be attached to a front panel VOC = logic 0 = high. The read data output is from 74125
by through-bolting. In the recessed position, the frame can tri-state drivers. The write data input goes directly to 74100
be attached to studs welded to the back of a front panel. latches. All other outputs are from either 7416 or equiva-
lent open collector buffer drivers. All inputs go to 7404 or
equivalent gates. Except for select 0 and 1, which go to a
Figure 24 illustrates cable modification procedure for 74155 2 line to 4 line decoder.
connecting one or more salve units to a master. Electrical
interconnection of the three subassemblies is accomplished Recommended logic interfaces for the DCD-l are as shown
as shown in Figure 2-5. The two PC Assemblies may be in Figure 2-6. When less than 4 feet of cable is used, the
mounted up to 12 inches away from the mechanical 220 ohm/330 ohm resistor terminations may be replaced
assembly. All connectors are keyed to prevent improper with lK ohm pull ups if desired.
interconnection.
2-2 POWER APPLICATION The interface signals of the OCD-l and their functions are
as described below. Details concerning the use of these
When applying power to the DCD-l, the +12 VDC power signals are presented in various sections dealing with spe-
should be applied prior to application of the +5 VDC power cific operations.
Smooth Side
of Cable
oeo-, Master Unit
Notch Insulation
Note*
Housing
Note*
To connect one or more OCO-1 slave units into a system add
connector kit 83-0003-1027-2 to 26 conductor cable as follows:
1. At the desired location on the cable where plug is to be added, score the insulation on the shielding side of the
cable (smooth side) to enable removal of 3/4" of insulation and shielding. Peel the insulation from the shield,
then peel the shield from the cable.
2. Cut sufficient amount of insulation from each side of cable to allow acceptance of the plug to be installed,
taking care not to cut into edge conductors.
3. Align plug on the prepared area of the cable, smooth surface to plug connectors.
4. Compress the cable between the plug and the plug plate. (If connector tool is not available for compressing
connectors on the cable, a vice may be used.) Top plate should be even with plug tabs when connector is prop-
erly seated.
Figure 2-4. Connecting One or More Slave DCD-! Units into a System
~C07
KEYED BETWEEN END
CONTACT NO. END SENSE CABLE SENSE
COO / 4AND6 10 CONDUCTOR FLAT CABLE (28 GAUGE)
C02 C01
3M #3365/10
______________________________________________________________
1
~
~
1
0
9
26 CONDUCTOR
FLAT CABLE J1A
CA1 J1A
3M #3469/26 J1B J1B
C01 C01
CA4
2 1
~2~1~~.--------------------10CIRCUITSOCKETCONNECTOR-------------------'.~~2~1 l-l
3M #3473-0000
26
DATA
CONTROL
INTERCONNECT
CABLE
.J MOTION
CONTROLI
KEYED ON CONTACT 7
KEY 3M #3435-0000
LOGIC RWAMP
<
#08-56-0110 >
> r LJ
28 AWG 3 CONDo SHIELDED
DEARBORN 942803 U J4
>--------.. .
1 'l)4 3 2
Ls CIRCUIT CONNECTOR
KEYED ON PIN 2
MOLEX #22-01-2051 NORTRONICS SINGLE PIN CONNECTORS
HEAD CASE
50
CA5
J5
:>
>
:>/
~
r'\
I
I
I
I
RED
BLK
CLR
22 AWG3CONDUCTOR
CABLED, SHI ELDED,
.r'\.
I
I
I
I
I
I
2;;.
4>
Lff >4>------1-
'7
3;;.
~ 00000' ,
>-1~_____--t~__....,
>2~_ _ _.......... OJ
CUSTOMERINTERFACE~
J3 \L ALPHA WIRE # 2403 rh
L . . 5 CIRCUIT CONNECTOR KEYED AT POSITION 1
MOTOR CASE
MOLEX #22-01-2051 WITH 08-56-0110 TERMINAL
C06 KEY MOLEX # 15-04-9209
CONNECTOR VVVVV
50 CIRCUIT CARD DISPLAY OPTION
EDGE CONNECTOR 4 CI RCUIT CONNECTOR 4 CIRCUIT CONNECTOR
CONNECTOR
3M #3415-0001 5 CIRCUIT MOLEX #09-50-3041 WITH 08-56-0108 TERMINAL MOLEX #09-90-1041
KEYED BETWEEN
MOLEX #22-01-2051
CONTACT NO.8 AND 10
KEY #3439·0000 C012 '--______________......... ~TERMINAL #08-56-0110
C013 I I
L-_ _ _ _ _ _ _ _ _ _ _ _~
50 CIRCUIT SOCKET
CONNECTOR
3M #3425-0000
50 CIRCUIT RIGHT /
ANGLE HEADER . - - - . /
3M # 3433-1 002
Figure 2·S. Interconnecting Cables
Flat Cable
NOTE: For short line «4 feet) these lines could be driven from aMOS tri-state driver.
Such as is used in some microprocessor systems.
7416 or Equivalent
Flat Cable
7404 or Equivalent
Flat Cable
7404 or Equivalent
Input to Driver
NOTE: For short lines «4 feet) each line may be pulled up with a single 1 K resistor to
+5V and driven by a MaS or standard TTL output. (Remove the 220 - 330 ohm
network in tape drive (RN1) and replace with a 1 K network.)
24 May 1977
24-1 STATUS OUTPUTS 24-24 RESET
Two lines which give data relating to tape position and A low going pulse on this input causes the READY input to
operational status of the drive. These outputs are: go low regardless of tape position. This line is used to clear
drive logic after a power interrupt. If tape is in motion
when the RESET pulse is applied, tape motion will halt.
24-1-1 BEGINNING OF TAPE (BOT) RESET should be a pulse of 500 nanoseconds minimum
duration and should be held low until power is completely
A low level output that occurs when tape is at BOT. A up. Note that RESET clears system logic and forces the
reverse direction motion command will not be accepted READY output to the true (low) state. Consequently, im-
when tape is at BOT. proper use of the RESET input (stopping at EOT, apply.
ing a reset pulse, commanding forward tape motion, and
repeating this sequence) could cause damage to the cart-
2-4-1-2 READY ridge. It is therefore recommended that after applying a
RESET command, the cartridge be rewound to BOT
An output that is low during read operations when tape is before commencing further operations.
between LOAD POINT and EARLY WARNING. See Fig-
ure 2-8. During write operations, the cartridge file protect
slide switch must be in the RECORD position and the tape 24·3 SELECT 0 AND SELECT 1
must be between LOAD POINT and EARLY WARNING
for READY to go low. These two lines are used to select the active drive in
multiple drive systems according to the following table:
I
(4 Lines)
Unit
1t t t Select
(2 Lines)
A low going pulse on this input causes information on the Pin Function
data bus to be strobed into the write buffer. This pulse
must be at least 500 nanoseconds but no greater than 1.5 1 + 12 VDC (Not Used)
microseconds long. (The LOAD WRITE BUFFER pulse 2 Ground
must occur less than 320 microseconds after WRITE 3 +5 VDC ±5% 1.5 Amps
BUFFER EMPTY goes low.) The LOAD WRITE BUFFER 4 Ground
pulse also clears the WRITE BUFFER EMPTY output 5 + 12 VDC (Not Used)
flag.
Once the cartridge has been inserted into the drive, the l1rst 7. Monitor the WRITE BUFFER EMPTY output. When
command issued must be for reverse motion (this is the this output goes true place the next byte to be writ-
8. Alternate between monitoring the READ BUFFER The only periodic maintenance required on the DCD-l is
FULL and INTERRECORD GAP flags. cleaning of the tape head and motor drive roller.
9. If READ BUFFER FULL goes low, return to Step S. These items should be cleaned with ethyl alcohol and a
cotton swab every 1,000 to 1,500 cartridge cycles. A cycle
10. If INTERRECORD GAP goes low, wait 5 milli- is defined as tape movement from BOT to EOT and back to
seconds and apply a pulse to the STOP input. Wait BOT.
20 milliseconds for tape motion to stop before issu-
ing further commands. A continuous read is accom- In harsh environments cleaning may be required more fre-
plished by not issuing the STOP pulse. quently.
The only periodic maintenance required on the mechanical 3-1-2-2 EOT-BOT BULB REPLACEMENT
assembly is cleaning of the tape head and the drive puck.
This cleaning operation should be accomplished every 1. Remove the two front bezel mounting screws.
1,000 - 1,500 tape cycles. In harsh environments, cleaning
on a more frequent basis may be required. 2. Remove the front bezel.
Cleaning should be accomplished with a cotton swab mois- 3. Unplug the cable from the EOT/BOT PC Board.
tened with ethyl alcohol by gently rubbing the head and
then the drive puck. 4. Remove the two rail mounting screws (left rail).
EDT/BOT PC
Assembly
Front Bezel
Mounting Screws
Figure 3- t. EOT/BOT Bulb Replacement
Mounting Screws
7. Remove Phillips mounting screw and plastic insula-
tion washer from the EOT/BOT PC Assembly.
Pivot
Clamp
8.
V
Remove the EOT/BOT PC Board and switch assembly
~tor
from the block.
9. Unsolder the old bulb from the board and clean the
solder from the holes. I/~V~
10. Place the new bulb leads through the holes and insert
the bulb fully into the block as the PC board is again -__"'\\\\1..< /'
fitted to the block. Secure with the Phillips mounting Power Cable
.~
screw and insulating washer.
11. Solder bulb leads with the bulb located all the way
into the block.
Motor Assembly I
12. Reverse the disassembly procedure from Step 6
i
through Step 1.
I
1
3-1-2-3 MOTOR REPLACEMENT
See Figure 3-2
3. Remove the two motor pivot mounting screws. Figure 3-2. Motor Replacement
6. Remount the motor using the screws and pivot hold 3-1-2-4 HEAD REPLACEMENT
down clamps. See Figure 3-3
7. No end play is permissible in the motor pivot mount. 1. Loosen the head clamp screw sufficiently to allow the
Secure one pivot clamp and force the other pivot pin head to be removed.
into the motor mount, tighten the second pivot
clamp. If end play is not completely removed, loosen 2. Be sure the new head has one wrap of mylar tape
one pivot clamp and force the pivot pin in, then re- around the body of the head to give insulation be-
tighten the clamp screw. tween head and the mounting bracket.
--------------
From Mechanical Assembly
WP CT HD HD
RWC RWC
!
Write
STP
RUN Drive
- Enable
Select WE
WD Logic
FIR WD HD
Write
Head Read Threshold
EN 0 t Driver
HD Amplifier Detector
EN 1
EN 2 RD Peak
Detector
EN 3
RST FWD
Command
Status REV
Interlock
I~ !£!1
From I!£.!. Status
Decode PC2 ---.,.-'
Mech <
Assembly C IN Logic To Servo Electronics
CIN
FP
BOT ROY RD
Drive Select
Logic
!!!
BOT ROY RD
Figure 34. Block Diagram - Drive Logic, Direction Control and Read/Write Amplifier
The status of this line detennines the direction of the An input from the Photocell Amplifier PC Assembly. Mo-
tape motion. A high level causes forward motion while mentarily high when a hole passes by the Photosensor. Used
a low causes a reverse motion when the RUN input pulse along with Photocell 2 to develop the various tape position
is applied. outputs. A hole in the tape passes by Photocell 1 before
Photocell 2 when the tape is moving in the forward direc-
tion.
3-2-6-5 RUN
- Automatic
Error
Switch Switch 2
~
Amplifier
Select ~
--
~ Driver 1
Forward
Reference
~
Reverse Amplifier
I f Mechanic
To Mota r
Bridge al
Assembl y
I
4~
Error
+ Amplifier Driver 2
I.....-
Back EMF Switch 1
Amplifier
One gate is provided with the WRITE DATA and the ABBREVIATION
other with WRITE DATA. The output of those two gates USED ON
(ICll, pin 11, ICll, pin 3) are then routed to the open col- SIGNAL SCHEMATIC PIN
lector drivers (lC 17, pin 9 and pin 11) which drive the tape
head. Photoce112 PC2 2
Photocell 1 PCl 4
Cartridge IN CIN 3
File Protect FP 5
3-2-11 READ CIRCUITRY
Ground GND 1
+ 12V Endsense +12V 9
The Read Amplifier section accepts the low level read data
Key Key 7
from the tape head and amplifies this signal to a nominal
+5V +5V 6
2.0 V pop level (ICI8, pin 6).
Write Protect WP 10
Cartridge COT 8
This amplified data is then clipped at a 28 percent level by
the threshold detector (lCI9, pin 14) to remove any back-
ground noise from the signal.
The peak detector senses peaks in the amplified signal and Table 3-3. Connector Pin Assignments
produces a TTL compatible reproduction of the data (lC 19, Servo Electronics and READ/WRITE
pin 1). Amplifier PC Assembly
J2 Head Connector
ABBREVIATION
USED ON
SIGNAL SCHEMATIC PIN
Table 3-1. Connector Pin Assignments
Servo Electronics and READ/WRITE Center Tap CT 3
Amplifier PC Assembly Head HD 5
CO 1 Connector Head HD 1
Shield SHLD 4
ABBREVIATION Key Key 2
USED ON
SIGNAL SCHEMATIC PIN
Table 3-6. Connector Pin Assignments The Servo Null Pot (R69) and the Motor Speed Adjust Pot
Servo Electronics and R/W Amplifier PC Assembly (R70) will require adjusting whenever components are
J 5 Motor Connector changed in the Reference or Back EMF Amplifiers. When-
ever these adjustments are made, they should be made
ABBREVIATION after the motor balance adjustment has been made.
USED ON
SIGNAL SCHEMATIC PIN
Reference Amplifier Null Adjust
Motor MTR 4
Motor MTR 5 1. Connect a VTVM or digital voltmeter between test
Shield SHLD 2 points TP2 and TP4, at J4 on the motion control
Sensing Coil SENS 3 board.
Key Key 1
2. Adjust R69 for zero volts (±5 mv) while the servo
3-2-12 MAINTENANCE system is operational. Whenever the Null R69 is ad-
See Figure 3-6 justed, the speed adjustment should be checked.
3-2-12-1 Motor Control Alignment Procedure The speed of the motor may be measured by using a
Motor Balance Adjustment 1600 frpi calibration test tape and a counter. Adjust
(a) Connect Motor cable to motor and motion control R70 to give 24 kHz at pin 5 on the COl connector.
PC Board connector (15). Another method is to use a stop watch to time the
length of the READY status output, while running a
(b) The following test fixture should be constructed to cartridge from BOT to EOT. 56 seconds is the proper
properly balance the Servo Bridge. time interval.
;;,.-------8
5::~~c~~~~~~-o-n-1w-_-_-_-~~~~~~l---;llt--l-*
ITP
IIIIIIII
1 2 3 I 4 0
5 6
J4 A,B
7 8
~ ~
I I !
L_J
:
L_..J
Figure 3-6. Motion Control R/W Amp Circuit Board, Test Points and Adjustment Potentiometers
R71
Gate
Enable
Servo Generator Read Bus
Electronics & (+128) Enable
ReadlWrite
Amplifier (Clear)
PC Assembly Intercharacter
Read Flag ~R ead Buffer
F ull
Gap
Logic
--
,)
~
Start
-
Stop
Encode Shift Parallel
to Serial
-- }
Write
Data
Timing ~
Input
Control Converter I
~
Character
Present
~
1
~
I
(Clear)
Write Flag
Logic
t Load Write
Buffer
Write Buffer
Empty
SYMBOL USED
FUNCTION ON SCHEMATIC PIN 3-3-2 VARIABLE CELL WIDTH RECORDING
Data 0 DATA 0 36 Variable cell width recording derives its name from the fact
Data 1 DATAl 38 that a given bit cell varies in width according to whether a
Data 2 DATA 2 44 "1" or a "0" is being recorded. As shown in Figure 3-8, a
Data 3 DATA 3 46 bit cell consists of two pulses, a timing pulse of length t
Data 4 DATA 4 42 followed by a data pulse of length t if the bit is a "0" or
Data 5 DATA 5 40 length 2t if the bit is a "1".
Data 6 DATA 6 50
Data 7 DATA 7 48
Read Bus Enable RDBEN 18
Interrecord Gap IRG 24
Write Buffer Enable WBE 22 I 1 111010101 110101 I0I 1 I
Load Write Buffer LWRTE 4
Read Buffer Full RBF 28
Incomplete Character ICC 26 --11 I.-OATA PULSE
Ready RDY 20 ~ ~TIMING PULSE
Beginning of Tape BOT 30 I- BYTE 1 _14 ICG.f..BYTE 2~
Reset RST 14
Forward/Reverse F/R 12 Figure 3-8. Variable Pulse Width Recording Format
Run RUN 2
Stop STP 16
Read Write Control RWC 10
Select 0 SEL-O 6
Select 1 SEL-l 8 When writing data, the length of the timing and data pulses
is derived from a crystal oscillator. Implementation of the
read decode function is as follows:
3-3 ENCODE/DECODE PC ASSEMBLY 1. When the first transition of the timing pulse occurs, a
counter is cleared and begins counting in a positive
3-3-1 DESCRIPTION direction at frequency f (7.665 mHz).
See Figure 3-7
2. At the next transition, which ends the timing pulse,
The Encode/Decode PC Assembly provides a serial byte the counter begins counting in a negative direction at
oriented (eight bit parallel) data interface for the user. frequency 0.8f (6.132 mHz).
During write operations the assembly accepts bytes to be
written and converts these bytes to a serial bit stream in 3. At the final transition of the bit cell, the counter con-
Variable Cell Width format (described in paragraph 3-3-2) tents are sampled. Since counting in the negative
for use by the Read/Write Amplifier PC Assembly. direction is accomplished at a lower frequency when
counting up, the counter will contain a positive num-
During read operations, the assembly accepts data from the ber if the recorded bit was a "0" and a negative num-
Read/Write Amplifier PC Assembly in a TTL compatible, ber if the recorded bit was a "I".
Variable Cell Width format and decodes this information
into an eight bit byte (high for a "Zero", low for a "One") This encode/decode technique can tolerate a total speed
for output to the user. variation of ±20% in the drive mechanism without causing
subsequent read errors or impairing the ability to inter-
Further, the assembly contains an Interrecord Gap Detector change data between drives.
and Error Detector with associated output flags.
As shown in Figure 3-8, each stream of recorded data ends
Also, the assembly contains a Select Decode function which with a timing pulse so that this encode/decode technique
allows one Encode/Decode Assembly to operate with up to may permit read reverse operation. Although read reverse is
SYMBOL USED
COl SIGNAL ON SCHEMATIC PIN 3-3-3 OPERA TION (Refer to Fold Out Schematic,
(F igure 4-7)
Write Data WD 13
Read Data RD 5 The encode/decode PC assembly operates as described
Ready ROY 3 below. A write operations timing diagram (Figure 3-9) and
Reset RST 17 a read operations timing diagram (Figure 3-10) are included
Forward/Reverse F/R 15 to aid the reader.
Run RUN 7
Stop STP 9
Read Write Control RWC 11 3-3-3-1 WRITE ENCODE
Encode 0 ENO 19
Encode 1 ENI 21 1. When the WRITE BUFFER EMPTY output flag is
Encode 2 EN2 23 low the user places an 8 bit byte (high for a "Zero"
Encode 3 EN3 25 bit, low for a "One") on the input and applies a low
Ground GND 2-26 going pulse on the LOAD WRITE BUFFER input
(IC24, pin 3).
IC2, PIN 1 LJ LJ LJ LJ LJ LJ L
IC2, PIN 3 (ENCODING DATA)
IC2, PIN 2
IC2, PIN 6 LJ LJ LJ LJ LJ LJ L
IC1,PIN1&4
ICl, PIN 5
IC16, PIN a
.... ----......
1 o o o 1 o o o o o o
LJ LJ ~~------------------------------------------------------------
____________ ~r_1~ ___ ~r_1~ ______________________________________ ~r_l~ ___ ~r_l~ ______________ ~r_l~ _________________________________________________________
LJ LJ LJ U LJ
.... ......
o o 1 1 o o o o 1 o o 1
BYTE 1 leG
~~---- ----~-------
BYTE 2
--~~~----- ........ --~~-----
IRG
........ --~~
(DECODED DATA) IC9, PIN 7 ______ ~rl~ ____ ~rl~ _______________________ __________
rl~ ~r1~ _________________________ ____
rl~ ~r1~ ___________ ____
r1~ ~rl~ _________________________________
(9 COUNT) IC12, PIN 11
........ -------........
------------------------------------------------------------------------------------~IACTIVETIME1
----.......... -----........
DATA LINES
----
I
May 1977
1 ... ,_/ASSUME DROPOUT THIS BYTE
____ ~n~ __________ ~n~ __ ~n~ ____ ~n~ ____ ~n~ __________ ~n~ ____ ~n~ __ ~n~ __ ______ __
~n~ ~ ~n~ __ ~n~ __ ~n~ __ __
~n~ ~n~ ______ __
n~ ~n~ __ ~n~ ____ ~n~ ________________________
~ ______~------------------------------------------~ L-J
u
L
------------------------------------tIACTIVE TIMEJ
3. When the first low going transition on the READ 7. The ninth pulse at IC22, pin 3 occurs at the start of
DAT A input is shifted through the synchronizer, the intercharacter gap, a timing pulse followed by a
IC20, pin 2 goes high and the 7.665 MHz clock is data pulse which is 4 times the length of the timing
enabled at ICI8, pin 8. This clock output, when pulse. When IC's 7, 8 and 9 reach a count of -128 (all
enabled, is applied to the count up input of the up- counter outputs are high except for a low on IC8, pin
down counters of the read decode circuit. The 7) a low level appears at NAND gate IC21, pin 8
counters then count up at the clock frequency until which in turn, creates a high level at IC22, pin 8. This
the READ DATA input returns high. high level causes buffer register (IC33) to be loaded
with the contents of serial to parallel shift register.
It also sets the read flag latch causing ICI0, pin 6 to
4. When READ DATA returns high, IC20, pin 3 goes
go high; this level is inverted to form the low going
high and the output of the clock divide circuit (lC 15,
READ BUFFER FULL output.
pin 8) is enabled (lCI9, pin 12). The clock divide
circuit creates a low level (lCI7, pin 8) every fifth If the counter (lCI3) had not reached a count of 9
period of the clock. This low level is applied to IC 15, (eight bits were not present in the byte) when the
pin 10 to prevent every fifth clock pulse from appear- intercharacter gap is sensed IC22, pin 8 goes high (as
ing at ICI5, pin 8. The net result is that the clock assumed in byte 2 of Figure 34), a low level is gener-
used at the count down input of the up-down count- ated at ICI9, pin 6. This low level sets the error flag
ers contains, per unit time, 0.8 the number of clock SET/RESET latch and ICI0, pin 8 goes high. This
transitions as the count up clock input. level is inverted at IC31, pin 12 to form the INC OM -
PLETE CHARACTER output flag. Sensing the inter-
5. During the timing pulse of a data bit, as described in character gap (high level at IC22, pin 8) also causes a
Paragraph 3-3-2, the up-down counters (IC's 7, 8, high going pulse to occur at ICI2, pin 6. This pulse
and 9) will be counting up at the clock frequency. clears the 9 bit counter (lCI3) of the error circuit.
When the READ DATA input returns high at the end
of the timing pulse, the counters will begin to count 8. If the timing pulse in 7 above is at the end of a rec-
down at a rate which is 0.8 that of count up opera- cord, the counters, IC's 7, 8 and 9 will continue in a
tion. At the end of the data pulse, when READ negative direction. When a count of -512 occurs (all
DATA switches low, counter output (lC9, pin 7) is counter outputs are high except for a low on IC9,
inverted and strobed into the serial to parallel register pin 2), a low level occurs on IC23, pin 3 which sets
(lC25, pins 1 and 2) by the pulse generated at IC22,
the interrecord gap latch and IC23, pin 6 goes high.
pin 3. This pulse also resets the counters.
This level is inverted at IC31, pin 4 to form the low
going INTERRECORD GAP, output. The low output
If the input bit to be decoded was a "Zero" the tim-
at IC23, pin 3 also disables the clock inputs to the
ing pulse and data pulse would be of the same length
up down counters at ICI9, pin 2 and at ICI9, pin 9.
as described in Paragraph 3-3-2. In this instance, the
contents of the counters would be positive at the end
9. After the READ BUFFER FULL output goes low,
of the data pulse and IC9, pin 7 would be at a low
the user must apply a low going pulse of at least 50
logic level. If the input bit was a "One", the data
nanoseconds duration to the READ BUS ENABLE
pulse would be twice as long as the timing pulse; at input. This pulse enables the tri-state data output
the end of the data pulse, the counter would contain gates (IC's 32 and 34) and resets the read flag and
a negative number and IC9, pin 7 would output a error flag latches.
high level.
6. When the ninth high going pulse occurs at IC22, pin 3-3-4 INTERRECORD GAP TIME CONSIDERATIONS
3, both the 20 and 23 output bits of counter ICI3 in
the error check circuit go high. The high level at the To insure the writing of proper length interrecord gaps, the
23 output (pin 11) resets the interrecord gap latch following delays should be used.
and IC23, pin 8 goes high. This high level enables
gates at the inputs to the latches for the READ BUF- 1. After commanding forward tape movement, delay 27
FER FULL and INCOMPLETE CHARACTER flags. milliseconds before entering the first data byte.
When writing data, the following timing restrictions must When reading data, the following timing restrictions must
be considered: be considered:
1. When the first byte of data is strobed in, WRITE 1. Mter the first byte is decoded, subsequent bytes will
BUFFER EMPTY will go low again within from occur on the average, every 350 microseconds.
16.67 microseconds to 83.5 microseconds, depending
on internal logic timing. 2. The READ BUS ENABLE input must be held true
for at least SO nanoseconds for valid data to appear
on the data bus. This input must occur no sooner
2. The LOAD WRITE BUFFER input must be a pulse than 20 nanoseconds after READ BUFFER FULL
of at least SO nanoseconds but no greater than 1.5 goes low. READ BUS ENABLE should return high
microseconds. The LOAD WRITE BUFFER input within 200 microseconds of READ BUFFER FULL
must occur no sooner than 4 microseconds but prior going low.
52
53
83·92604514·3
83·92604522-6
Screw - Pan H
Screw - Ma c.,
P
d 440 x 5/16
h an
Hd 440 x 1
.,
54 81·1530·9640·9 Front Bezel 1
55 83·9630-0085·2 1
56 81-14344820·7 Lug d 2-56 x 3/4 2
57 834930·3905·7
Screw
End Sense Asse~"bly (includes item 50)
- Pan H 1
58 81-0884·2440-8 W sher #4 PlastIC . 1
59 83-1550-6166-2 a
Switch - Snap Aclion Sens FPTI OOA 2
60 81-2712-7041-5 NPNPhoto 2
TSTR - SI Lens End TS1748
Lamp -2.SV
61 81-2712-1310-0 1
62 81-0430-9520-7 Washer - Shoulder 1 15
63 83-0003·t"016-S Head Oamp Assy.
50
.
Ex loded View, Drive Unit,
Figure 4-1. P 'cal Assembly
Mecharu
R15 -._..I<='l_.I=
VR1 .--- MI---C1
R16 R3 +12V
' - -..................J LSI
TS 1748
R17
Pl17
R18 2.7K
R10 R11 R9 R8 13
SW1 SW2
R12 +12V
Figure 4-2. End Sense Amplifier Board Component Layout lOOK
R18
CR2
2.7K
1NS14
C6 CARTRIDGE POSITION
r
500PF J1 SWITCH S2
R15 IN N.O.
10K R14 I
Parts List, End Sense Amplifier PC Assembly, 834930-3905-7, Issue E 10K I
I ~-
C __
+12V
VR1 C6 OUT' N.C.
R13 CIN
1N473SA
INDEX NUMBER PART NUMBER DESCRIPTION QTY. 6.SV
.0111f 20K
R3
':" 1K
C1 83-15104648-5 Capacitor - Fixed, Film, 1 UF 100V 10% I R11
1.3M +5
C3 83-1510-2354-2 Capacitor - Fixed, Elc, 100 UF 16V 1
C4 83-1510-1024-2 Capacitor - Fixed, Ceramic, 1000 PF 1000V 10% I RS
10K
C5 83-1510-5120-4 Capacitor - Fixed, Mic, 500 PF 500V 5% 1 +12V
R2 PC2 r----o N.C.
22M
C6 81·1510-10754 Capacitor - Fixed Ceramic, .01 UF 10V 1
CR2 83-1530-0083-7 Diode - SI Switching IN914 1 RS
R4
39K
ICI 83·1530-8307-2 IC - Quad Comp LM339N 1 B.2K
QI,Q2 81·2712·7041·5 Transistor - SI, NPN Photo-Sens FPT100A 2 ':" RS +5 J+-----....... ~ +5V
10K
Q3 83-1530-2434-0 Transistor - SI, NPN Power-Dad MJE800 1 R1
22M 2 PC1 C4
Rl,2 83·9520-2223-0 Resistor - Fixed, Comp, 22M Ohm 1/4W 5% 2 O.OO1j.lf
R3,18 83-9520·2088·7 Resistor - Fixed, Comp, lK Ohm 1/4W 5% 2
R5 H------+--_~ +12V
R4,5 83-9520-2089-5 Resistor - Fixed, Comp, 8.2K Ohm 1/4W 5% 2 S.2K
GJ
~
c::::::::::>C9 o
Figure 4-4. Servo Electronics and Read/Write Amplifier Board Component Layout
+'2V
END SELECT
FILE
PROTECT
(:);,.0 ~¢ ~",~O~:~cl ~o"'o~ ~o"'o~ 'I><i'<s>'" 'I>~,<s>'" TPS TP10
_ell!!!!! T! r- ~'---f----1f
GND
Pe2 PC, CIN GND SENSE KEY +5V WI' CT HO
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r:
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II ~ STATUS DECODE
LOGIC r - READAMPLiFlER - - r- -THREsHOLDDETEcTOR'
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a 5 4,::;:.06"---______ -+-+-______-+__________---, II ~~
~~. ~~
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10K 1I 9 + 3
+12V
L--------~----H,....J l 'OOOPF
I C15 +12V 1 r 1 lM339N 19 14
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.--+-++--+-__-'-'~~ 1 ~--,+-,314.I 5W- I g~3 ~K
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•
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+12v
I
I L-__ +-__....J T13
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I
21
L-
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L
C14
0.1
R13
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".3K
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l4/ 2 ~':K
3.3K
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r+- ~ I .----__
'~
+--_-+-+---+_ _+-+-----<>-+-+-+--_-+--J1
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8 cIa R21 4.3K R29 19
+5 +5 I. 9' 11 ~I- ~.~~ - 1 '00 ,. C29 J ~ 10K 6
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1
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1K 24K C3 ~.R II (ROY) a.. _ _ _ _ L.: _ _ _ _ _ _ _ _ _ -I
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r- .5-r-7 l000PF ~ I I AMP. ~P4 J ~~K I 1 ~1' 1
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2 _ 4 TP +12V +12V
-~ -1-1 I I I r----i I I
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681" 15K R75 ,-----,R81 R80
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~ ~6 ~ ~5 ~.-+-HI r~ ~~---+1-2V I I~~ i; ~"\ ~~O tu-I
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--+----------+-J1 2 12 • 9
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6'>"-8-+-+-l__+--+___________ 11 II-1I-+-f-+>
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....,"'%V'--->
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r-+--oTP7IL~~J
as :200 ?;53A
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J
_ _--t-+"LJI--+-t-+--+--
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I ~-------~+LH-k-I.! I ~ -B'-61pJ0
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.---------------=:"----------+--I-!----1
11'3~'2 ... - - - · ..
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:f~ :~J 19 13 3:~i>o_4~----3.9-·-4--""K'I'----i_f_-------------------------------1
I I ~~ ll" 1~3 11~ 1 1 SWITCH I v
2 '0 +5V
I_____________
~ ..J
~"~ !:E~~WRITE HEADI~":.. >-if-
SELECT
1 I l7
r: 2H
8 6 3 8 "
~
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15 R14 \. - - C7
r
II
I 3 _,,- _ .. _ _ 1_ ........ _ _ _
6 16 5 8 16 9
-.I--.J Mf- ~05 RB6 06
" Alll/2W RESISTORS ARE 2% - ALL
OTHERS 5%.
I
1 N4004 5 1V
o
g~~
1 2 3 IN MICROFARADS
rlc-
I +12V VR2
I:> C> 0 Q 6 oj J8 .l' ;,:>,,",VR3
lN4737A i;"lN4733A
I
Ir----f------+--+--+-I---.J
75V 51V
1 ~ ~ ~
1
r!l (1~ (1~ (1~ ('!l
1
L _COl CD lV lV (u - J6 0 (~ 0 001
Figure 4-5. Schematic, Servo Electrorucs and Read/Write Amplifier PC Assembly
BOT RDV STP RWC WD FIR RST ENO EN' EN 2 EN3 GND GND +12V GND +5V GND +12V
MTR
83-493()'3904-0 Issue E
All EVEN NO. PINS GROUNDED
R5
~
oCEJ o
C12 C7
Gn
R4
GJ
C1[J
R3 ==e::::::F=>
Gn oGlJ C6
10-12
I I I I '2 CK
W
16,23 I I
ICI3,18, 83 -1530-80664 IC - 4 Bit Counter SN7493N 4 I~~~~~~~--------~~
----'3--- ,
27,29 ):>"-,-'- - +------+---+--111-1+-_
,2 37
I
I
ENCODE TIMING CONTROL I
L ___________________________ I ~
. . - - - 1 -.....
QTY. NOTES FOR USER IN/OUT
1 OPTIONAL NETWORK FOR USER CABLE LENGTH
GF~EATER THEN 4 FT IF NETWORK IS UGED USER
7 2
MUST EMPlOV BUFfER DRIVER GATES
ALL NON TFHSIATE G~\TES REGUIRE PULLUPS
AT USER END
3 DATA BUSSHOULO BE: TERMINATED iIo'lTH
TRISTATE GATE'S
2
1
1
1
5
3
4
2
2
1
2
2
1
1
9
+5 GNO GNO we RD ROY BOT RST F'R RUN STP Rwe EN3 EN2 EN1 t:NO
THIS WARRANTY APPLIES TO DEFECTS ARISING OUT OF NORMAL USE AND SERVICE OF THE EQUIP-
MENT AS SPECIFIED BY 3M. THIS WARRANTY DOES NOT COVER ABNORMAL OPERATION OF THE
EQUIPMENT, ACCIDENT, ALTERATION, NEGLIGENCE, MISUSE AND REPAIRS OR SERVICING PER-
FORMED BY OTHER THAN 3M AUTHORIZED REPRESENTATIVES. PURCHASER SHALL UPON REQUEST
BY 3M FURNISH REASONABLE EVIDENCE THAT THE DEFECT AROSE FROM CAUSES PLACING A
LIABILITY ON 3M. IF THE DEFECT DID NOT ARISE FROM CAUSES PLACING A LIABILITY ON 3M, PUR-
CHASER SHALL REIMBURSE 3M FOR EXPENSES INCURRED IN INSPECTING THE EQUIPMENT AT THE
REQUEST OF PURCHASER.
MW-DCD-I