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 EC1265 – ELECTRONICS AND MICROPROCESSORS

(Common to Automobile, Mechanical and Production LTPC3003

UNIT I: SEMICONDUCTORS AND RECTIFIERS 9

Classification of solids based on energy band theory – Intrinsic semiconductors – Extrinsic

semiconductors – P-type and N-type – PN junction – Zener effect –Zener diode characteristics
– Half wave and full wave rectifiers – Voltage regulation

UNIT II: TRANSISTORS AND AMPLIFIERS 12

Bipolar junction transistor – CB, CE, CC configuration and characteristics – Biasing circuits –
Class A, B and C amplifiers – Field effect transistor –Configuration and characteristic of FET
amplifier –SCR, diac, triac, UJT – Characteristics and simple applications – Switching
transistors –Concept of feedback –Negative feedback – Application in temperature and motor
speed control.

UNIT III :DIGITAL ELECTRONICS 9

Binary number system – AND, OR, NOT, NAND, NOR circuits – Boolean algebra –
Exclusive ORgate – Flip flops – Half and full adders – Registers – Counters –A/D and D/A
conversion.

UNIT IV :8085 MICROPROCESSOR 9

Block diagram of microcomputer – Architecture of 8085 – Pin configuration – Instruction set

–Addressing modes – Simple programs using arithmetic and logical operations.

UNIT V: INTERFACING AND APPLICATIONS OF MICROPROCESSOR 6

Basic interfacing concepts – Interfacing of Input and output devices – Applications of

microprocessor temperature control – Stepper motor control – Traffic light control.

Total: 45
TEXT BOOKS

1. Milman and Halkias, ―Integrated Electronics‖, Tata McGraw-Hill Publishers, 1995.

2. Ramesh Goankar, ―Microprocessor Architecture, Programming and Applications with
8085‖,
Wiley Eastern, 1998.

REFERENCES

1. Malvino and Leach, ―Digital Principles and Applications‖, Tata McGraw-Hill, 1996.
2. Mehta, V.K., ―Principles of Electronics‖, S. Chand and Company Ltd, 1994.
3 Dougles V. Hall, ―Microprocessor and Interfacing, Programming and Hardware‖, Tata
McGraw-Hill, 1999.
 UNIT I: SEMICONDUCTORS AND RECTIFIERS

Classification of solids based on energy band theory – Intrinsic semiconductors – Extrinsic

semiconductors – P-type and N-type – PN junction – Zener effect –Zener diode characteristics
– Half wave and full wave rectifiers – Voltage regulation

Semiconductor diodes
A modern semiconductor diode is made of a crystal of semiconductor like silicon that has
impurities added to it to create a region on one side that contains negative charge
carriers (electrons), called n-type semiconductor, and a region on the other side that contains
positive charge carriers (holes), called p-type semiconductor. The diode's terminals are
attached to each of these regions. The boundary within the crystal between these two regions,
called a PN junction, is where the action of the diode takes place. The crystal
conducts conventional current in a direction from the p-type side (called the anode) to the n-
type side (called the cathode), but not in the opposite direction.
Another type of semiconductor diode, the Schottky diode, is formed from the contact between
a metal and a semiconductor rather than by a p-n junction.
Current–voltage characteristic
A semiconductor diode‘s behavior in a circuit is given by its current–voltage characteristic, or
I–V graph (see graph below). The shape of the curve is determined by the transport of charge
carriers through the so-called depletion layer or depletion region that exists at the p-n
junction between differing semiconductors. When a p-n junction is first created, conduction
band (mobile) electrons from the N-doped region diffuse into the P-doped region where there
is a large population of holes (vacant places for electrons) with which the electrons
―recombine‖. When a mobile electron recombines with a hole, both hole and electron vanish,
leaving behind an immobile positively charged donor (dopant) on the N-side and negatively
charged acceptor (dopant) on the P-side. The region around the p-n junction becomes depleted
of charge carriers and thus behaves as an insulator.
However, the width of the depletion region (called the depletion width) cannot grow without
limit. For each electron-hole pair that recombines, a positively charged dopant ion is left
behind in the N-doped region, and a negatively charged dopant ion is left behind in the P-
doped region. As recombination proceeds more ions are created, an increasing electric field
develops through the depletion zone which acts to slow and then finally stop recombination.
At this point, there is a ―built-in‖ potential across the depletion zone.
If an external voltage is placed across the diode with the same polarity as the built-in
potential, the depletion zone continues to act as an insulator, preventing any significant
electric current flow (unless electron/hole pairs are actively being created in the junction by,
for instance, light. see photodiode). This is the reverse bias phenomenon. However, if the
polarity of the external voltage opposes the built-in potential, recombination can once again
proceed, resulting in substantial electric current through the p-n junction (i.e. substantial
numbers of electrons and holes recombine at the junction). For silicon diodes, the built-in
potential is approximately 0.7 V (0.3 V for Germanium and 0.2 V for Schottky). Thus, if an
external current is passed through the diode, about 0.7 V will be developed across the diode
such that the P-doped region is positive with respect to the N-doped region and the diode is
said to be ―turned on‖ as it has a forward bias.
A diode‘s 'I–V characteristic' can be approximated by four regions of operation.
I–V characteristics of a P-N junction diode
At very large reverse bias, beyond the peak inverse voltage or PIV, a process called
reverse breakdown occurs which causes a large increase in current (i.e. a large number of
electrons and holes are created at, and move away from the pn junction) that usually damages
the device permanently. The avalanche diode is deliberately designed for use in the avalanche
region. In the zener diode, the concept of PIV is not applicable. A zener diode contains a
heavily doped p-n junction allowing electrons to tunnel from the valence band of the p-type
material to the conduction band of the n-type material, such that the reverse voltage is
―clamped‖ to a known value (called the zener voltage), and avalanche does not occur. Both
devices, however, do have a limit to the maximum current and power in the clamped reverse
voltage region. Also, following the end of forward conduction in any diode, there is reverse
current for a short time. The device does not attain its full blocking capability until the reverse
current ceases.
The second region, at reverse biases more positive than the PIV, has only a very small reverse
saturation current. In the reverse bias region for a normal P-N rectifier diode, the current
through the device is very low (in the µA range). However, this is temperature dependent, and
at sufficiently high temperatures, a substantial amount of reverse current can be observed (mA
or more).
The third region is forward but small bias, where only a small forward current is conducted.
As the potential difference is increased above an arbitrarily defined ―cut-in voltage‖ or ―on-
voltage‖ or ―diode forward voltage drop (Vd)‖, the diode current becomes appreciable (the
level of current considered ―appreciable‖ and the value of cut-in voltage depends on the
application), and the diode presents a very low resistance. The current–voltage curve
is exponential. In a normal silicon diode at rated currents, the arbitrary ―cut-in‖ voltage is
defined as 0.6 to 0.7 volts. The value is different for other diode types — Schottky diodes can
be rated as low as 0.2 V, Germanium diodes 0.25-0.3 V, and red or blue light-emitting
diodes (LEDs) can have values of 1.4 V and 4.0 V respectively.
At higher currents the forward voltage drop of the diode increases. A drop of 1 V to 1.5 V is
typical at full rated current for power diodes.
Shockley diode equation

The Shockley ideal diode equation or the diode law (named after transistor co-
inventor William Bradford Shockley, not to be confused with tetrode inventor Walter H.
Schottky) gives the I–V characteristic of an ideal diode in either forward or reverse bias (or no
bias). The equation is:

where
I is the diode current,
IS is the reverse bias saturation current (or scale current),
VD is the voltage across the diode,
VT is the thermal voltage, and
n is the ideality factor, also known as the quality factor or sometimes emission coefficient.
The ideality factor n varies from 1 to 2 depending on the fabrication process and
semiconductor material and in many cases is assumed to be approximately equal to 1 (thus the
notation n is omitted).
The thermal voltage VT is approximately 25.85 mV at 300 K, a temperature close to ―room
temperature‖ commonly used in device simulation software. At any temperature it is a known
constant defined by:

where k is the Boltzmann constant, T is the absolute temperature of the p-n junction, and q is
the magnitude of charge on an electron (the elementary charge).
The Shockley ideal diode equation or the diode law is derived with the assumption that the
only processes giving rise to the current in the diode are drift (due to electrical field),
diffusion, and thermal recombination-generation. It also assumes that the recombination-
generation (R-G) current in the depletion region is insignificant. This means that the Shockley
equation doesn‘t account for the processes involved in reverse breakdown and photon-assisted
R-G. Additionally, it doesn‘t describe the ―leveling off‖ of the I–V curve at high forward bias
due to internal resistance.
Under reverse bias voltages (see Figure 5) the exponential in the diode equation is negligible,
and the current is a constant (negative) reverse current value of −IS. The reverse breakdown
region is not modeled by the Shockley diode equation.
For even rather small forward bias voltages (see Figure 5) the exponential is very large
because the thermal voltage is very small, so the subtracted ‗1‘ in the diode equation is
negligible and the forward diode current is often approximated as

The use of the diode equation in circuit problems is illustrated in the article on diode
modeling.
Several types of junction diodes
There are several types of junction diodes, which either emphasize a different physical aspect
of a diode often by geometric scaling, doping level, choosing the right electrodes, are just an
application of a diode in a special circuit, or are really different devices like the Gunn and
laser diode and the MOSFET:
Normal (p-n) diodes, which operate as described above, are usually made of doped silicon or,
more rarely, germanium. Before the development of modern silicon power rectifier
diodes, cuprous oxide and later selenium was used; its low efficiency gave it a much higher
forward voltage drop (typically 1.4–1.7 V per ―cell‖, with multiple cells stacked to increase
the peak inverse voltage rating in high voltage rectifiers), and required a large heat sink (often
an extension of the diode‘s metal substrate), much larger than a silicon diode of the same
current ratings would require. The vast majority of all diodes are the p-n diodes found
inCMOS integrated circuits, which include two diodes per pin and many other internal diodes.
Avalanche diodes
Diodes that conduct in the reverse direction when the reverse bias voltage exceeds the
breakdown voltage. These are electrically very similar to Zener diodes, and are often
mistakenly called Zener diodes, but break down by a different mechanism, the avalanche
effect. This occurs when the reverse electric field across the p-n junction causes a wave of
ionization, reminiscent of an avalanche, leading to a large current. Avalanche diodes are
designed to break down at a well-defined reverse voltage without being destroyed. The
difference between the avalanche diode (which has a reverse breakdown above about 6.2 V)
and the Zener is that the channel length of the former exceeds the ―mean free path‖ of the
electrons, so there are collisions between them on the way out. The only practical difference is
that the two types have temperature coefficients of opposite polarities.
Constant current diodes
These are actually a JFET with the gate shorted to the source, and function like a two-
terminal current-limiter analog to the Zener diode, which is limiting voltage. They allow a
current through them to rise to a certain value, and then level off at a specific value. Also
called CLDs, constant-current diodes, diode-connected transistors, or current-regulating
diodes.
Esaki or tunnel diodes
These have a region of operation showing negative resistance caused by quantum tunneling,
thus allowing amplification of signals and very simple bistable circuits. These diodes are also
the type most resistant to nuclear radiation.
Gunn diodes
These are similar to tunnel diodes in that they are made of materials such as GaAs or InP that
exhibit a region of negative differential resistance. With appropriate biasing, dipole domains
form and travel across the diode, allowing high frequency microwave oscillators to be built.
Light-emitting diodes (LEDs)

In a diode formed from a direct band-gap semiconductor, such as gallium arsenide, carriers
that cross the junction emit photons when they recombine with the majority carrier on the
other side. Depending on the material, wavelengths (or colors)[11] from the infrared to the
near ultraviolet may be produced.[12] The forward potential of these diodes depends on the
wavelength of the emitted photons: 1.2 V corresponds to red, 2.4 V to violet. The first LEDs
were red and yellow, and higher-frequency diodes have been developed over time. All LEDs
produce incoherent, narrow-spectrum light; ―white‖ LEDs are actually combinations of three
LEDs of a different color, or a blue LED with a yellow scintillator coating. LEDs can also be
used as low-efficiency photodiodes in signal applications. An LED may be paired with a
photodiode or phototransistor in the same package, to form an opto-isolator.
Laser diodes
When an LED-like structure is contained in a resonant cavity formed by polishing the parallel
end faces, a laser can be formed. Laser diodes are commonly used in optical storage devices
and for high speed optical communication.
Thermal diodes
This term is used both for conventional PN diodes used to monitor temperature due to their
varying forward voltage with temperature, and for Peltier heat pumps for thermoelectric
heating and cooling.. Peltier heat pumps may be made from semiconductor, though they do
not have any rectifying junctions, they use the differing behaviour of charge carriers in N and
P type semiconductor to move heat.
Photodiodes

All semiconductors are subject to optical charge carrier generation. This is typically an
undesired effect, so most semiconductors are packaged in light blocking material. Photodiodes
are intended to sense light(photodetector), so they are packaged in materials that allow light to
pass, and are usually PIN (the kind of diode most sensitive to light).[13] A photodiode can be
used in solar cells, in photometry, or in optical communications. Multiple photodiodes may be
packaged in a single device, either as a linear array or as a two-dimensional array. These
arrays should not be confused with charge-coupled devices.

Point-contact diodes
These work the same as the junction semiconductor diodes described above, but their
construction is simpler. A block of n-type semiconductor is built, and a conducting sharp-
point contact made with some group-3 metal is placed in contact with the semiconductor.
Some metal migrates into the semiconductor to make a small region of p-type semiconductor
near the contact. The long-popular 1N34 germanium version is still used in radio receivers as
a detector and occasionally in specialized analog electronics.
PIN diodes
A PIN diode has a central un-doped, or intrinsic, layer, forming a p-type/intrinsic/n-type
structure.[14] They are used as radio frequency switches and attenuators. They are also used as
large volume ionizing radiation detectors and as photodetectors. PIN diodes are also used
in power electronics, as their central layer can withstand high voltages. Furthermore, the PIN
structure can be found in many power semiconductor devices, such as IGBTs,
power MOSFETs, and thyristors.

Schottky diodes

Schottky diodes are constructed from a metal to semiconductor contact. They have a lower
forward voltage drop than p-n junction diodes. Their forward voltage drop at forward currents
of about 1 mA is in the range 0.15 V to 0.45 V, which makes them useful in voltage clamping
applications and prevention of transistor saturation. They can also be used as low
loss rectifiers although their reverse leakage current is generally higher than that of other
diodes. Schottky diodes are majority carrier devices and so do not suffer from minority carrier
storage problems that slow down many other diodes — so they have a faster ―reverse
recovery‖ than p-n junction diodes. They also tend to have much lower junction capacitance
than p-n diodes which provides for high switching speeds and their use in high-speed circuitry
and RF devices such as switched-mode power
varactor diodes
Varactors are operated reverse-biased so no current flows, but since the thickness of
the depletion zone varies with the applied bias voltage, the capacitance of the diode can be
made to vary. Generally, the depletion region thickness is proportional to the square root of
the applied voltage; andcapacitance is inversely proportional to the depletion region thickness.
Thus, the capacitance is inversely proportional to the square root of applied voltage.
All diodes exhibit this phenomenon to some degree, but specially made varactor diodes
exploit the effect to boost the capacitance and variability range achieved - most diode
fabrication attempts to achieve the opposite.
In the figure we can see an example of a crossection of a varactor with the depletion layer
formed of a p-n-junction. But the depletion layer can also be made of a MOS-diode or
a Schottky diode. This is very important in CMOS and MMIC technology.

Zener diodes
Diodes that can be made to conduct backwards. This effect, called Zener breakdown, occurs at
a precisely defined voltage, allowing the diode to be used as a precision voltage reference. In
practical voltage reference circuits Zener and switching diodes are connected in series and
opposite directions to balance the temperature coefficient to near zero. Some devices labeled
as high-voltage Zener diodes are actually avalanche diodes (see above). Two (equivalent)
Zeners in series and in reverse order, in the same package, constitute a transient absorber
(or Transorb, a registered trademark). The Zener diode is named for Dr. Clarence Melvin
Zener of Carnegie Mellon University, inventor of the device.
Other uses for semiconductor diodes include sensing temperature, and computing
analog logarithms (see Operational amplifier applications#Logarithmic).
Zener diode is a type of diode that permits current not only in the forward direction like a
normal diode, but also in the reverse direction if the voltage is larger than the breakdown
voltage known as "Zener knee voltage" or "Zener voltage". The device was named
after Clarence Zener, who discovered this electrical property.
A conventional solid-state diode will not allow significant current if it is reverse below its
reverse breakdown voltage. When the reverse bias breakdown voltage is exceeded, a
conventional diode is subject to high current due to avalanche breakdown. Unless this current
is limited by circuitry, the diode will be permanently damaged. In case of large forward bias
(current in the direction of the arrow), the diode exhibits a voltage drop due to its junction
built-in voltage and internal resistance. The amount of the voltage drop depends on the
semiconductor material and the doping concentrations.
A Zener diode exhibits almost the same properties, except the device is specially designed so
as to have a greatly reduced breakdown voltage, the so-called Zener voltage. By contrast with
the conventional device, a reverse-biased Zener diode will exhibit a controlled breakdown and
allow the current to keep the voltage across the Zener diode at the Zener voltage. For example,
a diode with a Zener breakdown voltage of 3.2 V will exhibit a voltage drop of 3.2 V even if
reverse bias voltage applied across it is more than its Zener voltage. The Zener diode is
therefore ideal for applications such as the generation of a reference voltage (e.g. for
an amplifier stage), or as a voltage stabilizer for low-current applications.
The Zener diode's operation depends on the heavy doping of its p-n
junction allowing electrons to tunnel from the valence band of the p-type material to the
conduction band of the n-type material. In the atomic scale, this tunneling corresponds to the
transport of valence band electrons into the empty conduction band states; as a result of the
reduced barrier between these bands and high electric fields that are induced due to the
relatively high levels of dopings on both sides.[1] The breakdown voltage can be controlled
quite accurately in the doping process. While tolerances within 0.05% are available, the most
widely used tolerances are 5% and 10%. Breakdown voltage for commonly available zener
diodes can vary widely from 1.2 volts to 200 volts.
Another mechanism that produces a similar effect is the avalanche effect as in the avalanche
diode. The two types of diode are in fact constructed the same way and both effects are
present in diodes of this type. In silicon diodes up to about 5.6 volts, the Zener effect is the
predominant effect and shows a marked negative temperature coefficient. Above 5.6 volts,
the avalanche effect becomes predominant and exhibits a positive temperature coefficient[1].
In a 5.6 V diode, the two effects occur together and their temperature coefficients neatly
cancel each other out, thus the 5.6 V diode is the component of choice in temperature-critical
applications. Modern manufacturing techniques have produced devices with voltages lower
than 5.6 V with negligible temperature coefficients, but as higher voltage devices are
encountered, the temperature coefficient rises dramatically. A 75 V diode has 10 times the
coefficient of a 12 V diode.
All such diodes, regardless of breakdown voltage, are usually marketed under the umbrella
term of "Zener diode".

Current-voltage characteristic of a Zener diode with a breakdown voltage of 17 volt. Notice

the change of voltage scale between the forward biased (positive) direction and the reverse
biased (negative) direction.
Zener diodes are widely used as voltage references and as shunt regulators to regulate the
voltage across small circuits. When connected in parallel with a variable voltage source so
that it is reverse biased, a Zener diode conducts when the voltage reaches the diode's reverse
breakdown voltage. From that point on, the relatively low impedance of the diode keeps the
voltage across the diode at that value.
In this circuit, a typical voltage reference or regulator, an input voltage, UIN, is regulated down
to a stable output voltage UOUT. The intrinsic voltage drop of diode D is stable over a wide
current range and holds UOUT relatively constant even though the input voltage may fluctuate
over a fairly wide range. Because of the low impedance of the diode when operated like this,
Resistor R is used to limit current through the circuit.
In the case of this simple reference, the current flowing in the diode is determined using Ohms
law and the known voltage drop across the resistor R. IDiode = (UIN - UOUT) / RΩ
The value of R must satisfy two conditions:

1. R must be small enough that the current through D keeps D in reverse breakdown. The
value of this current is given in the data sheet for D. For example, the common
BZX79C5V6[2] device, a 5.6 V 0.5 W Zener diode, has a recommended reverse
current of 5 mA. If insufficient current exists through D, then UOUT will be
unregulated, and less than the nominal breakdown voltage (this differs to voltage
regulator tubes where the output voltage will be higher than nominal and could rise as
high as UIN). When calculating R, allowance must be made for any current through the
external load, not shown in this diagram, connected across UOUT.
2. R must be large enough that the current through D does not destroy the device. If the
current through D is ID, its breakdown voltage VB and its maximum power
dissipation PMAX, then IDVB < PMAX.
A load may be placed across the diode in this reference circuit, and as long as the zener stays
in reverse breakdown, the diode will provide a stable voltage source to the load.

Shunt regulators are simple, but the requirements that the ballast resistor be small enough to
avoid excessive voltage drop during worst-case operation (low input voltage concurrent with
high load current) tends to leave a lot of current flowing in the diode much of the time,
making for a fairly wasteful regulator with high quiescent power dissipation, only suitable for
smaller loads.
Zener diodes in this configuration are often used as stable references for more advanced
voltage regulator circuits.
These devices are also encountered, typically in series with a base-emitter junction, in
transistor stages where selective choice of a device centered around the avalanche/Zener point
can be used to introduce compensating temperature co-efficient balancing of the transistor PN
junction. An example of this kind of use would be a DC error amplifier used in a regulated
power supply circuit feedback loop system.
Zener diodes are also used in surge protectors to limit transient voltage spikes.
Another notable application of the zener diode is the use of noise caused by its avalanche
breakdown in a random number generator that never repeats.
 UNIT II: TRANSISTORS AND AMPLIFIERS

Bipolar junction transistor – CB, CE, CC configuration and characteristics – Biasing circuits –
Class A, B and C amplifiers – Field effect transistor –Configuration and characteristic of FET
amplifier –SCR, diac, triac, UJT – Characteristics and simple applications – Switching
transistors –Concept of feedback –Negative feedback – Application in temperature and motor
speed control.

Bipolar Transistor Basics

In the Diode tutorials we saw that simple diodes are made up from two pieces of
semiconductor material, either Silicon or Germanium to form a simple PN-junction and we
also learnt about their properties and characteristics. If we now join together two individual
diodes end to end giving two PN-junctions connected together in series, we now have a three
layer, two junction, three terminal device forming the basis of a Bipolar Junction
Transistor, or BJT for short. This type of transistor is generally known as a Bipolar
Transistor, because its basic construction consists of two PN-junctions with each terminal or
connection being given a name to identify it and these are known as the Emitter, Base and
Collector respectively.

The word Transistor is an acronym, and is a combination of the words Transfer Varistor used
to describe their mode of operation way back in their early days of development. There are
two basic types of bipolar transistor construction, NPN and PNP, which basically describes
the physical arrangement of the P-type and N-type semiconductor materials from which they
are made. Bipolar Transistors are "CURRENT" Amplifying or current regulating devices that
control the amount of current flowing through them in proportion to the amount of biasing
current applied to their base terminal. The principle of operation of the two transistor types
NPN and PNP, is exactly the same the only difference being in the biasing (base current) and
the polarity of the power supply for each type.

Bipolar Transistor Construction

The construction and circuit symbols for both the NPN and PNP bipolar transistor are shown
above with the arrow in the circuit symbol always showing the direction of conventional
current flow between the base terminal and its emitter terminal, with the direction of the arrow
pointing from the positive P-type region to the negative N-type region, exactly the same as for
the standard diode symbol.

There are basically three possible ways to connect a Bipolar Transistor within an electronic
circuit with each method of connection responding differently to its input signal as the static
characteristics of the transistor vary with each circuit arrangement.

1. Common Base Configuration - has Voltage Gain but no Current Gain.

2. Common Emitter Configuration - has both Current and Voltage Gain.
3. Common Collector Configuration - has Current Gain but no Voltage Gain.

The Common Base Configuration.

As its name suggests, in the Common Base or Grounded Base configuration, the BASE
connection is common to both the input signal AND the output signal with the input signal
being applied between the base and the emitter terminals. The corresponding output signal is
taken from between the base and the collector terminals as shown with the base terminal
grounded or connected to a fixed reference voltage point. The input current flowing into the
emitter is quite large as its the sum of both the base current and collector current respectively
therefore, the collector current output is less than the emitter current input resulting in a
Current Gain for this type of circuit of less than "1", or in other words it "Attenuates" the
signal.
The Common Base Amplifier Circuit

This type of amplifier configuration is a non-inverting voltage amplifier circuit, in that the
signal voltages Vin and Vout are In-Phase. This type of arrangement is not very common due
to its unusually high voltage gain characteristics. Its Output characteristics represent that of a
forward biased diode while the Input characteristics represent that of an illuminated photo-
diode. Also this type of configuration has a high ratio of Output to Input resistance or more
importantly "Load" resistance (RL) to "Input" resistance (Rin) giving it a value of "Resistance
Gain". Then the Voltage Gain for a common base can therefore be given as:

Common Base Voltage Gain

The Common Base circuit is generally only used in single stage amplifier circuits such as
microphone pre-amplifier or RF radio amplifiers due to its very good high frequency
response.

The Common Emitter Configuration.

In the Common Emitter or Grounded Emitter configuration, the input signal is applied
between the base, while the output is taken from between the collector and the emitter as
shown. This type of configuration is the most commonly used circuit for transistor based
amplifiers and which represents the "normal" method of connection. The common emitter
amplifier configuration produces the highest current and power gain of all the three bipolar
transistor configurations. This is mainly because the input impedance is LOW as it is
connected to a forward-biased junction, while the output impedance is HIGH as it is taken
from a reverse-biased junction.
The Common Emitter Amplifier Circuit

In this type of configuration, the current flowing out of the transistor must be equal to the
currents flowing into the transistor as the emitter current is given as Ie = Ic + Ib. Also, as the
load resistance (RL) is connected in series with the collector, the Current gain of the Common
Emitter Transistor Amplifier is quite large as it is the ratio of Ic/Ib and is given the symbol of
Beta, (β). Since the relationship between these three currents is determined by the transistor
itself, any small change in the base current will result in a large change in the collector
current. Then, small changes in base current will thus control the current in the
Emitter/Collector circuit.

By combining the expressions for both Alpha, α and Beta, β the mathematical relationship
between these parameters and therefore the current gain of the amplifier can be given as:

Where: "Ic" is the current flowing into the collector terminal, "Ib" is the current flowing into
the base terminal and "Ie" is the current flowing out of the emitter terminal.

Then to summarise, this type of bipolar transistor configuration has a greater input impedance,
Current and Power gain than that of the common Base configuration but its Voltage gain is
much lower. The common emitter is an inverting amplifier circuit resulting in the output
signal being 180o out of phase with the input voltage signal.

The Common Collector Configuration.

In the Common Collector or Grounded Collector configuration, the collector is now common
and the input signal is connected to the Base, while the output is taken from the Emitter load
as shown. This type of configuration is commonly known as a Voltage Follower or Emitter
Follower circuit. The Emitter follower configuration is very useful for impedance matching
applications because of the very high input impedance, in the region of hundreds of thousands
of Ohms, and it has relatively low output impedance.
The Common Collector Amplifier Circuit

The Common Emitter configuration has a current gain equal to the β value of the transistor
itself. In the common collector configuration the load resistance is situated in series with the
emitter so its current is equal to that of the emitter current. As the emitter current is the
combination of the collector AND base currents combined, the load resistance in this type of
amplifier configuration also has both the collector current and the input current of the base
flowing through it. Then the current gain of the circuit is given as:

This type of bipolar transistor configuration is a non-inverting amplifier circuit in that the
signal voltages of Vin and Vout are "In-Phase". It has a voltage gain that is always less than
"1" (unity). The load resistance of the common collector amplifier configuration receives both
the base and collector currents giving a large current gain (as with the Common Emitter
configuration) therefore, providing good current amplification with very little voltage gain.

Bipolar Transistor Summary.

The behaviour of the bipolar transistor in each one of the above circuit configurations is very
different and produces different circuit characteristics with regards to Input impedance,
Output impedance and Gain and this is summarised in the table below.

Transistor Characteristics

The static characteristics for Bipolar Transistor amplifiers can be divided into the following
main groups.
 Input Characteristics:- Common Base - IE ÷ VEB
Common Emitter - IB ÷ VBE

Output Characteristics:- Common Base - IC ÷ VC

Common Emitter - IC ÷ VC

Transfer Characteristics:- Common Base - IE ÷ IC

Common Emitter - IB ÷ IC

with the characteristics of the different transistor configurations given in the following table:

Common Common Common

Characteristic
Base Emitter Collector

Input impedance Low Medium High

Output impedance Very High High Low

Phase Angle 0o 180o 0o

Voltage Gain High Medium Low

Current Gain Low Medium High

Power Gain Low Very High

Transistor as a switch

BJT used as an electronic switch, in grounded-emitter configuration.

Transistors are commonly used as electronic switches, for both high power applications
including switched-mode power supplies and low power applications such as logic gates.
In a grounded-emitter transistor circuit, such as the light-switch circuit shown, as the base
voltage rises the base and collector current rise exponentially, and the collector voltage drops
because of the collector load resistor. The relevant equations:

VRC = ICE × RC, the voltage across the load (the lamp with resistance RC)
VRC + VCE = VCC, the supply voltage shown as 6V

If VCE could fall to 0 (perfect closed switch) then Ic could go no higher than VCC / RC, even
with higher base voltage and current. The transistor is then said to be saturated. Hence, values
of input voltage can be chosen such that the output is either completely off,[13] or completely
on. The transistor is acting as a switch, and this type of operation is common in digital circuits
where only "on" and "off" values are relevant.

Transistor as an amplifier

Amplifier circuit, standard common-emitter configuration.

The common-emitter amplifier is designed so that a small change in voltage in (Vin) changes
the small current through the base of the transistor and the transistor's current amplification
combined with the properties of the circuit mean that small swings in Vin produce large
changes in Vout.

Various configurations of single transistor amplifier are possible, with some providing current
gain, some voltage gain, and some both.

From mobile phones to televisions, vast numbers of products include amplifiers for sound
reproduction, radio transmission, and signal processing. The first discrete transistor audio
amplifiers barely supplied a few hundred milliwatts, but power and audio fidelity gradually
increased as better transistors became available and amplifier architecture evolved.

Modern transistor audio amplifiers of up to a few hundred watts are common and relatively
inexpensive
Voltage divider bias

Voltage divider bias

The voltage divider is formed using external resistors R1 and R2. The voltage across R2
forward biases the emitter junction. By proper selection of resistors R1 and R2, the operating
point of the transistor can be made independent of β. In this circuit, the voltage divider holds
the base voltage fixed independent of base current provided the divider current is large
compared to the base current. However, even with a fixed base voltage, collector current
varies with temperature (for example) so an emitter resistor is added to stabilize the Q-point,
similar to the above circuits with emitter resistor.

In this circuit the base voltage is given by:

voltage across

provided .

Also

For the given circuit,

Merits:

Unlike above circuits, only one dc supply is necessary.

Operating point is almost independent of β variation.
Operating point stabilized against shift in temperature.
Demerits:

In this circuit, to keep IC independent of β the following condition must be met:

which is approximately the case if

where R1 || R2 denotes the equivalent resistance of R1 and R2 connected in parallel.

As β-value is fixed for a given transistor, this relation can be satisfied either by
keeping RE fairly large, or making R1||R2 very low.

If RE is of large value, high VCC is necessary. This increases cost as well as

precautions necessary while handling.
If R1 || R2 is low, either R1 is low, or R2 is low, or both are low. A low R1 raises
VB closer to VC, reducing the available swing in collector voltage, and limiting
how large RC can be made without driving the transistor out of active mode. A
low R2 lowers Vbe, reducing the allowed collector current. Lowering both
resistor values draws more current from the power supply and lowers the input
resistance of the amplifier as seen from the base.

AC as well as DC feedback is caused by RE, which reduces the AC voltage gain of the
amplifier. A method to avoid AC feedback while retaining DC feedback is discussed
below.

Base Bias

The simplest biasing applies a base-bias resistor between the base and a base battery VBB. It is
convenient to use the existing VCC supply instead of a new bias supply. An example of an
audio amplifier stage using base-biasing is ―Crystal radio with one transistor . . . ‖ crystal
radio, Ch 9 . Note the resistor from the base to the battery terminal. A similar circuit is shown
in Figure below.

Write a KVL (Krichhoff's voltage law) equation about the loop containing the battery, R B, and
the VBE diode drop on the transistor in Figure below. Note that we use VBB for the base
supply, even though it is actually VCC. If β is large we can make the approximation that IC =IE.
For silicon transistors VBE≅0.7V.
Base-bias

Silicon small signal transistors typically have a β in the range of 100-300. Assuming that we
have a β=100 transistor, what value of base-bias resistor is required to yield an emitter current
of 1mA?

Solving the IE base-bias equation for RB and substituting β, VBB, VBE, and IE yields 930kΩ.
The closest standard value is 910kΩ.

What is the the emitter current with a 910kΩ resistor? What is the emitter current if we
randomly get a β=300 transistor?

The emitter current is little changed in using the standard value 910kΩ resistor. However,
with a change in β from 100 to 300, the emitter current has tripled. This is not acceptable in a
power amplifier if we expect the collector voltage to swing from near VCC to near ground.
However, for low level signals from micro-volts to a about a volt, the bias point can be
centered for a β of square root of (100·300)=173. The bias point will still drift by a
considerable amount . However, low level signals will not be clipped.

Base-bias by its self is not suitable for high emitter currents, as used in power amplifiers. The
base-biased emitter current is not temperature stable. Thermal run away is the result of high
emitter current causing a temperature increase which causes an increase in emitter current,
which further increases temperature.
Collector-feedback bias

Variations in bias due to temperature and beta may be reduced by moving the V BB end of the
base-bias resistor to the collector as in Figure below. If the emitter current were to increase,
the voltage drop across RC increases, decreasing VC, decreasing IB fed back to the base. This,
in turn, decreases the emitter current, correcting the original increase.

Write a KVL equation about the loop containing the battery, RC , RB , and the VBE drop.
Substitute IC≅IE and IB≅IE/β. Solving for IE yields the IE CFB-bias equation. Solving for IB
yields the IB CFB-bias equation.

Collector-feedback bias.

Find the required collector feedback bias resistor for an emitter current of 1 mA, a 4.7K
collector load resistor, and a transistor with β=100 . Find the collector voltage VC. It should be
approximately midway between VCC and ground.

The closest standard value to the 460k collector feedback bias resistor is 470k. Find the
emitter current IE with the 470 K resistor. Recalculate the emitter current for a transistor with
β=100 and β=300.
We see that as beta changes from 100 to 300, the emitter current increases from 0.989mA to
1.48mA. This is an improvement over the previous base-bias circuit which had an increase
from 1.02mA to 3.07mA. Collector feedback bias is twice as stable as base-bias with respect
to beta variation.

Emitter-bias

Inserting a resistor RE in the emitter circuit as in Figure below causes degeneration, also
known as negative feedback. This opposes a change in emitter current IE due to temperature
changes, resistor tolerances, beta variation, or power supply tolerance. Typical tolerances are
as follows: resistor— 5%, beta— 100-300, power supply— 5%. Why might the emitter
resistor stabilize a change in current? The polarity of the voltage drop across RE is due to the
collector battery VCC. The end of the resistor closest to the (-) battery terminal is (-), the end
closest to the (+) terminal it (+). Note that the (-) end of RE is connected via VBB battery and
RB to the base. Any increase in current flow through RE will increase the magnitude of
negative voltage applied to the base circuit, decreasing the base current, decreasing the emitter
current. This decreasing emitter current partially compensates the original increase.

Emitter-bias

Note that base-bias battery VBB is used instead of VCC to bias the base in Figure above. Later
we will show that the emitter-bias is more effective with a lower base bias battery.
Meanwhile, we write the KVL equation for the loop through the base-emitter circuit, paying
attention to the polarities on the components. We substitute IB≅IE/β and solve for emitter
current IE. This equation can be solved for RB , equation: RB emitter-bias, Figure above.

Before applying the equations: RB emitter-bias and IE emitter-bias, Figure above, we need to
choose values for RC and RE . RC is related to the collector supply VCC and the desired
collector current IC which we assume is approximately the emitter current IE. Normally the
bias point for VC is set to half of VCC. Though, it could be set higher to compensate for the
voltage drop across the emitter resistor RE. The collector current is whatever we require or
choose. It could range from micro-Amps to Amps depending on the application and transistor
rating. We choose IC = 1mA, typical of a small-signal transistor circuit. We calculate a value
for RC and choose a close standard value. An emitter resistor which is 10-50% of the collector
load resistor usually works well.

Collector-to-base biased bipolar amplifier

Figure 2: Left - small-signal circuit corresponding to Figure 1; center - inserting independent

source and marking leads to be cut; right - cutting the dependent source free and short-
circuiting broken leads

Figure 1 (top right) shows a bipolar amplifier with feedback bias resistor Rf driven by a
Norton signal source. Figure 2 (left panel) shows the corresponding small-signal circuit
obtained by replacing the transistor with its hybrid-pi model. The objective is to find the
return ratio of the dependent current source in this amplifier.[9] To reach the objective, the
steps outlined above are followed. Figure 2 (center panel) shows the application of these steps
up to Step 4, with the dependent source moved to the left of the inserted source of value it, and
the leads targeted for cutting marked with an x. Figure 2 (right panel) shows the circuit set up
for calculation of the return ratio T, which is

The return current is

The feedback current in Rf is found by current division to be:

The base-emitter voltage vπ is then, from Ohm's law:

Consequently,

Application in asymptotic gain model

The overall transresistance gain of this amplifier can be shown to be:

with R1 = RS || rπ and R2 = RD || rO.

This expression can be rewritten in the form used by the asymptotic gain model, which
expresses the overall gain of a feedback amplifier in terms of several independent factors that
are often more easily derived separately than the overall gain itself, and that often provide
insight into the circuit. This form is:

where the so-called asymptotic gain G∞ is the gain at infinite gm, namely:

and the so-called feed forward or direct feedthrough G0 is the gain for zero gm, namely:

For additional applications of this method, see asymptotic gain model.

1. DC Biasing Circuits
2. The ac operation of an amplifier depends on the initial dc values of IB, IC, and VCE.
3. By varying IB around an initial dc value, IC and VCE are made to vary around their
initial dc values.
 4. DC biasing is a static operation since it deals with setting a fixed (steady) level of
current (through the device) with a desired fixed voltage drop across the device.

+VCC

RC
RB
v out

v in vce
ib

ic

Purpose of the DC biasing circuit

1. To turn the device ―ON‖
2. To place it in operation in the region of its characteristic where the device operates
most linearly, i.e. to set up the initial dc values of IB, IC, and VCE

Voltage-Divider Bias
• The voltage – divider (or potentiometer) bias circuit is by far the most commonly used.
• RB1, RB2
voltage-divider to set the value of VB , IB +VCC
• C3
to short circuit ac signals to ground, while not effect the DC operating (or biasing)
of a circuit

RC
R1
(RE stabilizes the ac signals)

Bypass Capacitor

+VCC

Graphical DC Bias Analysis

IC RC
R1

R2
IE

RE
VCC ICRC VCE IERE 0
for I C IE
1 VCC
IC VCE
RC RE RC RE
Point - slope form of straight line equation :
y mx IC(sat)
c = VCC/(RC+RE)

DC Load Line
IC
(mA)
VCE(off) = VCC
• The straight line is know as the DC load line
• Its significance is that regardless of the behavior of the transistor, the collector current
IC and the collector-emitter voltage VCE must always lie on the load line, depends
ONLY on the VCC, RC and RE
• (i.e. The dc load line is a graph that represents all the possible combinations of IC
and VCE for a given amplifier. For every possible value of IC, and amplifier will
have a corresponding value of VCE.)
• It must be true at the same time as the transistor characteristic. Solve two condition
using simultaneous equation
graphically Q-point !!

Q-Point (Static Operation Point)

• When a transistor does not have an ac input, it will have specific dc values of IC and
VCE.
• These values correspond to a specific point on the dc load line. This point is called the
Q-point.
• The letter Q corresponds to the word (Latent) quiescent, meaning at rest.
• A quiescent amplifier is one that has no ac signal applied and therefore has constant dc
values of IC and VCE.
• The intersection of the dc bias value of IB with the dc load line determines the Q-
point.
• It is desirable to have the Q-point centered on the load line. Why?
• When a circuit is designed to have a centered Q-point, the amplifier is said to be
midpoint biased.
• Midpoint biasing allows optimum ac operation of the amplifier.

DC Biasing + AC signal
• When an ac signal is applied to the base of the transistor, IC and VCE will both vary
around their Q-point values.
• When the Q-point is centered, IC and VCE can both make the maximum possible
transitions above and below their initial dc values.
• When the Q-point is above the center on the load line, the input signal may cause the
transistor to saturate. When this happens, a part of the output signal will be clipped
off.
• When the Q-point is below midpoint on the load line, the input signal may cause the
transistor to cutoff. This can also cause a portion of the output signal to be clipped.

DC and AC Equivalent Circuits

+VCC
+VCC

RC
R1 IC RC
R1
R
 rC
vin vce

R1//R2

Bias Circuit DC equivalent circuit rC = RC//RL

AC equ ckt

• The ac load line of a given amplifier will not follow the plot of the dc load line.
• This is due to the dc load of an amplifier is different from the ac load.

ac load line

IC Q - point

dc load line

VCE

What does the ac load line tell you?

• The ac load line is used to tell you the maximum possible output voltage swing for a
given common-emitter amplifier.
• In other words, the ac load line will tell you the maximum possible peak-to-peak
output voltage (Vpp ) from a given amplifier.
• This maximum Vpp is referred to as the compliance of the amplifier.
(AC Saturation Current Ic(sat) , AC Cutoff Voltage VCE(off) )
Bias stabilization

The establishment of an operating point on the transistor volt-ampere characteristics by means

of direct voltages and currents.

Since the transistor is a three-terminal device, any one of the three terminals may be used as a
common terminal to both input and output. In most transistor circuits the emitter is used as the
common terminal, and this common emitter, or grounded emitter, is indicated in illus. a. If the
transistor is to used as a linear device, such as an audio amplifier, it must be biased to operate
in the active region. In this region the collector is biased in the reverse direction and the
emitter in the forward direction. The area in the common-emitter transistor characteristics to
the right of the ordinate VCE = 0 and above IC = 0 is the active region. Two more biasing
regions are of special interest for those cases in which the transistor is intended to operate as a
switch. These are the saturation and cutoffregions. The saturation region may be defined as
the region where the collector current is independent of base current for given values
of VCC and RL. Thus, the onset of saturation can be considered to take place at the knee of the
common-emitter transistor curves. See also Amplifier; Transistor.

Translator circuits. (a) Fixed-bias. (b) Collector-to-base bias. (c) Self-bias.

In saturation, the transistor current IC is nominally VCC/RL. Since RL is small, it may be

necessary to keep VCCcorrespondingly small in order to stay within the limitations imposed by
the transistor on maximum-current and collector-power dissipation. In the cutoff region it is
required that the emitter current IE be zero, and to accomplish this it is necessary to reverse-
bias the emitter junction so that the collector current is approximately equal to thereverse
saturation current ICO. A reverse-biasing voltage of the order of 0.1 V across the emitter
junction willordinarily be adequate to cut off either a germanium or silicon transistor.
The particular method to be used in establishing an operating point on the transistor
characteristics depends on whether the transistor is to operate in the active, saturation or cutoff
regions; on the application under consideration; on the thermal stability of the circuit; and on
other factors.

In a fixed-bias circuit, the operating point for the circuit of illus. a can be established by
noting that the required current IB is constant, independent of the quiescent collector
current IC, which is why this circuit is called the fixed-bias circuit. Transistor biasing circuits
are frequently compared in terms of the value of the stability factor S = ∂IC/∂ICO, which is the
rate of change of collector current with respect to reverse saturation current. The smaller the
value of S, the less likely the circuit will exhibit thermal runaway. S, as defined here, cannot
be smaller than unity. Other stability factors are defined in terms of dc current gain hFE as
∂IC/∂hFE, and in terms of base-to-emitter voltage as ∂IC/∂VBE. However, bias circuits with
small values of S will also perform satisfactorily for transistors that have large variations
of hFE and VBE. For the fixed-bias circuit it can be shown that S = hFE + 1, and if hFE = 50,
thenS = 51. Such a large value of S makes thermal runaway a definite possibility with this
circuit.

In collector-to-base bias, an improvement in stability is obtained if the resistor RB in illus. a is

returned to the collector junction rather than to the battery terminal. Such a connection is
shown in illus. b. In this bias circuit, if ICtends to increase (either because of a rise in
temperature or because the transistor has been replaced by another), then VCE decreases.
Hence IB also decreases and, as a consequence of this lowered bias current, the collector
current is not allowed to increase as much as it would if fixed bias were used. The stability
factor S is shown in Eq. (1).

1.
This value is smaller than hFE + 1, which is the value obtained for the fixed-bias case.

If the load resistance RL is very small, as in a transformer-coupled circuit, then the previous
expression for S shows that there would be no improvement in the stabilization in the
collector-to-base bias circuit over the fixed-bias circuit. A circuit that can be used even if there
is zero dc resistance in series with the collector terminal is the self-biasing configuration of
illus. c. The current in the resistance RE in the emitter lead causes a voltage drop which is in
the direction to reverse-bias the emitter junction. Since this junction must be forward-biased
(for active region bias), the bleeder R1-R2 has been added to the circuit.

If IC tends to increase, the current in RE increases. As a consequence of the increase in voltage

drop across RE, the base current is decreased. Hence IC will increase less than it would have
had there been no self-biasing resistor RE. The stabilization factor for the self-bias circuit is
shown by Eq. (2), where RB = R1R2/(R1 + R2). The smaller the value of RB, the

2.
better the stabilization. Even if RB approaches zero, the value of S cannot be reduced below
unity.

In order to avoid the loss of signal gain because of the degeneration caused by RE, this resistor
is often bypassed by a very large capacitance, so that its reactance at the frequencies under
consideration is very small.
The selection of an appropriate operating point (ID, VGS, VDS) for a field-effect transistor (FET)
amplifier stage is determined by considerations similar to those given to transistors, as
discussed previously. These considerations are output-voltage swing, distortion, power
dissipation, voltage gain, and drift of drain current. In most cases it is not possible to satisfy
all desired specifications simultaneously.
PART-B
 UNIT III: DIGITAL ELECTRONICS

Binary number system – AND, OR, NOT, NAND, NOR circuits – Boolean algebra –
Exclusive OR gate – Flip flops – Half and full adders – Registers – Counters –A/D and D/A
conversion.

BOOLEAN ALGEBRA AND MINIMIZATION

1.1 Introduction:

The English mathematician George Boole (1815-1864) sought to give symbolic form
to Aristotle‘s system of logic. Boole wrote a treatise on the subject in 1854, titled An
Investigation of the Laws of Thought, on Which Are Founded the Mathematical Theories of
Logic and Probabilities, which codified several rules of relationship between mathematical
quantities limited to one of two possible values: true or false, 1 or 0. His mathematical system
became known as Boolean algebra.
All arithmetic operations performed with Boolean quantities have but one of two possible
Outcomes: either 1 or 0. There is no such thing as ‖2‖ or ‖-1‖ or ‖1/2‖ in the Boolean world.
It is a world in which all other possibilities are invalid by fiat. As one might guess, this is not
the kind of math you want to use when balancing a checkbook or calculating current through a
resistor.
However, Claude Shannon of MIT fame recognized how Boolean algebra could be applied to
on-and-off circuits, where all signals are characterized as either ‖high‖ (1) or ‖low‖ (0).
His1938 thesis, titled A Symbolic Analysis of Relay and Switching Circuits, put Boole‘s
theoretical work to use in a way Boole never could have imagined, giving us a powerful
mathematical tool for designing and analyzing digital circuits.
Like ‖normal‖ algebra, Boolean algebra uses alphabetical letters to denote variables.
Unlike ‖normal‖ algebra, though, Boolean variables are always CAPITAL letters, never
lowercase.
Because they are allowed to possess only one of two possible values, either 1 or 0, each and
every variable has a complement: the opposite of its value. For example, if variable ‖A‖ has a
value of 0, then the complement of A has a value of 1. Boolean notation uses a bar above the
variable character to denote complementation, like this:

In written form, the complement of ‖A‖ denoted as ‖A-not‖ or ‖A-bar‖. Sometimes a ‖prime‖
symbol is used to represent complementation. For example, A‘ would be the complement of
A, much the same as using a prime symbol to denote differentiation in calculus rather than the
fractional notation dot. Usually, though, the ‖bar‖ symbol finds more widespread use than the
‖prime‖ symbol, for reasons that will become more apparent later in this chapter.

1.2 Boolean Arithmetic:

Let us begin our exploration of Boolean algebra by adding numbers together:

0+0=0
0+1=1
1+0=1
1+1=1
The first three sums make perfect sense to anyone familiar with elementary addition. The
Last sum, though, is quite possibly responsible for more confusion than any other single
statement in digital electronics, because it seems to run contrary to the basic principles of
mathematics.
Well, it does contradict principles of addition for real numbers, but not for Boolean numbers.
Remember that in the world of Boolean algebra, there are only two possible values for any
quantity and for any arithmetic operation: 1 or 0. There is no such thing as ‖2‖ within the
scope of Boolean values. Since the sum ‖1 + 1‖ certainly isn‘t 0, it must be 1 by process of
elimination.

1.2.1 Addition – OR Gate Logic:

Boolean addition corresponds to the logical function of an ‖OR‖ gate,

as well as to parallel switch contacts:
There is no such thing as subtraction in the realm of Boolean mathematics. Subtraction
Implies the existence of negative numbers: 5 - 3 is the same thing as 5 + (-3), and in Boolean
algebra negative quantities are forbidden. There is no such thing as division in Boolean
mathematics, either, since division is really nothing more than compounded subtraction, in the
same way that multiplication is compounded addition.

1.2.2 Multiplication – AND Gate logic

Multiplication is valid in Boolean algebra, and thankfully it is the same as in real-

number algebra: anything multiplied by 0 is 0, and anything multiplied by 1 remains
unchanged:
0×0=0
0×1=0
1×0=0
1×1=1
This set of equations should also look familiar to you: it is the same pattern found in the truth
table for an AND gate. In other words, Boolean multiplication corresponds to the logical
function of an ‖AND‖ gate, as well as to series switch contacts:
1.2.3 Complementary Function – NOT gate Logic

Boolean complementation finds equivalency in the form of the NOT gate, or a normally
closed switch or relay contact:

1.3 Boolean Algebraic Identities

In mathematics, an identity is a statement true for all possible values of its variable or
variables. The algebraic identity of x + 0 = x tells us that anything (x) added to zero equals the
original ‖anything,‖ no matter what value that ‖anything‖ (x) may be. Like ordinary algebra,
Boolean algebra has its own unique identities based on the bivalent states of Boolean
variables.
The first Boolean identity is that the sum of anything and zero is the same as the original
‖anything.‖ This identity is no different from its real-number algebraic equivalent:

No matter what the value of A, the output will always be the same: when A=1, the output
will also be 1; when A=0, the output will also be 0.
The next identity is most definitely different from any seen in normal algebra. Here we
discover that the sum of anything and one is one:

No matter what the value of A, the sum of A and 1 will always be 1. In a sense, the ‖1‖
signal overrides the effect of A on the logic circuit, leaving the output fixed at a logic level of
1.
Next, we examine the effect of adding A and A together, which is the same as connecting
both inputs of an OR gate to each other and activating them with the same signal:

In real-number algebra, the sum of two identical variables is twice the original variable‘s
value (x + x = 2x), but remember that there is no concept of ‖2‖ in the world of Boolean math,
only 1 and 0, so we cannot say that A + A = 2A. Thus, when we add a Boolean quantity to
itself, the sum is equal to the original quantity: 0 + 0 = 0, and 1 + 1 = 1.
Introducing the uniquely Boolean concept of complementation into an additive identity, we
find an interesting effect. Since there must be one ‖1‖ value between any variable and its
complement, and since the sum of any Boolean quantity and 1 is 1, the sum of a variable and
its complement must be 1:
Four multiplicative identities: Ax0, Ax1, AxA, and AxA‘. Of these, the first two are no
different from their equivalent expressions in regular algebra:

The third multiplicative identity expresses the result of a Boolean quantity multiplied by
itself. In normal algebra, the product of a variable and itself is the square of that variable (3x 3
= 32 = 9). However, the concept of ‖square‖ implies a quantity of 2, which has no meaning in
Boolean algebra, so we cannot say that A x A = A2. Instead, we find that the product of a
Boolean quantity and itself is the original quantity, since 0 x 0 = 0 and
1 x 1 = 1:

The fourth multiplicative identity has no equivalent in regular algebra because it uses the
complement of a variable, a concept unique to Boolean mathematics. Since there must be
one ‖0‖ value between any variable and its complement, and since the product of any Boolean
quantity and 0 is 0, the product of a variable and its complement must be 0:

1.4 Principle of Duality:

It states that every algebraic expression is deducible from the postulates of Boolean
algebra, and it remains valid if the operators & identity elements are interchanged. If the
inputs of a NOR gate are inverted we get a AND equivalent circuit. Similarly when the inputs
of a NAND gate are inverted, we get a OR equivalent circuit.
This property is called DUALITY.

1.5 Theorems of Boolean algebra:

The theorems of Boolean algebra can be used to simplify many a complex Boolean
expression and also to transform the given expression into a more useful and meaningful
equivalent expression. The theorems are presented as pairs, with the two theorems in a given
pair being the dual of each other. These theorems can be very easily verified by the method of
‗perfect induction‘. According to this method, the validity of the expression is tested for all
possible combinations of values of the variables involved. Also, since the validity of the
theorem is based on its being true for all possible combinations of values of variables, there is
no reason why a variable cannot be replaced with its complement, or vice versa, without
disturbing the validity. Another important point is that, if a given expression is valid, its dual
will also be valid
1.5.1 Theorem 1 (Operations with ‗0‘ and ‗1‘)

(a) 0.X = 0 and (b) 1+X= 1

Where X is not necessarily a single variable – it could be a term or even a large expression.

Theorem 1(a) can be proved by substituting all possible values of X, that is, 0 and 1, into the
given expression and checking whether the LHS equals the RHS:

• For X = 0, LHS = 0.X = 0.0 = 0 = RHS.

• For X= 1, LHS = 0.1 = 0 = RHS.

Thus, 0.X =0 irrespective of the value of X, and hence the proof.

Theorem 1(b) can be proved in a similar manner. In general, according to theorem 1,

0. (Boolean expression) = 0 and 1+ (Boolean expression) =1.

For example: 0. (A.B+B.C +C.D) = 0 and 1+ (A.B+B.C +C.D) = 1, where A, B and C are
Boolean variables.

1.5.2 Theorem 2 (Operations with ‗0‘ and ‗1‘)

(a) 1.X = X and (b) 0+X = X

where X could be a variable, a term or even a large expression. According to this theorem,
ANDing a Boolean expression to ‗1‘ or ORing ‗0‘ to it makes no difference to the expression:

• For X = 0, LHS = 1.0 = 0 = RHS.

• For X = 1, LHS = 1.1 = 1 = RHS.
Also,
1. (Boolean expression) = Boolean expression and 0 + (Boolean expression) = Boolean
expression.

For example,
1.(A+B.C +C.D) = 0+(A+B.C +C.D) = A+B.C +C.D

1.5.3 Theorem 3 (Idempotent or Identity Laws)

(a) X.X.X……X = X and (b) X+X+X +···+X = X

Theorems 3(a) and (b) are known by the name of idempotent laws, also known as identity
laws.

Theorem 3(a) is a direct outcome of an AND gate operation, whereas theorem 3(b) represents
an OR gate operation when all the inputs of the gate have been tied together. The scope of
idempotent laws can be expanded further by considering X to be a term or an expression. For
example, let us apply idempotent laws to simplify the following Boolean expression:

1.5.4 Theorem 4 (Complementation Law)

(a) X_X = 0 and (b) X+X = 1

According to this theorem, in general, any Boolean expression when ANDed to its
complement yields a ‗0‘ and when ORed to its complement yields a ‗1‘, irrespective of the
complexity of the expression:

Hence, theorem 4(a) is proved. Since theorem 4(b) is the dual of theorem 4(a), its proof is
implied.
The example below further illustrates the application of complementation laws:
1.5.5 Theorem 5 (Commutative property)

Mathematical identity, called a ‖property‖ or a ‖law,‖ describes how differing

variables relate to each other in a system of numbers. One of these properties is known as
the commutative property, and it applies equally to addition and multiplication. In essence, the
commutative property tells us we can reverse the order of variables that are either added
together or multiplied together without changing the truth of the expression:

Commutative property of addition

A+B=B+A

Commutative property of multiplication

AB = BA

1.5.6 Theorem 6 (Associative Property)

The Associative Property, again applying equally well to addition and multiplication.
This property tells us we can associate groups of added or multiplied variables together with
parentheses without altering the truth of the equations.

Associative property of addition

A + (B + C) = (A + B) + C

Associative property of multiplication

A (BC) = (AB) C

1.5.7 Theorem 7 (Distributive Property)

The Distributive Property, illustrating how to expand a Boolean expression formed by

the product of a sum, and in reverse shows us how terms may be factored out of Boolean
sums-of-products:
Distributive property
A (B + C) = AB + AC

1.5.8 Theorem 8 (Absorption Law or Redundancy Law)

(a) X+X.Y = X and (b) X.(X+Y) = X

The proof of absorption law is straightforward:

X+X.Y = X. (1+Y) = X.1 = X

Theorem 8(b) is the dual of theorem 8(a) and hence stands proved.
The crux of this simplification theorem is that, if a smaller term appears in a larger term, then
the larger term is redundant. The following examples further illustrate the underlying concept:

1.5.9 Demorgan‘s Theorem

De-Morgan was a great logician and mathematician. He had contributed much to

logic. Among his contribution the following two theorems are important

1.5.9.1 De-Morgan‘s First Theorem

It States that ―The complement of the sum of the variables is equal to the product of the
complement of each variable‖. This theorem may be expressed by the following Boolean
expression.
1.5.9.2 De-Morgan‘s Second Theorem

It states that the ―Complement of the product of variables is equal to the sum of complements
of each individual variables‖. Boolean expression for this theorem is

1.6 Boolean Function

Z=AB‘+A‘C+A‘B‘C‘

1.7 Canonical Form of Boolean Expressions

An expanded form of Boolean expression, where each term contains all Boolean variables in
their true or complemented form, is also known as the canonical form of the expression. As an
illustration, is a Boolean function of three variables
expressed in canonical form. This function after simplification reduces to and
loses its canonical form.

1.7.1 MIN TERMS AND MAX TERMS

Any boolean expression may be expressed in terms of either minterms or maxterms. To do
this we must first define the concept of a literal. A literal is a single variable within a term
which may or may not be complemented. For an expression with N variables, minterms and
maxterms are defined as follows :

• A minterm is the product of N distinct literals where each literal occurs exactly once.
• A maxterm is the sum of N distinct literals where each literal occurs exactly once.
Product-of-Sums Expressions

1.7.2 Standard Forms

A product-of-sums expression contains the product of different terms, with each term
being either a single literal or a sum of more than one literal. It can be obtained from the truth
table by considering those input combinations that produce a logic ‗0‘ at the output. Each such
input combination gives a term, and the product of all such terms gives the expression.
Different terms are obtained by taking the sum of the corresponding literals. Here, ‗0‘ and ‗1‘
respectively mean the uncomplemented and complemented variables, unlike sum-of-products
expressions where ‗0‘ and ‗1‘ respectively mean complemented and uncomplemented
variables.
Since each term in the case of the product-of-sums expression is going to be the sum of
literals, this implies that it is going to be implemented using an OR operation. Now, an OR
gate produces a logic ‗0‘ only when all its inputs are in the logic ‗0‘ state, which means that
the first term corresponding to the second row of the truth table will be A+B+C. The product-
of-sums Boolean expression for this truth table is given by Transforming the given product-
of-sums expression into an equivalent sum-of-products expression is a straightforward
process. Multiplying out the given expression and carrying out the obvious simplification
provides the equivalent sum-of-products expression:
A given sum-of-products expression can be transformed into an equivalent product-of-sums
expression by (a) taking the dual of the given expression, (b) multiplying out different terms
to get the sum-of products form, (c) removing redundancy and (d) taking a dual to get the
equivalent product-of-sums expression. As an illustration, let us find the equivalent product-
of-sums expression of the sum-of products expression

The dual of the given expression =

1.8 Minimization Technique

The primary objective of all simplification procedures is to obtain an expression that

has the minimum number of terms. Obtaining an expression with the minimum number of
literals is usually the secondary objective. If there is more than one possible solution with the
same number of terms, the one having the minimum number of literals is the choice.

There are several methods for simplification of Boolean logic expressions. The process is
usually called logic minimization‖ and the goal is to form a result which is efficient. Two
methods we will discuss are algebraic minimization and Karnaugh maps. For very
complicated problems the former method can be done using special software analysis
programs. Karnaugh maps are also limited to problems with up to 4 binary inputs. The Quine–
McCluskey tabular method is used for more than 4 binary inputs.

1.9 Karnaugh Map Method

Maurice Karnaugh, a telecommunications engineer, developed the Karnaugh map at

Bell Labs in 1953 while designing digital logic based telephone switching circuits.
Karnaugh maps reduce logic functions more quickly and easily compared to Boolean
algebra. By reduce we mean simplify, reducing the number of gates and inputs. We like to
simplify logic to a lowest cost form to save costs by elimination of components. We define
lowest cost as being the lowest number of gates with the lowest number of inputs per gate.
A Karnaugh map is a graphical representation of the logic system. It can be drawn directly
from either minterm (sum-of-products) or maxterm (product-of-sums) Boolean expressions.
Drawing a Karnaugh map from the truth table involves an additional step of writing the
minterm or maxterm expression depending upon whether it is desired to have a minimized
sum-of-products or a minimized product of-sums expression

1.9.1 Construction of a Karnaugh Map

An n-variable Karnaugh map has 2n squares, and each possible input is allotted a
square. In the case of a minterm Karnaugh map, ‗1‘ is placed in all those squares for which
the output is ‗1‘, and ‗0‘ is placed in all those squares for which the output is ‗0‘. 0s are
omitted for simplicity. An ‗X‘ is placed in squares corresponding to ‗don‘t care‘ conditions. In
the case of a maxterm Karnaugh map, a ‗1‘ is placed in all those squares for which the output
is ‗0‘, and a ‗0‘ is placed for input entries corresponding to a ‗1‘ output. Again, 0s are omitted
for simplicity, and an ‗X‘ is placed in squares corresponding to ‗don‘t care‘ conditions. The
choice of terms identifying different rows and columns of a Karnaugh map is not unique for a
given number of variables. The only condition to be satisfied is that the designation of
adjacent rows and adjacent columns should be the same except for one of the literals being
complemented. Also, the extreme rows and extreme columns are considered adjacent.

Some of the possible designation styles for two-, three- and four-variable minterm Karnaugh
maps are shown in the figure below.
The style of row identification need not be the same as that of column identification as long as
it meets the basic requirement with respect to adjacent terms. It is, however, accepted practice
to adopt a uniform style of row and column identification. Also, the style shown in the figure
below is more commonly used. A similar discussion applies for maxterm Karnaugh maps.
Having drawn the Karnaugh map, the next step is to form groups of 1s as per the following
guidelines:

1. Each square containing a ‗1‘ must be considered at least once, although it can be
considered as often as desired.

2. The objective should be to account for all the marked squares in the minimum number
of groups.

3. The number of squares in a group must always be a power of 2, i.e. groups can have
1,2, 4_ 8, 16, squares.

4. Each group should be as large as possible, which means that a square should not be
accounted for by itself if it can be accounted for by a group of two squares; a group of
two squares should not be made if the involved squares can be included in a group of
four squares and so on.

5. ‗Don‘t care‘ entries can be used in accounting for all of 1-squares to make optimum
groups. They are marked ‗X‘ in the corresponding squares. It is, however, not
necessary to account for all ‗don‘t care‘ entries. Only such entries that can be used to
advantage should be used.

Fig 1.9.1 Two variable K Map

Fig 1.9.2 Three variable K Map
Fig 1.9.3 Four variable K Map

Fig 1.9.4 Different Styles of row and column identification

Having accounted for groups with all 1s, the minimum ‗sum-of-products‘ or ‗product-of-
sums‘ expressions can be written directly from the Karnaugh map. Minterm Karnaugh map
and Maxterm Karnaugh map of the Boolean function of a two-input OR gate. The Minterm
and Maxterm Boolean expressions for the two-input OR gate are as follows:

Minterm Karnaugh map and Maxterm Karnaugh map of the three variable Boolean function
The truth table, Minterm Karnaugh map and Maxterm Karnaugh map of the four variable
Boolean function

To illustrate the process of forming groups and then writing the corresponding minimized
Boolean expression, The below figures respectively show minterm and maxterm Karnaugh
maps for the Boolean functions expressed by the below equations. The minimized expressions
as deduced from Karnaugh maps in the two cases are given by Equation in the case of the
minterm Karnaugh map and Equation in the case of the maxterm Karnaugh map:
1.10 Quine–McCluskey Tabular Method
 The Quine–McCluskey tabular method of simplification is based on the
complementation theorem, which says that

where X represents either a variable or a term or an expression and Y is a variable. This

theorem implies that, if a Boolean expression contains two terms that differ only in one
variable, then they can be combined together and replaced with a term that is smaller by one
literal. The same procedure is applied for the other pairs of terms wherever such a reduction is
possible. All these terms reduced by one literal are further examined to see if they can be
reduced further. The process continues until the terms become irreducible. The irreducible
terms are called prime implicants. An optimum set of prime implicants that can account for all
the original terms then constitutes the minimized expression. The technique can be applied
equally well for minimizing sum-of-products and product of-
sums expressions and is particularly useful for Boolean functions having more than six
variables as it can be mechanized and run on a computer. On the other hand, the Karnaugh
mapping method, to be discussed later, is a graphical method and becomes very cumbersome
when the number of variables exceeds six. The step-by-step procedure for application of the
tabular method for minimizing Boolean expressions,both sum-of-products and product-of-
sums, is outlined as follows:
1. The Boolean expression to be simplified is expanded if it is not in expanded form.
2. Different terms in the expression are divided into groups depending upon the number of 1s
they have.
True and complemented variables in a sum-of-products expression mean ‗1‘ and ‗0‘
respectively.

The reverse is true in the case of a product-of-sums expression. The groups are then arranged,
beginning with the group having the least number of 1s in its included terms. Terms within the
same group are arranged in ascending order of the decimal numbers represented by these
terms. As an illustration, consider the expression

As another illustration, consider a product-of-sums expression given by

The formation of groups and the arrangement of terms within different groups for the product-
of sums expression are as follows:

It may be mentioned here that the Boolean expressions that we have considered above did not
contain any optional terms. If there are any, they are also considered while forming groups.
This completes the first table.

3. The terms of the first group are successively matched with those in the next adjacent higher
order group to look for any possible matching and consequent reduction. The terms are
considered matched when all literals except for one match. The pairs of matched terms are
replaced with a single term where the position of the unmatched literals is replaced with a
dash (—). These new terms formed as a result of the matching process find a place in the
second table. The terms in the first table that do not find a match are called the prime
implicants and are marked with an asterisk (∗). The matched terms are ticked (_).
4. Terms in the second group are compared with those in the third group to look for a possible
match.
Again, terms in the second group that do not find a match become the prime implicants.
5. The process continues until we reach the last group. This completes the first round of
matching.
The terms resulting from the matching in the first round are recorded in the second table.
6. The next step is to perform matching operations in the second table. While comparing the
terms for a match, it is important that a dash (—) is also treated like any other literal, that is,
the dash signs also need to match. The process continues on to the third table, the fourth table
and so on until the terms become irreducible any further.
7. An optimum selection of prime implicants to account for all the original terms constitutes
the terms for the minimized expression. Although optional (also called ‗don‘t care‘) terms are
considered for matching, they do not have to be accounted for once prime implicants have
been identified.
Let us consider an example. Consider the following sum-of-products expression:

The second round of matching begins with the table shown on the previous page. Each term in
the first group is compared with every term in the second group. For instance, the first term in
the first group 00−1 matches with the second term in the second group 01−1 to yield 0−−1,
which is recorded in the table shown below. The process continues until all terms have been
compared for a possible match. Since this new table has only one group, the terms contained
therein are all prime implicants. In the present example, the terms in the first and second
tables have all found a match. But that is not always the case.

The next table is what is known as the prime implicant table. The prime implicant table
contains all the original terms in different columns and all the prime implicants recorded in
different rows as shown below:
Each prime implicant is identified by a letter. Each prime implicant is then examined one by
one and the terms it can account for are ticked as shown. The next step is to write a product-
of-sums expression using the prime implicants to account for all the terms. In the present
illustration, it is given as follows.

Obvious simplification reduces this expression to PQRS which can be interpreted to mean that
all prime implicants, that is, P, Q, R and S, are needed to account for all the original terms.
Therefore, the minimized expression =
What has been described above is the formal method of determining the optimum set of prime
implicants. In most of the cases where the prime implicant table is not too complex, the
exercise can be done even intuitively. The exercise begins with identification of those terms
that can be accounted for by only a single prime implicant. In the present example, 0011,
0110, 1001 and 1100 are such terms. As a result, P, Q, R and S become the essential prime
implicants. The next step is to find out if any terms have not been covered by the essential
prime implicants. In the present case, all terms have been covered by essential prime
implicants. In fact, all prime implicants are essential prime implicants in the present example.
As another illustration, let us consider a product-of-sums expression given by

The procedure is similar to that described for the case of simplification of sum-of-products
expressions.
The resulting tables leading to identification of prime implicants are as follows:

The prime implicant table is constructed after all prime implicants have been identified to
look for the optimum set of prime implicants needed to account for all the original terms. The
prime implicant table shows that both the prime implicants are the essential ones:
1.11 Universal Gates

OR, AND and NOT gates are the three basic logic gates as they together can be used
to construct the logic circuit for any given Boolean expression. NOR and NAND gates have
the property that they individually can be used to hardware-implement a logic circuit
corresponding to any given Boolean expression. That is, it is possible to use either only
NAND gates or only NOR gates to implement any Boolean expression. This is so because a
combination of NAND gates or a combination of NOR gates can be used to perform functions
of any of the basic logic gates. It is for this reason that NAND and
NOR gates are universal gates. As an illustration, Fig. 4.24 shows how two-input NAND
gates can be used to construct a NOT circuit, a two-input AND gate and a two-input OR gate.
Figure shows the same using NOR gates. Understanding the conversion of NAND to OR and
NOR to AND requires the use of DeMorgan‘s theorem, which is discussed in Chapter 6 on
Boolean algebra.

These are gates where we need to connect an external resistor, called the pull-up resistor,
between the output and the DC power supply to make the logic gate perform the intended
logic function. Depending on the logic family used to construct the logic gate, they are
referred to as gates with open collector output (in the case of the TTL logic family) or open
drain output (in the case of the MOS logic family). Logic families are discussed in detail in
Chapter 5. The advantage of using open collector/open drain gates lies in their capability of
providing an ANDing operation when outputs of several gates are tied together through a
common pull-up resistor,
Fig 1.11.1 Implementation of basic logic gates using only NAND gates.

without having to use an AND gate for the purpose. This connection is also referred to as
WIRE-AND connection. Figure shows such a connection for open collector NAND gates. The
output in this case would be
WIRE-AND connection with open collector/drain devices.
The disadvantage is that they are relatively slower and noisier. Open collector/drain devices
are therefore not recommended for applications where speed is an important consideration.

The Exclusive-OR function

One element conspicuously missing from the set of Boolean operations is that of Exclusive-
OR. Whereas the OR function is equivalent to Boolean addition, the AND function to
Boolean multiplication, and the NOT function (inverter) to Boolean complementation, there is
no direct Boolean equivalent for Exclusive-OR. This hasn‘t stopped people from developing a
symbol to represent it, though:

This symbol is seldom used in Boolean expressions because the identities, laws, and rules
of simplification involving addition, multiplication, and complementation do not apply to it.
However, there is a way to represent the Exclusive-OR function in terms of OR and AND, as
has been shown in previous chapters: AB‘ + A‘B.

Introduction
The term ‖combinational‖ comes to us from mathematics. In mathematics a
combination is an unordered set, which is a formal way to say that nobody cares which order
the items came in. Most games work this way, if you rolled dice one at a time and get a 2
followed by a 3 it is the same as if you had rolled a 3 followed by a 2. With combinational
logic, the circuit produces
the same output regardless of the order the inputs are changed. There are circuits which
depend on the when the inputs change, these circuits are called sequential logic. Even though
you will not find the term ‖sequential logic‖ in the chapter titles, the next several chapters will
discuss sequential logic. Practical circuits will have a mix of combinational and sequential
logic, with sequential logic making sure everything happens in order and combinational logic
performing functions like arithmetic, logic, or conversion.

3.1 Design Using Gates

A combinational circuit is one where the output at any time depends only on the
present combination of inputs at that point of time with total disregard to the past state of the
inputs. The logic gate is the most basic building block of combinational logic. The logical
function performed by a combinational circuit is fully defined by a set of Boolean
expressions. The other category of logic circuits, called sequential logic circuits, comprises
both logic gates and memory elements such as flip-flops. Owing to the presence of memory
elements, the output in a sequential circuit depends upon not only the present but also the past
state of inputs.
The Fig 3.1 shows the block schematic representation of a generalized combinational circuit
having n input variables and m output variables or simply outputs. Since the number of input
variables is
Fig 3.1 Generalized Combinational Circuit

n, there are 2n possible combinations of bits at the input. Each output can be expressed in
terms of input variables by a Boolean expression, with the result that the generalized system
of above fig can be expressed by m Boolean expressions. As an illustration, Boolean
expressions describing the function of a four-input OR/NOR gate are given as
….. Eq – 1

3.2 BCD Arithmetic Circuits

Addition and subtraction are the two most commonly used arithmetic operations, as
the other two, namely multiplication and division, are respectively the processes of repeated
addition and repeated subtraction, as was outlined in Chapter 2 dealing with binary arithmetic.
We will begin with the basic building blocks that form the basis of all hardware used to
perform the aforesaid arithmetic operations on binary numbers. These include half-adder, full
adder, half-subtractor, full subtractor and controlled inverter.

3.3 Binary Adder

3.3.1 Half-Adder

A half-adder is an arithmetic circuit block that can be used to add two bits. Such a
circuit thus has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY. Figure 3.2 shows the truth
table of a half-adder, showing all possible input combinations and the corresponding outputs.
The Boolean expressions for the SUM and CARRY outputs are given by the equations below

Fig 3.2 Truth Table of Half Adder

An examination of the two expressions tells that there is no scope for further simplification.
While the first one representing the SUM output is that of an EX-OR gate, the second one
representing the CARRY output is that of an AND gate. However, these two expressions can
certainly be represented in different forms using various laws and theorems of Boolean
algebra to illustrate the flexibility that the designer has in hardware-implementing as simple a
combinational function as that of a half-adder.
Fig 3.3 Logic Implementation of Half Adder
Although the simplest way to hardware-implement a half-adder would be to use a two-input
EX-OR gate for the SUM output and a two-input AND gate for the CARRY output, as shown
in Fig. 3.3, it could also be implemented by using an appropriate arrangement of either NAND
or NOR gates.

3.3.2 Full Adder

A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a
SUM and a CARRY output. Such a building block becomes a necessity when it comes to
adding binary numbers with a large number of bits. The full adder circuit overcomes the
limitation of the half-adder, which can be used to add two bits only. Let us recall the
procedure for adding larger binary numbers. We begin with the addition of LSBs of the two
numbers. We record the sum under the LSB column and take the carry, if any, forward to the
next higher column bits. As a result, when we add the next adjacent higher column bits, we
would be required to add three bits if there were a carry from the previous addition. We have a
similar situation for the other higher column bits. Also until we reach the MSB. A full adder is
therefore essential for the hardware implementation of an adder circuit capable of adding
larger binary numbers. A half-adder can be used for addition of LSBs only.

Fig 3.4 Truth Table of Full Adder

Figure 3.4 shows the truth table of a full adder circuit showing all possible input combinations
and corresponding outputs. In order to arrive at the logic circuit for hardware implementation
of a full adder, we will firstly write the Boolean expressions for the two output variables, that
is, the SUM and CARRY outputs, in terms of input variables. These expressions are then
simplified by using any of the simplification techniques described in the previous chapter. The
Boolean expressions for the two output variables are given in Equation below for the SUM
output (S) and in above Equation for the CARRY output (Cout):

The next step is to simplify the two expressions. We will do so with the help of the Karnaugh
mapping technique. Karnaugh maps for the two expressions are given in Fig. 3.5(a) for the
SUM output and Fig. 3.5(b) for the CARRY output. As is clear from the two maps, the
expression for the SUM (S) output cannot be simplified any further, whereas the simplified
Boolean expression for Cout is given by the equation
Figure 3.6 shows the logic circuit diagram of the full adder. A full adder can also be seen to
comprise two half-adders and an OR gate. The expressions for SUM and CARRY outputs can
be rewritten as follows:

Similarly, the expression for CARRY output can be rewritten as follows:

Fig 3.5 Karnaugh Map for the sum and carry out of a full adder
Fig 3.6 Logic circuit diagram of full adder

Boolean expression above can be implemented with a two-input EX-OR gate provided that
one of the inputs is Cin and the other input is the output of another two-input EX-OR gate
with A and B as its inputs. Similarly, Boolean expression above can be implemented by
ORing two minterms. One of them is the AND output of A and B. The other is also the output
of an AND gate whose inputs are Cin and the output of an EX-OR operation on A and B. The
whole idea of writing the Boolean expressions in this modified form was to demonstrate the
use of a half-adder circuit in building a full adder. Figure 3.7(a) shows logic implementation
of Equations above. Figure 3.7(b) is nothing but Fig. 3.7(a) redrawn with the portion of the
circuit representing a half-adder replaced with a block. The full adder of the type described
above forms the basic building block of binary adders. However, a single full adder circuit can
be used to add one-bit binary numbers only. A cascade arrangement of these adders can be
used to construct adders capable of adding binary numbers with a larger number of bits. For
example, a four-bit binary adder would require four full adders of the type shown in Fig. 3.7
to be connected in cascade. Figure 3.8 shows such an arrangement. (A3A2A1A0) and
(B3B2B1B0) are the two binary numbers to be added, with A0 and B0 representing LSBs and
A3 and B3 representing MSBs of the two numbers.
Fig 3.7 Logic Implementation of a full adder with Half Adders

Fig 3.8 Four Bit Binary Adder

3.4 Half-Subtractor

We will study the use of adder circuits for subtraction operations in the following pages.
Before we do that, we will briefly look at the counterparts of half-adder and full adder circuits
in the half-subtractor and full subtractor for direct implementation of subtraction operations
using logic gates.
A half-subtractor is a combinational circuit that can be used to subtract one binary digit from
another to produce a DIFFERENCE output and a BORROW output. The BORROW output
here specifies whether a ‗1‘ has been borrowed to perform the subtraction. The truth table of a
half-subtractor, as shown in Fig. 3.9, explains this further. The Boolean expressions for the
two outputs are given by the equations
Fig 3.9 Half Subtractor

Fig 3.10 Logic Diagram of a Half Subtractor

It is obvious that there is no further scope for any simplification of the Boolean expressions
given by above equations. While the expression for the DIFFERENCE (D) output is that of
an EX-OR gate, the expression for the BORROW output (Bo) is that of an AND gate with
input
A complemented before it is fed to the gate. Figure 3.10 shows the logic implementation of a
half-subtractor. Comparing a half-subtractor with a half-adder, we find that the expressions
for the SUM and DIFFERENCE outputs are just the same. The expression for BORROW in
the case of the half-subtractor is also similar to what we have for CARRY in the case of the
half-adder. If
the input A, that is, the minuend, is complemented, an AND gate can be used to implement
the
BORROW output. Note the similarities between the logic diagrams of Fig. 3.3 (half-adder)
and Fig. 3.10 (half-subtractor).

3.4.1 Full Subtractor

A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and
also takes into consideration whether a ‗1‘ has already been borrowed by the previous
adjacent lower minuend bit or not. As a result, there are three bits to be handled at the input of
a full subtractor, namely the two bits to be subtracted and a borrow bit designated as Bin .
There are two outputs, namely the DIFFERENCE output D and the BORROW output Bo. The
BORROW output bit tells whether the minuend bit needs to borrow a ‗1‘ from the next
possible higher minuend bit. Figure 3.11 shows the truth table of a full subtractor.
The Boolean expressions for the two output variables are given by the equations
Fig 3.11 Truth Table of Full Subtractor

Fig 3.12 K Maps for Difference and Borrow outputs

The Karnaugh maps for the two expressions are given in Fig. 3.12(a) for DIFFERENCE
output D and in Fig. 3.12(b) for BORROW output Bo. As is clear from the two Karnaugh
maps, no simplification is possible for the difference output D. The simplified expression for
Bo is given by the equation

If we compare these expressions with those derived earlier in the case of a full adder, we find
that the expression for DIFFERENCE output D is the same as that for the SUM output. Also,
the expression for BORROW output Bo is similar to the expression for CARRY-OUT Co. In
the case of a half-subtractor, the A input is complemented. By a similar analysis it can be
shown that a full subtractor can be implemented with half-subtractors in the same way as a
full adder was constructed using half-adders. Relevant logic diagrams are shown in Figs 3.7(a)
and (b) corresponding to Figs 3.7(a) and (b) respectively for a full adder. Again, more than
one full subtractor can be connected in cascade to perform subtraction on two larger binary
numbers. As an illustration, Fig. 3.13 shows a four-bit subtractor.
Fig 3.13 Four Bit Subtractor

Multipliers

Multiplication of binary numbers is usually implemented in microprocessors and

microcomputers by using repeated addition and shift operations. Since the binary adders are
designed to add only two binary numbers at a time, instead of adding all the partial products at
the end, they are added two at a time and their sum is accumulated in a register called the
accumulator register. Also, when the multiplier bit is ‗0‘, that very partial product is ignored,
as an all ‗0‘ line does not affect the final result. The basic hardware arrangement of such a
binary multiplier would comprise shift registers for the multiplicand and multiplier bits, an
accumulator register for storing partial products, a binary parallel adder and a clock pulse
generator to time various operations.
Binary multipliers are also available in IC form. Some of the popular type numbers in
the TTL family include 74261 which is a 2 × 4 bit multiplier (a four-bit multiplicand
designated as B0,B1,B2,B3 and B4, and a two-bit multiplier designated as M0, M1 and M2.
The MSBs B4 and M2 are used to represent signs. 74284 and 74285 are 4 × 4 bit multipliers.
They can be used together to perform high-speed multiplication of two four-bit numbers.
Figure 3.14 shows the arrangement. The result of multiplication is often required to be stored
in a register. The size of
this register (accumulator) depends upon the number of bits in the result, which at the most
can be equal to the sum of the number of bits in the multiplier and multiplicand. Some
multipliers ICs have an in-built register.
 Fig 3.14 4 x 4 Multiplier

Many microprocessors do not have in their ALU the hardware that can perform multiplication
or other complex arithmetic operations such as division, determining the square root,
trigonometric functions, etc. These operations in these microprocessors are executed through
software. For example, a multiplication operation may be accomplished by using a software
program that does multiplication through repeated execution of addition and shift instructions.
Other complex operations mentioned above can also be executed with similar programs.
Although the use of software reduces the hardware needed in the microprocessor, the
computation time in general is higher in the case of software-executed operations when
compared with the use of hardware to perform those operations.
MULTIPLEXERS

Many tasks in communications, control, and computer systems can be performed by

combinational logic circuits. When a circuit has been designed to perform some task in one
application, it often finds use in a different application as well. In this way, it acquires
different names from its various uses. In this and the following sections, we will describe a
number of such circuits and their uses. We will discuss their principles of operation,
specifying their MSI or LSI implementations. One common task is illustrated in Figure 12.
Data generated in one location is to be used in another location; A method is needed to
transmit it from one location to another through some communications channel. The data is
available, in parallel, on many different lines but must be transmitted over a single
communications link. A mechanism is needed to select which of the many data lines to
activate sequentially at any one time so that the data this line carries can be transmitted at that
time.This process is called multiplexing.An
example is the multiplexing of conversations on the telephone system. A number of telephone
conversations are alternately switched onto the telephone line many times per second.
Because of the nature of the human auditory system, listeners cannot detect that what they are
hearing is chopped up and that other people‘s conversations are interspersed with their own in
the transmission process.
Needed at the other end of the communications link is a device that will undo the
multiplexing: a demultiplexer. Such a device must accept the incoming serial data and direct it
in parallel to one of many output lines. The interspersed snatches of telephone conversations,
for example, must be sent to the correct listeners.
A digital multiplexer is a circuit with 2n data input lines and one output line. It must also have
a way of determining the specific data input line to be selected at any one time. This is done
with n other input lines, called the select or selector inputs, whose function is to select one of
the 2n data inputs for connection to the output. A circuit for n = 3 is shown in Figure 13. The
n selector lines have 2n = 8 combinations of values that constitute binary select numbers
Multiplexer with eight data inputs

Multiplexers as General-Purpose Logic Circuits

It is clear from Figures 13 and 14 that the structure of a multiplexer is that of a two-
level AND-OR logic circuit, with each AND gate having n + 1 inputs, where n is the number
of select inputs. It appears that the multiplexer would constitute a canonic sum-of-products
implementation of a switching function if all the data lines together represent just one
switching variable (or its complement) and each of the select inputs represents a switching
variable.
Let‘s work backward from a specified function of m switching variables for which we have
written a canonic sum-of-products expression. The size of multiplexer needed (number of
select inputs) is not evident. Suppose we choose a multiplexer that has m − 1 select inputs,
leaving only one other variable to accommodate all the data inputs.We write an output
function of these select inputs and the 2m–1 data inputs Di. Now we plan to assign m − 1 of
these variables to the select inputs; but how to make the assignment?4 There are really no
restrictions, so it can be done arbitrarily. The next step is to write the multiplexer output after
replacing the select inputs
with m − 1 of the variables of the given function. By comparing the two expressions term by
term, the Di inputs can be determined in terms of the remaining variable.

Demultiplexers
 The demultiplexer shown there is a single-input, multiple-output circuit. However, in
addition to the data input, there must be other inputs to control the transmission of the data to
the appropriate data output line at any given time. Such a demultiplexer circuit having eight
output lines is shown in Figure 16a. It is instructive to compare this demultiplexer circuit with
the multiplexer circuit in Figure 13. For the same number of control (select) inputs, there are
the same number of AND gates. But now each AND gate output is a circuit output. Rather
than each gate having its own separate data input, the single data line now forms one of the
inputs to each AND gate, the other AND inputs being control inputs.
When the word formed by the control inputs C2C1C0 is the binary equivalent of
decimal k, then the data input x is routed to output Dk. Viewed in another way, for a
demultiplexer with n control inputs, each AND gate output corresponds to a minterm of n
variables. For a given combination of control inputs, only one minterm can take on the value
1; the data input is routed to the AND gate corresponding to this minterm. For example, the
logical expression for the output D3 is xC2'C1C0. Hence, when C2C1C0 = 011, then D3 = x
and all other Di are 0. The complete truth table for the eight-output demultiplexer.
 PART -A
1) Define binary logic?
Binary logic consists of binary variables and logical operations. The variables are
designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having
only two distinct values: 1 and 0. There are three basic logic operations: AND, OR,
and NOT.

2) Convert (634) 8 to binary

6 3 4
110 011 100
Ans = 110011100

3) Convert (9B2 - 1A) H to its decimal equivalent.

N = 9 x 16 2 + B x 16 1 + 2 x 16 0 + 1 x 16 -1 + A (10) x 16 -2
= 2304 + 176 + 2 + 0.0625 + 0.039
= 2482.1 10

4) State the different classification of binary codes?

1. Weighted codes
2. Non - weighted codes
3. Reflective codes
4. Sequential codes
5. Alphanumeric codes
6. Error Detecting and correcting codes.

5) Convert 0.640625 decimal number to its octal equivalent.

0.640625 x 8 = 5.125
0.125 x 8 = 1.0
= 0.640 625 10 = (0.51) 8

6) Convert 0.1289062 decimal number to its hex equivalent

0.1289062 x 16 = 2.0625
 0.0625 x 16 = 1.0
= 0.21 16

7) Convert 22.64 to hexadecimal number.

16 22 -6
16 1 -1
0
0.64 x 16 = 10.24
0.24 x 16 = 3.84
0.84 x 16 = 13.44
.44 x 16 = 7.04
Ans = (16. A 3 D 7) 16

8) State the steps involved in Gray to binary conversion?

The MSB of the binary number is the same as the MSB of the gray code number. So
write it down. To obtain the next binary digit, perform an exclusive OR operation
between the bit just written down and the next gray code bit. Write down the result.

9) Convert gray code 101011 into its binary equivalent.

Gray Code: 1 0 1 0 1 1
Binary Code: 1 1 0 0 1 0

10) Substract (0 1 0 1) 2 from (1 0 1 1) 2

1010
0101
Answer = 0 1 1 0
11) Add (1 0 1 0) 2 and (0 0 1 1) 2
1010
0011
Answer = (1 1 0 1) 2
12) Using 10‘s complement subtract 72532 - 3250
M = 72532
10‘s complement of N = + 96750
-----------
Sum = 169282
Discard end carry
Answer = 69282
13) Find 2‘S complement of (1 0 1 0 0 0 1 1) 2
0 1 0 1 1 1 0 0 1 - 1‘s Complement
+00000001
0 1 0 1 1 1 0 1 0 - 2‘s complement.
14) Substract 1 1 1 0 0 1 2 from 1 0 1 0 1 1 2 using 2‘s complement method
101011
+ 0 0 0 1 1 1 - 2‘s comp. of 1 1 1 0 0 1
1 1 0 0 1 0 in 2‘s complement form
Answer (0 0 1 1 1 0 )2

15) Find the excess -3 code and 9‘s complement of the number 403 10
403
010000000011
001100110011+
0 1 1 1 0 0 1 1 0 1 1 0 ----- excess 3 code
9‘s complement 1 0 0 0 1 1 0 0 1 0 0 1

16) What is meant by bit?

A binary digit is called bit
17) Define byte?
 Group of 8 bits.
18) List the different number systems?
i) Decimal Number system
ii) Binary Number system
iii) Octal Number system
iv) Hexadecimal Number system
19) State the abbreviations of ASCII and EBCDIC code?
ASCII-American Standard Code for Information Interchange.
EBCDIC-Extended Binary Coded Decimal Information Code.
20) What are the different types of number complements?
i) r‘s Complement
ii) (r-1)‘s Complement.
21) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X -Y and (b) Y - X using 2's complements.
a) X = 1010100
2's complement of Y = 0111101
--------------
Sum = 10010001
Discard end carry
Answer: X - Y = 0010001
b) Y = 1000011
2's complement of X = + 0101100
---------------
Sum = 1101111
There is no end carry, The MSB BIT IS 1.
Answer is Y-X = -(2's complement of 1101111) = - 0010001

22) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction
(a) X -Y and (b) Y - X using 1's complements.
a) X - Y = 1010100 - 1000011
X = 1010100
 1's complement of Y = + 0111100
--------------
Sum = 10010000
End -around carry = + 1
--------------
Answer: X - Y = 0010001
b) Y - X = 1000011 - 1010100
Y = 1000011
1's complement of X = + 0101011
-----------
Sum = + 1101110
There is no end carry.
Therefore the answer is Y - X = -(1's complement of 1101110) = -0010001
23) Write the names of basic logical operators.
1. NOT / INVERT
2. AND
3. OR
24) What are basic properties of Boolean algebra?
The basic properties of Boolean algebra are commutative property, associative
property and distributive property.

25) State the associative property of boolean algebra.

The associative property of Boolean algebra states that the OR ing of several variables
results in the same regardless of the grouping of the variables. The associative
property is stated as follows:
A+ (B+C) = (A+B) +C
26) State the commutative property of Boolean algebra.
The commutative property states that the order in which the variables are OR ed
makes no difference. The commutative property is:
A+B=B+A
27) State the distributive property of Boolean algebra.
 The distributive property states that AND ing several variables and OR ing the result
with a single variable is equivalent to OR ing the single variable with each of the the
several variables and then AND ing the sums. The distributive property is:
A+BC= (A+B) (A+C)
28) State the absorption law of Boolean algebra.
The absorption law of Boolean algebra is given by X+XY=X, X(X+Y) =X.
29) Simplify the following using De Morgan's theorem [((AB)'C)'' D]'
[((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B']
= (AB)' C + D'
= (A' + B' )C + D'
30) State De Morgan's theorem.
De Morgan suggested two theorems that form important part of Boolean algebra. They
are,
1) The complement of a product is equal to the sum of the complements.
(AB)' = A' + B'
2) The complement of a sum term is equal to the product of the complements.
(A + B)' = A'B'
31) Reduce A.A'C
A.A'C = 0.C [A.A' = 1]
=0
31) Reduce A(A + B)
A(A + B) = AA + AB
= A(1 + B) [1 + B = 1]
= A.

32) Reduce A'B'C' + A'BC' + A'BC

A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1]
= A'(C' + BC)
= A'(C' + B) [A + A'B = A + B]
33) Reduce AB + (AC)' + AB'C(AB + C)
 AB + (AC)' + AB'C(AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + AB'CC [A.A' = 0]
= AB + (AC)' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' = A + B]
= A' + B'C + B + C' [A + A'B = A + B]
= A' + B + C' + B'C
=A' + B + C' + B'
=A' + C' + 1
= 1 [A + 1 =1]
34) Simplify the following expression Y = (A + B)(A + C' )(B' + C' )
Y = (A + B)(A + C' )(B' + C' )
= (AA' + AC +A'B +BC )(B' + C') [A.A' = 0]
= (AC + A'B + BC)(B' + C' )
= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC'
= AB'C + A'BC'
35) Show that (X + Y' + XY)( X + Y')(X'Y) = 0
(X + Y' + XY)( X + Y')(X'Y) = (X + Y' + X)(X + Y' )(X' + Y) [A + A'B = A + B]
= (X + Y' )(X + Y' )(X'Y) [A + A = 1]
= (X + Y' )(X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
= 0 [A.A' = 0]

36) Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC

ABC + ABC' + AB'C + A'BC=AB(C + C') + AB'C + A'BC
=AB + AB'C + A'BC
=A(B + B'C) + A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
 =AB + BC + AC
=AB + AC +BC ...Proved
37) Convert the given expression in canonical SOP form Y = AC + AB + BC
Y = AC + AB + BC
=AC(B + B' ) + AB(C + C' ) + (A + A')BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
38) Define duality property.
Duality property states that every algebraic expression deducible from the postulates
of Boolean algebra remains valid if the operators and identity elements are
interchanged. If the dual of an algebraic expression is desired, we simply interchange
OR and AND operators and replace 1's by 0's and 0's by 1's.
39) Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x(y'z' + yz). By
applying De-Morgan's theorem.
F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z')
F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)'
= x' + (y'z')'(yz)'
= x' + (y + z)(y' + z')
40) Simplify the following expression
Y = (A + B) (A = C) (B + C)
= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
=ABC+ACC+ABB+ABC+BBC+BCC
=ABC

41) What are the methods adopted to reduce Boolean function?

i) Karnaug map
ii) Tabular method or Quine Mc-Cluskey method
iii) Variable entered map technique.
42) State the limitations of karnaugh map.
i) Generally it is limited to six variable map (i.e) more then six variable
involving expression are not reduced.
 ii) The map method is restricted in its capability since they are useful for
simplifying only Boolean expression represented in standard form.
43) What is a karnaugh map?
A karnaugh map or k map is a pictorial form of truth table, in which the map diagram
is made up of squares, with each squares representing one minterm of the function.
44) Find the minterms of the logical expression Y = A'B'C' + A'B'C + A'BC + ABC'
Y = A'B'C' + A'B'C + A'BC + ABC'
=m0 + m1 +m3 +m6
=_m(0, 1, 3, 6)
45) Write the maxterms corresponding to the logical expression
Y = (A + B + C' )(A + B' + C')(A' + B' + C)
= (A + B + C' )(A + B' + C')(A' + B' + C)
=M1.M3.M6
=_ M(1,3,6)
46) What are called don‘t care conditions?
In some logic circuits certain input conditions never occur, therefore the
corresponding output never appears. In such cases the output level is not defined, it
can be either high or low. These output levels are indicated by ‗X‘ or‗d‘ in the truth
tables and are called don‘t care conditions or incompletely specified functions.
47) What is a prime implicant?
A prime implicant is a product term obtained by combining the maximum possible
number of adjacent squares in the map.
48) What is an essential implicant?
If a min term is covered by only one prime implicant, the prime implicant is
said to be essential
 Part – B
1) Simplify the boolean function using tabulation method.
F = _ (0,1,2,8,10,11,14,15)
List all the min terms
Arrange them as per the number of ones based on binary equivalent
Compare one group with another for difference in one and replace the bit with
dash.Continue this until no further grouping possible.
The unchecked terms represent the prime implicants.
F = W'X'Y' + X'Z' + WY
2) Determine the prime implicants of the function
F (W,X,Y,Z) = _ (1,4,6,7,8,9,10,11,15)
List all the min terms
Arrange them as per the number of ones based on binary equivalent
Compare one group with another for difference in one and replace the bit with dash.
Continue this until no further grouping possible.
The unchecked terms represent the prime implicants.
F = X'Y'Z + W'XZ' + W'XY + XYZ + WYZ + WX'
Minimum Set of prime implicants F = X'Y'Z + W'XZ' + XYZ + WX'
3) Simplify the Boolean function using K-map.
F(A,B,C,D,E) = (0,2,4,6,9,13,21,23,25,29,31)
Five variables hence two variable k maps one for A = 0 and the other for A=1.
F = A'B'E' + BD'E + ACE

4) Obtain the canonical sum of products of the function Y = AB + ACD

Y = AB (C + C')(D + D') + ACD (B + B')
Y = ABCD + ABCD' + ABC'D + ABC'D' + AB'CD
5) State the postulates and theorems of Boolean algebra.
 UNIT IV : 8085 MICROPROCESSOR

Block diagram of microcomputer – Architecture of 8085 – Pin configuration – Instruction set

–Addressing modes – Simple programs using arithmetic and logical operations.

Internal Architecture of 8085 Microprocessor

Control Unit
Generates signals within uP to carry out the instruction, which has been
decoded. In
reality causes certain connections between blocks of the uP to be opened or
closed, so
that data goes where it is required, and so that ALU operations occur.
Arithmetic Logic Unit
The ALU performs the actual numerical and logic operation such as ‗add‘,
‗subtract‘,
‗AND‘, ‗OR‘, etc. Uses data from memory and from Accumulator to perform
arithmetic. Always stores result of operation in Accumulator.
Registers
The 8085/8080A-programming model includes six registers, one accumulator,
and
one flag register, as shown in Figure. In addition, it has two 16-bit registers: the
stack
pointer and the program counter. They are described briefly as follows.
 The 8085/8080A has six general-purpose registers to store 8-bit data; these are
identified as B,C,D,E,H, and L as shown in the figure. They can be combined as
register pairs - BC, DE, and HL - to perform some 16-bit operations. The
programmer can use these registers to store or copy data into the registers by
using
data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU).
This
register is used to store 8-bit data and to perform arithmetic and logical
operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
Flags
The ALU includes five flip-flops, which are set or reset after an operation
according
to data conditions of the result in the accumulator and other registers. They are
called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they
are
listed in the Table and their bit positions in the flag register are shown in the
Figure
below. The most commonly used flags are Zero, Carry, and Sign. The
microprocessor
uses these flags to test data conditions.
For example, after an addition of two numbers, if the sum in the accumulator id
larger than eight bits,
the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one.
When an arithmetic
operation results in zero, the flip-flop called the
Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag
register, adjacent to the accumulator. However, it is not used as a register; five
bit
positions out of eight are used to store the outputs of the five flip-flops. The
flags are
stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the
microprocessor.
The conditions (set or reset) of the flags are tested through the software
instructions. For example, the instruction JC (Jump on Carry) is implemented to
change the sequence of a program when CY flag is set. The thorough
understanding
of flag is essential in writing assembly language programs.
Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This
register
is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a
16-bit register.
The microprocessor uses this register to sequence the execution of the
instructions.
 The function of the program counter is to point to the memory address from
which the
next byte is to be fetched. When a byte (machine code) is being fetched, the
program
counter is incremented by one to point to the next memory location
Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer. The stack concept is
explained
in the chapter "Stack and Subroutines."
Instruction Register/Decoder
Temporary store for the current instruction of a program. Latest instruction sent
here
from memory prior to execution. Decoder then takes instruction and ‗decodes‘
or
interprets the instruction. Decoded instruction then passed to next stage.
Memory Address Register
Holds address, received from PC, of next program instruction. Feeds the address
bus
with addresses of location of the program under execution.
Control Generator
Generates signals within uP to carry out the instruction which has been decoded.
In
reality causes certain connections between blocks of the uP to be opened or
closed, so
that data goes where it is required, and so that ALU operations occur.
Register Selector
This block controls the use of the register stack in the example. Just a logic
circuit
which switches between different registers in the set will receive instructions
from
Control Unit.
General Purpose Registers
uP requires extra registers for versatility. Can be used to store additional data
during a
program. More complex processors may have a variety of differently named
registers.
Microprogramming
How does the μP knows what an instruction means, especially when it is only a
binary number? The microprogram in a uP/uC is written by the chip designer
and tells
the uP/uC the meaning of each instruction uP/uC can then carry out operation.

2. 8085 System Bus:

Typical system uses a number of busses, collection of wires, which transmit
binary
numbers, one bit per wire. A typical microprocessor communicates with
memory and
other devices (input and output) using three busses: Address Bus, Data Bus and
Control Bus.
Address Bus
One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts
 memory to ‗open‘ the designated box. Data (binary) can then be put in or taken
out.The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16
bits. A
16 bit binary number allows 216 different numbers, or 32000 different numbers,
ie
0000000000000000 up to 1111111111111111. Because memory consists of
boxes,
each with a unique address, the size of the address bus determines the size of
memory,
which can be used. To communicate with memory the microprocessor sends an
address on the address bus, eg 0000000000000011 (3 in decimal), to the
memory. The
memory the selects box number 3 for reading or writing data. Address bus is
unidirectional, ie numbers only sent from microprocessor to memory, not other
way.
Question?: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits),
how many wires does the address bus need, in order to be able to specify an
address in
this memory? Note: the memory is organized in groups of 8 bits per location,
therefore, how many locations must you be able to specify?
Data Bus
Data Bus: carries ‗data‘, in binary form, between μP and other external units, such as
memory. Typical size is 8 or 16 bits. Size determined by size of boxes in
memory and
μP size helps determine performance of μP. The Data Bus typically consists of 8
wires. Therefore, 28 combinations of binary digits. Data bus used to transmit
"data",
ie information, results of arithmetic, etc, between memory and the
microprocessor.
Bus is bi-directional. Size of the data bus determines what arithmetic can be
done. If
only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore,
larger
number have to be broken down into chunks of 255. This slows microprocessor.
Data
Bus also carries instructions from memory to the microprocessor. Size of the bus
therefore limits the number of possible instructions to 256, each specified by a
separate number.
Control Bus
Control Bus are various lines which have specific functions for coordinating and
controlling uP operations. Eg: Read/NotWrite line, single binary digit. Control
whether memory is being ‗written to‘ (data stored in mem) or ‗read from‘ (data
taken
out of mem) 1 = Read, 0 = Write. May also include clock line(s) for
timing/synchronising, ‗interrupts‘, ‗reset‘ etc. Typically μP has 10 control lines.
Cannot function correctly without these vital control signals.
The Control Bus carries control signals partly unidirectional, partly bi-
directional.
Control signals are things like "read or write". This tells memory that we are
either
reading from a location, specified on the address bus, or writing to a location
specified. Various other signals to control and coordinate the operation of the
system.
 Modern day microprocessors, like 80386, 80486 have much larger busses.
Typically
16 or 32 bit busses, which allow larger number of instructions, more memory
location, and faster arithmetic. Microcontrollers organized along same lines,
except:
because microcontrollers have memory etc inside the chip, the busses may all be
internal. In the microprocessor the three busses are external to the chip (except
for the
internal data bus). In case of external busses, the chip connects to the busses via
buffers, which are simply an electronic connection between external bus and the
internal data bus.
3. 8085 Pin description.
Properties
Single + 5V Supply
4 Vectored Interrupts (One is Non Maskable)
Serial In/Serial Out Port
Decimal, Binary, and Double Precision Arithmetic
Direct Addressing Capability to 64K bytes of memory
The Intel 8085A is a new generation, complete 8 bit parallel central processing
unit
(CPU). The 8085A uses a multiplexed data bus. The address is split between the
8bit
address bus and the 8bit data bus. Figures are at the end of the document.
Pin Description

The following describes the function of each pin:

A6 - A1s (Output 3 State)
Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0
address,3 stated during Hold and Halt modes.
AD0 - 7 (Input/Output 3state)
Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address)
appear on the bus during the first clock cycle of a machine state. It then becomes the
data bus during the second and third clock cycles. 3 stated during Hold and Halt modes.
ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of a machine state
and
 enables the address to get latched into the on chip latch of peripherals. The
falling
edge of ALE is set to guarantee setup and hold times for the address information.
ALE can also be used to strobe the status information. ALE is never 3stated.
SO, S1 (Output) Data Bus Status. Encoded status of the bus cycle:
S1 S0
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.
RD (Output 3state)
READ; indicates the selected memory or 1/0 device is to be read and that the
Data
Bus is available for the data transfer.
WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written into the selected
memory
. Data is set up at the trailing edge of WR. 3stated during Hold and Halt
modes.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait for
Ready to go high before completing the read or write cycle.
HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and
Data
Buses. The CPU, upon receiving the Hold request. will relinquish the use of
buses as
soon as the completion of the current machine cycle. Internal processing can
continue.
The processor can regain the buses only after the Hold is removed. When the
Hold is
Acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request
and

that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold
request is removed. The CPU takes the buses one half clock cycle after HLDA
goes
low.
INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled
only
during the next to the last clock cycle of the instruction. If it is active, the
Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued.
During
this cycle a RESTART or CALL instruction can be inserted to jump to the
interrupt
service routine. The INTR is enabled and disabled by software. It is disabled by
Reset
 and immediately after an interrupt is accepted.
INTA (Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing
as) RD
during the Instruction cycle after an INTR is accepted. It can be used to activate
the
8259 Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS;
These three inputs have the same timing as I NTR except
they cause an internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have
a
higher priority than the INTR.
TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same
time as
INTR. It is unaffected by any mask or Interrupt Enable. It has the highest
priority of
any interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and
HLDA
flipflops. None of the other flags or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output)
Indicates CPlJ is being reset. Can be used as a system RESET. The signal is
synchronized to the processor clock.
X1, X2 (Input)
Crystal or R/C network connections to set the internal clock generator X1 can
also be
an external clock input instead of a crystal. The input frequency is divided by 2
to
give the internal operating frequency.
CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as
an
input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during
Hold and
Halt modes.
SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7
whenever a
RIM instruction is executed.
SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM
 instruction.
Vcc
+5 volt supply.
Vss
Ground Reference.

4. 8085 Functional Description

The 8085A is a complete 8 bit parallel central processor. It requires a single +5
volt
supply. Its basic clock speed is 3 MHz thus improving on the present 8080's
performance with higher system speed. Also it is designed to fit into a minimum
system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.
The 8085A uses a multiplexed Data Bus. The address is split between the higher
8bit
Address Bus and the lower 8bit Address/Data Bus. During the first cycle the
address
is sent out. The lower 8bits are latched into the peripherals by the Address Latch
Enable (ALE). During the rest of the machine cycle the Data Bus is used for
memory
or l/O data.
The 8085A provides RD, WR, and lO/Memory signals for bus control. An
Interrupt
Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are
synchronized. The 8085A also provides serial input data (SID) and serial output
data
(SOD) lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts and
one
non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for
Bus
control.
Status Information
Status information is directly available from the 8085A. ALE serves as a status
strobe.
The status is partially encoded, and provides the user with advanced timing of
the
type of bus transfer being done. IO/M cycle status signal is provided directly
also.
Decoded So, S1 Carries the following status information:
HALT, WRITE, READ, FETCH
S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of
address
are multiplexed with the data instead of status. The ALE line is used as a strobe
to
enter the lower half of the address into the memory or peripheral address latch.
This
also frees extra pins for expanded interrupt capability.
Interrupt and Serial l/O:
The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP.
INTR
is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5,
6.5.
7.5, has a programmable mask. TRAP is also a RESTART interrupt except it is
nonmaskable. The three RESTART interrupts cause the internal execution of RST
(saving the program counter in the stack and branching to the RESTART address) if the
interrupts are enabled and if the interrupt mask is not set. The non-maskable TRAP
causes the internal execution of a RST independent of the state of the interrupt enable
or masks. The interrupts are arranged in a fixed priority that determines which interrupt
is to be recognized if more than one is pending as follows: TRAP highest priority, RST
7.5,
RST 6.5, RST 5.5, INTR lowest priority This priority scheme does not take into
account the priority of a routine that was started by a higher priority interrupt.
RST
5.5 can interrupt a RST 7.5 routine if the interrupts were re-enabled before the
end of
the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as
power failure or bus error. The TRAP input is recognized just as any other
interrupt
but has the highest priority. It is not affected by any flag or mask. The TRAP
input is
both edge and level sensitive.

Basic System Timing

The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the
lower
8bits of address on the Data Bus. Figure 2 shows an instruction fetch, memory read
and l/ O write cycle (OUT). Note that during the l/O write and read cycle that the l/O
port address is copied on both the upper and lower half of the address. As in the 8080,
the READY line is used to extend the read and write pulse lengths so that the 8085A
can be used with slow memory. Hold causes the CPU to relingkuish the bus when it is
through with it by floating the Address and Data Buses.
System Interface
8085A family includes memory components, which are directly compatible to
the
8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and
8355 will have the following features:
· 2K Bytes ROM
· 256 Bytes RAM
· 1 Timer/Counter
· 4 8bit l/O Ports
· 1 6bit l/O Port
· 4 Interrupt Levels
· Serial In/Serial Out Ports
In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing
technique. With this technique, an area of memory address space is assigned for l/O
address, thereby, using the memory address for I/O manipulation. The 8085A CPU
can also interface with the standard memory that does not have the multiplexed
address/data bus.

5. The 8085 Programming Model

In the previous tutorial we described the 8085 microprocessor registers in
reference to
the internal data operations. The same information is repeated here briefly to provide
the continuity and the context to the instruction set and to enable the readers who
prefer to focus initially on the programming aspect of the microprocessor.
The 8085 programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer
and the program counter. They are described briefly as follows.
Registers
The 8085 has six general-purpose registers to store 8-bit data; these are
identified as
B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs
-
BC, DE, and HL - to perform some 16-bit operations. The programmer can use
these
registers to store or copy data into the registers by using data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU).
This
register is used to store 8-bit data and to perform arithmetic and logical
operations.
The result of an operation is stored in the accumulator. The accumulator is also
identified as register A.
ACCUMULATOR A (8) FLAG REGISTER
B (8)
D (8)
H (8)
Stack Pointer (SP) (16)
Program Counter (PC) (16)
C (8)
E (8)
L (8)
Data Bus Address Bus
8 Lines Bidirectional 16 Lines unidirectional
Flags
The ALU includes five flip-flops, which are set or reset after an operation
according
to data conditions of the result in the accumulator and other registers. They are
called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their
bit
positions in the flag register are shown in the Figure below. The most commonly
used
flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data
conditions.
For example, after an addition of two numbers, if the sum in the accumulator id
larger than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) –
is set to one. When an arithmetic operation results in zero, the flip-flop called the
Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag
register, adjacent to the accumulator. However, it is not used as a register; five
bit
positions out of eight are used to store the outputs of the five flip-flops. The
flags are
stored in the 8-bit register so that the programmer can examine these flags (data
conditions) by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the
microprocessor. The conditions (set or reset) of the flags are tested through the software
instructions. For example, the instruction JC (Jump on Carry) is implemented to
 change the sequence of a program when CY flag is set. The thorough
understanding
of flag is essential in writing assembly language programs.
Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This
register
is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a
16-bit register.
The microprocessor uses this register to sequence the execution of the
instructions.
The function of the program counter is to point to the memory address from
which the
next byte is to be fetched. When a byte (machine code) is being fetched, the
program
counter is incremented by one to point to the next memory location
Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a
memory location in R/W memory, called the stack. The beginning of the stack is
defined by loading 16-bit address in the stack pointer.
This programming model will be used in subsequent tutorials to examine how
these
registers are affected after the execution of an instruction.
D7 D6 D5 D4 D3 D2 D1 D0
6. The 8085 Addressing Modes
Addressing Modes of 8085
To perform any operation, we have to give the corresponding instructions to the
microprocessor.
In each instruction, programmer has to specify 3 things:
◦ Operation to be performed.
◦ Address of source of data.
◦ Address of destination of result.
The method by which the address of source of data or the address of destination of
result is given in the instruction is called Addressing Modes. The term addressing mode
refers to the way in which the operand of the instruction is specified.
Types of Addressing Modes
Intel 8085 uses the following addressing modes:
1. Direct Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implicit Addressing Mode
Direct Addressing Mode
In this mode, the address of the operand is given in the instruction itself.
LDA 4500H- Load the contents of memory location 4500H in
accumulatorDA2500
tor.

LDA is the operation.

4500 H is the address of source.
Accumulator is the destination.
Register Addressing Mode

In this mode, the operand is in general purpose register.

MOV A,B – Move the contents of register B to A
MOV is the operation.
B is the source of data.
A is the destination.
Register Indirect Addressing Mode
In this mode, the address of operand is specified by a register pair.

MOVA,M- Move data from memory location specified by HL pair to

accumulator
MOV is the operation.
M is the memory location specified by H-L register pair.
A is the destination
Immediate Addressing Mode
In this mode, the operand is specified within the instruction itself.
MVI A,05 H- Move 05 H in accumulator
MVI is the operation.
05 H is the immediate data (source).
A is the destination
Implicit Addressing Mode
If address of source of data as well as address of destination of result is fixed,
then there is no need to give any operand along with the instruction.
CMA- Complement Accumulator
CMA is the operation.
A is the source.
A is the destination.

{The instructions MOV B, A or MVI A, 82H are to copy data from a source into a
destination. In these instructions the source can be a register, an input port, or an 8-bit
number (00H to FFH). Similarly, a destination can be a register or an output port. The
sources and destination are operands. The various formats for specifying operands are
called the ADDRESSING MODES. For 8085, they are:
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
Immediate addressing
 Data is present in the instruction. Load the immediate data to the destination
provided.
Example: MVI R,data
Register addressing
Data is provided through the registers.
Example: MOV Rd, Rs
Direct addressing
Used to accept data from outside devices to store in the accumulator or send the
data
stored in the accumulator to the outside device. Accept the data from the port
00H and
store them into the accumulator or Send the data from the accumulator to the
port 01H.
Example: IN 00H or OUT 01H
Indirect Addressing
This means that the Effective Address is calculated by the processor. And the
contents of the address (and the one following) is used to form a second address.
The
second address is where the data is stored. Note that this requires several
memory
accesses; two accesses to retrieve the 16-bit address and a further access (or
accesses)
to retrieve the data which is to be loaded into the register.}
7. Instruction Set Classification
An instruction is a binary pattern designed inside a microprocessor to perform a
specific function. The entire group of instructions, called the instruction set,
determines what functions the microprocessor can perform. These instructions can be
classified into the following five functional categories: data transfer (copy)
operations, arithmetic operations, logical operations, branching operations, and
machine-control operations.
Data Transfer (Copy) Operations
This group of instructions copy data from a location called a source to another
location called a destination, without modifying the contents of the source. In
technical manuals, the term data transfer is used for this copying function. However,
the term transfer is misleading; it creates the impression that the contents of the
source are destroyed when, in fact, the contents are retained without any modification.
The various types of data transfer (copy) are listed below together with examples of
each type:
Types
Examples
1. Between Registers.
Copy the contents of the register B into register D.
2. Specific data byte to a register or a memory location.
Load register B with the data byte 32H.
3. Between a memory location and a register.
From a memory location 2000H to register B.
4. Between an I/O device and the accumulator.
From an input keyboard to the accumulator.
Arithmetic Operations
These instructions perform arithmetic operations such as addition, subtraction,
increment, and decrement.

Addition - Any 8-bit number, or the contents of a register or the contents of a

memory location can be added to the contents of the accumulator and the sum is
stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the
contents of register B cannot be added directly to the contents of the register C). The
instruction DAD is an exception; it adds 16-bit data directly in register pairs.

Subtraction - Any 8-bit number, or the contents of a register, or the contents of a

memory location can be subtracted from the contents of the accumulator and the
results stored in the accumulator. The subtraction is performed in 2's compliment, and
the results if negative, are expressed in 2's complement. No two other registers can be
subtracted directly.

Increment/Decrement - The 8-bit contents of a register or a memory location can be

incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such
as BC) can be incremented or decrement by 1. These increment and decrement
operations differ from addition and subtraction in an important way; i.e., they can be
performed in any one of the registers or in a memory location.

Logical Operations
These instructions perform various logical operations with the contents of the
accumulator.
AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of
a memory location can be logically ANDed, Ored, or Exclusive-ORed with the
contents of the accumulator. The results are stored in the accumulator.

Rotate- Each bit in the accumulator can be shifted either left or right to the next
position.

Compare- Any 8-bit number, or the contents of a register, or a memory location can
be compared for equality, greater than, or less than, with the contents of the
accumulator.
Complement - The contents of the accumulator can be complemented. All 0s are
replaced by 1s and all 1s are replaced by 0s.

Branching Operations
This group of instructions alters the sequence of program execution either
conditionally or unconditionally.

Jump - Conditional jumps are an important aspect of the decision-making process in

the programming. These instructions test for a certain conditions (e.g., Zero or Carry
flag) and alter the program sequence when the condition is met. In addition, the
instruction set includes an instruction called unconditional jump.

Call, Return, and Restart - These instructions change the sequence of a program
either by calling a subroutine or returning from a subroutine. The conditional Call and
Return instructions also can test condition flags.

Machine Control Operations

These instructions control machine functions such as Halt, Interrupt, or do nothing.
The microprocessor operations related to data manipulation can be summarized in
four functions:
1. copying data
2. performing arithmetic operations
3. performing logical operations
 4. testing for a given condition and alerting the program sequence
Some important aspects of the instruction set are noted below:
1. In data transfer, the contents of the source are not destroyed; only the contents
of
the destination are changed. The data copy instructions do not affect the flags.
2. Arithmetic and Logical operations are performed with the contents of the
accumulator, and the results are stored in the accumulator (with some
expectations). The flags are affected according to the results.
3. Any register including the memory can be used for increment and decrement.
4. A program sequence can be changed either conditionally or by testing for a
given
data condition.
8. Instruction Format
An instruction is a command to the microprocessor to perform a given task on a
specified data. Each instruction has two parts: one is task to be performed, called the
operation code (opcode), and the second is the data to be operated on, called the
operand. The operand (or data) can be specified in various ways. It may include 8-bit
(or 16-bit ) data, an internal register, a memory location, or 8-bit (or 16-bit) address.
In some instructions, the operand is implicit.
Instruction word size
The 8085 instruction set is classified into the following three groups according
to
word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor.
However, instructions are commonly referred to in terms of bytes rather than words.
One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte.
Operand(s)
are internal register and are coded into the instruction.
For example:
Task Opcode Operand Binary Code Hex Code
Copy the contents of the accumulator in the register C.
MOV C,A 0100 1111 4FH

Add the contents of register B to the contents of the accumulator.

ADD B 1000 0000 80H
Invert (compliment) each bit in the accumulator.
CMA 0010 1111 2FH
These instructions are 1-byte instructions performing three different tasks. In the
first
instruction, both operand registers are specified. In the second instruction, the operand
B is specified and the accumulator is assumed. Similarly, in the third instruction, the
accumulator is assumed to be the implicit operand. These instructions are stored in 8-
bit binary format in memory; each requires one memory location.
MOV rd, rs
rd <-- rs copies contents of rs into rd.
Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is
the destination of the data, sss is the code of the source register.
Example: MOV A,B
Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction
design of such processors).
ADD r
A <-- A + r
Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the
second
byte specifies the operand. Source operand is a data byte immediately following the
opcode. For example:
Task Opcode Operand Binary Code Hex Code
Load an 8-bit data byte in the accumulator.
MVI A, Data 3E
Data
First Byte
Second Byte
Assume that the data byte is 32H. The assembly language instruction is written as
Mnemonics Hex code
MVI A, 32H 3E 32H
The instruction would require two memory locations to store in memory.
MVI r,data
r <-- data
Example: MVI A,30H coded as 3EH 30H as two contiguous bytes. This is an
example of immediate addressing.
ADI data
A <-- A + data
OUT port
0011 1110
DATA
where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but
points directly to where it is located this is called direct addressing.
Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two
bytes specify the 16-bit address. Note that the second byte is the low-order address
and the third byte is the high-order address.
opcode + data byte + data byte
For example:
Task Opcode Operand Binary code Hex Code
Transfer the program sequence to the memory location 2085H.
JMP 2085H C3
85
20
First byte
Second Byte
Third Byte
This instruction would require three memory locations to store in memory.
Three byte instructions - opcode + data byte + data byte
LXI rp, data16
rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data
bytes are 16-bit data in L H order of significance.
rp <-- data16
Example:
LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate
addressing.
LDA addr
 A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as
3AH 34H 21H. This is also an example of direct addressing.
9. Sample Programs
Write an assembly program to add two numbers
Program
MVI D, 8BH
MVI C, 6FH
MOV A, C
1100 0011
1000 0101
0010 0000
ADD D
OUT PORT1
HLT
Write an assembly program to multiply a number by 8
Program
MVI A, 30H
RRC
RRC
RRC
OUT PORT1
HLT
Write an assembly program to find greatest between two numbers
Program
MVI B, 30H
MVI C, 40H
MOV A, B
CMP C
JZ EQU
JC GRT
OUT PORT1
HLT
EQU: MVI A, 01H
OUT PORT1
HLT
GRT: MOV A, C
OUT PORT1
HLT
Differences between Intel 8080 and 8085 processors

Features 8085
8080

1. Processorspeed (MHz) 3-6

2 - 3.1

2. Power supply +5V,-

+5V
5Vand +12V

Clock oscillator (similar to

3. On-chip peripherals
8224) system controller
 (similar to 8228)
Serial I/O lines

Separate
Multiplexed address
4. Address/Data bus address and
and data
data busses

Reset Out pin

RD bus signal
WR bus signal
IO/MM bus signal
5. Pins/signals ALE pin provides
encoded bus
status information

Three maskable interrupts and

6. Interrupts one non- maskable

RIM - read interrupt mask

7. Instruction set SIM - Set interrupt mask

8085 microprocessor questions

1. What are the various registers in 8085? - Accumulator register, Temporary register,
Instruction register, Stack Pointer, Program Counter are the various registers in 8085 .
2. In 8085 name the 16 bit registers? - Stack pointer and Program counter all have 16
bits.
3. What are the various flags used in 8085? - Sign flag, Zero flag, Auxillary flag, Parity
flag, Carry flag.
4. What is Stack Pointer? - Stack pointer is a special purpose 16-bit register in the
Microprocessor, which holds the address of the top of the stack.
5. What is Program counter? - Program counter holds the address of either the first byte
of the next instruction to be fetched for execution or the address of the next byte of a
multi byte instruction, which has not been completely fetched. In both the cases it gets
incremented automatically one by one as the instruction bytes get fetched. Also Program
register keeps the address of the next instruction.
6. Which Stack is used in 8085? - LIFO (Last In First Out) stack is used in 8085.In this
type of Stack the last stored information can be retrieved first.
7. What happens when HLT instruction is executed in processor? - The Micro Processor
enters into Halt-State and the buses are tri-stated.
8. What is meant by a bus? - A bus is a group of conducting lines that carriers data,
address, & control signals.
9. What is Tri-state logic? - Three Logic Levels are used and they are High, Low, High
impedance state. The high and low are normal logic levels & high impedance state is
electrical open circuit conditions. Tri-state logic has a third line called enable line.
10. Give an example of one address microprocessor? - 8085 is a one address
microprocessor.
11. In what way interrupts are classified in 8085? - In 8085 the interrupts are classified as
Hardware and Software interrupts.
12. What are Hardware interrupts? - TRAP, RST7.5, RST6.5, RST5.5, INTR.
13. What are Software interrupts? - RST0, RST1, RST2, RST3, RST4, RST5, RST6,
RST7.
14. Which interrupt has the highest priority? - TRAP has the highest priority.
15. Name 5 different addressing modes? - Immediate, Direct, Register, Register indirect,
Implied addressing modes.
16. How many interrupts are there in 8085? - There are 12 interrupts in 8085.
17. What is clock frequency for 8085? - 3 MHz is the maximum clock frequency for 8085.
18. What is the RST for the TRAP? - RST 4.5 is called as TRAP.
19. In 8085 which is called as High order / Low order Register? - Flag is called as Low
order register & Accumulator is called as High order Register.
20. What are input & output devices? - Keyboards, Floppy disk are the examples of input
devices. Printer, LED / LCD display, CRT Monitor are the examples of output devices.
21. Can an RC circuit be used as clock source for 8085? - Yes, it can be used, if an
accurate clock frequency is not required. Also, the component cost is low compared to
LC or Crystal.
22. Why crystal is a preferred clock source? - Because of high stability, large Q (Quality
Factor) & the frequency that doesn‘t drift with aging. Crystal is used as a clock source
most of the times.
23. Which interrupt is not level-sensitive in 8085? - RST 7.5 is a raising edge-triggering
interrupt.
24. What does Quality factor mean? - The Quality factor is also defined, as Q. So it is a
number, which reflects the lossness of a circuit. Higher the Q, the lower are the losses.
25. What are level-triggering interrupt? - RST 6.5 & RST 5.5 are level-triggering
interrupts.

TWO MARK QUESTIONS - 8085 Microprocessor

1.What is Microprocessor? Give the power supply & clock frequency of
8085?
Ans:A microprocessor is a multipurpose, programmable logic device that reads
binary instructions from a storage device called memory accepts binary data as input
and processes data according to those instructions and provides result as output. The
power supply of 8085 is +5V and clock frequency in 3MHz.

2. List few applications of microprocessor-based system.

Ans: It is used:
i. For measurements, display and control of current, voltage, temperature, pressure, etc.
ii. For traffic control and industrial tool control.
iii. For speed control of machines.

3. What are the functions of an accumulator?

Ans:The accumulator is the register associated with the ALU operations and
sometimes I/O operations. It is an integral part of ALU. It holds one of data to be
processed by ALU. It also temporarily stores the result of the operation performed by
the ALU.

4. List the 16 – bit registers of 8085 microprocessor.

Ans:Stack pointer (SP) and Program counter (PC).

5. List the allowed register pairs of 8085.

Ans: B-C register pair
 D-E register pair

H-L register pair

6. Mention the purpose of SID and SOD lines

Ans:SID (Serial input data line): It is an input line through which the microprocessor
accepts serial data.
SOD (Serial output data line): It is an output line through which the
microprocessor sends output serial data.

7. What is an Opcode?
Ans: The part of the instruction that specifies the operation to be performed is
called the operation code or opcode.

8. What is the function of IO/M signal in the 8085?

Ans: It is a status signal. It is used to differentiate between memory locations
and I/O operations. When this signal is low (IO/M = 0) it denotes the memory
related operations. When this signal is high (IO/M = 1) it denotes an I/O
operation.

9. What is an Operand?
Ans: The data on which the operation is to be performed is called as an Operand.

10. How many operations are there in the instruction set of 8085 microprocessor?
Ans: There are 74 operations in the 8085 microprocessor.

11. List out the five categories of the 8085 instructions. Give examples of
the instructions for each group.
Ans:

• Data transfer group – MOV, MVI, LXI.

• Arithmetic group – ADD, SUB, INR.
• Logical group –ANA, XRA, CMP.
• Branch group – JMP, JNZ, CALL.
• Stack I/O and Machine control group – PUSH, POP, IN, HLT.

12. Explain the difference between a JMP instruction and CALL instruction.
Ans: A JMP instruction permanently changes the program counter. A CALL
instruction leaves information on the stack so that the original program
execution sequence can be resumed.

13. Explain the purpose of the I/O instructions IN and OUT.

Ans: The IN instruction is used to move data from an I/O port into the accumulator. The
OUT instruction is used to move data from the accumulator to an I/O port. The IN &
OUT instructions are used only on microprocessor, which use a separate address space
for interfacing.

14. What is the difference between the shift and rotate instructions?
Ans: A rotate instruction is a closed loop instruction. That is, the data moved
out at one end is put back in at the other end. The shift instruction loses the data
that is moved out of the last bit locations.

15. How many address lines in a 4096 x 8 EPROM CHIP?

Ans: 12 address lines.

16. What are the Control signals used for DMA operation?
Ans:-HOLD & HLDA.
17. What is meant by Wait State?

Ans:-This state is used by slow peripheral devices. The peripheral devices can transfer
the data to or from the microprocessor by using READY input line. The microprocessor
remains in wait state as long as READY line is low. During the wait state, the contents
of the address, address/data and control buses are held constant.

18. List the four instructions which control the interrupt structure of the 8085
microprocessor.
Ans:-
DI ( Disable Interrupts )
EI ( Enable Interrupts )
RIM ( Read Interrupt Masks )
SIM ( Set Interrupt Masks )

19. What is meant by polling?

Ans:-Polling or device polling is a process which identifies the device that has
interrupted the microprocessor.

20. What is meant by interrupt?

Ans:-Interrupt is an external signal that causes a microprocessor to jump to a
specific subroutine.

21. Explain priority interrupts of 8085.

Ans:-The 8085 microprocessor has five interrupt inputs. They are TRAP, RST 7.5, RST
6.5, RST 5.5, and INTR. These interrupts have a fixed priority of interrupt service. If
two or more interrupts go high at the same time, the 8085 will service them on priority
basis. The TRAP has the highest priority followed by RST 7.5, RST 6.5, RST 5.5. The
priority of interrupts in 8085 is shown in the table.

TRAP 1

RST 7.5 2

RST 6.5 3
RST 5.5 4
INTR 5
22. What is a microcomputer?
Ans:-A computer that is designed using a microprocessor as its CPU is called
Microcomputer
23. What is the signal classification of 8085
Ans:-All the signals of 8085 can be classified into 6 groups
Address bus
Data bus
Control and status signals
Power supply and frequency signals
Externally initiated signals
 Serial I/O ports
24. What are operations performed on data in 8085
Ans:- The various operations performed are Store 8-bit data Perform arithmetic and
logical operationsTest for conditions Sequence the execution of instructions Store data
temporarily during execution in the defined R/W memory locations called the stack

25. Steps involved to fetch a byte in 8085

Ans:-
i. The PC places the 16-bit memory address on the address bus
ii. The control unit sends the control signal RD to enable the memory chip
iii. The byte from the memory location is placed on the data bus
iv. The byte is placed in the instruction decoder of the microprocessor and the task is
carried out according to the instruction
26. How many interrupts does 8085 have, mention them
Ans:-The 8085 has 5 interrupt signals; they are INTR, RST7.5, RST6.5, RST5.5
and TRAP

27. Basic concepts in memory interfacing

Ans:-The primary function of memory interfacing is that the microprocessor should be
able to read from and write into a given register of a memory chip. To perform these
operations the microprocessor should Be able to select the chipIdentify the register
.Enable the appropriate buffer
28. Define instruction cycle, machine cycle and T-state

Ans:-Instruction cycle is defined, as the time required completing the execution of an

instruction. Machine cycle is defined as the time required completing one operation of
accessing memory, I/O or acknowledging an external request. Tcycle is defined as one
subdivision of the operation performed in one clock period

29. What is an instruction?

Ans:-An instruction is a binary pattern entered through an input device to
command the microprocessor to perform that specific function
30. What is the use of ALE

Ans:-The ALE is used to latch the lower order address so that it can be available in T2
and T3 and used for identifying the memory address. During T1 the ALE goes high, the
latch is transparent ie, the output changes according to the input data, so the output of
the latch is the lower order address. When ALE goes low the lower order address is
latched until the next ALE.

31. How many machine cycles does 8085 have, mention them
Ans:The 8085 have seven machine cycles. They are
Opcode fetch
Memory read
Memory write
I/O read
I/O write
Interrupt acknowledge
Bus idle

32. Explain the signals HOLD, READY and SID

Ans:HOLD indicates that a peripheral such as DMA controller is requesting the use of
address bus, data bus and control bus. READY is used to delay the microprocessor read
or write cycles until a slow responding peripheral is ready to send or accept data.SID is
used to accept serial data bit by bit

33. Mention the categories of instruction and give two examples for each category.
Ans:The instructions of 8085 can be categorized into the following five
categories

Data transfer Instructions -MOV Rd,Rs STA 16-bit

Arithmetic Instructions -ADD R DCR M
Logical Instructions -XRI 8-bit RAR
Branching Instructions -JNZ CALL 16-bit
Machine control Instructions -HLT NOP

34. Explain LDA, STA and DAA instructions

Ans:LDA copies the data byte into accumulator from the memory location specified by
the 16-bit address. STA copies the data byte from the accumulator in the memory
location specified by 16-bit address. DAA changes the contents of the accumulator from
binary to 4-bit BCD digits.

35. Explain the different instruction formats with examples

Ans:The instruction set is grouped into the following formats
One byte instruction -MOV C,A
Two byte instruction -MVI A,39H
Three byte instruction -JMP 2345H

36. What is the use of addressing modes, mention the different types

Ans:The various formats of specifying the operands are called addressing modes, it is
used to access the operands or data. The different types are as follows
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implicit addressing
37. What is the use of bi-directional buffers?
Ans:It is used to increase the driving capacity of the data bus. The data bus of a
microcomputer system is bi-directional, so it requires a buffer that allows the data to
flow in both directions.
38. Give the register organization of 8085
Ans:
W(8) Temp. Reg
Z(8) Temp. Reg
B(8) Register
C(8) Register
D(8) Register
E(8) Register
H(8) Register
L(8) Register
Stack Pointer (16)
Program Counter (16)
39. Define stack and explain stack related instructions

Ans:The stack is a group of memory locations in the R/W memory that is used for the
temporary storage of binary information during the execution of the program. The stack
related instructions are PUSH & POP

40. Why do we use XRA A instruction

Ans:The XRA A instruction is used to clear the contents of the Accumulator and store
the value 00H.
41. Compare CALL and PUSH instructions
Ans:
CALL PUSH
1.When CALL is executed the microprocessor automatically stores the 16-bit address of
the instruction next to CALL on the stack.
2.When CALL is executed the stack pointer is decremented by two
1.PUSH The programmer uses the instruction to save the contents of the register pair on
the stack
2. When PUSH is executed the stack pointer is decremented by two

42. What is Microcontroller and Microcomputer

Ans:Microcontroller is a device that includes microprocessor; memory and I/O
signal lines on a single chip, fabricated using VLSI technology. Microcomputer
is a computer that is designed using microprocessor as its CPU. It includes
microprocessor, memory and I/O.

43. Define Flags

Ans:The flags are used to reflect the data conditions in the accumulator. The 8085 flags
are S-Sign flag, Z-Zero flag, AC-Auxiliary carry flag, P-Parity flag, CYCarry flag, D7
D6 D5 D4 D3 D2 D1 D0

44. How does the microprocessor differentiate between data and instruction?

Ans:When the first m/c code of an instruction is fetched and decoded in the instruction
register, the microprocessor recognizes the number of bytes required to fetch the entire
instruction. For example MVI A, Data, the second byte is always considered as data. If
the data byte is omitted by mistake whatever is in that memory location will be
considered as data & the byte after the ―data‖ will be treated as the next instruction.

45. Compare RET and POP

Ans:
RET POP

1.RET transfers the contents of the top two locations of the stack to the PC
 2.When RET is executed the SP is incremented by two
3.Has 8 conditional RETURN instructions

1.POP transfers the contents of the top two locations of the stack to the specified
register pair
2. When POP is executed the SP is incremented by two
3.No conditional POP instructions

46.What is interrupt service routine?

Ans:Interrupt means to break the sequence of operation. While the CPU is
executing a program an interrupt breaks the normal sequence of execution of
instructions & diverts its execution to some other program. This program to which the
control is transferred is called the interrupt service routine.

PART—B

1. Draw the functional block diagram of 8085, and explain in brief. (16)
2. What are the different addressing modes used in 8085. Explain with an example. (16)
3. Discuss the interrupt system in 8085. (16)
4. What are the memories mapped I/O, I/O mapped & I/O explain. (16)
5. Draw the timing diagram for IN & OUT instructions of 8085. (16)
7. a. Draw the block diagram of 8085 mp and explain? (12)

b. Write an assembly language program to add two 2-digits BCD Number? (4)
8. a. Explain the instruction set of 8085? (10)
b. Write notes on status flag? (6)
9. a. Explain the architecture of Intel 8085 with the help of a block diagram? (12)
b. Explain the similarities diff b/w subtract and compare instructions in 8085? (4) 10
10. a. Describe the sequence of event that may occur during the different T state in the opcode
Fetch machine cycle of 8085? (8)
b. Write an assembly language program to convert on array of ASCII code to corresponding
Binary (hex) value. The ASCII array is stored starting from 4200H.The first element of the
number of elements in the array. (8)
11. a. With neat block diagram explain the architecture of 8085? (10)
b. List out the maskable and non maskable interrupts available in 8085? (6)
12. a. How do the instructions of 8085 is classified based on their function and word length?
Give
an example? (8)
b. Write an ALP to Add two 8bit numbers? (8)
13. (a)Specify the contents of the registers and the flag status as the following instructions are
executed.(8)
i. MVI A, 00H
ii. MVI B, F8H
iii. MOV C, A
iv. MOV D, B
v. HLT
(b)Write instructions to load the hexadecimal number 65H in register C and 92H in
accumulator A. Display the number 65H at PORT0 and 92H at PORT1.(8)
14. (a)Why the lower order address bus is multiplexed with data bus? How they will be de
multiplexed? (8) (b) Differentiate between maskable and non-maskable interrupts.(8)
15 .(a)Write an 8085 assembly language program using minimum number of instructions to
add the 16 bit no. in BC, DE & HL. Store the 16 bit result in DE pair. (8)
b) Explain the similarities diff b/w subtract and compare instructions in 8085? (8)
16. (a)Explain in detail the following instructions:- (i) ADC (ii) LHLD (iii) RLC (iv) DI
(b) Define & explain the term addressing modes.
 UNIT V: INTERFACING AND APPLICATIONS OF
MICROPROCESSOR
Basic interfacing concepts – Interfacing of Input and output devices –
Applications of microprocessor temperature control – Stepper motor control –
Traffic light control.

UART Functionality
The UART is a universal asynchronous receiver/transmitter, which is modeled on the
real-world. Intel® 8251 peripheral interface adapter component. In the model we are
considering, the UART consists of three main blocks.
• a serial transmit block
• a serial receive block and
• a CPU Interface (I/F) block.
The serial transmit block has two buffers (FIFO) into which data is written by
the CPU I/F block. After the data is written into the buffers it is transmitted serially onto
TXD. As long as the FIFO is not full the serial transmit block sets the signal TX_RDY
high.
The serial receive block has four buffers (FIFO). The block checks for the parity
and the validity of the data frame on the RXD input and then writes correct data into its
buffers. It also sets the signal RX_RDY low if its FIFO is empty.
The CPU I/F block is responsible for reading the status register, data register and
writing data into interrupt enable register and data register. It receives control signals
from the CPU for
performing certain tasks. The different functions for the set of control signals is given in
a
tabular form below.

D_XS R/W CPU I/F Function

0 R Read status register

0 W Write interrupt enable

register

1 R Receive data from

receive block into data
register.

1 W Write data register &

transmit data into
transmit FIFO.

The XINT is asserted when there is an interrupt factor, i.e. atleast one of status
register bits is asserted, and is also not masked by a corresponding bit in the interrupt
enable register. Bits 0, 1, 2 of the interrupt enable register mask the bits 0, 1,2 of the
status register. The block diagram for the UART with its I/O ports and three main
blocks is given below in Figure1
 The timing chart for the reading and writing operations, and the serial data
format, are given below in Figure 2 (2.1 through 2.3).
2. System partitioning and Component Description
The UART can be divided into several sub-components, according to different
functionality. The description of each of these components is given next section. The
block diagram depicting the more detailed component partitioning is shown in Figures 3
and 4.
 The block diagram shows the different components. The D_XS, XCS, DATA,
XWR, XRD inputs are synchronized with the clock by their respective synchronizing
blocks each of which register the signals twice.

The CPU I/F registers the status register, interrupt enable register, and data
register are modeled separately. Each of these components have DXS1, X_WR/X_RD
as control signals. The transmit and receive FIFO‘s are separated from their
corresponding control blocks the transmit and receive blocks. The RXD is passed
through an IFF and the TXD goes through an OFF before being output. The data goes
through an OFF before being written onto DATA output.
2.1. The Components

DATASynch: This component registers the DATA signal twice so as to synchronize it

with the
system clock CLK16M. The synchronized signal is data_bus1.

DXSSynch: This component registers the D_XS signal twice so as to synchronize it

with the
system clock CLK16M. The synchronized output is DXS1.

XCSSynch: This component registers the XCS signal twice so as to synchronize it with
the
system clock CLK16M. The synchronized output is XCS1.

XWRSynch: This component registers the XWR signal twice so as to synchronize it

with the
system clock CLK16M. The synchronized output is X_WR.

XRDSynch: This component registers the XRD signal twice so as to synchronize it with
the
system clock CLK16M. The synchronized output is X_RD.
RXDIFF: The RXD input is synchronized with the clock before being read by the
receive block.
The synchronized output is r_xd.

DATAOFF: The data from the data register/status register is registered once before
being
written onto DATA output.

Data Tristate Buffer: This component drives the data bus output. It sets it to data_bus2
when
the XRD is asserted and to high impedance otherwise.

XINTOFF: The interrupt factor signal xintd is registered once before being output as
XINT.

TXDOFF: The transmit data signal from the serial transmit block txd is synchronized
with the
clock before being output onto TXD output.

Status Register: This component represents the status of the UART. The register has
TX_RDY,
RX_RDY, PERR as its contents corresponding to bits 0, 1, 2 respectively. Its data is
used to
generate the interrupt factor xintd.

Interrupt Enable Register: The contents of this register are used to mask the interrupts
the CPU
does not want to process. Data on the data_bus1 bus (bits 2 downto 0) is written into
this register
when both DXS1 and X_WR are low. The XINT generator uses this register contents to
mask
the unwanted interrupts.

XINT Generator: This component generates the interrupt from the status register data
and the
interrupt enable register data. The equation for the interrupt signal xintd generation is as
given
below.

Transmit FIFO: The FIFO is 8-bit by 2-word. It receives control signals from the serial
transmit
block. The data on signal data_bus1 is written into its buffer when WRP is asserted. At
the same
time the write pointer is incremented. The data is read onto the stb_fifo_data signal
when the
stb_fifo_read is asserted. The stb_fifo_read_inc asserted at the same time as
stb_fifo_read,
increments the read pointer by one. The read pointer is reset when the read pointer has
reached
its maximum. The write pointer is cleared when the write pointer has reached its
maximum. The
TX_RDY is set low when the FIFO is full.

Receive FIFO: The FIFO is 8-bit by 4-word. It receives control signals from the serial
receive
block. The data received from the receive block, rec_data is written into its buffer when
srb_fifo_write is asserted. The srb_fifo_write_inc asserted at the same time as
srb_fifo_write,
increments the write pointer by one.
The data is read onto the data_bus2 signal when the XRD is asserted. The
srb_fifo_read_inc
asserted at the same time as srb_fifo_read increments the read pointer by one. The read
pointer is
reset when the read pointer has reached its maximum value. The write pointer is cleared
when
the write pointer reaches its maximum limit before further increment. The RX_RDY is
asserted
low when the FIFO is empty.

Serial Transmit Block: This component is responsible for serial transmission of data
onto TXD.
It generates the requisite control signals for reading and writing the transmit FIFO. This
component can be divided into sub-components to make modeling easier. The block
diagram for
this is given below in Figure 3.
All the sub-components have XCS1 as chip enable and XRST as reset signals. The
transmit
clock counter counts the CLK16M clock cycles and sets the stb_clk16 high after every
16 clock
cycles. This signal is used as a enable by the transmit data counter, and the transmit
block. The
transmit data counter keeps count of the number of data bits transmitted onto tx_d. The
data
count is incremented when stb_dci is asserted and cleared when stb_dcc is asserted.
These
signals are provided by the transmit control block. The parity counter counts the number
of bits
that were high in the eight bits of data being transmitted. The parity count is
incremented on
assertion of stb_pci and cleared on assertion of stb_pcc. These two signals are provided
by the
transmit block.
 The transmit control block controls the whole process of transmission. It is
modeled in the form of a state machine. The state machine has three states namely:
IDLE, FIFO_READ,
DATA_TRANSMIT. Initially the machine is in the IDLE state. When DXS1 is high and
XWR is
low it jumps to FIFO_READ state. In the FIFO_READ state the data in the FIFO is read
onto its
output stb_fifo_data by setting stb_fifo_read and stb_fifo_read_inc high. It then jumps
to
DATA_TRANSMIT state. In DATA_TRANSMIT state the transmit and the stb_dci
signals are
asserted. The machine waits in this state until the signal transmitted is asserted by the
transmit
block and upon which it asserts stb_dcc and goes back to IDLE state. When XRST is
asserted it
resets all its output signals.
The transmit block has stb_clk_16 as clock and XRST as asynchronous reset. It
is enabled when transmit signal is asserted. It then transmits data serially onto the tx_d
depending upon the value of the stb_data _count. It sends the start bit when the count is
less than 1. It then transmits the data bit by bit on every stb_clk16 high until the count
reaches 9. After this it sends the parity bit corresponding to the parity count
stb_par_count. When the count becomes greater than 10 it transmits stop bit and asserts
transmitted signal.

Serial Receive Block: This component is responsible for serial receiving of data on
RXD. It
generates the requisite control signals for reading and writing the receive FIFO. This
component
can be further divided into sub-components to make modeling easier. The block
diagram for this
is given below in Figure 4.

All the sub-components have XCS1 as chip enable and XRST as reset signals. The
receive clock
counter counts the CLK16M clock cycles. It at first counts upto 8 clock cycles when the
start bit
is received. It then starts counting and sets the srb_clk16 high after every 16 clock
cycles. This
signal is used as a clock by the transmit data counter, transmit parity counter, and the
transmit
block. The transmit data counter keeps count of the number of data bits received from
rx_d. The
data count is incremented when srb_dci is asserted and cleared when srb_dcc is
asserted. These
signals are provided by the receive control block. The parity counter counts the number
of bits
that were high in the eight bits of data being recieved. The parity count is incremented
on
assertion of srb_pci and cleared on assertion of srb_pcc. These two signals are provided
by the
receive block.
The receive control block controls the whole receiving process. It is modeled in the
form of a
state machine. The state machine has four states namely: IDLE, FIFO_WRITE,
FIFO_READ,
DATA_RECEIVE. Initially the machine is in the IDLE state. In this state when the start
bit is
received on rx_d it jumps to DATA_RECEIVE state. In the DATA_RECEIVE state,
receive and
the srb_dci signals are asserted. The machine waits in this state until the signal received
is
asserted by the receive block. When received is asserted it checks for PERR and x_fre
before it
asserts srb_dcc and jumps to FIFO_WRITE state. If PERR is high or x_fre is low it
jumps to
IDLE state instead. In the FIFO_WRITE state it asserts the srb_fifo_write and
srb_fifo_write_inc
signals and then jumps to IDLE state so that it remains in the FIFO_WRITE state for
only one
clock cycle. This ensures that the data is written in only one of the buffers, as the FIFO
read and
write processes are clock sensitive.
The receive block has srb_clk_16 as clock and XRST as asynchronous reset. It is
enabled when
receive signal is asserted. It then receives data serially from rx_d depending upon the
value of
the srb_data _count. It receives data bit by bit into rec_data on every srb_clk16 high
until the
data count reaches 8. After this it receives the parity bit. When the count becomes
greater than 8
it checks for the stop bit.

PARALLEL I/O 8255:

The Intel 8255 (or i8255) Programmable Peripheral Interface chip is a peripheral chip
originally developed for the Intel 8085 microprocessor, and as such is a member of a
large array of such chips, known as the MCS-85 Family. This chip was later also used
with the Intel 8086 and its descendants. It was later made (cloned) by many other
manufacturers. It is made in DIP 40 and PLCC 44 pins encapsulated versions.

This chip is used to give the CPU access to programmable parallel I/O, and is similar to
other such chips like the Motorola 6520 PIA (Peripheral Interface Adapter) the MOS
Technology 6522 (Versatile Interface Adapter) and the MOS Technology CIA
(Complex Interface Adapter) all developed for the 6502 family. Other such chips are the
2655 Programmable Peripheral Interface from the Signetics 2650 family of
microprocessors, the 6820 PIO (Peripheral Input/Output) from the Motorola 6800
family, the Western Design Center WDC 65C21, an enhanced 6520, and many others.

The 8255 is widely used not only in many microcomputer/microcontroller systems

especially Z-80 based, home computers such as SV-328 and all MSX, but also in the
system board of the best known original IBM-PC, PC/XT, PC/jr, etc. and clones.
However, most often the functionality the 8255 offered is now not implemented with
the 8255 chip itself anymore, but is embedded in a larger VLSI chip as a sub function.
The 8255 chip itself is still made, and is sometimes used together with a micro
controller to expand its I/O capabilities.

Functional Block of 8255

The 8255 has 24 input/output pins in all. These are divided into three 8-bit ports. Port A
and port B can be used as 8-bit input/output ports. Port C can be used as an 8-bit
input/output port or as two 4-bit input/ouput ports or to produce handshake signals for
ports A and B.

The three ports are further grouped as follows:

1) Group A consisting of port A and upper part of port C.

2) Group B consisting of port B and lower part of port C.

Eight data lines (D0 - D7) are available (with an 8-bit data buffer) to read/write data into
the ports or control register under the status of the "RD" (pin 5) and WR" (pin 36),
which are active low signals for read and write operations respectively. The address
lines A1 and A0 allow to successively access any one of the ports or the control register
as listed below:

A1 A0 Function
0 0 port A
0 1 port B
1 0 port C
1 1 control register

The control signal "'CS" (pin 6) is used to enable the 8255 chip. It is an active low
signal, ie, when CS = '0, the 8255 is enabled. The RESET input (pin 35) is connected to
a system (like 8085, 8086, etc. ) reset line so that when the system is reset, all the ports
are initialised as input lines. This is done to prevent 8255 and/or any peripheral
connected to it, from being destroyed due to mismatch of ports. This is explained as
follows. Suppose an input device is connected to 8255 at port A. If from the previous
operation, port A is initialised as an output port and if 8255 is not reset before using the
current configuration, then there is a possibility of damage of either the input device
connected or 8255 or both since both 8255 and the device connected will be sending out
data.

The control register or the control logic or the command word register is an 8-bit
register used to select the modes of operation and input/output designation of the ports.

Operational Modes of 8255

There are two main operational modes of 8255:

1. Input/output mode 2. Bit set/reset mode

Input/Output Mode

There are three types of the input/output mode. They are as follows:
Mode 0

In this mode, the ports can be used for simple input/output operations without
handshaking. If both port A and B are initialized in mode 0, the two halves of port C can
be either used together as an additional 8-bit port, or they can be used as individual 4-bit
ports. Since the two halves of port C are independent, the may be used such that one-
half is initialized as an input port while the other half is initialized as an output port.

Mode 1

When we wish to use port A or port B for handshake (strobed) input or output operation,
we initialise that port in mode 1 (port A and port B can be initilalised to operate in
different modes,ie, for eg, port A can operate in mode 0 and port B in mode 1). Some of
the pins of port C function as handshake lines.

For port B in this mode (irrespective of whether is acting as an input port or output
port), PC0, PC1 and PC2 pins function as handshake lines.

If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as
handshake signals. Pins PC6 and PC7 are available for use as input/output lines.

If port A is initialised as mode 1 output port, then pins PC3, PC6 and PC7 function as
handshake signals. PC4 and PC5 are available as input/output lines.

Mode 2

Only group A can be initialised in this mode. Port A can be used for bidirectional
handshake data transfer. This means that data can be input or output on the same eight
lines (PA0 - PA7). Pins PC3 - PC7 are used as hanshake lines for port A. The remaining
pins of port C (PC0 - PC2) can be used as input/output lines if group B is initialised in
mode 0. In this mode, the 8255 may be used to extend the system bus to a slave
microprocessor or to transfer data bytes to and from a floppy disk controller.

Bit Set/Reset (BSR) mode

In this mode only port C can be used (as an output port). Each line of port C (PC0 -
PC7) can be set/reset by suitably loading the command word register.no effect occurs in
input-output mode.

Control Word Format

Input/output mode format

Control Word format in input/output mode

The figure shows the control word format in the input/output mode. This mode is
selected by making D7 = '1' .

D0, D1, D3, D4 are for lower port C, port B, upper port C and port A respectively.
When D0 or D1 or D3 or D4 are "SET", the corresponding ports act as input ports. For
eg, if D0 = D4 = '1', then lower port C and port A act as input ports. If these bits are
"RESET", then the corresponding ports act as output ports. For eg, if D1 = D3 = '0', then
port B and upper port C act as output ports.
 D2 is used for mode selection for group B (Port B and Lower Port C). When D2 = '0',
mode 0 is selected and when D2 = '1', mode 1 is selected.

D5, D6 are used for mode selection for group A (Upper Port C and Port A). The
format is as follows:

D6 D5 mode
0 0 0
0 1 1
1 x 2

Example: If port B and upper port C have to be initialised as input ports and lower port
C and port A as ouput ports (all in mode 0), what is the control word?

o 1. Since it is an input/ouput mode, D7 = '1'.

o 2. Mode selection bits, D2, D5, D6 are all '0' for mode 0 operation.
o 3. Port B should operate as input port, hence, D1 = '1'.
o 4. Upper port C should also be an input port, hence, D3 = '1'.
o 5. Port A has to operate output port, hence, D4 = '0'.
o 6. Lower port C should also operate as output port, hence, D0 = '0'.

Applying the corresponding values to the format in input/output mode, we get the
control word as "8A (hex)"

BSR mode format

Control Word format in BSR mode

The figure shows the control word format in BSR mode. This mode is selected by
making D7='0'.

D0 is used for bit set/reset. When D0= '1', the port C bit selected (selection of a port C
bit is shown in the next point) is SET, when D0 = '0', the port C bit is RESET.

D1, D2, D3 are used to select a particular port C bit whose value may be altered using
D0 bit as mentioned above. The selection of the port C bits are done as follows:

D3 D2 D1 bit/pin of port C selected

0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

D4, D5, D6 are not used.

Example: If the 5th bit (PC5) of port C has to be "SET", then what is the control word?
o 1. Since it is BSR mode, D7 = '0'.
o 2. Since D4, D5, D6 are not used, assume them to be '0'.
o 3. PC5 has to be selected, hence, D3 = '1', D2 = '0', D1 = '1'.
o 4. PC5 has to be set, hence, D0 = '1'.

Applying the above values to the format for BSR mode, we get the control word as "0B
(hex)".

KEYBOARD/DISPLAY CONTROLLER - INTEL 8279

The INTEL 8279 is specially developed for interfacing keyboard and display devices to
8085/8086/8088 microprocessor based system. The important features of 8279 are,

o Simultaneous keyboard and display operations.

o Scanned keyboard mode.
o Scanned sensor mode.
o 8-character keyboard FIFO.
o 1 6-character display.
o Right or left entry 1 6-byte display RAM.
o Programmable scan timing.

Block diagram of 8279:

The functional block diagram of 8279 is shown.

Keyboard section:
 The keyboard section consists of eight return lines RL0 - RL7 that can be used to form
the columns of a keyboard matrix.
It has two additional input : shift and control/strobe. The keys are automatically
debounced.
The two operating modes of keyboard section are 2-key lockout and N-key rollover.
In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is
recognized.
In the N-key rollover mode simultaneous keys are recognized and their codes are
stored in FIFO.
The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.
The FIFO can store eight key codes in the scan keyboard mode. The status of the shift
key and control key are also stored along with key code. The 8279 generate an interrupt
signal when there is an entry in FIFO. The format of key code entry in FIFO for scan
keyboard mode is,

In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in
FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ
as high to interrupt the processor.

Display section:

The display section has eight output lines divided into two groups A0-A3 and B0-B3.
The output lines can be used either as a single group of eight lines or as two groups of
four lines, in conjunction with the scan lines for a multiplexed display.
The output lines are connected to the anodes through driver transistor in case of
common cathode 7-segment LEDs.
The cathodes are connected to scan lines through driver transistors.
The display can be blanked by BD (low) line.
The display section consists of 16 x 8 display RAM. The CPU can read from or write
into any location of the display RAM.

Scan section:

The scan section has a scan counter and four scan lines, SL0 to SL3.
In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.
In encoded scan mode, the output of scan lines will be binary count, and so an external
decoder should be used to convert the binary count to decoded output.
 The scan lines are common for keyboard and display.
The scan lines are used to form the rows of a matrix keyboard and also connected to
digit drivers of a multiplexed display, to turn ON/OFF.

CPU interface section:

The CPU interface section takes care of data transfer between 8279 and the processor.
This section has eight bidirectional data lines DB0 to DB7 for data transfer between
8279 and CPU.
It requires two internal address A =0 for selecting data buffer and A = 1 for selecting
control register of8279.
The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to
8279.
It has an interrupt request line IRQ, for interrupt driven data transfer with processor.
The 8279 require an internal clock frequency of 100 kHz. This can be obtained by
dividing the input clock by an internal prescaler.
The RESET signal sets the 8279 in 16-character display with two -key lockout
keyboard modes.

Programming the 8279:

The 8279 can be programmed to perform various functions through eight command
words.

DIGITAL TO ANALOG CONVERTOR:

To convert the digital signal to analog signal a Digital-to-Analog Converter (DAC) has
to be employed.The DAC will accept a digital (binary) input and convert to analog
voltage or current. Every DAC will have "n" input lines and an analog output. The DAC
require a reference analog voltage (Vref) or current (Iref) source. The smallest possible
analog value that can be represented by the n-bit binary code is called resolution. The
resolution of DAC with n-bit binary input is 1/2nof reference analog value. Every
analog output will be a multiple of the resolution. For example, consider an 8-bit DAC
with reference analog voltage of 5 volts. The analog values for all possible digital input
are as shown.
PIN DIGRAM & BLOCK DIAGRAM OF DAC0800

The DAC0800 is an 8-bit, high speed, current output DAC with a typical settling time
(conversion time) of 100 ns. It produces complementary current output, which can be
converted to voltage by using simple resistor load.The DAC0800 require a positive and
a negative supply voltage in the range of ± 5V to ±18V. It can be directly interfaced
with TTL, CMOS, PMOS and other logic families.For TTL input, the threshold pin
should be tied to ground (VLC = 0V). The reference voltage and the digital input will
decide the analog output current, which can be converted to a voltage by simply
connecting a resistor to output terminal or by using an op-amp I to V converter.The
DAC0800 is available as a 16-pin IC in DIP.
The pin configuration of DAC0800 is
 The internal block diagram of DACO800 is,

ANALOG TO DIGITAL CONVERTOR

The ADC0809 is an 8-bit successive approximation type ADC with inbuilt 8-channel
multiplexer.The ADC0809 is suitable for interface with 8086 microprocessor. The
ADC0809 is available as a 28 pin IC in DIP (Dual Inline Package). The ADC0809 has a
total unadjusted error of ±1 LSD (Least Significant Digit). The ADC0808 is also same
as ADC0809 except the error. The total unadjusted error in ADC0808 is ± 1/2 LSD. The
pin configuration of ADC0809/ADC0808 is
PIN DESCRIPTION OF ADC0809

The internal block diagram of ADC0809/ADC0808 is

The various functional blocks of ADC are 8-channel multiplexer, comparator, 256R
resistor ladder, switch tree, successive approximation register, output buffer, address
latch and decoder.

The 8-channel multiplexer can accept eight analog inputs in the range of 0 to 5V and
allow one by one for conversion depending on the 3-bit address input. The channel
selection logic is,

The successive approximation register (SAR) performs eight iterations to determine

the digital code for input value. The SAR is reset on the positive edge of START pulse
and start the conversion process on the falling edge of START pulse.

A conversion process will be interrupted on receipt of new START pulse. The End-Of-
Conversion (EOC) will go low between 0 and 8 clock pulses after the positive edge of
START pulse. The ADC can be used in continuous conversion mode by tying the EOC
output to START input. In this mode an external START pulse should be applied
whenever power is switched ON.

The 256'R resistor network and the switch tree is shown in fig.
 The 256R ladder network has been provided instead of conventional R/2R ladder
because of its inherent monotonic, which guarantees no missing digital codes. Also the
256R resistor network does not cause load variations on the reference voltage.The
comparator in ADC0809/ADC0808 is a chopper- stabilized comparator. It converts the
DC input signal into an AC signal, and amplifies the AC sign using high gain AC
amplifier. Then it converts AC signal to DC signal. This technique limits the drift
component of the amplifier, because the drift is a DC component and it is not
amplified/passed by the AC amp1ifier. This makes the ADC extremely insensitive to
temperature, long term drift and input offset errors.In ADC conversion process the input
analog value is quantized and each quantized analog value will have a unique binary
equivalent.

The quantization step in ADC0809/ADC0808 is given by,

Inter Integrated Circuits interfacing (I2C Standard)

I²C (Inter-Integrated Circuit) is a multi-master serial computer bus invented by Philips

that is used to attach low-speed peripherals to a motherboard, embedded system, or
cellphone. SM Bus is a subset of I²C that defines stricter electrical and protocol
conventions. One purpose of SM Bus is to promote robustness and interoperability.
Accordingly, modern I²C systems incorporate policies and rules from SM Bus, and the
line between these two standards is often blurred in practice.

Design
A sample schematic with one master (a microcontroller) and three slave nodes (an
ADC, a DAC, and another microcontroller) with pull up resistors Rp
I²C uses only two bidirectional open-drain lines, Serial Data (SDA) and Serial Clock
(SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although
systems with other, higher or lower, voltages are permitted.

The I²C reference design has a 7-bit address space with 16 reserved addresses, so a
maximum of 112 nodes can communicate on the same bus. The most common I²C bus
modes are the 100 kbit/s standard mode and the 10 kbit/s low-speed mode, but clock
frequencies down to DC are also allowed. Recent revisions of I²C can host more nodes
and run faster (400 kbit/s Fast mode, 1 Mbit/s Fast mode plus or Fm+, and 3.4 Mbit/s
High Speed mode), and also support other extended features, such as 10-bit addressing.

The maximum number of nodes is obviously limited by the address space, and also by
the total bus capacitance of 400 pF, because it restricts practical communication
distances to a few meters.

Reference design

The reference design, as mentioned above, is a bus with a clock (SCL) and data (SDA)
lines with 7-bit addressing. The bus has two roles for nodes: master and slave:

Master node — node that issues the clock and addresses slaves
Slave node — node that receives the clock line and address.

The bus is a multi-master bus which means any number of master nodes can be present.
Additionally, master and slave roles may be changed between messages (after a STOP
is sent).

There are four potential modes of operation for a given bus device, although most
devices only use a single role and its two modes:

master transmit — master node is sending data to a slave

master receive — master node is receiving data from a slave
slave transmit — slave node is sending data to a master
slave receive — slave node is receiving data from the master

The master is initially in master transmit mode by sending a start bit followed by the 7-
bit address of the slave it wishes to communicate with, which is finally followed by a
single bit representing whether it wishes to write(0) to or read(1) from the slave.

If the slave exists on the bus then it will respond with an ACK bit (acknowledge) for
that address. The master then continues in either transmit or receive mode (according to
the read/write bit it sent), and the slave continues in its complementary mode (receive or
transmit, respectively).

The address and the data bytes are sent most significant bit first. The start bit is
indicated by a high->low transition of SDA with SCL high; the stop bit is indicated by a
low->high transition of SDA with SCL high.

If the master wishes to write to the slave then it repeatedly sends a byte with the slave
sending an ACK bit. (In this situation, the master is in master transmit mode and the
slave is in slave receive mode.)
If the master wishes to read from the slave then it repeatedly receives a byte from the
slave, the master sending an ACK bit after every byte but the last one. (In this situation,
the master is in master receive mode and the slave is in slave transmit mode.)

The master then ends transmission with a stop bit, or it may send another START bit if
it wishes to retain control of the bus for another transfer (a "combined message").

Message Protocols

I²C defines three basic types of message, each of which begins with a START and ends
with a STOP:

Single message where a master writes data to a slave;

Single message where a master reads data from a slave;
"Combined" messages, where a master issues at least two reads and/or writes to one or
more slaves.

In a combined message, each read or write begins with a START and the slave address.
After the first START, these are also called "repeated START" bits; repeated START
bits are not preceded by STOP bits, which is how slaves know the next transfer is part
of the same message.

Any given slave will only respond to particular messages, as defined by its product
documentation.

Pure I²C systems support arbitrary message structures. SMBus is restricted to nine of
those structures, such as "read word N" and "write word N", involving a single slave.

With only a few exceptions, neither I²C nor SMBus define message semantics, such as
the meaning of data bytes in messages. Message semantics are otherwise product-
specific. Those exceptions include messages addressed to the I²C "general call" address
(0x00) or to the SMBus "Alert Response Address"; and messages involved in the
SMBus "Address Resolution Protocol" (ARP) for dynamic address allocation and
management.

In practice most slaves adopt request/response control models, where one or more bytes
following a write command are treated as a command or address. Those bytes determine
how subsequent written bytes are treated and/or how the slave responds on subsequent
reads. Most SMBus operations involve single byte commands.

Messaging Example: 24c32 EEPROM

One specific example is the 24c32 type EEPROM, which uses two request bytes that are
called Address High and Address Low. (Accordingly, these EEPROMs aren't usable by
pure SMBus hosts, which only support single byte commands.) These bytes are used to
address bytes within the 32 kbit (4 kB) supported by that EEPROM; the same two byte
addressing is also used by larger EEPROMs, such as 24c512 ones storing 512 kbits (64
kB).

To write to the EEPROM, a single message is used. After the START, the master sends
the chip's bus address with the direction bit clear ("write"), then sends the two byte
address of data within the EEPROM and then sends data bytes to be written starting at
that address, followed by a STOP. When writing multiple bytes, all the bytes must be in
the same 32 byte page. While it's busy saving those bytes to memory, the EEPROM
won't respond to further I2C requests. (That's another incompatibility with SMBus:
SMBus devices must always respond to their bus addresses.)

To read starting at a particular address in the EEPROM, a combined message is used.

After a START, the master first writes that chip's bus address with the direction bit clear
("write") and then the two bytes of EEPROM data address. It then sends a (repeated)
START and the EEPROM's bus address with the direction bit set ("read"). The
EEPROM will then respond with the data bytes beginning at the specified EEPROM
data address -- a combined message, first a write then a read. The master issues a STOP
after the first data byte it NAKs rather than ACks (when it's read all it wants). The
EEPROM increments the address after each data byte transferred; multi-byte reads can
retrieve the entire contents of the EEPROM using one combined message.

Applications

I²C is appropriate for peripherals where simplicity and low manufacturing cost are more
important than speed. Common applications of the I²C bus are:

Reading configuration data from SPD EEPROMs on SDRAM, DDR SDRAM, DDR2
SDRAM memory sticks (DIMM) and other stacked PC boards
Supporting systems management for PCI cards, through an SMBus 2.0 connection.
Accessing NVRAM chips that keep user settings.
Accessing low speed DACs.
Accessing low speed ADCs.
Changing contrast, hue, and color balance settings in monitors (Display Data
Channel).
Changing sound volume in intelligent speakers.
Controlling OLED/LCD displays, like in a cellphone.
Reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan
speed.
Reading real time clocks.
Turning on and turning off the power supply of system components.

A particular strength of I²C is that a microcontroller can control a network of device

chips with just two general-purpose I/O pins and software.

Peripherals can also be added to or removed from the I²C bus while the system is
running, which makes it ideal for applications that require hot swapping of components.

Buses like I²C became popular when computer engineers realized that much of the
manufacturing cost of an integrated circuit design results from its package size and pin
count. A smaller package also usually weighs less and consumes less power, which is
especially important in cellphones and portable computing.

Limitations

The assignment of slave addresses is one weakness of I²C. Seven bits is too few to
prevent address collisions between the many thousands of available devices, and
manufacturers rarely dedicate enough pins to configure the full slave address used on a
given board. While some devices can set multiple address bits per pin, e.g. by using a
spare internal ADC channel to sense one of eight ranges set by an external voltage
divider, usually each pin controls one address bit. Manufacturers may provide pins to
configure a few low order bits of the address and arbitrarily set the higher order bits to
some value based on the model. This limits the number of devices of that model which
may be present on the same bus to some low number, typically between two and eight.
That partially addresses the issue of address collisisons between different vendors. The
addition of ten-bit addresses to I²C hasn't really caught on yet. Neither has the complex
SMBus "ARP" scheme for dynamically assigning addresses (other than for PCI cards
with SMBus presence, for which it is required).

Automatic bus configuration is a related issue. A given address may be used by a

number of different protocol-incompatible devices in various systems, and hardly any
device types can be detected at runtime. For example 0x51 may be used by a 24LC02 or
24C32 EEPROM, with incompatible addressing; or by a PCF8563 RTC, which can't
reliably be distinguished from either (without changing device state, which might not be
allowed). The only reliable configuration mechanisms available to hosts involve out-of-
band mechanisms such as tables provided by system firmware which list the available
devices. Again, this issue can partially be addressed by ARP in SMBus systems,
especially when vendor and product identifiers are used; but that hasn't really caught on.
The rev 03 version of the I²C specification adds a device ID mechanism, which at this
writing has not had time to catch on either.

I²C supports a limited range of speeds. Hosts supporting the multi-megabit speeds are
rare. Support for the Fm+ one-megabit speed is more widespread, since its electronics
are simple variants of what is used at lower speeds. Many devices don't support the 400
kbit/s speed (in part because SMBus doesn't yet support it). I²C nodes implemented in
software (instead of dedicated hardware) may not even support the 100 kbit/s speed; so
the whole range defined in the specification is rarely usable. All devices must at least
partially support the highest speed used or they may spuriously detect their device
address. Devices are allowed to stretch clock cycles to suit their particular needs, which
can starve bandwidth needed by faster devices and increase latencies when talking to
other device addresses. Bus capacitance also places a limit on the transfer speed,
especially when current sources aren't used to increase signal rise times.

PART-A

1.What are the various programmed data transfer methods?

Ans:i) Synchronous data transfer
ii) Asynchronous data transfer
iii) Interrupt driven data transfer

2. What is synchronous data transfer?

Ans:It is a data method which is used when the I/O device and the
microprocessor match in speed. To transfer a data to or from the device, the user
program issues a suitable instruction addressing the device. The data transfer is
completed at the end of the execution of this instruction.

3. What is asynchronous data transfer?

Ans:It is a data transfer method which is used when the speed of an I/O device
does not match with the speed of the microprocessor. Asynchronous data
transfer is also called as Handshaking.

4. What are the basic modes of operation of 8255?

 Ans: There are two basic modes of operation of 8255, They are:
1. I/O mode.
2. BSR mode.

In I/O mode, the 8255 ports work as programmable I/O ports, while In BSR
mode only port C (PC0-PC7) can be used to set or reset its individual port bits. Under
the IO mode of operation, further there are three modes of operation of 8255, So as to
support different types of applications, viz. mode 0, mode 1 and mode 2.

• Mode 0 - Basic I/O mode

• Mode 1 - Strobed I/O mode
• Mode 2 - Strobed bi-directional I/O.

5. Write the features of mode 0 in 8255?

Ans:1. Two 8-bit ports (port A and port B) and two 4-bit ports (port C upper
and lower) are available. The two 4-bit ports can be combined used as a third 8-
bit port.
2. Any port can be used as an input or output port.
3.Output ports are latched. Input ports are not latched.
4. A maximum of four ports are available so that overall 16 I/O configurations
are possible.

6. What are the features used mode 1 in 8255?

Ans:Two groups – group A and group B are available for strobed data transfer.
1. Each group contains one 8-bit data I/O port and one 4-bit control/data port.
2. The 8-bit data port can be either used as input or output port. The inputs and
outputs both are latched.
3. Out of 8-bit port C, PC0-PC2 is used to generate control signals for port B and
PC3=PC5 are used to generate control signals for port A. The lines PC6, PC7 may be
used as independent data lines.

7. What are the signals used in input control signal & output control signal?
Ans: Input control signal
• STB (Strobe input)
• IBF (Input buffer full)
• INTR(Interrupt request)
Output control signal
• OBF (Output buffer full)
• ACK (Acknowledge input)
• INTR(Interrupt request)

8. What are the features used mode 2 in 8255?

Ans:The single 8-bit port in-group A is available.
1. The 8-bit port is bi-directional and additionally a 5-bit control port is available.
2. Three I/O lines are available at port C, viz PC2-PC0.
3. Inputs and outputs are both latched.
4. The 5-bit control port C (PC3=PC7) is used for generating/accepting handshake
signals for the 8-bit data transfer on port A.
 9. What are the modes of operations used in 8253?
Ans:Each of the three counters of 8253 can be operated in one of the following
six modes of operation.

1. Mode 0 (Interrupt on terminal count)

2. Mode 1 (Programmable monoshot)
3. Mode 2 (Rate generator)
4. Mode 3 (Square wave generator)
5. Mode 4 (Software triggered strobe)
6. Mode 5 (Hardware triggered strobe)

10.Give the different types of command words used in 8259a?

Ans:The command words of 8259A are classified in two groups
1. Initialization command words (ICWs)
2. Operation command words (OCWs)
11. Give the operating modes of 8259a?
Ans:

(a) Fully Nested Mode

(b) End of Interrupt (EOI)
(c) Automatic Rotation
(d) Automatic EOI Mode
(e) Specific Rotation
(f) Special Mask Mode
(g) Edge and level Triggered Mode
(h) Reading 8259 Status
(i) Poll command

12. Define scan counter?

Ans:The scan counter has two modes to scan the key matrix and refresh the display. In
the encoded mode, the counter provides binary count that is to be externally decoded to
provide the scan lines for keyboard and display. In the decoded scan mode, the counter
internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on
SL0-SL3.The keyboard and display both are in the same mode at a time.

13. What is the output modes used in 8279?

Ans:8279 provides two output modes for selecting the display options.
1.Display Scan
In this mode, 8279 provides 8 or 16 character-multiplexed displays those can be
organized as dual 4-bit or single 8-bit display units.
2.Display Entry
8279 allows options for data entry on the displays. The display data is entered
for display from the right side or from the left side.
14. What are the modes used in keyboard modes?
Ans:1. Scanned Keyboard mode with 2 Key Lockout.
2. Scanned Keyboard with N-key Rollover.
3. Scanned Keyboard special Error Mode.
4. Sensor Matrix Mode.
15. What are the modes used in display modes?
Ans:1. Left Entry mode
In the left entry mode, the data is entered from the left side of the display unit.
2. Right Entry Mode.
In the right entry mode, the first entry to be displayed is entered on the
rightmost display.

16. What is the use of modem control unit in 8251?

Ans:The modem control unit handles the modem handshake signals to
coordinate the communication between the modem and the USART

17. What is interfacing?

Ans:An interface is a shared boundary between the devices which involves
sharing information. Interfacing is the process of making two different systems
communicate with each other.
18. List the operation modes of 8255
Ans:a) I.O Mode
i. Mode 0-Simple Input/Output.
ii. Mode 1-Strobed Input/Output (Handshake mode)
iii. Mode 2-Strobed bidirectional mode

b) Bit Set/Reset Mode.

19. What is a control word?

Ans:It is a word stored in a register (control register) used to control the
operation of a program digital device.

20. What is the purpose of control word written to control register in 8255?
Ans:The control words written to control register specify an I/O function for
each I.O port. The bit D7 of the control word determines either the I/O function
of the BSR function.

21.What is the size of ports in 8255?

Ans:
• Port-A : 8-bits
• Port-B : 8-bits
• Port-CU : 4-bits
• Port-CL : 4-bits

22. Distinguish between the memories mapped I/O peripheral I/O?

Ans:
Memory Mapped I/O Peripheral MappedI/O

16-bit device address 8-bit device address

Data transfer between Data is transfer only

between
any general-purpose
accumulator and I.O por
 register and I/O port

The memory map (64K) The I/O map is

independent of the
is shared between I/O device memory map; 256 input
and system memory. device and 256 output
device can be connected

More hardware is required to Less hardware is required

decode 16- bit address to decode 8-bit address

Arithmetic or logic operation Arithmetic or logical

can be directly performed operation cannot be
with I/O data directly performed with
I/O data

23.What is memory mapping?

Ans: The assignment of memory addresses to various registers in a
memory chip is called as memory mapping.

24. What is I/O mapping?

Ans:The assignment of addresses to various I/O devices in the memory
chip is called as I/O mapping.

25.What is an USART?
Ans:USART stands for universal synchronous/Asynchronous Receiver/Transmitter. It is
a programmable communication interface that can communicate by using either
synchronous or asynchronous serial data.

26.What is the use of 8251 chip?

8251 chip is mainly used as the asynchronous serial interface between the
processor and the external equipment.

27. What is 8279?

Ans:The 8279 is a programmable Keyboard/Display interface.

28. List the major components of the keyboard/Display interface.

a. Keyboard section
b. Scan section
c. Display section
d. CPU interface section

29. What is Key bouncing?

Ans: Mechanical switches are used as keys in most of the keyboards. When a key is
pressed the contact bounce back and forth and settle down only after a small time delay
 (about 20ms). Even though a key is actuated once, it will appear to have been actuated
several times. This problem is called Key Bouncing.

PART-B

1.. Sketch and explain the interface of PPI 8255 to the 8085 microprocessor .
2.Interface4 7 segment LEDs to display as a BCD counter.
3.Sketch and explain the interface of 8279 to the 8085 microprocessor Interface 8x8 key pad
4 Draw the block diagram of 8255 and explain its working. What is Control Word?
Determine the control word for the following configuration of 8255:- 4 Port A – Output Mode
of port A – Mode 1 Port B – Output Mode of port B – Mode 0 Port C lower (pins PC0 – PC2)
– Output
5.Explain major components of 8259 with the aid of suitable diagram. .
6. Explain the command words/control words of 8251in details.16/10/8 marks
UNIVERSITY QUESTION PAPERS