INDEX

S.NO: TITLE PAGE NO: DATED SIGN.

1 Design and analysis of basic of logic 1-8
gates: AND, OR, NOR, NAND,
NOT, XOR, XNOR.
2 Design and implementation of Half 9 - 11
Adder and Full Adder using CMOS
logic.
3 Design Of 3-8 Decoder using CMOS 12
Technology.
4 Design and implementation of 4:1 13 - 15
Multiplexer.
5 Design and implementation of D Flip 16 - 19
Flop Circuit.
6 Design and simulation the schematic 20 - 21
of the Common Drain Amplifier.
7 Design and simulation the schematic 22
of the Differential Amplifier.
8 Design and simulation the schematic 23
of the Operational Transconductance
Amplifier.
 Experiment-1
Aim: Design and analysis of basic of logic gates: AND, OR, NOR, NAND, NOT, XOR, XNOR.

Software used: Cadence Virtuoso

Design:

1. NOT Gate

Fig. 1.1: NOT Gate Schematic

Fig.1.2: NOT Gate Testbench

1
 Fig.1.3: NOT Gate Simulation Result

2. NAND Gate

Fig.1.4: NAND Gate Schematic

2
 Fig.1.5: NAND Gate Testbench

Fig.1.6: NAND Gate Simulation Result

3
3. NOR Gate

Fig1.7: NOR Gate Schematic

Fig.1.8: NOR Gate Testbench

4
 Fig.1.9: NOR Gate Simulation Result

4. AND Gate

Fig1.10: AND Gate Testbench

Fig.1.11: AND Gate Simulation Result

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5. OR Gate

Fig.1.12: OR Gate Testbench

Fig.1.13: OR Gate Simulation Result

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6. XOR Gate

Fig.1.14: XOR Gate Schematic and Testbench

Fig1.15: XOR Gate Simulation Result

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 7. XNOR

Fig.1.16: XNOR Gate Schematic and Testbench

Fig1.17: XNOR Gate Simulation Result

Result: Design and analysis of basic of logic gates: AND, OR, NOR, NAND, NOT, XOR,
XNOR has been done successfully.

8
 Experiment 2

Aim: Design and implementation of half adder and full adder using CMOS logic.
Software Used: Cadence Virtuoso
Design:

1. Half Adder

Fig.2.1: Half Adder Schematic

Fig.2.2: Half Adder Testbench

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 Fig.2.3: Half Adder Simulation Result

2. Full Adder:

Fig.2.4: Full Adder Schematic

Fig.2.5: Full Adder testbench

10
 Fig.2.6: Full Adder Simulation Result

Result: Design and implementation of half adder and full adder using CMOS logic has
been done successfully.

11
 Experiment 3
Aim: Design of 3-8 Decoder using CMOS technology.

Software Used: Cadence Virtuoso

Design:

Fig.3.1: 3:8 Decoder Schematic

Fig.3.2: 3:8 Decoder Simulation Result

Result: Design of 3-8 Decoder using CMOS technology has been done successfully.

12
 Experiment-4
Aim: Design and implementation of 4:1 Multiplexer.

Software Used: Cadence Virtuoso

Design:

1. 2:1 MUX

Fig.4.1: 2:1 MUX Schematic

Fig.4.2: 2:1 MUX Testbench

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 Fig.4.3: 2:1 MUX Simulation Result

2. 4:1 MUX using 2:1 MUX

Fig.4.4: 4:1 MUX Schematic

14
 Fig.4.5: 4:1 MUX Testbench

Fig.4.6: 4:1 MUX Simulation Result

Result: Design and implementation of 4:1 Multiplexer logic has been done successfully.

Experiment-5
15
Aim: Design and implementation of D Flip Flop circuit.

Software used: Cadence Virtuoso

Design:

1. D Latch

Fig.5.1: Pass Transistor Logic Schematic

Fig.5.2: D-Latch Schematic

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 Fig.5.3: D-Latch Testbench

Fig.5.4: D-Latch Simulation Result

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2. D Flip Flop Using Latch

Fig.5.5: D Flip Flop Schematic

Fig.5.6: D Flip Flop Testbench

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 Fig.5.7: D Flip Flop Simulation Result

Result: Design and implementation of D Flip Flop circuit has been done successfully.

19
 Experiment 6
Aim: Design and simulation the schematic of the Common Drain Amplifier.
Software used: Cadence Virtuoso
Design:

Fig.6.1: Common Drain Amplifier Schematic

Fig.6.2: Common Drain Amplifier Testbench

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 Fig.6.3: Common Drain Amplifier Simulation Result

Result: Design and simulation the schematic of the Common Drain Amplifier has been done
successfully.

21
 Experiment 7

Aim: Design and simulation the schematic of the Differential Amplifier.

Software used: Cadence Virtuoso
Design:

Fig.7.1: Differential Amplifier Schematic

Fig.7.2: Differential Amplifier Simulation Result

Result: Design and simulation the schematic of the Differential Amplifier has been done
successfully.

22
 Experiment 8
Aim: Design and simulation the schematic of the Operational Transconductance Amplifier.
Software used: Cadence Virtuoso
Design:

Fig.8.1: Operational Transconductance Amplifier Circuit Schematic

Fig.8.2: Operational Transconductance Amplifier Simulation Result

Result: Design and simulation the schematic of the Operational Transconductance has been done
successfully.

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