This article has been accepted for inclusion in a future issue of this journal.
Content is final as presented, with the exception of pagination.
IEEE TRANSACTIONS ON ELECTRON DEVICES
A Review of Hot Carrier Degradation in
n-Channel MOSFETs—Part II:
Technology Scaling
Souvik Mahapatra , Fellow, IEEE, and Uma Sharma , Student Member, IEEE
Abstract — Transistor parametric drift due to conduction
mode hot carrier degradation (HCD) is reviewed. The time
kinetics in n-channel MOSFETs and FinFETs is analyzed
for channel length (LCH ) variation from ∼2 μm to ∼20 nm
and oxide thickness (TOX ) scaling from ∼20 to ∼1 nm, for
drain bias (VD ) variation from ∼8 to ∼1 V, and gate bias (VG )
chosen to achieve a maximum HCD for a particular type of
device. The time kinetics shape variation from long-channel
heavily doped abrupt junction devices through moderately
long-channel lightly doped drain (LDD) devices to short-
channel devices featuring moderately doped source–drain
extensions (SDEs) is reviewed. The temperature (T ) depen-
dence of HCD and the comparison of dc and ac HCD stress
kinetics are reviewed in long LCH at high VD and in short
LCH at low VD stress. The observed data are qualitatively
explained.
Index Terms — Defect generation, device scaling, hot car-
riers, parametric drift, T dependence.
I. I NTRODUCTION
T HE drift of transistor parameters, such as threshold
voltage (VT ), linear (IDLIN ) and saturation (IDSAT )
drain current, transconductance (G M ), and subthreshold
slope (S), due to hot carrier degradation (HCD) is an
important reliability issue. The HCD magnitude depends on
stress gate (VG ), drain (VD ), and substrate (VB ) bias, as shown
in part I of this article. HCD peaks at VG ∼ VD /2 but reduces
at VG < VD /2 and VG > VD /2 stress, and higher HCD is
observed at VB < 0 V stress, for long L CH devices having
thick TOX and at high stress VD (see part I of this article
for relevant definitions; L CH : channel length and TOX : oxide
thickness). HCD peaks at VG ≥ VD , while the impact of VB
is reduced due to the reduction in body effect, for short L CH
devices having thin TOX and at low stress VD .
HCD increases at smaller L CH if VD is kept fixed, which
is expected and is reported across wide variation in L CH
covering higher [1]–[4] and lower [5]–[7] stress VD . Reduction
in TOX , however, reduces HCD if VD is kept fixed, which is
Manuscript received April 19, 2020; revised May 4, 2020; accepted
May 6, 2020. The review of this article was arranged by Editor C. Monzio
Compagnoni. (Corresponding author: Souvik Mahapatra.)
The authors are with the Department of Electrical Engineering,
IIT Bombay, Mumbai 400076, India (e-mail: souvik@ee.iitb.ac.in;
sharma.uma2211@gmail.com).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2020.2994301
0018-9383 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
1
reported across a wide range of TOX variation covering higher
[1], [3], [4] and lower [8] stresses VD . The operating voltage
(VDD) reduces with technology scaling and scaling of device
dimensions (L CH and TOX ). The dependence on stress VD can
be obtained from the time-axis scaling shown in Section IV of
part I of this article, and the voltage acceleration factor (VAF)
is ∼25–30 for most devices with single (gradual) and lightly
doped drain (LDD)/source–drain extension (SDE)–based dual
source/drain (S/D) junctions.
HCD time kinetics shows power law with slope n ∼0.5 in
most cases (device type and measurement probe) at VG ∼
VD /2 stress in long L CH devices though there are exceptions
(see Table I of part I of this article and related discussions in
Section IV-B). The slope reduces at VG > VD /2 and VB < 0 V
in most of such devices. Furthermore, the slope is ∼0.5 at
VG ∼ VD /2 and VG = VD in most of the short L CH devices (see
Table II of part I of this article); again there are exceptions.
Such mostly universal features are reported for the scaling of
L CH (∼100X), TOX (∼20X), and stress VD (∼10X).
However, there are notable exceptions for the time kinetics.
The single-junction and SDE dual-junction MOSFETs, FDSOI
MOSFETs, and FinFETs show power-law time kinetics, while
some LDD devices show a nonpower-law self-saturated trend
(refer to Fig. 8 and Tables I and II of part I of this article).
This self-saturated time kinetics is widely reported for worst
case VG ∼ VD /2 stress in LDD devices [9]–[13], also for worst
case low VG stress in drain-extended devices [14], and for high
stress VD , and sensed by charge pumping (CP) and IDLIN .
Moreover, most devices show similar power-law time slope for
various measurement probes (see Tables I and II of part I of
this article). However, this feature is not seen in some LDD
devices under high VD stress [15]–[20]. Such LDD devices
indeed show power-law time kinetics but show lower slope n
for IDLIN compared with VT or G M . The lower than n ∼
0.5 value is also reported in some short L CH devices at low
VD stress for different measurement probes (CP [21], IDLIN
[6], [22], [23], and VT [24], see Table II of part I of this
article). Note that, in modern technology nodes, the low VD
core devices show the correlation of parameters from various
probes, while the high voltage input–output (I/O) devices show
higher n for VT and IDSAT compared with IDLIN [25].
As mentioned in part I of this article, there are other
differences as well. The temperature (T ) activation is
negative (HCD increases at lower T ) in long L CH devices
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE TRANSACTIONS ON ELECTRON DEVICES
for VG ∼ VD /2 worst case stress at high VD [5], [26]–[32],
while it is positive (HCD increases at higher T ) in short L CH
devices at VG = VD worst case condition and low VD [5],
[22], [33], [34]. The difference between stress versus sense T
[31], [35] and the self-heating (SH) effect in modern devices
[36], [37] plays important roles. Furthermore, the long L CH
devices at high VD ac stress show higher HCD compared with
dc (at VG ∼ VD /2 worst case condition) [38]–[42]. However,
the short L CH devices at low VD ac stress show lower HCD
compared with dc (at VG ≥ VD worst case condition) [7],
[22], [34]. It is remarkable that larger drift is obtained for
ring-oscillator (RO) clocking at higher frequency ( f ) for fixed
duration stress, as the number of high/low transitions are large
[34]. However, the opposite can happen when devices suffer
from significant SH effect (since SH reduces at higher f and
HCD has positive T activation in short L CH devices) [37].
The HCD time kinetics at varying VG /VD ratio without and
with reverse VB and a different stress VD is reviewed in part
I of this article. The physical mechanisms likely responsible
for the transition from classical-to-nonclassical VG /VD depen-
dence of HCD and the impact of stress VB are qualitatively
discussed. The worst case stress condition is identified for the
long and short L CH devices, respectively, at higher and lower
stresses VD . The reasons for widely varying time power-law
slope (n ∼ 0.2–0.5) across various reports are not well under-
stood and needs more work. The SH related effects are recently
reviewed [37] and, hence, are not considered in this article.
In this article, Section II discusses the time kinetics of HCD
at worst case dc stress condition in devices having different
S/D junction structures. The nonpower-law time kinetics in
some LDD MOSFETs and a different slope n for different
measurement probes (when obtained from the same device)
in some other LDD MOSFETs are qualitatively explained.
The impact of L CH and TOX scaling for higher and low VD
stresses is discussed in Section III. The T dependence of HCD
and the comparison of ac and dc stress kinetics in long and
short L CH devices are discussed, respectively, in Sections IV
and V. Finally, this article is concluded in Section VI, with
comments on the capabilities of technology CAD (TCAD)
simulation to capture scaling trends.
All data are reported at VG ∼ VD /2 in long L CH devices and
at VG = VD in short L CH devices, as these are the worst case
stress conditions in the respective type of devices. All data are
at room temperature (RT), unless otherwise mentioned.
II. T IME K INETICS U NDER DC S TRESS
In this section, experimental data demonstrating power-law
and nonpower-law time kinetics are shown first, and the impact
of measurement probes on power-law time slope is shown in
the following. The mechanisms responsible for different time
kinetics shapes are analyzed afterward.
A. Power-Law Versus Nonpower Law
As shown in Figs. 4, 6, and 8 and Tables I and II of
part I of this article, the long L CH single-junction MOSFETs
and the short L CH SDE bulk and FDSOI MOSFETs and
FinFETs show power-law time kinetics (although the slope
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
Fig. 1. Measured time kinetics of (a) ΔVT and (b) ΔGM for stress at
VG ∼ VD /2 and a different (high) VD in single-junction MOSFET [1].
varies between reports) under worst case stress condition.
Moreover, the slope n is identical for different measurement
probes from a given report. As an example, Fig. 1 shows the
plots of the measured time kinetics of VT [see Fig. 1(a)]
and G M [see Fig. 1(b)] at VB < 0 V and a different stress
VD in a single-junction MOSFET [1]. HCD increases at high
VD when L CH and TOX are held fixed, with power-law time
slope n that does not vary between different probes and when
VD is varied. Note that identical power-law kinetics and n
are also obtained from CP measurements in this device (not
explicitly shown) [43]. Similar VD dependence is reported
in Fig. 8(a), (c), and (d) of part I of this article in other
MOSFETs [24], [26] and FinFET [33].
However, the shape of HCD kinetics drastically changes for
gradual-junction LDD devices. Fig. 2 shows the plots of the
measured time kinetics of IDLIN [see Fig. 2(a)] and ICP
[see Fig. 2(b)] at a different VD (but VB = 0 V), in LDD
MOSFET [10] having similar L CH and TOX values, as shown
in Fig. 1. Interestingly, the kinetics does not show a simple
power law but a self-saturating trend. The early part time slope,
for a power-law fit over a small but fixed measurement time
range, is n ∼ 0.5 for IDLIN and somewhat higher (∼0.6)
for ICP for the lowest VD data set, but n reduces at high
VD . However, the longer time asymptotic slope is ∼0.25 for
both IDLIN and ICP , across all VD . This behavior is first
reported in [9] and elsewhere (see Fig. 8(b) of part I of this
article) [11]–[13], including in drain extended devices under
low stress VG but varying VD [14]. Note that such a self-
saturation trend is found to be stronger in devices having lower
L CH and thin TOX [9].
Note that the presence (see Fig. 1) or absence (see Fig. 2) of
reverse VB has nothing to do with the time kinetics shape (we
could not find a better example of abrupt and LDD MOSFETs,
with similar L CH /TOX and stress VD /T, with two different
probes). It is noteworthy that the data shown in Fig. 8(a) of part
I of this article are at VB = 0 V stress and also show simple
power-law time kinetics. The reason for the difference in time
kinetics shape between single-junction and LDD devices is
discussed in Section II-C.
B. Impact of Measurement Probe on Power-Law Slope
The slope of power-law time kinetics is generally identical
across measurement probes; however, there are few exceptions.
Fig. 3 shows the plots of the measured time kinetics of G M
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—II
Fig. 2. Measured time kinetics of (a) ΔIDLIN and (b) ΔICP for stress at
VG ∼ VD /2 and a different (high) VD in LDD MOSFET [10]. The shorter
and longer time data can be individually “fit” with different power-law
dependence, shown for the lowest data set.
Fig. 3. Measured time kinetics of (a) ΔGM and ΔIDLIN for different
junction profiles [15] and (b) ΔVT and ΔIDLIN for different spacer types
[17] in LDD MOSFETs under VG ∼ VD /2 and high VD stress.
and IDLIN [see Fig. 3(a)] in LDD devices with different drain
junction types [15] and VT and IDLIN [see Fig. 3(b)] in
LDD devices with different spacer types [17], under VG ∼
VD /2 condition. The slope n of IDLIN is lower than that
of G M for different junction types shown in Fig. 3(a),
and notably, the type showing lower G M shows higher
IDLIN , and vice versa. Moreover, both VT and IDLIN
show similar slope n for the oxide-padded polysilicon spacer
device; however, n is lower for IDLIN than VT for the oxide
spacer in Fig. 3(b). There are other examples (see Table I of
part I of this article).
Note that VT is impacted by charges in the channel, G M
by charges in the channel (via mobility degradation, μEFF ),
and in the LDD and spacer regions (via series resistance
degradation, RS ). Charges in all regions impact IDLIN .
Therefore, the data in Fig. 3 indicate different contributions of
degradation from the channel and the LDD or spacer regions
in these devices. This aspect is discussed in detail in the next
section.
C. Explanation of Time-Kinetics Shape
The drain voltage drops primarily across the channel region
in long L CH single-junction MOSFETs because of high S/D
doping. HCD at worst case VG ∼ VD /2 stress is due to
generated defects in the channel region and near the drain
junction of the device. Hence, simple power-law time kinetics
is obtained. As mentioned in Section IV-B of part I of this
article, the slope n is ∼0.5 in all such devices if measurement
issues are considered. The S/D overlap lengths are large
in these devices, and the drain-side overlap remains mostly
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
3
Fig. 4. Schematic of (a) an LDD MOSFET and (b) time evolution of
defects as per discussions in [12] and [13].
undegraded (barring close to the drain junction). Hence, VT
and G M are due to generated channel charges and show
correlation (see [44] for additional details).
Several reports have attempted to explain the soft-saturated
time kinetics in LDD devices [10]–[13], [18]–[20]. Note that
the drain voltage drops across both the channel and the
drain extension regions in LDD MOSFETs due to the lighter
doping and longer length of the LDD region. This implies
the availability of hot carriers in the channel near the drain
junction (relatively less hot) and in the overlap/LDD region
(relatively hotter). As a result, defect generation starts at the
gate/spacer edge of the overlap/LDD region at a shorter time.
The defect generation rate slows down due to the finite density
of defect precursors and due to the charges in the generated
defects that push the carrier energy maximum away from the
gate/spacer edge toward the channel with the passage of time.
This increases the carrier energy in the channel, and defect
generation gradually moves toward the channel at longer stress
time. This mechanism is proposed using the analysis of CP
and IDLIN measurements in [12] and [13] and is illustrated in
Fig. 4. The CP and IDLIN measurements probe a different trap
generation magnitude and the rate at various spatial locations
of the LDD MOSFET for a given time window, with higher
degradation but slower rate or saturation in the overlap /LDD
and relatively lower degradation but faster rate toward the
channel. Overall, ICP and IDLIN are the sum of different
power-law rates at different spatial locations and can explain
the nonpower-law time kinetics, as shown in Fig. 2.
If the early part is avoided (either due to faster degradation
rate or by choosing the measurement window at a longer time),
the degradation would show power law (the asymptotic longer
time part of Fig. 2) with lower slope n. This is presumably
the case of Fig. 3, which is further discussed in the following.
The charging of the channel and LDD regions would show
up as μEFF and RS . Prestress and poststress transfer ID
versus VG sweeps (ID is the drain current) can be fit by
compact models to find μEFF and RS [18]–[20]. Fig. 5
shows the plots of the time kinetics of extracted μEFF [see
Fig. 5(a)] and RS [see Fig. 5(b)], obtained from measured
time kinetics of IDLIN and G M at VG ∼ VD /2 and different
stresses VD in LDD MOSFET [20]. Note that power-law time
kinetics is obtained, and the % drift in RS is larger than
that of μEFF , while the slope n of RS is smaller (∼0.2)
than that of μEFF (∼0.6), for identical stress condition
and measurement window. This indicates a higher defect
generation magnitude but a lower rate in the overlap/LDD
compared with the channel region, which is expected. It is
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 5. Extracted time kinetics of (a) mobility and (b) series resistance
drift in LDD MOSFET under VG ∼ VD /2 and high VD stress [20].
remarkable that the time slope of μEFF is ∼0.6, which is
due to defect generation in the channel region and is the same
as in the abrupt junction devices (see Fig. 1). The RS slope
is lower as the ∼saturated part is captured. This explains
lower n probed by IDLIN compared with VT and G M
in LDD devices. This is consistent with reported [16] slopes
of VT (∼0.67, due to defects generated in the channel),
G M (∼0.33, due to defects in the channel impacting μEFF
and RS ), and IDLIN (∼0.22, due to defects everywhere),
with lower defect generation rate in the channel and higher
(∼saturation) rate in the overlap/LDD regions. This can also
explain higher slope n for IDSAT than IDLIN in I/O devices
[25] since the impact of charges in the overlap/LDD region
gets screened at higher sense VD . Finally, electron trapping in
devices having a nonoptimized spacer can further impact RS
and, hence, IDLIN [17].
The drain voltage drops partly across the SDE but primarily
across the channel region in short L CH SDE bulk and FDSOI
MOSFETs and FinFETs due to moderately high SDE doping
and shorter SDE length. Therefore, although the overlap/SDE
and channel (near the drain junction) regions are degraded,
the impact of defects on RS is smaller than LDD devices.
Hence, IDLIN is primarily governed by VT and μEFF ,
and identical slopes are obtained across different measurement
probes [25], [45] similar to abrupt junction devices [1].
III. I MPACT OF D IMENSIONAL S CALING
A. High VD Stress
As mentioned in Section I and reviewed in detail in part
I of this article, classical HCD implies the correlation of the
substrate current (ISUB ) and device parametric drift peaks at
VG ∼ VD /2 condition under high VD (>3V) stress in long
L CH devices. Hence, the impact of device dimensional scaling
on HCD is studied at peak ISUB stress conditions in these
devices.
Fig. 6 shows the plots of the measured time kinetics of VT
in abrupt, highly doped junction devices having different L CH
but fixed TOX and stress VD [see Fig. 6(a)] [2], and IDLIN
in different LDD devices having varying L CH and TOX but
fixed stress VD [see Fig. 6(b)] [10], [11], [13]. As discussed
before, single-junction devices show simple power-law time
kinetics; the time slope n does not change with VD [1], and
the same holds for variation in L CH [see Fig. 6(a)]. Table I of
part I of this article lists the time slopes for different long L CH
devices. LDD devices show nonpower-law time kinetics, with
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
Fig. 6. Measured time kinetics of (a) ΔVT for a different LCH in single-
junction MOSFET [2] and (b) ΔIDLIN for a different LCH and TOX in LDD
MOSFETs [10], [11], [13], at high VD stress.
Fig. 7. Measured ISUB and fixed time ΔGM and ΔICP for variation in
(a) LCH (at fixed TOX ) and (b) TOX (at fixed LCH ) in LDD MOSFETs at
high VD stress [4].
reduced time slope at high VD for a given measurement time
window. The soft-saturated time kinetics is reported in devices
from various sources [see Fig. 6(b)]; refer to the original
references for the measured time kinetics at a different VD .
HCD increases with a reduction in L CH at fixed stress VD as
expected [see Fig. 6(a)]. This is also observed in Fig. 6(b);
however, note that the exact comparison is difficult because
TOX is also varied, as data are from different sources.
As described in Section III of part I of this article, HCD at
peak ISUB (VG ∼ VD /2) stress condition is due to acceptor-like
defect generation at (or near) the channel/gate oxide interface;
no net trapping occurs due to coinjection of electrons and
holes. Therefore, scaling of L CH and TOX would impact:
1) carrier heating (as measured by ISUB ) at a given VD ;
2) defect generation due to carrier heating; and 3) impact of
generated defects on device ID –VG characteristics.
Fig. 7 shows the plots of the measured ISUB and fixed time
G M and ICP for variations in L CH (at fixed TOX ) [see
Fig. 7(a)] and TOX (at fixed L CH ) [see Fig. 7(b)] at fixed stress
VD [4]. ISUB increases with a reduction in L CH and TOX . Both
ICP and G M increase at lower L CH , while ICP increases,
but G M does not vary (within measurement error) as TOX
is reduced.
Fig. 8 shows the plots of the measured fixed time NIT [see
Fig. 8(a)] [3] and ICP [see Fig. 8(b)] [4] as a function of
peak ISUB for variations in L CH and TOX . Note that generated
defects can be correlated with peak ISUB (at VG ∼ VD /2 stress)
for a range of device dimensions, and this holds true for both
reports. The increase in ICP observed in Fig. 7 at lower
L CH and TOX can, therefore, be correlated with the increase
in carrier heating (peak ISUB ) in these devices.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—II
Fig. 8. Measured fixed time (a) ΔNIT in single-junction MOSFET [3] and
(b) ΔICP in LDD MOSFET [4] versus ISUB for variations in LCH and TOX ,
at high VD stress. In (b), TOX variation is with fixed LCH (= 0.3 µm), and
LCH variation is with fixed TOX (= 11 nm).
Fig. 9. Measured fixed time ΔGM and ΔICP for variation in (a) LCH (at
fixed TOX ) and (b) TOX (at fixed LCH ) under high VD but iso-ISUB stress
[4]. Data from Fig. 7 are also shown after normalizing to the ratio of ISUB
of a device to ISUB of (a) largest LCH or (b) thickest TOX device: LDD
MOSFETs.
Fig. 9 shows the plots of the measured fixed time G M
for variations in L CH (at fixed TOX ) [see Fig. 9(a)] and TOX
(at fixed L CH ) [see Fig. 9(b)] under fixed ISUB [4]. Note that
ISUB can be kept constant as L CH and TOX are reduced by
suitably reducing the stress VD . Furthermore, data from Fig. 7
(constant VD stress) are replotted by normalizing by the ratio
of ISUB of a given device and ISUB of the device having the
largest dimension (L CH or TOX ). Note that G M increases
at short L CH even if ISUB is kept fixed since the fraction
of the degraded channel is higher at short L CH . However,
an increase in G M is ∼2X at constant ISUB as opposed
to ∼6X at constant VD (see Fig. 7) for extreme L CH values
(scaling by ∼3X) due to the impact of both higher ISUB and
larger fraction of the degraded channel under constant VD
stress. However, when normalized to ISUB , G M shows ∼2X
increase even for constant VD stress.
However, G M reduces as TOX is scaled, ∼2.5X between
the extreme TOX values (scaling by ∼2.5X) for both constant
ISUB and constant VD (when normalized by ISUB ) stress,
showing a 1:1 dependence. The same is also shown elsewhere
[3], where IDLIN /ISUB is reported to reduce with TOX . This is
attributed to a reduction in the impact of defects on the ID –VG
characteristics (VT shift and μEFF reduction) at lower TOX .
Although TOX scaling helps, drain junction engineering has
been used to keep HCD under control when L CH is scaled,
but VDD is not identically reduced (e.g., the introduction of
LDD S/D junctions) [15], [46]. Other processes, such as gate
oxide growth temperature [47], nitrogen [48] and/or fluorine
[49] incorporation in the gate oxide, and replacing hydrogen
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
5
Fig. 10. Measured time kinetics of ΔIDSAT at a different LCH at
(a) VG ∼ 0.6∗VD stress with fixed VD at different LCH [7] and (b) VG = VD
stress but with VD suitably reduced at lower LCH [5]: SDE MOSFETs.
postmetallization anneal (PMA) by deuterium [50], impact
HCD reliability. Biaxial mechanical strain also helps improve
HCD [51] although this is not a standard process. HCD
is expected to reduce with technology scaling due to the
reduction in VDD , which, however, is not the case (refer to
Section IV-B of part I of this article for related discussion).
B. Low VD Stress
As shown in Section III of part I of this article, the condition
for peak HCD gradually shifts from VG ∼ VD /2 to VG = VD
as L CH is scaled, and the exact VG /VD ratio of maximum HCD
depends on L CH and TOX for low VD (<3 V) stress.
Fig. 10 shows the plots of the time kinetics of the measured
IDSAT as L CH is varied, under VG ∼ 0.6∗VD stress with fixed
VD in devices having fixed TOX [see Fig. 10(a)] [7] and VG =
VD stress at suitably varying VD in devices having varying
TOX [see Fig. 10(b)] [5], all are SDE MOSFETs. Note that
the VG /VD ratio is suitably chosen for maximum HCD in the
device of interest. The time kinetics shows power law, and
the time slope n remains the same across L CH when VD is
kept fixed but reduces at lower L CH as stress VD is reduced
at smaller L CH . Table II of part I of this article lists the time
slopes in various short L CH devices. HCD increases at lower
L CH when stress VD is kept constant [see Fig. 10(a)] or when
stress VD is reduced at lower L CH [see Fig. 10(b)]. However,
as the TOX and VD are also reduced with L CH in Fig. 10(b),
the increase in IDLIN is lower than that would have been if
TOX and VD were held fixed [as in Fig. 10(a)]. It is observed in
FDSOI MOSFETs that IDLIN increases as L CH is reduced,
while it reduces as TOX is reduced under fixed VG and VD
across device dimensions (refer to Fig. 5 of part I of this article
[6], [8]). However, the peak IDLIN (note that the peak shifts
to higher VG values at lower L CH and thicker TOX ) increases
at lower L CH (discussed in the following) but remains similar
across TOX when normalized to TOX variation (3.4–4.5 nm).
It is notable that the ISUB values are not available for data
shown in Fig. 10, and ISUB cannot be measured in FDSOI
MOSFETs. Thus, an analysis similar to the previous section
is not possible.
Fig. 11 shows the plots of the fixed time IDLIN [see
Fig. 11(a)] [6], [8] and IDSAT [see Fig. 11(b)] [5], [7] versus
L CH in FDSOI [see Fig. 11(a)] and SDE MOSFETs [see
Fig. 11(b)]. It is important to note that the original data are
at the same TOX and VD for IDLIN (for a particular data
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
6 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 11. Estimated (see text for explanation) fixed time (a) ΔIDLIN in
FDSOI MOSFETs [6], [8] and (b) ΔIDSAT in SDE MOSFETs having a
different LCH . The time is 1 ks in (b), taken from Fig. 10, and not available
for (a). Due to different sense conditions, the relative magnitude should
not be compared across data sets.
Fig. 12. Measured time kinetics of (a) ΔVT [26] and (b) ΔGM [28] at
various T under VG ∼ VD /2 stress at high VD in long LCH single-junction
MOSFETs.
set) but are at a different TOX and VD for IDSAT (even for a
particular data set). Therefore, data from original reports are
scaled to VD = 1 V (time-scaled using VAF = 25 as shown
in Section IV-A of part I of this article) and normalized by
TOX to make “fair” comparison (within the uncertainties of
such extrapolations). HCD increases exponentially at reduced
L CH for a particular data set. A higher rate is obtained for
IDSAT compared with IDLIN . The rate would depend on
the damage region (∼potential drop) near the drain junction
of the device. It would also depend on the pre- and post-ID
sense conditions. Therefore, it is not possible to conclusively
comment on the differences in the L CH -dependent rate across
different data sets shown in Fig. 11.
Moreover, to the best of our knowledge, a detailed study of
device scaling is not yet available for FinFETs. It is important
to note that care should be given regarding SH effect related
HCD increase as dimensions are scaled in FDSOI MOSFETs
and FinFETs [36], [37].
IV. T EMPERATURE D EPENDENCE
A. Classical Behavior (Long LCH and High VD )
Fig. 12 shows the plots of the time kinetics of measured
VT [see Fig. 12(a)] [26] and G M [see Fig. 12(b)] [28]
at a different T, for peak ISUB (VG ∼ VD /2) stress of
maximum HCD in long L CH devices under high stress VD .
It is remarkable that HCD increases at lower T, but the time
slope n remains unchanged. This negative T activation is seen
over a wide T range, covering above and below RT, and is
defined as classical T dependence.
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
Fig. 13. Measured (a) ΔICP and (b) ΔVT time kinetics at a different
T. Lifetime based on extrapolated (c) ΔICP and (d) ΔVT for a different
stress and sense T. Data from single-junction MOSFETs [31].
As explained in part I of this article, Section III, HCD at
VG ∼ VD /2 stress condition is primarily due to generated
defects, and the impact of T can be explained as follows.
1) Carrier heating increases at lower T due to reduced
phonon scattering, as evident from higher ISUB at lower T
[29], [31].
2) Defect generation reduces at lower T since any bond
dissociation is a thermally activated process.
3) Impact of locally generated defects near the drain junc-
tion of the device on the potential barrier, which is higher at
lower T [27].
Fig. 13 shows the plots of the time kinetics of measured
ICP [see Fig. 13(a)] and VT [see Fig. 13(b)] at VG ∼
VD /2 stress for T range of 77 K–295 K [31]. Note that the
increase in VT is much larger than ICP at lower T although
the slope n remains unchanged. Fig. 13 also shows the plots of
the measured lifetime (time to reach a particular degradation
level, obtained by using temporal extrapolation of measured
data) as a function of ISUB /IS (IS is the source current) for
ICP [see Fig. 13(c)] and VT [see Fig. 13(d)] when stress
and measurement T are both high (HH) and low (LL) [31].
In Fig. 13(c), the condition when stress T is low but the
measurement T is high (LH) is shown, while in Fig. 13(d),
both LH and HL (stress high T but measurement low T ) are
shown. The lifetime is multiplied by IS for a fair comparison.
Note that higher ICP lifetime versus ISUB /IS slope at
higher ISUB /IS (it is obtained by reducing VG at a fixed VD )
suggests the more efficient generation of defects under hot hole
injection [see Fig. 13(c)]. This is consistent with the results
shown in Section III of part I of this article. For a fixed
ISUB /IS , the lifetime is higher (and ICP is lower) for LH
compared with the LL case, and this is a measurement issue
due to the T dependence of CP current [31]. For identical
sense T, however, the lifetime is indeed lower for HH than
LH at iso ISUB /IS and is due to positive T activation of the
defect generation (bond dissociation) process.
For VT [see Fig. 13(d)], the lifetime is similar between LL
and HL and also between LH and HH, implying similar VT
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—II
Fig. 14. Measured time kinetics of (a) ΔIDSAT at VG > VD in SDE
MOSFET [22] and (b) ΔVT at VG = VD in FinFET [33] for low VD stress
at a different T.
(due to generated defects) at low and high stresses T when
stressed at fixed ISUB /IS . The lifetime is lower (VT is higher)
for LL and HL compared with the LH and HH cases due to
the higher impact of locally generated defects on the potential
barrier at lower T, which is first reported in [27]. Hence,
the carrier heating and impact of localized defects on the
potential barrier (both are higher at lower T ) overcompensates
for the positive T activation of defect generation, and hence,
the overall HCD has negative T activation in these devices
(long L CH and stressed under high VD stress).
B. Nonclassical Behavior
Fig. 14 shows the plots of the time kinetics of measured
IDSAT at VG > VD [see Fig. 14(a)] [22] and VT at
VG = VD [see Fig. 14(b)] [33] at a different T, in short
L CH devices for low VD stress. Note that the power-law
time slope n is ∼0.25 in Fig. 14(a) and ∼0.5 in Fig. 14(b);
however, they do not vary with T for a particular device. The
T activation is positive (higher HCD at higher T ) in these
experiments, which is identified as the nonclassical effect.
However, it is important to ascertain that the contribution
from positive bias temperature instability (PBTI) [51]–[54] is
not significant in these devices. Note that the T activation
energy (EA ) is higher, while the power-law time slope n is
lower for PBTI [51], [54], compared with HCD in short L CH
devices [22], [33]. Hence, if present, the ratio of PBTI/HCD
would become higher, and the overall slope n would reduce
at higher T, which is not seen in Fig. 14 but is indeed
shown in [36]. The PBTI absence is easier to ascertain in
Fig. 14(b), as the slope (∼0.5) is much larger than the PBTI
slope (∼0.17), and the devices have replacement metal gate
(RMG)-based high-K metal gate (HKMG) process that shows
negligible PBTI [53]. The slope is lower (∼0.25) in Fig. 14(a),
making it hard to fully ascertain if PBTI is present (or not).
Note that the gate-first (GF) HKMG process is used in the
devices shown in Fig. 14(a), which has nonnegligible PBTI
[22], [51], [54]. The importance of PBTI is discussed in
Section IV-D of part I of this article although it is notable
that its impact would reduce at VD > 0 V stress.
Note that the T activation of ISUB is positive in such
devices [5]. This is presumably due to: 1) higher IS due to
a large reduction in prestress VT and 2) lower impact of
phonon-scattering in these short-channel devices, at higher
T. Hence, the positive T dependence of ISUB and defect
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
7
Fig. 15. Lifetime estimated from measured HCD kinetics versus ID
(varying VG but fixed VD ) at a different T for (a) long LCH devices at
moderate stress VD and (b) short LCH devices at low stress VD ; all are
SDE MOSFETs [5].
generation (always positively activated) can overcompensate
for the impact of locally generated defects on the potential
barrier (always larger at lower T and is negative T activated),
and so the overall T activation of HCD becomes positive in
these devices. Remarkably, the positive T activation of ISUB in
smaller L CH devices [5] is contrary to the negative T activation
of ISUB in long L CH devices shown in [29] and [31], where
phonon scattering impact would dominate over the reduction
in VT at higher T.
Fig. 15 shows the plots of the measured lifetime versus ID
during stress (ID is varied by varying VG , but VD is kept fixed)
in relatively long [see Fig. 15(a)] and short[see Fig. 15(b)]
L CH devices at a different T [5]. In long L CH devices stressed
at moderate VD , lower lifetime (or higher HCD) is seen
at lower T up to a particular VG (or ID ) value; however,
the situation flips for higher VG (or ID ) stress, and lower
lifetime (or higher HCD) is seen at higher T [see Fig. 15(a)].
This holds for a different L CH studied in this case. Hence,
the classical-to-nonclassical transition is observed in this case
as VG (or ID ) crosses a particular threshold. We speculate
that the T activation of defect generation can be higher at
higher VG since the AHI-initiated process gets triggered (see
Section V of part I of this article), which can explain the
observed flipping of the T dependence of lifetime. Moreover,
note that a broader defect distribution profile (at higher stress
VG , due to gate-assisted AHI) would certainly reduce the
“higher impact of localized defects at lower T ” and can also
explain the results. However, lower lifetime is seen at higher
T for all VG (or ID ) values in short L CH devices under low
stress VD [see Fig. 15(b)] and nonclassical HCD is observed,
which is consistent with the results reported in Fig. 14.
Since the impact of localized defects on I –V has negative
T dependence (more impact at lower T ), E A of HCD would
depend on whether sense T is kept fixed and stress T is
only varied, or whether both stress and sense T are varied
(and they are same); refer to [35] for further details. This
is consistent with the observations of Fig. 13(b) [31]. This
is of importance in FDSOI and FinFETs suffering from SH
effects [36], [37].
V. T IME K INETICS D URING AC S TRESS
Early reports show very high HCD for ac compared with
dc stress, with significant variation with the rise/fall times of
the ac gate pulse [38], [39], which was later identified as
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 16. Measured time kinetics of ΔIDLIN during (a) inverter-like ac
and dc stress at VG ∼ VD /2 and (b) alternating dc stress between low
and high VG and dc stresses at VG ∼ VD /2 and VG = VD , under high
stress VD [41].
Fig. 17. Measured time kinetics of (a) and (b) ΔIDSAT in planar
MOSFETs having a different LCH [7], and (c) ΔVT [33] and (d) ΔIDSAT
[34] in FinFETs for dc and ac stresses under low stress VD .
artifacts due to the inductive ringing effects [40]. However,
even after taking care of inductive ringing and verifying no
rise/fall time dependence, ac stress still results in higher HCD
compared with dc stress at peak-ISUB condition, for high VD
stress [40]–[42].
Fig. 16(a) shows the plots of the time kinetics of measured
IDLIN during dc stress at VG ∼ VD /2 condition at two values
of VD and for inverter-like ac stress with alternating gate and
drain pulses with maximum VG /VD equal to the low VD value
used for dc stress [41]. IDLIN for ac is lower than that of
dc at a short time, but ac HCD has higher rate, and hence,
it surpasses the dc HCD at a longer time compared at the same
VD and tends to move closer to dc HCD at high VD . Fig. 16(b)
shows the plots of the time kinetics of the measured IDLIN
during dc stress at VG ∼ VD /2 and for dc stress alternating
between VG < VD /2 and VG = VD conditions, for same VD in
both cases [41]. IDLIN at VG ∼ VD /2 is highest for pure dc
stress as expected. However, the dc stress alternating between
low and high VG conditions shows higher IDLIN than that at
VG ∼ VD /2 pure dc stress.
As discussed in Section III in part I of this article, the ICP
versus VG plot is broader with peak located at somewhat lower
VG than the VG ∼ VD /2 condition corresponding to peak ISUB
although the G M peak coincides with that of peak ISUB due
to hole trapping at VG < VD /2. The generated neutral electron
traps in the oxide at VG < VD /2 also remain invisible due
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
to hole trapping. Note that ac stress alternating between low
and high VG shows negligible net trapping, as both holes and
electrons are injected at low and high VG , respectively, and
the generated neutral electrons traps get exposed [40], [55].
Moreover, defect generation due to the trapped hole/injected
electron recombination happens under alternating stress. These
are believed to be the reasons behind higher ac HCD than the
maximum HCD under dc stress at VG ∼ VD /2 condition.
As mentioned earlier, the injection of holes or electrons
into the gate oxide is negligible under low VD (<3 V) stress.
Fig. 17 shows the plots of the time kinetics of HCD under dc
and ac stress at low stress VD , measured in relatively long [see
Fig. 17(a)] and short [see Fig. 17(b)] L CH planar MOSFETs
by IDSAT [7] and in short L CH FinFETs by VT [see
Fig. 17(c)] [33] and IDSAT [see Fig. 17(d)] [34]. The peak
HCD condition is at VG ∼ 0.6∗VD in Fig. 17(a) and at VG =
VD in Fig. 17(b)–(d) under dc stress. Note that the time kinet-
ics shape shows power law with n ∼ 0.5 in Fig. 17(a) and (c),
n ∼ 0.4 in Fig. 17(b), and n ∼ 0.45 with soft saturation in
Fig. 17(d), but it is similar between dc and ac stress. The ac
HCD is lower than dc stress (at peak HCD condition), which
is as expected. The difference between Figs. 16 and 17 is the
presence or absence of hot carrier injection-related effects,
respectively, at high and low stresses VD .
VI. C ONCLUSION
The following conclusions can be drawn regarding the HCD
physical mechanism changes as the technology scales and the
suitability of TCAD to address the same.
Scaling involves the reduction in L CH , TOX , VDD , and
changes in drain junction structure. These, in turn, impact
carrier heating, generation of defects (the primary mechanism
at worst case), and the impact of generated defects on ID . The
carrier heating increases when L CH and/or TOX are reduced at
constant stress VD . It also depends on the potential drop in the
pinch-off and near-drain regions and junction doping profile.
Higher carrier heating results in higher generated defects. For
a given density of generated defects, HCD parametric drift
is higher in smaller L CH devices as a larger fraction of the
channel gets degraded, and it reduces when TOX is reduced as
the impact of defects on VT and μEFF also reduces. TCAD
is capable of simulating the impact of geometry and bias
changes on carrier heating. It can also calculate the impact of
charges, generated in various physical locations of the device,
on the parametric drift. However, the physical mechanisms of
defect generation time kinetics are yet to be implemented and
validated, as discussed in detail in part I of this article.
The HCD time kinetics shape depends on the drain junc-
tion structure and whether the overlap/junction region is
affected (and plays an important role) or not. The region
is not affected for long L CH single-junction devices, and
although affected, it does not have a significant effect on short
L CH SDE devices. HCD shows power-law time kinetics, and
different parameters stay correlated. The region is affected
and impacts parametric drift in long L CH LDD devices. HCD
shows nonpower-law time kinetics, and different parameters
are not correlated. The impact of structure on the carrier
heating location can be properly simulated using TCAD.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—II
Self-consistent solutions are needed, as charges in the gen-
erated defects impact the subsequent carrier heating process.
This would affect simulation run time, more so for FinFETs
and other 3-D cases.
The T dependencies of hot carrier density, defect generation,
and impact of generated defects determine the T activation of
HCD. Defect generation has positive T activation (increases at
higher T ), but the impact of generate defects on I –V increases
at lower T (negative T activation), and so these sort of balance
each other over T. However, the hot carrier density reduces at
higher T in long L CH but increases at higher T in short L CH
devices. Hence, HCD has negative and positive T activations,
respectively, in long and short L CH devices. Carrier heating
and impact of localized charges on ID can be simulated using
TCAD in its present form at various T.
The ac stress shows higher HCD than the peak dc stress
due to additional defect generation by hot hole and electron
injection effects in long L CH devices for high VD stress.
Injection- and trapping-related effects are not seen in short
L CH devices due to low VD and thin TOX , and ac stress shows
lower HCD than dc stress. The high-VD injection effects are
not available in TCAD at this moment and are needed for the
simulation of long L CH , high VD noncore devices.
Conventional theory suggests the reduction in HCD as VDD
is scaled with technology scaling, down to ∼1 V for sub-20-
nm nodes. However, HCD is still present in scaled FinFETs
and is presumably due to vertical field-induced enhancements
and also SH effects. Careful adjustment of the drain doping
profile to optimize the potential drop in the pinch-off region
and the reduction of SH effects by optimal layouts are needed
to keep HCD under control. The gate oxide thermal budget and
its link to the density and bond strength of defect precursors
also need to be understood and optimized. Finally, since
HCD in digital logic circuits depends on activity (∼clock),
the f dependence of SH and HCD needs to be properly
estimated.
Finally, it is important to remark that the process variability
and stochastic defect generation would become important as
the device dimensions continue to scale. These aspects are not
reviewed in this article.
R EFERENCES
[1] E. Takeda and N. Suzuki, “An empirical model for device degradation
due to hot-carrier injection,” IEEE Electron Device Lett., vol. EDL-4,
no. 4, pp. 111–113, Apr. 1983, doi: 10.1109/EDL.1983.25667.
[2] K.-L. Chen, S. A. Saller, I. A. Groves, and D. B. Scott, “Reliability
effects on MOS transistors due to hot-carrier injection,” IEEE Trans.
Electron Devices, vol. EDL-32, no. 2, pp. 386–393, Feb. 1985, doi:
10.1109/T-ED.1985.21953.
[3] Y. Toyoshima, H. Iwai, F. Matsuoka, H. Hayashida, K. Maeguchi,
and K. Kanzaki, “Analysis on gate-oxide thickness dependence of
hot-carrier-induced degradation in thin-gate oxide nMOSFET’s,” IEEE
Trans. Electron Devices, vol. 37, no. 6, pp. 1496–1503, Jun. 1990, doi:
10.1109/16.106245.
[4] S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan, and
J. Vasi, “Device scaling effects on hot-carrier induced interface and
oxide-trapped charge distributions in MOSFETs,” IEEE Trans. Electron
Devices, vol. 47, no. 4, pp. 789–796, Apr. 2000, doi: 10.1109/16.830995.
[5] A. Bravaix, C. Guerin, V. Huard, D. Roy, J. M. Roux, and E. Vincent,
“Hot-carrier acceleration factors for low power management in DC-
AC stressed 40 nm NMOS node at high temperature,” in Proc. IEEE
Int. Rel. Phys. Symp, Apr. 2009, pp. 531–548, doi: 10.1109/IRPS.2009.
5173308.
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
9
[6] W. Arfaoui et al., “Energy-driven hot-carrier model in advanced nodes,”
in Proc. IEEE Int. Rel. Phys. Symp., Jun. 2014, pp. XT.12.1–XT.12.5,
doi: 10.1109/IRPS.2014.6861189.
[7] C. Schlunder et al., “Circuit relevant HCS lifetime assessments
at single transistors with emulated variable loads,” in Proc. IEEE
Int. Rel. Phys. Symp. (IRPS), Apr. 2017, pp. 2D-2.1-2D-2.7, doi:
10.1109/IRPS.2017.7936262.
[8] W. Arfaoui, X. Federspiel, A. Bravaix, P. Mora, A. Cros, and D. Roy,
“Application of compact HCI model to prediction of process effect in
28FDSOI technology,” in Proc. IEEE Int. Integr. Rel. Workshop Final
Rep. (IIRW), South Lake Tahoe, CA, USA, Oct. 2014, pp. 69–72, doi:
10.1109/IIRW.2014.7049513.
[9] K. M. Cham, J. Hui, P. V. Voorde, and H. S. Fu, “Self-limiting
behavior of hot carrier degradation and its implication on the validity
of lifetime extraction by accelerated stress,” in Proc. 25th Int. Rel.
Phys. Symp., San Diego, CA, USA, Apr. 1987, pp. 191–194, doi:
10.1109/IRPS.1987.362177.
[10] V.-H. Chan and J. E. Chung, “Two-stage hot-carrier degradation and its
impact on submicrometer LDD NMOSFET lifetime prediction,” IEEE
Trans. Electron Devices, vol. 42, no. 5, pp. 957–962, May 1995, doi:
10.1109/16.381994.
[11] J.-S. Goo, Y.-G. Kim, H. L’Yee, H.-Y. Kwon, and H. Shin, “An analytical
model for hot-carrier-induced degradation of deep-submicron n-channel
LDD MOSFETs,” Solid-State Electron., vol. 38, no. 6, pp. 1191–1196,
1995, doi: 10.1016/0038-1101(94)00221-Z.
[12] A. Raychaudhuri, M. J. Deen, W. S. Kwan, and M. I. H. King,
“Features and mechanisms of the saturating hot-carrier degradation
in LDD NMOSFETs,” IEEE Trans. Electron Devices, vol. 43, no. 7,
pp. 1114–1122, Jul. 1996, doi: 10.1109/16.502423.
[13] D. Ang and C. Ling, “On the time-dependent degradation of LDD n-
MOSFETs under hot-carrier stress,” Microelectron. Rel., vol. 39, no. 9,
pp. 1311–1322, 1999, doi: 10.1016/S0026-2714(99)00053-0.
[14] D. Varghese, P. Moens, and M. A. Alam, “On-state hot carrier
degradation in drain-extended NMOS transistors,” IEEE Trans. Elec-
tron Devices, vol. 57, no. 10, pp. 2704–2710, Oct. 2010, doi:
10.1109/TED.2010.2059632.
[15] C. Min-Liang, L. Chung-Wai, W. T. Cochran, W. Jungling, C. Dziuba,
and Y. Tungsheng, “Suppression of hot-carrier effects in submicrometer
CMOS technology,” IEEE Trans. Electron Devices, vol. ED-35, no. 12,
pp. 2210–2220, Dec. 1988, doi: 10.1109/16.8795.
[16] S. Aur, “Kinetics of hot carrier effects for circuit simulation,” in Proc.
27th Annu. Int. Rel. Phys. Symp., Phoenix, AZ, USA, 1989, pp. 88–91,
doi: 10.1109/RELPHY.1989.36323.
[17] I.-C. Chen, C. C. Wei, and C. W. Teng, “Simple gate-to-drain overlapped
MOSFETs using poly spacers for high immunity to channel hot-electron
degradation,” IEEE Electron Device Lett., vol. 11, no. 2, pp. 78–81,
Feb. 1990, doi: 10.1109/55.46934.
[18] Y. Pan, K. K. Ng, and C. C. Wei, “Hot-carrier induced electron
mobility and series resistance degradation in LDD NMOSFET’s,” IEEE
Electron Device Lett., vol. 15, no. 12, pp. 499–501, Dec. 1994, doi:
10.1109/55.338416.
[19] C.-L. Lou, W.-K. Chim, D. S.-H. Chan, and T. Pan, “A novel
single-device DC method for extraction of the effective mobility
and source-drain resistances of fresh and hot-carrier degraded drain-
engineered MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, no. 6,
pp. 1317–1323, Jun. 1998, doi: 10.1109/16.678559.
[20] G. G. Oh, W. K. Chim, D. S. H. Chan, and C. L. Lou, “Series resistance
and effective channel mobility degradation in LDD nMOSFETs under
hot-carrier stressing,” in Proc. 7th Int. Symp. Phys. Failure Anal. Integr.
Circuits, Singapore, 1999, pp. 99–103, doi: 10.1109/IPFA.1999.791314.
[21] L. Brunet et al., “Impact of backside interface on hot carriers degra-
dation of thin film FDSOI nmosfets,” in Proc. IEEE Int. Rel. Phys.
Symp. (IRPS), Anaheim, CA, USA, Apr. 2012, pp. 3B.2.1–3B.2.5, doi:
10.1109/IRPS.2012.6241806.
[22] A. Bravaix et al., “Impact of the gate-stack change from 40 nm node
SiON to 28 nm High-K metal gate on the hot-carrier and bias tempera-
ture damage,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Anaheim, CA,
USA, Apr. 2013, pp. 2D.6.1–2D.6.9, doi: 10.1109/IRPS.2013.6531961.
[23] M. Bina et al., “Predictive hot-carrier modeling of n-channel MOS-
FETs,” IEEE Trans. Electron Devices, vol. 61, no. 9, pp. 3103–3110,
Sep. 2014, doi: 10.1109/TED.2014.2340575.
[24] M. Duan et al., “Interaction between hot carrier aging and PBTI
degradation in nMOSFETs: Characterization, modelling and lifetime
prediction,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Monterey, CA,
USA, Apr. 2017, pp. XT-5.1-XT-5.7, doi: 10.1109/IRPS.2017.7936419.
[25] C. Edoardo, private communication, Analog Devices.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10
[26] F.-C. Hsu and K.-Y. Chiu, “Temperature dependence of hot-
electron-induced degradation in MOSFET’s,” IEEE Electron
Device Lett., vol. EDl-5, no. 5, pp. 148–150, May 1984, doi:
10.1109/EDL.1984.25865.
[27] J. Y. C. Sun and M. R. Wordeman, “Degradation of 77-K MOSFET
characteristics due to channel hot electrons,” IEEE Trans. Electron
Devices, vol. ED-31, no. 12, p. 1970, Dec. 1984, doi: 10.1109/T-
ED.1984.21849.
[28] J. J. Tzou, C. C. Yao, R. Cheung, and H. Chan, “Hot-electron-
induced MOSFET degradation at low temperatures,” IEEE Elec-
tron Device Lett., vol. EDL-6, no. 9, pp. 450–452, Sep. 1985, doi:
10.1109/EDL.1985.26189.
[29] T.-C. Ong, P. K. Ko, and C. Hu, “50-Å gate-oxide MOSFET’s at 77 k,”
IEEE Trans. Electron Devices, vol. ED-34, no. 10, pp. 2129–2135,
Oct. 1987, doi: 10.1109/T-ED.1987.23207.
[30] T.-C. Ong, M. Levi, P.-K. Ko, and C. Hu, “Recovery of threshold voltage
after hot-carrier stressing,” IEEE Trans. Electron Devices, vol. ED-35,
no. 7, pp. 978–984, Jul. 1988, doi: 10.1109/16.3354.
[31] P. Heremans, G. Van den Bosch, R. Bellens, G. Groeseneken, and
H. E. Maes, “Temperature dependence of the channel hot-carrier degra-
dation of n-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 37,
no. 4, pp. 980–993, Apr. 1990, doi: 10.1109/16.52433.
[32] M. Song, K. P. MacWilliams, and J. C. S. Woo, “Comparison of NMOS
and PMOS hot carrier effects from 300 to 77 K,” IEEE Trans. Electron
Devices, vol. 44, no. 2, pp. 268–276, Feb. 1997, doi: 10.1109/16.557714.
[33] Y. Qu et al., “Ultra-fast (<1 ns) electrical characterization of self-
heating effect and its impact on hot carrier injection in 14 nm
FinFETs,” in IEDM Tech. Dig., Dec. 2017, pp. 39.2.1–39.2.4, doi:
10.1109/IEDM.2017.8268520.
[34] A. Kerber, S. Cimino, F. Guarin, and T. Nigam, “Assessing device
reliability margin in scaled CMOS technologies using ring oscillator cir-
cuits,” in Proc. IEEE Electron Devices Technol. Manuf. Conf. (EDTM),
Feb. 2017, pp. 28–30, doi: 10.1109/EDTM.2017.7947495.
[35] X. Federspiel, G. Torrente, W. Arfaoui, F. Cacho, and V. Huard, “Tem-
perature sense effect in HCI self-heating de convolution: Application to
28 nm FDSOI,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Apr. 2016,
pp. XT-09-1-XT-09-4, doi: 10.1109/IRPS.2016.7574651.
[36] H. Jiang, X. Liu, N. Xu, Y. He, G. Du, and X. Zhang, “Investigation
of self-heating effect on hot carrier degradation in multiple-fin SOI
FinFETs,” IEEE Electron Device Lett., vol. 36, no. 12, pp. 1258–1260,
Dec. 2015, doi: 10.1109/LED.2015.2487045.
[37] M. A. Alam, B. K. Mahajan, Y.-P. Chen, W. Ahn, H. Jiang, and
S. H. Shin, “A device-to-system perspective regarding self-heating
enhanced hot carrier degradation in modern field-effect transistors:
A topical review,” IEEE Trans. Electron Devices, vol. 66, no. 11,
pp. 4556–4565, Nov. 2019.
[38] W. Weber, C. Werner, and G. Dorda, “Degradation of n-MOS-transistors
after pulsed stress,” IEEE Electron Device Lett., vol. EDL-5, no. 12,
pp. 518–520, Dec. 1984, doi: 10.1109/EDL.1984.26010.
[39] J. Y. Choi, P. K. Ko, and C. Hu, “Hot-carrier-induced MOSFET
degradation: AC versus DC stressing,” in Symp. VLSI Technol. Dig. Tech.
Papers, Karuizawa, Japan, 1987, pp. 45–46.
[40] K. Mistry and B. Doyle, “The role of electron trap creation in enhanced
hot-carrier degradation during AC stress (n-channel MOSFET),” IEEE
Electron Device Lett., vol. 11, no. 6, pp. 267–269, Jun. 1990, doi:
10.1109/55.55276.
[41] M. Brox and W. Weber, “Dynamic degradation in MOS-
FET’s. I. The physical effects,” IEEE Trans. Electron Devices, vol. 38,
no. 8, pp. 1852–1858, Aug. 1991, doi: 10.1109/16.119025.
Authorized licensed use limited to: Auckland University of Technology. Downloaded on June 03,2020 at 13:28:43 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON ELECTRON DEVICES
[42] K. R. Mistry and B. Doyle, “AC versus DC hot-carrier degradation in
n-channel MOSFETs,” IEEE Trans. Electron Devices, vol. 40, no. 1,
pp. 96–104, Jan. 1993, doi: 10.1109/16.249430.
[43] E. Takeda, A. Shimizu, and T. Hagiwara, “Role of hot-hole
injection in hot-carrier effects and the small degraded channel
region in MOSFET’s,” IEEE Electron Device Lett., vol. EDL-
4, no. 9, pp. 329–331, Sep. 1983, doi: 10.1109/EDL.1983.
25751.
[44] C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill,
“Hot-electron-induced MOSFET degradation–model, monitor, and
improvement,” IEEE J. Solid-State Circuits, vol. 20, no. 1, pp. 295–305,
Feb. 1985, doi: 10.1109/JSSC.1985.1052306.
[45] D. Varghese, M. A. Alam, and B. Weir, “A generalized, IB-independent,
physical HCI lifetime projection methodology based on universality
of hot-carrier degradation,” in Proc. Int. Rel. Phys. Symp., 2010,
pp. 1091–1094, doi: 10.1109/IRPS.2010.5488666.
[46] J. J. Sanchez, K. K. Hsueh, and T. A. DeMassa, “Drain-engineered
hot-electron-resistant device structures: A review,” IEEE Trans. Elec-
tron Devices, vol. 36, no. 6, pp. 1125–1132, Jun. 1989, doi:
10.1109/16.24357.
[47] A. Joshi and D.-L. Kwong, “Study of the growth temperature depen-
dence of performance and reliability of thin MOS gate oxides,” IEEE
Trans. Electron Devices, vol. 39, no. 9, pp. 2099–2107, Sep. 1992, doi:
10.1109/16.155883.
[48] B. S. Doyle and A. Philipossian, “P-channel hot-carrier optimiza-
tion of RNO gate dielectrics through the reoxidation step,” IEEE
Electron Device Lett., vol. 14, no. 4, pp. 161–163, Apr. 1993, doi:
10.1109/55.215164.
[49] N. Kasai, P. J. Wright, and K. C. Saraswat, “Hot-carrier-degradation
characteristics for fluorine-incorporated nMOSFET’s,” IEEE Trans.
Electron Devices, vol. 37, no. 6, pp. 1426–1431, Jun. 1990, doi: 10.1109/
16.106236.
[50] K. Hess, I. C. Kizilyalli, and J. W. Lyding, “Giant isotope effect in hot
electron degradation of metal oxide silicon devices,” IEEE Trans. Elec-
tron Devices, vol. 45, no. 2, pp. 406–416, Feb. 1998, doi: 10.1109/16.
658674.
[51] D. Onsongo, D. Q. Kelly, S. Dey, R. L. Wise, C. R. Cleavelin,
and S. K. Banerjee, “Improved hot-electron reliability in strained-Si
nMOS,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2193–2199,
Dec. 2004.
[52] A. Kerber and E. A. Cartier, “Reliability challenges for
CMOS technology qualifications with hafnium oxide/titanium
nitride gate stacks,” IEEE Trans. Device Mater. Rel., vol. 9,
no. 2, pp. 147–162, Jun. 2009, doi: 10.1109/TDMR.2009.
2016954.
[53] S. Ramey et al., “Intrinsic transistor reliability improvements from
22 nm tri-gate technology,” in Proc. IEEE Int. Rel. Phys. Symp.
(IRPS), Apr. 2013, pp. 4C.5.1–4C.5.5, doi: 10.1109/IRPS.2013.
6532017.
[54] S. Mukhopadhyay et al., “Trap generation in IL and HK lay-
ers during BTI/TDDB stress in scaled HKMG N and P MOS-
FETs,” in Proc. IEEE Int. Rel. Phys. Symp., Waikoloa, HI,
USA, Jun. 2014, pp. GD.3.1–GD.3.11, doi: 10.1109/IRPS.2014.
6861146.
[55] B. S. Doyle et al., “The generation and characterization of elec-
tron and hole traps created by hole injection during low gate volt-
age hot-carrier stressing of n-MOS transistors,” IEEE Trans. Electron
Devices, vol. 37, no. 8, pp. 1869–1876, Aug. 1990, doi: 10.1109/16.
57138.