This article has been accepted for inclusion in a future issue of this journal.
Content is final as presented, with the exception of pagination.
IEEE TRANSACTIONS ON ELECTRON DEVICES
A Review of Hot Carrier Degradation in
n-Channel MOSFETs—Part I:
Physical Mechanism
Souvik Mahapatra , Fellow, IEEE, and Uma Sharma , Student Member, IEEE
Abstract — Transistor parametric drift due to conduction-
mode hot carrier degradation (HCD) in n-MOSFETs is
reviewed, for long- and short-channel length (LCH ) devices
having different source/drain (S/D) junction structures. The
HCD magnitude and time kinetics shape are discussed
for stress under different gate (VG ) and drain (VD ) biases
with varying VG /VD ratio, and without and with substrate
bias (VB ). Post-dc stress kinetics is discussed. The pub-
lished data are qualitatively analyzed to identify the roles of
different underlying physical mechanisms. In part II of this
article, impacts of technology scaling and stress tempera-
ture (T) and comparison of dc and ac stress are discussed.
Index Terms — Anode-hole injection (AHI), channel hot
electron (CHE), channel initiated secondary electron
(CHISEL), electron and hole trappings, hot carriers, impact
ionization, parametric drift, substrate and gate current, trap
generation.
I. I NTRODUCTION
T HE drift of transistor parameters, such as threshold
voltage (VT ), linear (IDLIN ) and saturation (IDSAT )
drain current, transconductance (G M ), and subthreshold
slope (S), due to hot carrier effect, first reported ∼40 years
ago [1] remains as a well-known reliability concern for
long and short L CH bulk [2]–[4] and fully depleted silicon-
on-insulator (FDSOI) [5] MOSFETs and FinFETs [6]. The
parametric drift is due to localized charge buildup near the
drain junction of the device at or near the channel and gate
oxide interface. The localized charges result in the higher
parametric drift when measured under reverse (source-drain
flipped) compared with the forward (normal) mode [7]. Hot
carrier degradation (HCD) was reported in MOSFETs with
different source/drain (S/D) junction structures, for the reduc-
tion in channel length (L CH ) from ∼2 μm to ∼20 nm,
oxide thickness (TOX ) from ∼20 to ∼1 nm, and drain bias
(VD ) from ∼10 to ∼1 V [1]–[7]. Note that the bias scaling
Manuscript received April 19, 2020; revised May 4, 2020; accepted
May 6, 2020. The review of this article was arranged by Editor C. Monzio
Compagnoni. (Corresponding author: Souvik Mahapatra.)
The authors are with the Department of Electrical Engineering,
IIT Bombay, Mumbai 400076, India (e-mail: souvik@ee.iitb.ac.in;
sharma.uma2211@gmail.com).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2020.2994302
0018-9383 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
1
was less than the dimensional scaling, resulting in a higher
electric field in the device. Hence, the S/D junctions of the
device were changed from a conventional single junction to
lightly doped drain (LDD)-based double junctions to reduce
HCD with technology scaling [8]. However, due to aggressive
junction scaling to mitigate short channel effects (SCEs) with
further technology scaling, the doping of the LDD regions was
increased to minimize the S/D series resistance (RSD ). Hence,
these devices have source–drain extension (SDE)-based S/D
double junctions. The HCD became less of a concern with the
introduction of LDD devices (∼1990s). However, it gradually
showed up in SDE devices (∼2000s) and is now an important
issue again in high-performance FinFETs.
It is important to remark that many key HCD features have
changed over the years with technology scaling.
1) The worst case HCD condition got shifted from
VG ∼ VD /2 in long L CH [1]–[3] to VG ≥VD in short L CH
[4]–[6] devices (VG : gate bias, the definition of long and
short L CH is shown in Section III).
2) The time kinetics shape got changed from a simple
power law in single, heavily doped drain junction
devices [2] to self-saturated nonpower-law in LDD
devices [3] and again back to power law with soft
saturation at long stress time in SDE devices [4]–[6]
(self-saturation and soft-saturation of time kinetics are
defined in Section IV).
3) The temperature (T) activation got shifted from negative
(HCD increases at lower T) in long L CH [7], [9] to
positive (HCD increases at higher T) in short L CH [6],
[7] devices.
4) Higher HCD was reported for ac compared with
dc stress in long L CH [10], and HCD got reduced
for ac compared with dc stress in short L CH [6]
devices.
5) The reverse substrate bias (VB ) resulted in increased
HCD in bulk, long L CH devices [7], [11] although, for
FDSOI, HCD reduces with reverse back-gate bias [12].
The short L CH devices handle lower voltages and are used in
modern logic cores, and long L CH devices are routinely used
in many circuits (e.g., memory periphery and display drivers)
and handle higher voltages (the classification of low and high
stress VD is done in Section II). Unlike core devices for logic
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE TRANSACTIONS ON ELECTRON DEVICES
circuits, HCD has always remained an important concern in
high-voltage devices for analog applications [13].
This two-part article provides a comprehensive review and
qualitative analysis of important experimental data for HCD
in n-channel MOSFETs and FinFETs published over the last
∼40 years, i.e., the features listed earlier in 1)–5), with the
following targeted goals. First, this would serve as a reference
for graduate students and practicing engineers especially those
entering the field. Next, this would guide the development
and benchmark of technology CAD (TCAD)-based models for
predictive simulation of HCD, to help device design. Finally,
this would also help in accessing the qualification and lifetime
projection methodologies for different device technologies.
In this article, experimental data are reviewed for various
types of devices (single, LDD and SDE junction-based planar
and FDSOI MOSFETs and FinFETs), for the wide variation
in device dimensions (L CH and TOX ) and stress conditions
(VG , VD , and VB ), to develop a comprehensive (although
qualitative) picture of the HCD physical mechanism. Although
no new data are shown, some of the results are reinterpreted.
The debates or gaps in the present understanding are also
highlighted. In addition, the worst case HCD stress condition
is identified for various types of devices. Section II provides
an introduction to the HCD mechanism and discusses various
processes that get triggered at different stress conditions. The
impact of varying the stress VG -to-VD ratio, in long L CH
devices under high stress VD and short L CH devices under
low stress VD , is discussed in Section III. The impact of
stress VD variation is discussed in Section IV. The impact of
anode-hole injection (AHI) during stress under high VG /VD
ratio and reverse VB is discussed in Section V, and its
effect on the post-dc stress kinetics is also discussed. This
article is concluded, and modeling guidelines are provided in
Section VI.
In part II of this article, experimental data at worst case
stress conditions for different devices (L CH /TOX , and S/D
junction) are reviewed to understand the impact of technology
scaling. The differences in the time kinetics shape of different
S/D junction devices are discussed. The impact of L CH and
TOX scaling is analyzed. The impact of T variation in long and
short L CH devices is explained. The dc and ac stress kinetics
are compared under high and low VD stress conditions.
II. D IFFERENT H OT C ARRIER P ROCESSES
Fig. 1(a) shows the schematic of an LDD MOSFET. For
conduction-mode HCD stress (VG > VT0 , VT0 is the prestress
threshold voltage, and VD > 0 V), the applied drain bias drops
across the channel (primarily) and LDD (depends on doping)
regions. The lateral electric field (E LAT ) increases from the
source toward the drain, peaks at the channel/LDD junction,
and reduces toward the LDD/drain junction; the direction of
E LAT is from drain to source. The vertical electric field (E VRT )
peaks at the source end of the channel and reduces toward the
drain. The direction of E VRT is from gate to channel although
in some cases (VG <VD ), the direction can flip especially near
the drain end of the channel.
The conventional channel hot electron (CHE) process is
qualitatively explained using Fig. 1(a). Electrons gain energy
Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
(increase in carrier T) as they drift in the channel from
source to drain under a favorable E LAT . Most of the electrons
undergo various forms of scattering and lose energy by the
time they reach the drain. However, a few of them escape
scattering and continue to gain energy, and these hot electrons
initiate the following phenomena near the drain end of the
MOSFET: 1) impact ionization and generation of electron–
hole pairs and holes give rise to substrate current (ISUB ) [14],
while electrons flow to the drain; 2) gate current (IG ) due
to the injection of holes at low VG (VG <VD /2) and electrons
at high VG (VG > VD /2) into the gate aided by favorable
E VRT direction [15], [16]; 3) generation of new defects at
or near the channel/gate insulator interface, which can be
probed by the charge pumping (CP) technique1 [3]–[5], [11],
[17]–[23]; and 4) hole and electron trapping in the gate oxide,
respectively, at low and high stress VG ’s [16]–[18], [24]–[27].
These generated defects and trapped charges are responsible
for device parametric drift. Charges in the channel region
impact VT and G M , in the overlap and LDD/SDE regions’
impact series resistance (R S ) and G M (by R S ), and
charges in all the regions impact drain current (ID ). However,
IDSAT is lower than IDLIN due to charge screening near the
drain end at high sense VD .
Fig. 1(b) shows the energy band diagram (for VG –VD > 0 V)
along with the gate to substrate direction to highlight several
energy values of interest: Si bandgap of ∼1.1 eV for impact
ionization and conduction (valence) band offset between the
channel and gate oxide for electron (hole) injection of ∼3.1 eV
(∼4.7 eV)2 [16]. It is important to remark that although ISUB
is traditionally used as a measure of hot electrons [2], [14],
an electron resulting in impact ionization (ISUB /ID ∼ 10−3 ) is
not the one responsible for the creation of new defect as the
original electron and generated electron–hole pair are of low
energy after the impact ionization event. Few hot electrons,
after redirectional collision toward the gate oxide/channel
interface, can either get injected into the gate and result in IG
at high VG (IG /ID ∼ 10−9 ) or get trapped in the preexisting
gate insulator defects, or can collide with the defect precursors
and generate defects. Holes generated out of impact ionization
move toward the source due to favorable E LAT and gain energy
and can either result in IG at low VG (IG / ID ∼ 10−11 ), or get
trapped, or generate new defects. Therefore, the electrons (or
holes) that constitute IG do not result in defect generation
and/or trapping, and vice versa. Note that the ratios shown
earlier are typical peak values to indicate the probability of
different processes, and these would change across devices
and stress conditions. The electrons and holes responsible for
HCD are denoted as “lucky carriers” [28].
1 In CP technique, the gate of the MOSFET is repetitively pulsed between
accumulation and inversion, the source and drain are tied together to ground
(or slightly reverse biased), and the substrate current is measured, which is
coming from trap (∼defect) assisted electron–hole recombination at or near
the channel/gate insulator interface. Increase in CP current after HCD stress
is due to generation of new traps. Besides channel region, CP can be used to
probe defect generation inside the drain junction, especially in LDD devices,
under the application of large gate pulse [3].
2 In these papers, high V and low V regimes are denoted, respectively,
D D
by whether VD is above or below the voltage (∼3 V) corresponding to the
electron injection barrier.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—I 3

Although computationally heavy, the most accurate method

to calculate carrier heating is to solve the Boltzmann transport
equation using the kinetic Monte Carlo (KMC) method [29].
Fig. 1(c) shows the plots of the distribution of hot electrons
(E > 3.1 eV) and holes (E > 4.7 eV) along the channel near
the drain from KMC simulations in an LDD MOSFET [11].
The energy cutoffs are for carrier injection over the electron
and hole energy barriers; however, the energy threshold for
defect creation can be much lower (see Section IV-B). The
distribution of hot holes is a bit shifted from the drain
junction toward the channel center than that of hot electrons.
Fig. 1(d) shows the plots of the peak hot electron and hot hole
density (HHD) as a function of VD . Although both reduce at
lower VD , the HHD reduces much faster than hot electrons as
the energy barrier is higher for holes than electrons. Therefore,
the injection of hot holes and electrons would reduce with
device scaling due to the coreduction in stress VD . Note that
the abovementioned results are for illustrative purposes and
can change across devices and stress conditions.
Under the application of reverse VB in bulk MOSFETs, Fig. 1. (a) Schematic of an LDD MOSFET. Carrier heating process,
the holes generated out of the primary impact ionization primary and secondary impact ionization, respectively, at VB = 0 V and
undergo secondary impact ionization as they flow toward VB <0 V, and gate injection are shown. Charges due to HCD in the chan-
nel (square), gate–drain overlap (triangle), and spacer (diamond) regions
the substrate and generate additional electron–hole pairs, are shown. (b) Energy band diagram showing the energy thresholds for
as shown in Fig. 1(a) [29]. The resulting holes increase impact ionization, and electron and hole injection over their respective
ISUB (ISUB /ID ∼ 10−1 ), and the secondary electrons have channel-oxide barriers. AHI process (refer to Section V) is illustrated at
(VG –VD )> 0 V. KMC simulated (c) hot electron density (HED) and HHD
higher energy for injection into the gate and increase IG distributions in the channel and (d) peak HED and HHD as a function of
(IG /ID ∼ 10−7 ) compared with the CHE process; the ratios VD (normalized) (see [11]). HHD is negligible at VG = VD in (d).
denote typical peak probabilities. This is known as the chan-
nel initiated secondary electron or “CHISEL” process. More
energetic carriers are generated, and the hot electron/hole
distributions are also broader due to the secondary ionization
process (not explicitly shown) [11].
AHI process is routinely invoked in the time-dependent
dielectric breakdown (TDDB) studies [30], [31]. Under HCD
stress, AHI can get triggered at a higher VG /VD ratio [see
Fig. 1(b)]. In the portion of the channel where the direction
of E VRT is favorable, electrons would get injected from the
channel to the gate and initiate impact ionization to gener-
ate electron–hole pairs in the gate, and the generated holes
are injected back into the oxide and generate defects. The Fig. 2. Measured VG dependence of (a) ISUB and IG in single-junction
MOSFET at high VD [32] and (b) ISUB in different LCH FinFETs at low
favorable position is near the drain junction if VG /VD ratio VD [33].
becomes high, and this would aid the injection of hot electrons
into the gate to trigger the AHI-initiated trap generation3 [11].
AHI also becomes higher for VB <0 V stress, which results [32]. Note that ISUB peaks at VG ∼ VD /2; similar data are
in more energetic carriers due to the secondary ionization shown in other reports [2], [14]–[16], [28]. The bell-shaped
process [11], [29]. characteristics are due to two competing processes: reduction
The abovementioned processes are invoked to qualitatively in E LAT (∼carrier heating) and an increase in the drain current
explain the experimental results presented in this article. All (ID ) at higher VG . It is noteworthy that the ISUB /ID ratio,
data shown are at room temperature (RT) unless specified an indicator of carrier heating, decreases monotonically as
otherwise. VG is increased (fixed VD ) for classical HCD (not explicitly
shown).4 IG is due to hot holes at lower VG and hot electrons at
III. I MPACT OF S TRESS G ATE B IAS ON CHE P ROCESS higher VG since the ratio of VG /VD determines the magnitude
A. Substrate and Gate Currents and direction of E VRT near the drain junction of the device
where hot holes and electrons exist. E VRT direction toward the
Fig. 2(a) shows the plots of the measured ISUB and IG as a
gate is favorable for hole injection at VG <VD /2 and toward the
function of VG in a long L CH device under high stress VD
substrate favors electron injection at VG > VD /2 (refer to [16]
3 Pure AHI due to tunneling of channel electrons to gate can happen near
the source end of the channel, provided that TOX is thin enough for tunneling 4 Devices featuring this bell-shaped I
SUB versus VG curve are classified as
and VG is high enough for the impact ionization event. long L CH . All features reported in such devices are defined as classical HCD.

Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 3. Measured fixed time (a) ΔVT and ΔICP (normalized to the
respective peak values) at 1.8 ks [18] and (b) ΔGM and ΔICP [26] versus
stress VG . (b) Data (ΔGM ) are shown for basic HCD at 500 s (ΔGM ) and
also after an electron injection phase of 10 s (ΔGM and ΔICP ). Single-
junction long LCH MOSFETs.
for details). IG due to hot holes peaks at VG ∼ VD /4 and
reduces at lower VG as ID is small (fewer electrons to initiate
impact ionization). IG is small at VG ∼ VD /2 because of the
simultaneous injection of electrons and holes. IG due to hot
electrons peaks at VG ∼ VD , and reduces at higher VG as carrier
heating reduces.
Fig. 2(b) shows the plots of the measured ISUB versus VG
in different L CH devices at fixed (low) VD [33]. ISUB is higher
at lower L CH at fixed VG and VD as expected due to higher
hot carrier density. However, the ISUB versus VG dependence
gets shifted from the conventional bell shape with a peak at
VG ∼ VD /2 (in long L CH ) to monotonically increasing at higher
VG as L CH is reduced.5 It is noteworthy that the ISUB /ID
ratio remains almost constant as VG is increased in short
L CH devices (not explicitly shown) [33], which is unlike the
classical behavior seen in long L CH devices. The same is also
reported in [34]. Note that IG due to the hot hole and electron
injection would reduce in short L CH devices as VD is scaled.
IG due to the quantum mechanical tunneling can be large due
to thinner TOX (<3 nm) in these devices [7].
B. Classical HCD Behavior (High VD )
Fig. 3 shows the plots of the measured ICP and VT [18]
[see Fig. 3(a)] and ICP and G M [26] versus stress VG [see
Fig. 3(b)], where ICP is the increase in the CP current due
to stress-generated defects. The HCD peaks at VG ∼ VD /2 and
reduces for VG <VD /2 and VG > VD /2 conditions. Note that
G M and VT (poststress minus initial) are negative and
positive, respectively, and indicate mobility reduction and
negative oxide charge buildup as VG is varied, except at
really low VG (in Fig. 3(a) and in [16] and [24]) when the
exact opposite is reported. The generation of acceptor-like
defects (negatively charged only if occupied by electrons,
neutral otherwise) and electron trapping are responsible for the
reduction in mobility and negative gate oxide charge buildup.
However, at very low VG , oxide trapped holes overcompensate
for the effect of acceptor-like generated defects; GM increases
due to channel shortening (not seen in Fig. 3(b) but shown
in [16] and [24]), and negative VT shift is observed.
5 Devices featuring this monotonically increasing I
SUB versus VG curve are
classified as short L CH . All features reported in such devices are defined as
nonclassical HCD.
Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
Note that the maximum G M and VT at VG ∼ VD /2 con-
dition is primarily due to generated defects (∼ ICP ) as both
holes and electrons are injected into the gate resulting in
smaller overall trapping. This coincides with the peak of the
ISUB versus VG curve [see Fig. 2(a)], and many have used this
condition to study HCD in long L CH devices under higher
stress VD . However, although the peaks of ICP and VT are
at VG ∼ VD /2 [see Fig. 3(a)], the peak is somewhat broader
for ICP with larger spread toward lower VG compared with
that of VT ; similar results are shown in [19] and [22]. The
broader ICP peak toward lower VG indicates that hot holes
are efficient in defect generation. Hole injection and trapping
at VG <VD /2 stress reduce VT compared with ICP due to
compensation and can explain the narrower peak or shaper
reduction of VT than ICP as VG is reduced.
Indeed, many have suggested the injection of hot holes
into the gate oxide as a precondition for defect genera-
tion [16], [18], [26]. It has been suggested that the energy
released due to the recombination of trapped holes (following
hot hole injection) and electrons (also injected) triggers defect
generation in these devices, having long L CH and stressed
under high VD [35]. However, it observed that the HCD defects
are chemically not the same (and/or are not formed by the
same mechanism) as those generated by uniformly injected
carriers into the gate oxide for VG > 0 V/VD = 0 V stress6 [36].
Therefore, “injection inside the oxide bulk” is not a basic
requirement; energetic holes during HCD stress can collide
with the defect precursors at or near the channel/gate oxide
interface to generate defects.
However, if present, “hole injection inside the oxide bulk”
can generate additional defects. As proof, Fig. 3(b) shows
the plots of the measured G M versus stress VG following
a short electron injection phase at VG = VD condition after
the basic HCD stress [26]. Note that G M increases after the
short electron injection phase, and the peak G M location is
shifted toward lower VG . ICP also increases by ∼20% after
the short poststress electron injection phase (data shown only
after the final short electron injection phase, but not right after
basic HCD). However, the electron injection phase itself, i.e.,
when done alone, does not generate defects in any measurable
quantity. Remarkably, the difference in G M between the
original HCD and post electron injection is larger when the
original stress is done at lower VG .
It has been suggested that neutral electron traps (defects) are
created in the oxide bulk by injected holes at VG <VD /2 stress
(more on this in Section V) [26], and these traps get activated
during the brief electron injection phase. It is also possible that
additional defects are created during the poststress electron
injection phase since a ∼20% increase in ICP is present due
to the trapped hole and electron recombination process [35].
This explains a larger G M increase after electron injection
when the original stress is done at lower VG . In addition,
neutralization of trapped holes by the injected electrons would
make G M primarily due to generated acceptor-like defects
6 The impact of deuterium (D )-based postmetallization anneal (PMA) is
2
observed for HCD stress but not much for uniform stress under VD = 0 V.
It is now well established that defect generation is lower under HCD stress in
D2 PMA compared with the conventional hydrogen (H2 )-based PMA devices
(refer to [36] and references therein).
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—I 5

TABLE I
P OWER -L AW S LOPE F ROM D IFFERENT R EPORTS (H IGH VD S TRESS )

Fig. 4. Measured time kinetics of (a) ΔGM in LDD MOSFET [37] and
(b) ΔVT in single-junction MOSFET [27] at different VG /VD ratios.

and can also explain the observation. Therefore, the net

increase in negative charges results in higher G M after the
short electron injection phase. This has important implications
for ac stress at high VD , which is discussed in part II of this
article.
Note that ICP , G M , and VT reduce similarly when VG
is increased beyond the VG ∼ VD /2 condition, which indicates
the inefficiency of defect creation by hot electron injection
(and/or collision) alone (E VRT is less conducive for hot hole
injection at VG > VD /2). As shown in [19], hot electron injec-
tion is less efficient than hot hole injection (either alone,
or recombination of trapped holes by injected electrons) in
generating defects at or near the channel/gate oxide interface.
Moreover, negligible electron trapping is observed in these
devices due to a similar reduction in ICP , G M , and VT
at VG > VD /2 stress condition. In the presence of electron
trapping, G M (and/or VT ) would reduce less compared
with ICP at VG > VD /2 stress (refer to [17] for additional
details).
Fig. 4 shows the plots of the measured time kinetics of
G M [see Fig. 4(a)] [37] and VT [see Fig. 4(b)] [27]
esis (the slopes are identical for VG = VD /2 stress). Hence,
for stress under varying VG /VD ratio. Note that G M
when stress VG is increased beyond VD /2, the reduction in
reduces (negative) and VT increases (positive) monotonically
NIT from CHE or pure HCD [however, the AHI contribution
for VG ∼ VD /2 and VG > VD /2 conditions and shows power-law
can increase in some cases (see Section V)] and increase in
time dependence with slope n. This is observed across various
electron trapping (depends on the oxide quality and thickness)
reports [2], [3], [9], [11], [17], [20], [22], [27], [28], [36]–[41],
can explain the time kinetics of parametric shift.
and the time slopes are listed in Table I, together with device
However, G M increases first and then reduces with time at
and experimental details. Note that HCD is primarily due to
VG <VD /2 stress condition (switches from positive to negative).
defect generation at VG ∼ VD /2 stress, as the same n is reported
This is because of the dominance of hole trapping at an
for NIT , the generated interface trap density measured by CP,
early time and acceptor-like generated defects at a longer time
and G M [17]. However, the slope varies between different
(as trapping saturates), visible, respectively, before and after
published reports, which is further discussed in Section IV-B.
the “dip” in the log–log plot. The long-time slope n (after
The slope reduces at VG > VD /2 stress compared from the
“dip”) appears larger due to the early hole trapping phase.
same report (although this is not always the case, e.g., [37],
Finally, the generation of neutral oxide traps, if any, has no
[41]), see Table I. Such reduction is presumably due to
impact, unless trap filling is done to expose those, as shown
AHI-initiated defect generation (impacts NIT , VT , and
in [26]. Therefore, the relative and opposing contribution of
G M ) and electron trapping (impacts VT and G M ). The
hole trapping and trap generation would explain the time
AHI process is explained in Section V. Note that electron
kinetics of parametric shift as stress VG is reduced below VD /2.
trapping is negligible at VG ∼ VD /2 but can show up under
VG > VD /2. By invoking fast saturation of the electron trapping
time kinetics (n∼0 in a log–log plot at longer stress time [42]), C. Scaling and Nonclassical HCD Behavior (Low VD )
the reduction in time slope can be explained (addition of Fig. 5 shows the plots of the measured IDLIN versus VG
power-law time kinetics (n > 0) and saturated time kinetics for the variation in L CH (at fixed TOX ) [see Fig. 5(a)] [12] and
(n = 0) would reduce the slope of the resultant time kinetics). TOX (at fixed L CH ) [see Fig. 5(b)] [43]; for a similar type of
The measured n for G M is lower compared with NIT at devices, the stress VD is low and kept fixed for both plots.
VG = VD for the same device [17], which proves this hypoth- For a fixed VG , IDLIN increases at short L CH but reduces

Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
6 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 5. Measured fixed time ΔIDLIN from devices having variation in
(a) LCH (at fixed TOX ) [12] and (b) TOX (at fixed LCH ) [43] versus stress VG .
All data are from FDSOI MOSFETs. The value of stress time is not
available.
Fig. 6. Measured ΔIDLIN time kinetics at different stress VD in
(a) relatively long LCH SDE MOSFETs at VG ∼ VD /2, VG ∼ VD and only
VG (VD = 0 V) stress [46] and (b) relatively short LCH FDSOI MOSFETs
at VG ∼ VD /2 and VG = VD stress [12].

at thinner TOX ; the scaling effects are discussed in detail in TABLE II

P OWER -L AW S LOPE F ROM D IFFERENT R EPORTS (L OW VD S TRESS )
part II of this article. However, of interest is the shape of
the IDLIN versus VG plot, which gradually shifts from bell-
shaped to monotonically increasing dependence, as either L CH
is reduced or TOX is increased.
Note that the original explanation of increased HCD at
VG = VD is defect generation by multi (two), hot (moder-
ately) electron interaction process [12], [43]–[45]. An alter-
native explanation is as follows. For a well-controlled, “long-
channel” device, the pinch-off region and E LAT reduce sharply
at higher VG (fixed VD ), which reduces carrier heating. This
is evident from the reduction in ISUB with VG in long L CH
devices [see Fig. 2(b)]. The same does not hold in a device
encountering relatively larger SCE (short L CH at fixed TOX or
thicker TOX at fixed L CH ), as evident from the monotonically
increasing ISUB versus VG plot in short L CH devices [see
Fig. 2(b)]. Hence, the carriers are still hot at high VG (as
E LAT is high and pinch-off region exist) and are also high
in density (∼higher ID ); hence, the CHE process does not
reduce like the long channel case and is presumably the reason
for the nonclassical VG dependence of HCD. It is remarkable
that hot holes are present in devices showing high ISUB at
VG = VD stress. Since hot holes are more efficient than
electrons in generating defects, as discussed in Section III-B,
it is possible that enhanced HCD at higher VG is linked to hot
holes. However, it is difficult to be fully certain if this is the
case, or it is just the hot electrons that generate defects in these
conditions [7]. Proper quantification is needed to resolve such this also suggests a reduction of the AHI-initiated process (see
differences, which is beyond the scope of this review article. Section V) at VG = VD condition near the drain due to low VD .
Fig. 6 plots the measured IDLIN time kinetics in relatively However, the gate bias-assisted AHI process can still happen,
long [see Fig. 6(a)] [46] and short [see Fig. 6(b)] [12] L CH especially near the source side of the channel, although note
devices for VG ∼ VD /2 and VG = VD conditions at low VD that the uniform stress (VD = 0 V) shows much lower IDLIN
(<3 V) stress (note that the L CH in Fig. 6(a) is much shorter compared with HCD stress (VD > 0 V) [see Fig. 6(a)]; refer to
than those used in Fig. 4). Note that power-law time kinetics the next section for a related discussion of Fig. 6(b). The slope
is observed [with soft-saturation at longer stress time, see n from various reports shows a widespread even for low VD
Fig. 6(a)] but with very different slope n of ∼0.5 (the early stress (n ∼ 0.2−0.5) [4]–[7], [12], [44], [46]–[51]. The slopes
part before saturation) in Fig. 6(a) and ∼0.18 in Fig. 6(b). are listed in Table II and discussed further in Section IV-B.
However, the slope does not vary with variation in VG /VD ratio.
The invariance of n as VG is varied is unlike that observed for
high VD stress (see Fig. 4). This is due to the negligible injec- D. Effect of Positive Bias Temperature Instability (PBTI)
tion of hot electrons at VG = VD condition, since VD is low, Note that PBTI became an important concern espe-
and negligible electron trapping (even though the tunneling is cially for the high-K metal gate (HKMG) gate insulator
large) due to thinner TOX and low trapping volume. Moreover, process [52], [53]. It depends on E VRT and degrades the

Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—I 7

Fig. 7. Correlation of ΔIDLIN and ΔVT for IDLIN sensed in (a) subthreshold
and (b) above the threshold for HCD stress at different VD /VG ratios; data
from PBTI stress are shown for comparison [56]. SDE MOSFET, TOX , not
available.

channel region (not overlap), and the defects are nonuniform
(reduce toward the drain) for VD > 0 V stress. It affects
VT and IDLIN (not G M and R S ). It can influence
the HCD parametric drift, especially for VG = VD stress,
used in short L CH devices under lower VD stress [54], [55].
On the contrary, HCD affects VT , G M , R S , and IDLIN .
Therefore, a correlation of IDLIN to VT would help estimate
the contribution of PBTI during HCD stress.
Fig. 7 shows the plots of the measured IDLIN versus
VT for stressing at different VG /VD conditions in a short
L CH device at low stress VD when IDLIN is sensed in
subthreshold [see Fig. 7(a)] and above threshold regimes [see
Fig. 7(b)] [56]. Note that this device uses HKMG-based gate-
stack where PBTI is present. For a given VT , very large %
IDLIN is seen for subthreshold sense as the prestress IDLIN is
small. IDLIN and VT are perfectly correlated for HCD (all
VD /VG ratios) and PBTI (VD = 0 V) stress. However, IDLIN
and VT are not correlated with HCD and PBTI when sensed
above the threshold. IDLIN at a given VT reduces at a lower
VD /VG ratio, with a very similar correlation between the HCD
at VD <VG and PBTI (VD = 0 V) stress.
The original interpretation is the HCD results in more
uniform channel degradation for multicarrier-based defect
generation processes at VG ≥VD compared with the single
carrier process at VG <VD /2, with a larger spread for the many
carrier processes at VG > VD than the two-carrier process at
VG = VD [12], [43], [44]. PBTI (VD = 0 V) results in fully
uniform channel degradation. Hence, the IDLIN versus VT
correlation for PBTI and HCD (at VG > VD ) stress gets closer
to each other.
An alternative explanation is as follows. The subthreshold
sense is not affected by R S , both IDLIN and VT are
due to defect generation in the channel, and they perfectly
correlate for HCD stress at various VG /VD conditions and
PBTI. IDLIN is affected by R S when sensed above the
threshold. IDLIN versus VT varies for PBTI and HCD
stress due to the difference in the relative degradation of the
channel and overlap/SDE regions. The relative contribution
of channel degradation is larger than that of the overlap/SDE
Fig. 8. Measured time kinetics of (a), (c), and (d) ΔVT and (b) ΔIDLIN
at different stress VD for (a) and (b) VG ∼ VD /2 and (c) and (d) VG = VD
stress. Data are scaled along the time axis to universal relation (solid
symbols). See text for device details. Data in (b) are at RT. Time-axis
scaled data are shown as crossed symbols.
IDLIN versus VT correlation is largest in this case. Note
that PBTI shows up at VG = VD and more so at VG > VD
condition, making the overall (HCD+PBTI) degradation more
uniform in the channel, which reduces the IDLIN versus VT
correlation toward pure PBTI case. Since the time slope n is
very similar between PBTI (n ∼ 0.17) [52], [53] and pure
HCD [n ∼0.18 at VG ∼ VD /2, see Fig. 6(b)] in this case, n
does not change under VG = VD stress, as shown in Fig. 6(b).
IV. I MPACT OF S TRESS D RAIN B IAS ON CHE P ROCESS
A. Time Kinetics and Universal Scaling
Fig. 8 shows the plots of the time kinetics of measured VT
in a long L CH planar MOSFET with a single S/D junction
[see Fig. 8(a)] [9], IDLIN in a long L CH LDD MOSFET
[see Fig. 8(b)] [3], VT in a short L CH SDE MOSFET [see
Fig. 8(c)] [51], and VT in a short L CH FinFET [6] as a
function of VD [see Fig. 8(d)]. The stress VD is high and
VG ∼ VD /2 in Fig. 8(a) and (b), and the stress VD is low and
VG = VD in Fig. 8(c) and (d). Power-law time kinetics is seen
in Fig. 8(a), (c), and (d), while a self-saturating nonpower-
law time dependence is seen in Fig. 8(b). The difference in
the time-dependent shape between the LDD device versus
the others7 is discussed in detail in part II of this article.
Note that a comparison of HCD magnitude across devices
in Fig. 8 is challenging due to the very different nature of
gate oxide quality (more on this in Section IV-B) and data at
different T (more on this in part II of this article). However,
VD dependence can be studied.
Conventionally, the fixed-time degradation is plotted versus
1/VD on a semilog scale (exponential dependence) [2], [22].
This is done as the same holds for the VD dependence of
7 In Fig. 6(a), the time kinetics shows power law at shorter time, and a

region for PBTI (VD = 0 V) stress, and IDLIN versus VT
correlation is lowest. PBTI is negligible at very low VG , and
VG ∼ VD /2 stress is due to HCD localized near the drain. The
relative contribution from channel degradation is lowest, and
soft-saturation is seen at longer time only when the degradation becomes
high and reaches the maximum. However, in Fig. 8(b), the rate of degra-
dation reduces continuously (self-saturation) at the beginning of stress and
asymptotically settles to a final value even if the degradation is far from the
maximum limit.

Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 9. Correlation of 1/S versus VD for (a) single-junction MOSFETs
having abrupt and graded junctions and different LCH [39] and (b) data
obtained from Fig. 8 (see text for details). The data sets are arbitrarily
shifted along the Y-axis for clarity, so only the slope (∼VAF) should be
considered.
ISUB (∼carrier heating) [2] due to the exponential dependence
of ISUB on 1/E LAT (see the Lucky-Electron model in [28]).
The voltage acceleration factor (VAF), i.e., the slope of the
HCD versus 1/VD plot, depends on L CH /TOX [2] and junction
profile [38], as these quantities impact E LAT .
Note that the VD dependence of degradation can be found
at a fixed time in Fig. 8(a), (c), and (d) as the time kinetics
shows power law with similar n across VD . This is not feasible
in Fig. 8(b), as the nonpower law dependence would make
the fixed time VD values dependent on the time when it is
recorded. Therefore, the time kinetics at a different VD is
scaled by a factor S along time (X-axis) to obtain a unique
behavior as shown; S is larger for higher VD , and vice versa.
The time axis scaling is explained in detail in [3], [4], [13],
and [57]. Moreover, it is realized afterward that HCD is an
energy-driven process [45], [58]. Since carrier energy is ∼VD ,
1/S, which is a measure of a lifetime, is plotted versus VD in
a log–log plot (power-law VD dependence) [57].
Fig. 9 shows the plots of the VD dependence of 1/S for
abrupt and graded single-junction MOSFETs with fixed TOX
but a different L CH [see Fig. 9(a)] [38] and for different
devices [see Fig. 9(b)] corresponding to Fig. 8. The power-law
VAF is higher (∼38) for the abrupt compared with the graded
(∼30) single-junction devices from the same report [38], but
it does not vary with L CH for a given type of junction.
Moreover, similar VAF (∼24–30) is seen for the other devices
in Fig. 8 [3], [6], [9], [51] and also for other devices listed in
Tables I and II [4], [20], [40], [46], [50] (not explicitly shown,
see [57] for additional cases), covering wide variation in L CH ,
TOX , and stress VD .
The time-axis scaling at a different stress VD (with VG
chosen to represent the worst case or more realistic use
condition) can be used for lifetime determination under HCD
stress. This can be used for all types of devices to remain
consistent across all technologies, as the method can account
for any soft- or self-saturation effect.
B. Discussion on Defects and Time Kinetics
Note that Pb centers (Si3 –Si–) [59] are often associated
with defects generated during HCD (CHE stress) [7]. It is
indeed intriguing that appreciable HCD is observed for stress
at low VD of ∼1 V [6], as this is much below the critical
Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
energy (E C ) of ∼1.5 eV often assigned to the dissociation
of hydrogen (H)-passivated Pb centers [7], [60], [61]. One
possibility can be the carrier–carrier scattering induced carrier
energy enhancement [29]. It is also possible that the bond
strength is lower in some devices [6]. It is remarkable that
the HKMG devices have a chemical oxide-based interlayer
(between the channel and high-K layers), which is a low T
process [62]. It is reported that the oxide growth T (∼oxide
quality) can impact the bond strength and hence the magnitude
of HCD [39]. The self-heating (SH) effect [63] in FinFETs
(and FDSOI) can further activate HCD (see part II of this
article for T activation of HCD). More work is needed to
understand these issues.
Except for LDD devices [see Fig. 8(b)], other devices
show power-law time dependence. In general, power-law time
kinetics can be explained either by a reaction-limited process
(e.g., spread in the energy required to break a defect) [64]
or a diffusion-limited process [65]. More analysis is required
to identify the correct physical process. Moreover, the effect
of generated charges on the potential and electric field in the
channel needs to be considered, which can reduce the carrier
heating (∼ISUB ) with the passage of time, to estimate HCD
time kinetics.
Another intriguing factor is the wide range of n reported
in Tables I and II. This can be partially explained as follows.
The HCD generated Pb centers do not recover [33] unless a
very high T bake is used after stress [61]. The parametric
drift can recover after stress, more likely for thicker TOX
devices when electron trapping is present during stress [66].
Note that electron trapping can be small but present even for
VG ∼ VD /2 stress, as the electron and hole spatial profiles are
physically separate [see Fig. 1(c)], while it can certainly be
present for VG > VD /2 stress.
On the other hand, during CP measurements, any bulk gate
oxide traps (generated during HCD stress if VD is high) would
get filled by holes and electrons, respectively, during the pulse
low/high phases. Note that the energy bandgap scanned by CP
depends on the local VFB and VT values8 (in accumulation
and inversion for pulse low/high phases), and these would
change (VFB becomes more negative and VT more positive
due to hole and electron trapping, respectively) during CP
measurements. The energy bandgap scanned by CP would
reduce and results in a reduction in CP current (∼recovery)
when the measurement is done after stress.
It is now well-known that recovery increases the power-law
slope n when measured using the slow method [67]. The
slopes listed in Tables I and II (except in [6], [49], and [50])
are measured using slow methods, and so the actual value
would be a bit lower than shown, especially for the thicker
TOX devices. This, however, is unlikely the case for thinner
TOX devices since the electron trapping is negligible. Hence,
if “properly” measured, we speculate that the reported n shown
in Table I would be ∼0.5 at VG ∼ VD /2 stress for most cases.
Note that n ∼ 0.5 is reported for most cases also in Table II.
However, the spread in n toward lower (than n ∼ 0.5) values
8 In the CP method, V
FB and VT are defined as the gate voltage needed
to achieve critical hole and electron density at the channel surface so that
complete trap filling happens during the duration of pulse low/high phase,
respectively [19].
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—I
Fig. 10. Impact of stress VG on measured (a) fixed time ΔIDLIN in a
different LCH FDSOI MOSFETs [43] and (b) 1/lifetime (from 10% reverse
ΔIDSAT ) at a different VD in LDD MOSFET [45].
in Tables I and II is hard to explain and needs more work.
The nonpower-law time dependence, often reported in LDD
devices [3], [20], [40], is discussed in part II of this article.
Interestingly, similar n is seen from different probes in single-
junction [28] and SDE [4] devices, while this is not the case for
some LDD devices (the ones showing power-law time kinetics)
[37], [41]. This aspect is also discussed in part II of this article.
Finally, as mentioned earlier, n reduces for VG > VD /2 condi-
tion because of electron trapping and AHI. The impact of the
AHI-initiated process is discussed in the following.
V. I MPACT OF A NODE -H OLE I NJECTION
A. Stress Under High VG /VD Ratio
Fig. 10(a) shows the plots of the measured IDLIN versus
VG at fixed VD in devices having different L CH (but fixed TOX )
[43]. Fig. 10(b) shows the plots of the inverse of estimated
lifetime versus VG at various stress VD (but fixed L CH and
TOX ); lifetime equals the time to reach 10% IDSAT , measured
in the reverse mode [45]. These are relatively “long-channel”
devices and show bell-shaped IDLIN (and 1/lifetime) versus
VG dependence for VG variation up to VD . It is interesting
to remark that the peak IDLIN point shifts toward higher
VG as L CH is scaled (as the device slowly becomes “short-
channel” type, but the “bell-shape” is present) [see Fig. 10(a)].
However, the increase in HCD is observed for VG > VD , which
is more prominent at short L CH [see Fig. 10(a)] and higher
VD /VG ratio [see Fig. 10(b)]. Note that this feature has been
reported in [58] first, which prompted a shift in the under-
standing of the HCD mechanism from field to energy-driven
process. Note that the original explanation of increased HCD
at VG > VD is the generation of defects by multi (many) cold
electron interaction process [12], [43]–[45]. An alternative
explanation is the triggering of the AHI-initiated process for
both Fig. 10(a) and (b) and electron trapping for Fig. 10(b);
trapping is less significant in Fig. 10(a) due to thinner TOX .
The impact of the AHI-initiated trap generation can be
directly estimated using CP measurements. Fig. 11 shows
the plots of the measured ICP time kinetics during [see
Fig. 11(a)] and after [see Fig. 11(b)] stress at VG = VD /2 and
VG = VD conditions in devices having different TOX [11].
HCD is due to the pure CHE process and shows a power-law
slope of n ∼ 0.6 at VG = VD /2 stress and no recovery after
stress. The power-law slope reduces, and recovery is observed,
Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
9
Fig. 11. Measured ΔICP time kinetics (a) during and (b) after stress at
different VG /VD ratio in LDD MOSFET having a different TOX [11].
Fig. 12. Measured fixed time ΔIDSAT from forward and reverse mode
sense in devices having (a) long and (b) short LCH versus stress VG , for
VB = 0 V and VB <0 V stress, SDE MOSFETs [7]. Stress time is 4 ks.
for VG = VD stress; the reduction in n and recovery are more
for the thinner TOX device. The results can be explained as
follows.
The AHI process, illustrated using Fig. 1(b), is triggered
at VG = VD stress. By assuming power-law time kinetics
but lower slope n for the AHI-initiated defect generation,
the reduction in n at higher VG stress can be explained (e.g.,
Fig. 11 and also in [17], see Table I). However, the chemical
nature of defects generated by the AHI-initiated process is
likely different from those generated by the pure HCD process,
as they show a lower power-law slope during stress and
recovery after stress. The contribution due to pure HCD (CHE)
would reduce, while that from the AHI-initiated process would
increase as VG is increased (for classical devices), and the
impact will be more at thinner TOX (when everything else
stays same), which can explain the features reported in Fig. 11.
However, AHI would reduce in short L CH devices, even having
thinner TOX since the stress biases (VG and VD ) are reduced
and if the VG /VD ratio is not high. Therefore, short L CH devices
show the same n at various VG /VD ratio (VG ≤VD ) [see Fig. 6]
and no poststress recovery [33], as they are governed by the
CHE process.
B. Stress Under Reverse VB
Fig. 12 shows the plots of the measured IDSAT versus
VG for VB = 0 V and VB <0 V stress, in devices having
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10
Fig. 13. Measured ΔNIT time kinetics (a) during and (b) after stress
without and with reverse VB in LDD MOSFET [11].
relatively long [see Fig. 12(a)] and short [see Fig. 12(b)] L CH ,
and stressed, respectively, at relatively higher and lower VD
(note that the L CH and VD values in Fig. 12(a) are smaller than
the values in Fig. 3) [7]. The relatively long and short L CH
devices show, respectively, the bell-shaped and monotonic VG
dependence as expected. However, higher IDSAT is observed
for VB <0 V stress due to secondary ionization related effects.
HCD stays localized near the drain junction for both devices,
without and with reverse VB stress, since the drift is larger
for reverse compared with the forward measurement mode.
The impact of VB is more at long L CH and results in higher
IDSAT , more so at higher stress VG . Hence, IDSAT at VB <0
V stress does not fall off as sharply as that for the VB = 0
V case, which can be explained using the AHI-induced trap
generation effect. The impact of reverse VB stress is lower in
the short L CH device due to reduced body effect.
Fig. 13 shows the plots of the measured ICP time kinetics
during [see Fig. 13(a)] and after [see Fig. 13(b)] stress at
VG = VD /2 condition but without and with VB (reverse
bias) [11]. The power-law slope reduces during stress, and
recovery is observed after stress under VB <0 V condition.
Note that the core CHE process should reduce under reverse
VB due to the increase in VT0 and reduction in ID that triggers
the carrier heating process. This is indeed the case in FDSOI
when stressed under reverse back-gate bias [12]. Therefore,
Fig. 13 can be explained by again invoking the AHI-initiated
process, as higher electron energy in the substrate, due to the
secondary impact ionization event, would also result in higher
electron injection and AHI at VB <0 V stress (see [11] and [29]
for details).
C. Discussion on Defects and Time Kinetics
Based on the poststress buildup of defects after HCD stress
at VG <VD /2 [68] and irradiation [69], the following is a likely
process for AHI-induced generated traps. For large VG /VD or
VB <0 V stress, hot electrons, upon injection from the substrate
to the gate near the drain region of the device, trigger impact
ionization in the gate. Resulting holes are injected back into
the oxide, and they break hydrogen (H)-passivated defects to
produce atoms (H) and/or ions (H+ ). This is followed by the
diffusion (or drift) of H (or H+ ) toward the channel/gate oxide
interface and subsequent generation of defects at or near the
channel/gate oxide interface, which can be measured using the
CP method.
Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON ELECTRON DEVICES
A potential candidate for AHI-initiated defects is hydro-
gen (H) bridge (O3 –Si–H) [70], which can convert into
Oxygen vacancy (Ov) when H is dislodged. The generated
Ov centers can repassivate if H atoms are nearby and can
be probed by CP if these are located near the channel/gate
oxide interface (depends on the CP frequency) [71]. Note that
Ov defects (∼neutral electron traps) in the oxide bulk would
result in stress-induced leakage current (SILC) during TDDB
stress [72], [73]. Also note that the power-law slope for SILC
is n∼0.35 [74], lower than that (n∼0.5) seen for most CHE
stress. Such neutral electron trap creation is also suggested
after the hole injection in Fig. 3(b) [26]. However, this is
purely speculation at this moment, and other candidates are
indeed possible for the AHI defects.
VI. C ONCLUSION
The following conclusions can be drawn regarding the
HCD physical mechanism in n-channel MOSFETs and the
suitability of TCAD for predictive simulation.
HCD can be classified whether hot carriers are injected into
the gate oxide or not, which depends on stress VD . Generation
of acceptor-like defects is always present, which is augmented
by injection and trapping of electrons at high VG /VD ratio and
high VD above ∼3 V and holes at low VG /VD ratio and high VD
above ∼4.7 V, in long L CH , thicker TOX devices. Trapping is
not seen in short L CH , thinner TOX devices at VD <3 V stress,
while trap generation is even down to VD ∼1 V stress. Hence,
it is imperative that the TCAD framework for different classes
of devices should contain these relevant physical processes.
Defect generation under CHE stress is linked to the genera-
tion of hot holes from the impact ionization process (∼ISUB ).
Both peaks at mid-VG in long L CH devices at high VD stress
and in some short L CH devices under low VD stress when
devices do not suffer from SCE. However, both peaks at
VG ∼ VD stress in short L CH devices when SCE is large.
The carrier heating follows this trend, and hence, it is not
possible to ascertain if hot holes or hot electrons are the
candidates that produce these defects. It is highly probable that
the hot carriers collide with near interfacial defect precursors
to generate defects, and the injection into the oxide is not
needed. However, coinjection of holes and electrons into the
oxide, when present (VD > 4.7 V), generates additional defects.
TCAD presently can explain the ISUB versus VG dependence in
long and short L CH devices. However, a connection needs to be
established between carrier heating and the defect generation
processes at different VG /VD ratio, without and with the
situation when hot carriers are coinjected into the gate oxide
(for high-voltage devices).
The CHE process would reduce at higher VG /VD ratio (since
the pinch-off region and carrier heating reduce) and at reverse
VB (as ID reduces and so the density of hot carriers). However,
AHI-initiated defect generation is seen in such cases, triggered
by hot electron injection from the channel for VD > 3 V stress.
AHI triggered by tunneling of channel electrons and PBTI can
also generate defects, especially in thinner TOX devices and
higher VG /VD stress. To the best of our knowledge, AHI and
related processes are not available in TCAD at present.
Both electron and hole trappings, when present, saturate at
longer stress time. However, defect generation shows power-
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MAHAPATRA AND SHARMA: REVIEW OF HCD IN n-CHANNEL MOSFETs—I
law time dependence although with a wide range of power-law
slope. The reason for this is not fully understood although a
few possibilities have been discussed. A suitable framework
for the time kinetics of trap generation and trapping needs to
be adopted in TCAD. In particular, the setup should be able to
explain the wide range of measured time slopes for the CHE
trap generation process and the lower (presumably) slope for
the AHI-initiated trap generation process.
Trap generation and trapping at various parts of the device
differently affects the time kinetics of different parameters of
the device. It is understood that the present TCAD maturity is
sufficient to handle the connection between generated charges
and changes in the device parametric drift.
R EFERENCES
[1] R. B. Fair and R. C. Sun, “Threshold voltage instability in MOSFET’s
due to channel hot hole emission,” in IEDM Tech. Dig., Washington,
DC, USA, Dec. 1980, pp. 746–749, doi: 10.1109/IEDM.1980.189944.
[2] E. Takeda and N. Suzuki, “An empirical model for device degradation
due to hot-carrier injection,” IEEE Electron Device Lett., vol. EDL-4,
no. 4, pp. 111–113, Apr. 1983, doi: 10.1109/EDL.1983.25667.
[3] D. S. Ang and C. H. Ling, “On the time-dependent degradation of LDD
n-MOSFETs under hot-carrier stress,” Microelectron. Rel., vol. 39, no. 9,
pp. 1311–1322, 1999, doi: 10.1016/S0026-2714(99)00053-0.
[4] D. Varghese, M. A. Alam, and B. Weir, “A generalized, I B -independent,
physical HCI lifetime projection methodology based on universality of
hot-carrier degradation,” in Proc. IEEE Int. Rel. Phys. Symp., May 2010,
pp. 1091–1094, doi: 10.1109/IRPS.2010.5488666.
[5] L. Brunet et al., “Impact of backside interface on hot carriers degra-
dation of thin film FDSOI Nmosfets,” in Proc. IEEE Int. Rel. Phys.
Symp. (IRPS), Anaheim, CA, USA, Apr. 2012, pp. 3B.2.1–3B.2.5, doi:
10.1109/IRPS.2012.6241806.
[6] Y. Qu et al., “Ultra fast (<1 ns) electrical characterization of self-
heating effect and its impact on hot carrier injection in 14 nm
FinFETs,” in IEDM Tech. Dig., Dec. 2017, pp. 39.2.1–39.2.4, doi:
10.1109/IEDM.2017.8268520.
[7] A. Bravaix, C. Guerin, V. Huard, D. Roy, J. M. Roux, and E. Vincent,
“Hot-carrier acceleration factors for low power management in DC-AC
stressed 40 nm NMOS node at high temperature,” in Proc. Int. Rel. Phys.
Symp., Apr. 2009, pp. 531–548, doi: 10.1109/IRPS.2009.5173308.
[8] J. J. Sanchez, K. K. Hsueh, and T. A. DeMassa, “Drain-engineered
hot-electron-resistant device structures: A review,” IEEE Trans. Elec-
tron Devices, vol. 36, no. 6, pp. 1125–1132, Jun. 1989, doi:
10.1109/16.24357.
[9] F.-C. Hsu and K.-Y. Chiu, “Temperature dependence of hot-electron-
induced degradation in MOSFET’s,” IEEE Electron Device Lett.,
vol. EDL-5, no. 5, pp. 148–150, May 1984, doi: 10.1109/EDL.
1984.25865.
[10] K. Mistry and B. Doyle, “The role of electron trap creation in enhanced
hot-carrier degradation during AC stress (n-channel MOSFET),” IEEE
Electron Device Lett., vol. 11, no. 6, pp. 267–269, Jun. 1990, doi:
10.1109/55.55276.
[11] S. Mahapatra, D. Saha, D. Varghese, and P. B. Kumar, “On the
generation and recovery of interface traps in MOSFETs subjected to
NBTI, FN, and HCI stress,” IEEE Trans. Electron Devices, vol. 53,
no. 7, pp. 1583–1592, Jul. 2006, doi: 10.1109/TED.2006.876041.
[12] W. Arfaoui et al., “Energy-driven hot-carrier model in advanced nodes,”
in Proc. IEEE Int. Rel. Phys. Symp., Jun. 2014, pp. XT.12.1–XT.12.5,
doi: 10.1109/IRPS.2014.6861189.
[13] D. Varghese, P. Moens, and M. A. Alam, “On-state hot carrier
degradation in drain-extended NMOS transistors,” IEEE Trans. Elec-
tron Devices, vol. 57, no. 10, pp. 2704–2710, Oct. 2010, doi:
10.1109/TED.2010.2059632.
[14] T. Kamata, K. Tanabashi, and K. Kobayashi, “Substrate current due to
impact ionization in MOS-FET,” Jpn. J. Appl. Phys., vol. 15, no. 6,
pp. 1127–1133, Jun. 1976.
[15] K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-
channel MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-30, no. 8,
pp. 871–876, Aug. 1983, doi: 10.1109/T-ED.1983.21229.
[16] K. R. Hofmann, C. Werner, W. Weber, and G. Dorda, “Hot-electron
and hole-emission effects in short n-channel MOSFET’s,” IEEE Trans.
Electron Devices, vol. ED-32, no. 3, pp. 691–699, Mar. 1985, doi:
10.1109/T-ED.1985.22000.
Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
11
[17] E. Takeda, A. Shimizu, and T. Hagiwara, “Role of hot-hole injection in
hot-carrier effects and the small degraded channel region in MOSFET’s,”
IEEE Electron Device Lett., vol. EDL-4, no. 9, pp. 329–331, Sep. 1983,
doi: 10.1109/EDL.1983.25751.
[18] P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, “Consis-
tent model for the hot-carrier degradation in n-channel and p-channel
MOSFETs,” IEEE Trans. Electron Devices, vol. ED-35, no. 12,
pp. 2194–2209, Dec. 1988, doi: 10.1109/16.8794.
[19] P. Heremans, G. Van den Bosch, R. Bellens, G. Groeseneken, and
H. E. Maes, “Temperature dependence of the channel hot-carrier degra-
dation of n-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 37,
no. 4, pp. 980–993, Apr. 1990, doi: 10.1109/16.52433.
[20] V.-H. Chan and J. E. Chung, “Two-stage hot-carrier degradation and its
impact on submicrometer LDD NMOSFET lifetime prediction,” IEEE
Trans. Electron Devices, vol. 42, no. 5, pp. 957–962, May 1995, doi:
10.1109/16.381994.
[21] A. Raychaudhuri, M. J. Deen, W. S. Kwan, and M. I. H. King,
“Features and mechanisms of the saturating hot-carrier degradation
in LDD NMOSFETs,” IEEE Trans. Electron Devices, vol. 43, no. 7,
pp. 1114–1122, Jul. 1996, doi: 10.1109/16.502423.
[22] S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan, and J. Vasi,
“A comprehensive study of hot-carrier induced interface and oxide trap
distributions in MOSFETs using a novel charge pumping technique,”
IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 171–177, Jan. 2000,
doi: 10.1109/16.817583.
[23] S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan, and
J. Vasi, “Device scaling effects on hot-carrier induced interface and
oxide-trapped charge distributions in MOSFETs,” IEEE Trans. Electron
Devices, vol. 47, no. 4, pp. 789–796, Apr. 2000, doi: 10.1109/16.830995.
[24] T. Tsuchiya, T. Kobayashi, and S. Nakajima, “Hot-carrier-injected oxide
region and hot-electron trapping as the main cause in Si nMOS-
FET degradation,” IEEE Trans. Electron Devices, vol. ED-34, no. 2,
pp. 386–391, Feb. 1987, doi: 10.1109/T-ED.1987.22934.
[25] T. Tsuchiya, “Trapped-electron and generated interface-trap effects
in hot-electron-induced MOSFET degradation,” IEEE Trans. Electron
Devices, vol. ED-34, no. 11, pp. 2291–2296, Nov. 1987, doi: 10.1109/T-
ED.1987.23234.
[26] B. S. Doyle et al., “The generation and characterization of electron and
hole traps created by hole injection during low gate voltage hot-carrier
stressing of n-MOS transistors,” IEEE Trans. Electron Devices, vol. 37,
no. 8, pp. 1869–1876, Aug. 1990, doi: 10.1109/16.57138.
[27] B. Doyle, M. Bourcerie, J.-C. Marchetaux, and A. Boudou, “Interface
state creation and charge trapping in the medium-to-high gate voltage
range (Vd /2 ≥ Vg ≥ Vd ),” IEEE Trans. Electron Devices, vol. 37, no. 3,
pp. 744–754, Mar. 1990, doi: 10.1109/16.47781.
[28] C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill,
“Hot-electron-induced MOSFET degradation–model, monitor, and
improvement,” IEEE J. Solid-State Circuits, vol. SSC-20, no. 1,
pp. 295–305, Feb. 1985, doi: 10.1109/JSSC.1985.1052306.
[29] S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL flash EEPROM.
I. Performance and scaling,” IEEE Trans. Electron Devices, vol. 49,
no. 7, pp. 1296–1301, Jul. 2002, doi: 10.1109/TED.2002.1013289.
[30] K. F. Schuegraf and C. Hu, “Hole injection SiO2 breakdown model for
very low voltage lifetime extrapolation,” IEEE Trans. Electron Devices,
vol. 41, no. 5, pp. 761–767, May 1994, doi: 10.1109/16.285029.
[31] M. A. Alam, J. Bude, and A. Ghetti, “Field acceleration for oxide
breakdown-can an accurate anode hole injection model resolve the
E vs. 1/E controversy?” in Proc. IEEE 38th Annu. Int. Rel. Phys.
Symp., San Jose, CA, USA, Apr. 2000, pp. 21–26, doi: 10.1109/REL
PHY.2000.843886.
[32] P. Heremans, H. E. Maes, and N. Saks, “Evaluation of hot carrier degra-
dation of N-channel MOSFET’s with the charge pumping technique,”
IEEE Electron Device Lett., vol. EDL-7, no. 7, pp. 428–430, Jul. 1986.
[33] A. Chasm et al., “Hot-carrier analysis on nMOS Si FinFETs with
solid source doped junction,” in Proc. IEEE Int. Rel. Phys. Symp.
(IRPS), Pasadena, CA, USA, Apr. 2016, pp. 4B-4–4B-4B-4-6, doi:
10.1109/IRPS.2016.7574535.
[34] E. Li, E. Rosenbaum, J. Tao, G. C.-F. Yeap, M. Lin, and P. Fang, “Hot
carrier effects in nMOSFETs in 0.1 μm CMOS technology,” in Proc.
IEEE 37th Annu. Int. Rel. Phys. Symp., San Diego, CA, USA, Mar. 1999,
pp. 253–258, doi: 10.1109/RELPHY.1999.761622.
[35] S. J. Wang, J. M. Sung, and S. A. Lyon, “Relationship between hole
trapping and interface state generation in metal-oxide-silicon structures,”
Appl. Phys. Lett., vol. 52, no. 17, pp. 1431–1433, Apr. 1988, doi:
10.1063/1.99690.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12
[36] Z. Chen et al., “On the mechanism for interface trap generation in MOS
transistors due to channel hot carrier stressing,” IEEE Electron Device
Lett., vol. 21, no. 1, pp. 24–26, Jan. 2000, doi: 10.1109/55.817441.
[37] C. Min-Liang, L. Chung-Wai, W. T. Cochran, W. Jungling, C. Dziuba,
and Y. Tungsheng, “Suppression of hot-carrier effects in submicrometer
CMOS technology,” IEEE Trans. Electron Devices, vol. ED-35, no. 12,
pp. 2210–2220, Dec. 1988, doi: 10.1109/16.8795.
[38] K.-L. Chen, S. A. Saller, I. A. Groves, and D. B. Scott, “Reliability
effects on MOS transistors due to hot-carrier injection,” IEEE Trans.
Electron Devices, vol. ED-32, no. 2, pp. 386–393, Feb. 1985, doi:
10.1109/T-ED.1985.21953.
[39] A. Joshi and D.-L. Kwong, “Study of the growth temperature depen-
dence of performance and reliability of thin MOS gate oxides,” IEEE
Trans. Electron Devices, vol. 39, no. 9, pp. 2099–2107, Sep. 1992, doi:
10.1109/16.155883.
[40] J.-S. Goo, Y.-G. Kim, H. L’Yee, H.-Y. Kwon, and H. Shin, “An analytical
model for hot-carrier-induced degradation of deep-submicron n-channel
LDD MOSFETs,” Solid-State Electron., vol. 38, no. 6, pp. 1191–1196,
1995, doi: 10.1016/0038-1101(94)00221-Z.
[41] C.-L. Lou, W.-K. Chim, D. S.-H. Chan, and T. Pan, “A novel
single-device DC method for extraction of the effective mobility
and source-drain resistances of fresh and hot-carrier degraded drain-
engineered MOSFET’s,” IEEE Trans. Electron Devices, vol. 45, no. 6,
pp. 1317–1323, Jun. 1998, doi: 10.1109/16.678559.
[42] S. Mukhopadhyay et al., “Trap generation in IL and HK layers
during BTI/TDDB stress in scaled HKMG N and P MOSFETs,” in
Proc. IEEE Int. Rel. Phys. Symp., Waikoloa, HI, USA, Jun. 2014,
pp. GD.3.1–GD.3.11, doi: 10.1109/IRPS.2014.6861146.
[43] W. Arfaoui, X. Federspiel, A. Bravaix, P. Mora, A. Cros, and D. Roy,
“Application of compact HCI model to prediction of process effect in
28FDSOI technology,” in Proc. IEEE Int. Integr. Rel. Workshop Final
Rep. (IIRW), South Lake Tahoe, CA, USA, Oct. 2014, pp. 69–72, doi:
10.1109/IIRW.2014.7049513.
[44] A. Bravaix et al., “Impact of the gate-stack change from 40 nm node
SiON to 28 nm high-K metal gate on the hot-carrier and bias tempera-
ture damage,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Anaheim,
CA, USA, Apr. 2013, pp. 2D.6.1–2D.6.9, doi: 10.1109/IRPS.2013.
6531961.
[45] C. Guerin, V. Huard, and A. Bravaix, “The energy-driven hot-carrier
degradation modes of nMOSFETs,” IEEE Trans. Device Mater. Rel.,
vol. 7, no. 2, pp. 225–235, Jun. 2007, doi: 10.1109/TDMR.2007.
901180.
[46] T. Di Gilio and A. Bravaix, “Lifetime prediction of ultra-thin gate
oxide PMOSFETs submitted to hot hole injections,” in Proc. IEEE Int.
Integr. Rel. Workshop, S. Lake Tahoe, CA, USA, Oct. 2005, p. 5, doi:
10.1109/IRWS.2005.1609562.
[47] P. Magnone et al., “Impact of hot carriers on nMOSFET variability in 45-
and 65-nm CMOS technologies,” IEEE Trans. Electron Devices, vol. 58,
no. 8, pp. 2347–2353, Aug. 2011, doi: 10.1109/TED.2011.2156414.
[48] M. Bina et al., “Predictive hot-carrier modeling of n-channel MOS-
FETs,” IEEE Trans. Electron Devices, vol. 61, no. 9, pp. 3103–3110,
Sep. 2014, doi: 10.1109/TED.2014.2340575.
[49] A. Kerber, S. Cimino, F. Guarin, and T. Nigam, “Assessing device
reliability margin in scaled CMOS technologies using ring oscillator cir-
cuits,” in Proc. IEEE Electron Devices Technol. Manuf. Conf. (EDTM),
Feb. 2017, pp. 28–30, doi: 10.1109/EDTM.2017.7947495.
[50] C. Schlunder et al., “Circuit relevant HCS lifetime assessments
at single transistors with emulated variable loads,” in Proc. IEEE
Int. Rel. Phys. Symp. (IRPS), Apr. 2017, pp. 2D-2.1–2D-2.7, doi:
10.1109/IRPS.2017.7936262.
[51] M. Duan et al., “Interaction between hot carrier aging and PBTI
degradation in nMOSFETs: Characterization, modelling and lifetime
prediction,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Monterey,
CA, USA, Apr. 2017, pp. XT-5.1–XT-5.7, doi: 10.1109/IRPS.2017.
7936419.
[52] A. Kerber and E. A. Cartier, “Reliability challenges for CMOS tech-
nology qualifications with hafnium oxide/titanium nitride gate stacks,”
IEEE Trans. Device Mater. Rel., vol. 9, no. 2, pp. 147–162, Jun. 2009,
doi: 10.1109/TDMR.2009.2016954.
[53] S. Mukhopadhyay et al., “Trap generation in IL and HK layers
during BTI/TDDB stress in scaled HKMG N and P MOSFETs,” in
Proc. IEEE Int. Rel. Phys. Symp., Waikoloa, HI, USA, Jun. 2014,
pp. GD.3.1–GD.3.11, doi: 10.1109/IRPS.2014.6861146.
[54] E. Amat et al., “Channel hot-carrier degradation in short chan-
nel devices with high-k/metal gate stacks,” in Proc. Spanish
Conf. Electron Devices, Santiago de Compostela, Spain, Feb. 2009,
pp. 238–241.
Authorized licensed use limited to: University of Exeter. Downloaded on June 09,2020 at 15:01:54 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON ELECTRON DEVICES
[55] X. Federspiel, F. Cacho, and D. Roy, “Experimental characterization of
the interactions between HCI, off-state and BTI degradation modes,” in
Proc. IEEE Int. Integr. Rel. Workshop Final Rep., South Lake Tahoe,
CA, USA, Oct. 2011, pp. 133–136.
[56] W. Arfaoui, X. Federspiel, P. Mora, M. Rafik, D. Roy, and A. Bravaix,
“Experimental analysis of defect nature and localization under hot-
carrier and bias temperature damage in advanced CMOS nodes,” in Proc.
IEEE Int. Integr. Rel. Workshop Final Rep., Oct. 2013, pp. 78–83, doi:
10.1109/IIRW.2013.6804163.
[57] S. Mahapatra and R. Saikia, “On the universality of hot carrier
degradation: Multiple probes, various operating regimes, and different
MOSFET architectures,” IEEE Trans. Electron Devices, vol. 65, no. 8,
pp. 3088–3094, Aug. 2018, doi: 10.1109/TED.2018.2842129.
[58] S. E. Rauch and G. La Rosa, “The energy-driven paradigm of NMOS-
FET hot-carrier effects,” IEEE Trans. Device Mater. Rel., vol. 5, no. 4,
pp. 701–705, Dec. 2005, doi: 10.1109/TDMR.2005.860560.
[59] J. H. Stathis and E. Cartier, “Atomic hydrogen reactions with Pb centers
at the (100) Si/SiO2 interface,” Phys. Rev. Lett., vol. 25, pp. 2745–2748,
Apr. 1994, doi: 10.1103/PhysRevLett.72.2745.
[60] A. Stesmans, “Passivation of Pb0 and Pb1 interface defects in thermal
(100) Si/SiO2 with molecular hydrogen,” Appl. Phys. Lett., vol. 68,
no. 15, pp. 2076–2078, Apr. 1996, doi: 10.1063/1.116308.
[61] G. Pobegen, M. Nelhiebel, and T. Grasser, “Detrimental impact
of hydrogen passivation on NBTI and HC degradation,” in Proc.
IEEE Int. Rel. Phys. Symp. (IRPS), Anaheim, CA, USA, Apr. 2013,
pp. XT.10.1–XT.10.6.
[62] K. Joshi et al., “HKMG process impact on N, P BTI: Role of ther-
mal IL scaling, IL/HK integration and post HK nitridation,” in Proc.
IEEE Int. Rel. Phys. Symp. (IRPS), Anaheim, CA, USA, Apr. 2013,
pp. 4C.2.1–4C.2.10.
[63] C. Prasad et al., “Self-heat reliability considerations on Intel’s 22 nm tri-
gate technology,” in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), Anaheim,
CA, USA, Apr. 2013, pp. 5D.1.1–5D.1.5.
[64] D. Varghese et al., “Off-state degradation in drain-extended NMOS tran-
sistors: Interface damage and correlation to dielectric breakdown,” IEEE
Trans. Electron Devices, vol. 54, no. 10, pp. 2669–2678, Oct. 2007.
[65] S. Chakravarthi, A. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan,
“A comprehensive framework for predictive modeling of negative bias
temperature instability,” in Proc. IEEE Int. Rel. Phys. Symp., Phoenix,
AZ, USA, Apr. 2004, pp. 273–282.
[66] T.-C. Ong, M. Levi, P.-K. Ko, and C. Hu, “Recovery of threshold voltage
after hot-carrier stressing,” IEEE Trans. Electron Devices, vol. ED-35,
no. 7, pp. 978–984, Jul. 1988, doi: 10.1109/16.3354.
[67] D. Varghese, D. Saha, S. Mahapatra, K. Ahmed, F. Nouri, and M. Alam,
“On the dispersive versus arrhenius temperature activation of NBTI time
evolution in plasma nitrided gate oxides: Measurements, theory, and
implications,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2005,
pp. 684–687, doi: 10.1109/IEDM.2005.1609444.
[68] E. de Schrijver, P. Heremans, R. Bellens, G. Groeseneken, and
H. E. Maes, “Analysis of post-stress effects in passivated MOSFET’s
after hot-carrier stress,” in Proc. 21st Eur. Solid State Device Res.
Conf. (ESSDERC), Montreux, Switzerland, 1991, pp. 437–440, doi:
10.1016/0167-9317(91)90259-G.
[69] N. S. Saks and D. B. Brown, “Interface trap formation via the two-stage
H+ process,” IEEE Trans. Nucl. Sci., vol. 36, no. 6, pp. 1848–1857,
Dec. 1989, doi: 10.1109/23.45378.
[70] S. Ling, A.-M. El-Sayed, F. Lopez-Gejo, M. B. Watkins, V. V. Afanas’ev,
and A. L. Shluger, “A computational study of Si–H bonds as pre-
cursors for neutral E’ centres in amorphous silica and at the Si/SiO2
interface,” Microelectron. Eng., vol. 109, pp. 310–313, Sep. 2013, doi:
10.1016/j.mee.2013.03.028.
[71] M. Masuduzzaman, A. E. Islam, and M. A. Alam, “Physics and mech-
anisms of dielectric trap profiling by multi-frequency charge pumping
(MFCP) method,” in Proc. IEEE Int. Rel. Phys. Symp., Montreal, QC,
Canada, Apr. 2009, pp. 13–20, doi: 10.1109/IRPS.2009.5173218.
[72] D. Ielmini, A. S. Spinelli, M. A. Rigamonti, and A. L. Lacaita,
“Modeling of SILC based on electron and hole tunneling. II. steady-
state,” IEEE Trans. Electron Devices, vol. 47, no. 6, pp. 1266–1272,
Jun. 2000, doi: 10.1109/16.842972.
[73] M. A. Alam, “SILC as a measure of trap generation and predictor of
T B D in ultrathin oxides,” IEEE Trans. Electron Devices, vol. 49, no. 2,
pp. 226–231, Feb. 2002, doi: 10.1109/16.981211.
[74] E. Y. Wu, J. Sune, and W. Lai, “On the Weibull shape factor of intrinsic
breakdown of dielectric films and its accurate experimental determina-
tion. Part II: Experimental results and the effects of stress conditions,”
in IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2141–2150,
Dec. 2002.