1.

Introductions:
Since the launch of the first artificial satellite, Sputnik 1, by the Soviet Union in 1957,
satellites have found many applications that have benefited large segments of the world
population. For example, Ariane 5 and GOES-16 satellites have been used for
telecommunications and weather forecasting respectively, both of which are technologies that
modern life heavily depends on. However, these traditional satellites have been limited in
their scalability due to their exorbitant costs. With recent miniaturisation of computers and
other hardware, hundreds of satellites are being launched into space every year at a fraction
of the cost. This has significantly reduced the barrier to entry into space for both commercial
and military applications. Satellites offer a unique vantage point with unobstructed lines of
sight and communication for various remote sensing tasks as well as reconnaissance
missions. The computational demands on spacecraft are rapidly increasing. The complexity
of satellites has continued to increase, and the focus of satellite competition has shifted from
the launch of success to communication capacity, performance indicators, degree of
flexibility, and continuous service capabilities. So, the importance of onboard avionics
system is becoming increasingly prominent. In the future, the advanced avionics system to
integrates most of the platform’s electronic equipment. The design level of the system largely
determines the performance of the satellite platform. Current on-board computing
components and architectures cannot keep up with the growing requirements. Only a small
selection of space-qualified processors and FPGAs are available and current architectures
stick with the inflexible cold redundant structure. With the continuous advancement of
electronics and computer technology, the functions and performance of spacecraft avionics
system have also continuously improved, covering functions such as spacecraft remote
measurement and remote management, energy management, thermal management, health
management, payload information processing, and mission task management. Avionics
system plays a core role in the realization of information sharing and comprehensive
utilization, function integration, resource reorganization and optimization, and information
processing and transmission [1]. Avionics of the spacecraft’s is the foundation for spacecraft
to implement autonomous management and control and is also a bridge for communication
management from a spacecraft to other spacecrafts and ground station [2].
Potential missions could include critical applications like spacecraft avionics or payload data
handling. The two applications have quite different requirements on the on-board computer
architecture. On the one hand control tasks need a very high reliability and have strict timing
constraints. On the other hand, payload processing can be computationally intensive without
the requirement to finalize processing at a tight deadline. An application combining both
extremes could be a navigation and guidance system based on complex computer vision
algorithms. To fulfil all these requirements, we need a scalable system, which can be easily
adapted to different mission.
Current space-qualified computing technology must be configured around the part of a
mission that requires the most power – a practice which targets mission success but leads to
inefficient use of resources over the lifetime of a mission. For example, a Mars/Lunar surface
mission has extreme needs for high-speed data movement and intense calculation, as well as
stringent fault tolerance, during the planetary landing sequence. The flight computer must be
configured to meet these needs, which draws significant power and other resources.
However, once safely landed, routine mobility and science operations may rarely need that
same level of capability, at least not in a sustained manner. Night time operations can require
even less resources. By improved design it can offer the flexibility for the computing
processing power to subside and flow depending on the mission and operational
requirements. This will save a large amount of energy and improve overall computing
efficiency.
Because of this energy saving and increased computing efficiency, this high-performing
computing chip will benefit many areas of spaceflight operations, including extreme terrain
landing, managing a vehicle’s health, automated guidance, navigation and control,
autonomous and telerobotic construction, and more. Because all types of ISRO missions
require computing capabilities, then the updated design could benefit all of ISRO’s future
undertakings, from earth science missions, to deep space missions, to human spaceflight.
Future ISRO space mission scenarios require an improved computing system with
significantly expanded computational performance and more efficient use of energy. While
up until now, a mission has had a limited number of functions and goals, this new paradigm
would allow us to rethink satellites as reconfigurable for different missions. Several
applications could be run simultaneously on-board or the same satellite could be re-used for
different functions. With that, the hardware would no longer be dedicated to one specific
mission. Moreover, the concept of using satellites as a service is slowly gaining in popularity.
The idea behind it is to run applications on the satellites, where users can access the data in
real-time. A further idea is to use multiple satellites in a constellation for running algorithms
in AI, with the purpose of increasing the available processing power.
With a growing demand for edge computing, there has been a surge in the availability of off-
the-shelf hardware platforms and frameworks that support model compression and hardware
acceleration. The key metrics that determine the choice of hardware platforms for a given
application are the floating-point operations (FLOPs), memory requirements and performance
per watt of the model. The choice of AI-ML development framework follows from the choice
of hardware, which determines the operating system capable of being flashed onto the
hardware.

2. Background on the workload of high-performance computations

on spacecraft’s on-board processing
High performance on-board processing can be applied both on a payload and platform level
of a satellite respectively. Payload applications are linked to the instruments that promote the
satellite’s primary function to fulfil a mission’s goals. The platform or operations system on
the other hand, ensures the satellite’s functioning and well-being, and high-performance
efficient algorithms could be applied on a system or subsystem level therein. The following
sections show a comprehensive but non-exhaustive overview of possible application areas of
high performance computing on-board satellites, divided into the two aforementioned
categories. As this overview is non-exhaustive, the aim is not to show a complete compilation
of applications, but rather to give an idea of the vastness of the applicability of processing on-
board computation. It is also important to keep in mind that some of these have been applied
on-board satellites already, while others have not yet been developed.

2.1 Computing applications for a satellite payload

Figure 1 gives an overview of possible payload applications with high performance on-board
processing power. The vast majority of applications in this category is linked to Earth
observation, which along with space observation falls under remote sensing and is typically
based on image processing. On the one hand, intelligence on-board autonomy can assist with
monitoring of the atmosphere, for instance for making weather predictions. On the other
hand, ground cover can be classified, in order to map different land covers, which can be of
interest from a political point of view. Additionally, change detection is an important
application area. This includes the detection of illegal forest cutting or changes in the ice
caps. Disaster relief is a further possible use case and includes the early detection and
notification of wildfires or floods. Finally, object detection finds an important application in
maritime safety and vessel surveillance, but also, for detection of aircraft and buildings and
the movement across the border with neighbouring countries. Closely linked to payload
imaging instruments is instrument calibration, where high performance computing could be
applied for tasks including focal plane calibration and adaptive optics [3]. Object detection as
part of space observation on the other hand, could involve the early detection of meteoroids,
that could otherwise potentially cause harm to the Earth. Another important area of
application for processing with high performance computing on-board satellites is space
radiation monitoring, which is used for acquiring insight knowledge on current and future
radiation levels, predominantly originating from the Sun, as this can have a detrimental
impact on ground-based networks. High performance computing could increase the data
acquisition rate at times of high activity and enable early notification of radiation levels when
these surpass a certain threshold. Finally, some satellites have navigation-based tasks as part
of their mission goal, such as the removal of debris, which is why this is included as a
payload application.

Figure 1: Payload computation requirements

2.2 Computing applications for a satellite platform

Platform applications for which high performance computing could be used are in turn
presented in figure 2. As can be seen from this figure, platform applications can be boiled
down to applications promoting autonomous operation of the satellite. This involves on the
one hand attitude determination with autonomous, onboard intelligence-based star
identification. Alternatively, high performance vision-based computing could be used for
navigation. For example, it could be used for collision avoidance, given the presence of space
debris and other satellites. Further vision-based tasks linked to navigation include
manoeuvres such as rendezvous and docking, but also slew manoeuvres. Finally, a topic of
relevance given the emergence of satellite constellations is relative position keeping, which
provides awareness of a satellite’s relative position with regard to its surrounding ones.
Alternatively, on-board computing could be used with health management of different
subsystems. This could include the detection, isolation and recovery of faults, but also early
prediction thereof. Finally, another application area with many different use cases is
communication, these find good use with the rise of satellite constellations, for instance using
high performance computing with routing, but also given the increased traffic in LEO.

Figure 2: Computation loads of the spacecrafts.

For the latter, network traffic forecasting and automated ground station scheduling could be
greatly optimized with AI. Likewise, beam hopping and anti-jamming, but also parameter
optimization in Software-Defined Radios (SRDs) could be formidable use cases of high-
performance computing on-board satellites [4].

3. Major challenging applications of on-board computation

Among all the applications mentioned above, following two are the major computation
intensive applications for onboard processors.

3.1 In-orbit servicing: Active space debris removal

VISION-BASED navigation (VBN) endows robotic systems with the ability to guide
themselves autonomously in an unknown environment by using active or passive image
sensors to perceive their surroundings. Vision applications in space vary from rover
exploration on Mars with simultaneous localization and mapping to moon landing with
landmark tracking and hazard avoidance, and to spacecraft proximity operations with pose
estimation of cooperative or uncooperative orbiting targets. However, the ever-increasing
computational demands of these enabling technologies are now challenging classical onboard
computing, both in terms of architecture and processing power. One example where this
becomes especially apparent concerns active debris removal (ADR) scenarios, whose aim is
to actively remove heavy debris objects by capturing them and then either disposing them by
destructive re-entry in the atmosphere or moving them to graveyard orbits [5]. Another
examples is In-Orbit Servicing (IOS) refers to extending the life or functionalities of
spacecraft that are already in orbit. This can be done by performing maintenance, adjusting a
spacecraft’s orbit, changing the direction it is facing, providing more fuel, or even changing
or upgrading the instruments onboard. In future ADR missions, chaser spacecraft must rely,
among others, on high-definition cameras and complex computer vision algorithms
performing image feature extraction, matching, three-dimensional (3-D) reconstruction,
tracking, etc., at high frame rates. Advanced image processing systems and complex
guidance, navigation, and control (GNC) will become the enabling building blocks in ADR,
as well as in similar future space proximity operations such as inspection, in-orbit servicing,
cargo and satellite delivery, space tug, in-orbit structure assembly, etc. [6–9]. Novel image
processing will be combined with data fusion from a number of sensors providing
information on the sun, earth, stars, spacecraft inertia, etc., to feed the control algorithms and
provide dependable autonomous navigation. However, adjectives such as “advanced”,
“complex”, and “autonomous” conceal increased processing workloads and decreased time
budgets. Put into perspective, conventional space-grade processors, such as LEON3 and
RAD750, can provide only a very limited level of performance (e.g., 50–400 Dhrystone
million instructions per second, or DMIPS), whereas the COTS desktop central processing
units (CPUs) used by algorithm designers during the early development stages of VBN
techniques provide 10–100x more speed when processing images. Even with the latest space-
grade devices, such as LEON4 and RAD5545 that achieve 10x more speed compared to their
predecessors, or even with embedded COTS processors, the current onboard CPU
performance seems to be one order of magnitude less than that necessary to execute
computationally expensive vision algorithms at adequate frame rates. Therefore, to support
reliable autonomous VBN, we should consider advancing the space avionics architectures by
including hardware accelerators, such as field-programmable gate arrays (FPGAs), graphics
processing units (GPUs), or multicore very long instruction word (VLIW) DSP processors.
That is, in short, use VLIWs or GPUs consisting of a number of cores able to execute bigger
or smaller instructions and facilitate data parallelization. In contrast, the FPGAs consist of a
network of much smaller processing/storage elements (such as flip-flops), which can be
combined altogether to create bigger components with very deep pipelining and
parallelization at multiple levels.
Designing new high-performance avionics architectures for embedded computing becomes
particularly challenging when one is also required to meet stringent constraints related to
space. The spacecraft resources available to electronic systems are restricted, with the three
most critical limiting factors being mass, power, and volume. Power availability in space is
low due to solar powering and power dissipation capabilities, whereas volume and mass have
enormous costs per unit. Furthermore, the engineers must factor in reconfigurability,
application-design complexity, fault/radiation tolerance, vibration tolerance, component
pricing, etc. Last but not least, one of the most crucial factors is the achieved processing
power, all of the aforementioned parameters are competing against each other in a mission-
specific trade-off manner, which becomes even more complex when the types of the
aforementioned hardware accelerators are included in the architecture.

3.2 Onboard Powered-Descent Guidance

SOFT landing on other planetary bodies generally requires powered-descent guidance (PDG)
to plan a trajectory onboard a lander for the final kilometers of descent to landing on rocket
engines. It is emphasized that “guidance” in this context means planning a reference
trajectory for a control system, including feedforward control. The powered-descent
trajectory must be planned onboard because the state of the lander at the start of powered
descent cannot be adequately predicted beforehand due to atmospheric uncertainties and/or
the limits of deep space navigation. Generally, a lateral divert is included in powered descent,
for example, to land away from a parachute, to avoid a known hazard in the landing ellipse
(such as a hill or inescapable crater), or to reach a specific pinpoint destination (such as a
habitation module). Future precision-landing missions to Mars could require lateral diverts
during powered descent of 5–10km and to Europa of several kilometres. The principal
limitation of polynomial PDG is lack of constraints. As diverts become longer relative to
initial altitude, polynomial PDG can generate trajectories that exceed maximum thrust and
speed and even have subsurface “flight.” Propellant optimality is not the issue: even with
unlimited propellant, the trajectory would not be realizable in practice. As a result, longer
diverts without constraint enforcement require starting at higher altitudes, incurring a
corresponding propellant mass penalty for gravity loss and additional significant system-level
impacts (e.g., even more propellant is needed because a parachute has less time to decelerate
a lander). To address suboptimality and absence of constraints, several theoretical advances
within the last decade have shown that the fully- constrained, fuel-optimal PDG problem can
be cast as a convex optimization [10–12]. As a result, a globally fuel-optimal solution can be
used(the thrust profile to reach the destination) that satisfies all the relevant vehicle
constraints can be computed efficiently to a prescribed accuracy using interior point methods
(IPMs) [13,14]. Computation requirement for these fuel-optimal PDG problem is very high,
and required very high performance computing onboard.
Ref. [22] provides a novel, programmable accelerator architecture for general-purpose linear
algebra applications. It is designed to enable many of the architectural features typically
available in custom supercomputing machines in an accelerator form factor that can be
deployed in System-On-a-Chip (SoC) based designs1. LACore has several features, such as
heterogeneous data-streaming LAMemUnits, a configurable systolic datapath that supports
scalar, vector and multi-stream output modes, and a decoupled architecture that overlap
memory transfer and execution. The authors have implemented LACore as an extension to
the RISC-V ISA in the gem5 cycle-accurate simulator1. LACore outperforms other
platforms, such as an in-order RISC-V CPU, a superscalar x86 CPU with SSE2, and a scaled
NVIDIA Fermi GPU, in the HPCC benchmark suite by an average of 3.43x to 12.04x1.
Similar type of accelerators can be implemented for our on-board PDG applications.

3.2 Software-Defined Radios in Satellite Communications

A Software Defined Radio (SDR) is a flexible technology that enables the design of adaptive
communications systems. The interest in small satellites (or SmallSats) is continuously
growing, both in CubeSats and other customised platforms. Many universities and other
organisations around the world are investing in this type of space technology for various
applications, such as space exploration and Earth observation. When observing our planet
there are two especially relevant areas to focus on: oceans, as 71 % of the Earth is water, and
Arctic monitoring, because of the dramatic effect of global warming. In-situ monitoring of
these extremely harsh areas is difficult, expensive and they are not fully covered by
communication systems. This is one reason why it is important to research new solutions in
order to improve ocean and Arctic monitoring. One possibility is to deploy a coordinated
infrastructure composed of different types of vehicles and platforms, such as autonomous
underwater vehicles (AUVs) and a single unmanned aerial vehicles (UAVs) and and small
satellites [15].
Most importantly in addition to requirements for frequency, bandwidth and regulations found
in every communication system, Software Defined Radios (SDR) are highly dependent on the
hardware platform used to run the software. In small satellites, the main design drivers are
size, mass, cost and power consumption.

4. Different types of accelerators can be implemented for on-board

applications.

4.1 Onboard Processing in Satellite Communications

Using AI Accelerators
SATELLITE communication (SatCom) systems operations centers currently require high
human intervention, which leads to increased operational expenditure (OPEX) and implicit
latency in human action that causes degradation in the quality of service (QoS).
Consequently, new SatCom systems leverage artificial intelligence and machine learning
(AI/ML) to provide higher levels of autonomy and control. Onboard processing for advanced
AI/ML algorithms, especially deep learning algorithms, requires an improvement of several
magnitudes in computing power compared to what is available with legacy, radiation-
tolerant, space-grade processors in space vehicles today. The next generation of onboard
AI/ML space processors will likely include a diverse landscape of heterogeneous systems.
With continuing advances of modern ML technologies such as DNNs and especially
Convolutional Neural Networks, space applications can take advantage of the capabilities of
models and algorithms. This helps to extend the functionalities of on-board computers in
satellites for various applications such as, e.g., Earth observation or optical guidance,
navigation and control (GN&C). Therefore, all the Space Agencies already started working
for deploying ML workloads to on-board computers.
Deploying ML inference to on-board computers of satellites brings multiple advantages,
including saving the on-board storage, and saving the limited bandwidth between satellites
and ground stations. Additionally, it enhances the capabilities of on-board computers for
data-driven real-time decision making.
On-board decision making requires some degrees of AI to be present on-board. AI is a broad
definition, and the type of AI employed changed over time. Regardless of the level of AI
employed, AI typically implies a large amount of matrix calculations on a large set of data.
We will be mostly focussing on how to speedup matrix calculations, while handling large
data sets, which may require different solutions compared with general-purpose processors
[59] and different memory consistency models [60].
Today terrestrial applications are in a new phase where systems employ statistical learning to
adapt their behaviours to unexpected changes. This approach is typically referred to as ma-
chine learning (ML). Some terrestrial applications rely on convolutional neural networks
(CNNs). CNNs are composed of discrete time convolutions, which are basically matrix-vec-
tor products. CNNs are booming in terrestrial applications, thanks to the availability of large
data sets from “big data” and the availability of graphics processing units (GPUs) that en-
abled elaborations of large data sets in reasonable timescales [61]. This approach is typically
referred to as deep learning. GPUs have paved the way for implementations heavily based on
PLP (often the term “manycore” is employed to highlight an heavier use of PLP compared
with the “multicore” processors), employing new software models. For instance, NVIDIA re-
leased CUDA in 2007 [62], adopting a single instruction multiple thread (SIMT) model.
SIMT implementations act on data of different threads, allowing software to scale transpar-
ently to hundreds of processing cores [62].

Figure 3: Motivation for on-orbit computing. The left image (a) indicates the drawbacks of
over-reliance on cloud computing for processing satellite workloads. In addition to incurring
latency and high-power draw, it remains susceptible to interceptions by hackers. On the other
hand, the right-hand image (b) indicates that on-orbit computing can overcome these
challenges by processing at the edge without off-loading sensitive or noisy data.

4.2 Graphical Processing Units (GPU)

A graphics processing unit (GPU) is a circuit designed to manipulate graphics and images
with a highly parallelised computing structure. It was originally designed for graphical
processing and gaming. Since a lot of DL computations are inherently parallelisable, GPUs
are more efficient compared to CPUs and have been widely adopted in training deep neural
networks. In fact, growing GPU capability is the very reason for the rise of DL over the past
decade. Popular options for GPUs include the Nvidia RTX series, e.g. RTX 3090, and AMD
Radeon RX series, e.g. RX 6800, 6900 XT. Nvidia also provides the CUDA parallel
computing framework for GPU programming, which is the interface for the DL frameworks,
such as TensorFlow and PyTorch, to communicate with GPUs. In summary, GPUs are ideal
devices for DL practices on the ground. However, there are still obstacles to overcome to be
able to use them in space.
Typically, a GPU is a co-processor that receives tasks from a CPU and its main function is to
accelerate data processing. Therefore, it is typically run alongside a CPU rather than
completely on its own. Popular examples of such GPU-integrated systems on a chip (SoC)
include the Jetson Nano, TX1, TX2 and Xavier platforms 14 . However, GPU-only systems
are far more favourable for space applications. Therefore, a special type of GPU has been
developed called general purpose GPUs (GPGPUs), which can be run independently in
specialised embedded systems. The Intel Xeon Phi is a GPGPU with certain versions able to
run as a primary processor in a Linux-based operating system [16]. It stemmed from the
Larrabee project and was mainly designed for high performance computing and ML use
cases.
Despite there being no existing reports on employing GPUs alone in space, research has been
widely carried out to test their feasibility. Government and national agencies play an
important role in setting benchmarks and performing tests. Based on a NASA technical
report, GPUs and GPGPUs are tested for a range of ML-centric tasks including scientific
sensing, object tracking, obstacle identification, neural network convergence, image
processing and data compression [17]. Controlled radiation experiments were conducted
using devices such as Nvidia TX1 SoC, GTX 1050, Intel Skylake and AMD RX460.
Measurements were reported on key radiation characteristics such as the cross-section and
flux of the proton particles. Similarly, academic literature has been actively searching for
possible GPU-based solutions for space missions. Adams et al. [18] developed a high-
performance on-orbit computing system by integrating a traditional flight computer with an
existing GPU, the Nvidia Tegra X2/X2i.

4.3 Trigonometric Hardware Accelerator

For on-board applications computational tasks have become far more complex than the way
general-purpose computers can serve them. Thus, processor efficiency requirements are
becoming increasingly critical. Accelerators are extensively used for many intensive
computational tasks, reducing execution time and energy consumption. Different companies
and research groups are developing accelerators in RISC-V for various applications such as
digital signal processing, artificial intelligence, and solving mathematical algorithms.
Among heavy computational tasks, the calculation of trigonometric functions is widely used,
especially in digital signal processing algorithms of on-board sensor data processing.
However, the complexity of trigonometric algorithms makes it a problem when computing in
the digital realm. If a general-purpose processor executes the algorithms, it will break down
the algorithms into multiple simple calculations, reducing its efficiency. To cope with this
problem, an accelerator specialized in trigonometry computation is in need.

4.4 GPU SIMD accelerator/ RISC-V vector?

Due to the widespread adoption of Internet of things (IoT) and smart devices, an increasing
amount of embedded applications must deal with complex data analytics algorithms for on-
board applications. While most embedded applications involving computations with high
dynamic range are performed using binary64 (double-precision) or binary32 (single-
precision) floating-point (FP) formats, an emerging trend focuses on adapting the FP
arithmetic precision of applications according to the specific constrains of the applications or
their domains.
To trade-off the energy per operation with dynamic range and precision, the IEEE 754
specification includes a 16-bit format referred to as binary16 (half-precision). In recent years
significant advances in research have been made to exploit approximation even more
aggressively, aiming at relaxing the "always maximum precision" abstraction [19]. The most
promising approaches are moving beyond the concept of approximation alone, toward a
novel paradigm called transprecision computing [20], which aims at designing system to
deliver just the required precision for intermediate computations rather than tolerating errors
implied by imprecise HW or SW computations [21]. Recent works in this research area have
published encouraging initial results on the adoption of smaller-than-32-bit formats on
embedded systems [21].
As noted in [68], even if SIMD solutions have been successful on the consumer market, they
are a suboptimal choice for an ISA. SIMD processors are usually implemented replicating the
ALU and providing new opcodes to the ISA in order to exploit this parallelism. This makes
ISA instructions dependent on the implementation-specific degree of parallelism and new in-
structions must be added when new specific operations are needed. As a consequence, in
order to increase performance and assure backward compatibility, also the number of instruc-
tions has to increase. Under this assumption, the maximum performances for processors em-
ploying this approach have a theoretical upper limit because at some point no opcodes will be
available anymore. Moreover, when the software executes instructions with less data parallel-
ism than provided by the hardware, some of the ALUs will remain idle, and thus the hard-
ware will be underused. For these reasons, Ref. [68] proposes vector processors (based on the
concept of vector lane) as an improved version of data-parallel processors, exploiting both
spatial (ALU replication) and temporal reuse. In these platforms, the vector length and the
types of elements are configured before the operations, reducing hardware overhead and not
requiring a new instruction for each new operation supported by the hardware. RISC-V
dropped the proposal of a SIMD standard extension (P) and proposes a “Vector” (V) standard
extension (in the process of being standardized), derived by the development of the Hwacha
coprocessor [69]. The “V” extension aims to be flexible and reconfigurable for different data
types and sizes on the run, with the goal to support both implicit auto vectorization in
(OpenMP) and explicit SPMD (OpenCL). As the capability of autonomous decision making
becomes crucial in many applications, vector lanes in processors could be as common in the
future as FPUs are today.

4.5 Matrix multipliers?

The task of multiplying two matrices is one of the most fundamental problems in linear
algebra. Matrix multiplication (MM) plays pivotal role in various engineering
applications and scientific computations, like digital image processing, digital signal
processing (DSP), computer graphics, radar, sonar, multimedia, and sensor data processing.
Moreover, MM is the basic key for many other challenging problems related to matrix, like
calculation of Nth power, inverse, determinant, eigenvalues, characteristic polynomial etc.
So, the implementation of a high speed, area efficient matrix multiplier processor design is
still a timely demand for the on-board applications. Owing to the requirement of large scale
of operations, ranging from large amount of multiplications to additions, it is a challenging
task to implement a high-speed matrix multiplier design. The growing use of Machine
Learning (ML) or DNN models in wide range of applications has increased the demand to
run the DNN/ML models more efficiently. There is, thus the need to improve the model’s
efficiency from the hardware and software point of view. As discussed earlier, the efficiency
of the DNN models can be improved by Quantizing, Pruning and Approximation techniques.
These methods compress the models and reduce the memory footprint and computation time.
Traditionally the ML/DNN models are run in GPGPU (General Purpose Graphical
Processing Unit) because of its parallelism and easy programmability. But GP-GPUs are
inefficient in running these compressed models as efficiently as compared to hardware built
to support these compressed models. We can implement accelerator which support variable
bit precision in the hardware to support machine learning/Deep Neural Network tasks such as
Dedicated Accelerators (ASIC), FPGA Based Accelerators with RISC-V ISA Extensions.

5. Modular RISC-V for space applications:

Some of the benefits of using RISC-V in space are:
- Openness: RISC-V is an open ISA that allows anyone to use, modify, and extend it without
paying royalties or licenses. This enables the use of existing software tools and ecosystems
for developing and testing RISC-V processors. It also fosters innovation and collaboration
among different stakeholders in the RISC-V community¹.
- Modularity: RISC-V is designed to be modular, meaning that it can be customized to meet
specific needs and requirements. The ISA consists of a base integer instruction set (RV32I)
and optional extensions for floating-point (RV32F), vector (RV64IMAFDC), compressed
instructions (RV64C), packed SIMD (RV64GC), atomic operations (RV64A), bit
manipulation (RV64B), etc. The extensions can be enabled or disabled depending on the
application domain¹. The microarchitecture can also be tailored to optimize performance,
power consumption, area, or reliability².
- Flexibility: RISC-V supports different privilege modes (M, S, U) that allow fine-grained
control over access rights and security features. It also supports different instruction formats
(32-bit or 64-bit) that can be used for different data types and operations. Moreover, it
supports various addressing modes (immediate, register indirect, direct, base register indirect)
that can be used for different memory operands¹.
- Performance: RISC-V processors can achieve high performance by using advanced
techniques such as pipelining, superscalar execution, out-of-order execution, branch
prediction, cache coherence protocols, etc. Several open-source implementations of RISC-V
processors have been developed for terrestrial applications that demonstrate high
performance in terms of speedup factors over proprietary processors¹.

Some of the challenges of using RISC-V in space are:

- Fault tolerance: Space systems are exposed to harsh environments such as radiation,
temperature extremes, vibration, shock waves, etc. These factors can cause errors or failures
in the hardware components or software systems. Therefore, space processors need to be
designed with fault tolerance mechanisms that can detect and correct errors without
compromising functionality or safety².
- Technology readiness level: Space systems are subject to strict regulations and standards
regarding reliability and quality. Therefore, space processors need to meet certain technology
readiness levels (TRLs) that indicate their maturity and suitability for space applications.
TRLs are defined by ESA's Space Systems Life Cycle Management Framework². However,
there is no clear definition or agreement on what constitutes a TRL for space processors
based on RISC-V.
- Integration: Space systems often involve complex integration challenges such as power
management, thermal management, communication protocols, data formats standardization
etc. These challenges require coordination among different subsystems and interfaces within
a space system. Therefore, space processors need to support interoperability with other
components such as sensors, actuators, controllers, etc. that may use different ISAs or
technologies.

Some of the examples of using RISC-V in space are:

- Delft University of Technology has proposed a roadmap for leveraging the openness and
modularity of RISC-V in space applications across the full range of requirements from low-
power microcontrollers up to high-end payload processors for artificial intelligence
applications. The roadmap identifies four types of processors based on their area/power
requirements: low-area/low-power microcontrollers, on-board computers, general-purpose
processors for payloads, and enhanced payload processors for artificial intelligence. The
roadmap also compares several solutions based on RISC-V with proprietary commercial-off-
the-shelf and space-grade solutions and shows their potential benefits and drawbacks for each
type of processor. The roadmap also discusses some open issues and future directions for
developing and validating RISC-V-based processors for space applications.
- In the paper [23] on the openness and modularity of RISC-V in space applications that
presents ESA's roadmap for RISC-V-based processors. The paper describes some existing
projects and initiatives that aim to develop and demonstrate RISC-V-based processors for
various domains such as navigation, communication, science, etc. The paper also outlines
some key challenges and opportunities for advancing the adoption of RISC-V in space
systems.

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