Instruction: A computer instruction is a binary code that specifies a sequence of

micro operations for the computer. Instruction codes together with data are stored
in memory. The computer reads each instruction from memory and places it in a
control register. The control then interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of micro operations. Every computer
has its own unique instruction set
An instruction code is a group of bits that instruct the computer to perform a
specific operation. It is usually divided into parts, each having its own particular
interpretation. The most basic part of an instruction code is its operation part. The
operation code of an instruction is a group of bits that define such operations as
add, subtract, multiply, shift, and complement. The number of bits required for the
operation code of an instruction depends on the total number of operations
available in the computer

Instruction types

Data transfer instructions: Data transfer instructions perform data transfer between
the various storage places in the computer system, viz. registers, memory and I/O.
Since, both the instructions as well as data are stored in memory, the processor needs
to read the instructions and data from memory. After processing, the results must be
stored in memory. Therefore, two basic operations involving the memory are needed,
namely, Load (or Read or Fetch) and Store (or Write). The Load operation transfers a
copy of the data from the memory to the processor and the Store operation moves the
data from the processor to memory. Other data transfer instructions are needed to
transfer data from one register to another or from/to I/O devices and the processor.

Data manipulation instructions: Data manipulation instructions perform operations

on data and indicate the computational capabilities for the processor. These operations
can be arithmetic operations, logical operations or shift operations. Arithmetic
operations include addition (with and without carry), subtraction (with and without
borrow), multiplication, division, increment, decrement and finding the complement
of a number. The logical and bit manipulation instructions include AND, OR, XOR,
Clear carry, set carry, etc. Similarly, you can perform different types of shift and
rotate operations.

Program sequencing and control instructions: branch instructions. This type of

instruction loads a new value into the program counter. An unconditional
branch instruction does a branch to the specified address irrespective of any
condition. A conditional branch instruction causes a branch only if a specified
condition is satisfied. If the condition is not satisfied, the PC is incremented in the
normal way, and the next instruction in sequential address order is fetched and
executed

Input and output instructions: Input and Output instructions are used for
transferring information between the registers, memory and the input / output devices.
It is possible to use special instructions that exclusively perform I/O transfers, or use
memory – related instructions itself to do I/O transfers.

Instruction Formats (Zero, One, Two and Three Address Instruction)

Computer perform task on the basis of instruction provided. An instruction in
computer comprises of groups called fields. These field contains different
information as for computers every thing is in 0 and 1 so each field has different
significance on the basis of which a CPU decide what to perform. The most
common fields are:
 Operation field which specifies the operation to be performed like addition.
 Address field which contain the location of operand, i.e., register or memory
location.
 Mode field which specifies how operand is to be founded.
An instruction is of various length depending upon the number of addresses it
contain. Generally CPU organization are of three types on the basis of number of
address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization
In first organization operation is done involving a special register called
accumulator. In second on multiple registers are used for the computation purpose.
In third organization the work on stack basis operation due to which it does not
contain any address field. It is not necessary that only a single organization is
applied a blend of various organization is mostly what we see generally.
On the basis of number of address, instruction are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.

1. Zero Address Instructions –

A stack based computer do not use address field in instruction. To evaluate a expression
first it is converted to revere Polish Notation i.e. Post fix Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

One Address Instructions –

This use a implied ACCUMULATOR register for data manipulation. One operand is in
 accumulator and other is in register or memory location. Implied means that the CPU
already knows that one operand is in accumulator so there is no need to specify it.

Expression: X = (A+B)*(C+D)
AC is accumulator
M[X] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

2. Two Address Instructions –

This is common in commercial computers. Here two addresses can be
specified in the instruction. Unlike earlier in one address instruction the result
was stored in accumulator here result can be stored at different location rather
than just accumulator, but require more number of bit to represent address.

Here destination address can also contain operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[X] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

 MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

3. Three Address Instructions –

This has three address field to specify a register or a memory location. Program created are
much short in size but number of bits per instruction increase. These instructions make
creation of program much easier but it does not mean that program will run much faster
because now instruction only contain more information but each micro operation will be
performed in one cycle only.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[X] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

INSTRUCTION CYCLE
Registers Involved In Each Instruction Cycle:
 Memory address registers (MAR) : It is connected to the address lines of
the system bus. It specifies the address in memory for a read or write
operation.
  Memory Buffer Register (MBR) : It is connected to the data lines of the
system bus. It contains the value to be stored in memory or the last value read
from the memory.
 Program Counter (PC) : Holds the address of the next instruction to be
fetched.
 Instruction Register (IR) : Holds the last instruction fetched.

Instruction Cycle:

The main execution process is done by the processor. The processing of instruction
involves two steps, instruction fetch and instruction execution. Each instruction is
fetched from the memory separately and executed. Depending on the nature of the
instruction its execution may deal with a number of operations.

An instruction cycle refers to the processing of a particular instruction. Each

instruction cycle goes through the following phases during its processing:

1. Fetching instruction from memory.

2. Decoding the instruction.

3. Reading the effective address from memory in case of indirect address.

4. Executing the instruction

Fetch the Instruction

1. The CPU sends the contents of the PC to the MAR and sends a read
command on the address bus
2. In response to the read command (with address equal to PC), the memory
returns the data stored at the memory location indicated by PC on the data
bus
3. The CPU copies the data from the data bus into its MDR (also known as
MBR; see section Role of components above)
4. A fraction of a second later, the CPU copies the data from the MDR to the
instruction register for instruction decoding
5. The PC is incremented so that it points to the next instruction. This step
prepares the CPU for the next cycle.

The control unit fetches the instruction's address from the memory unit.
Decode the Instruction
The decoding process allows the CPU to determine what instruction is to be
performed so that the CPU can tell how many operands it needs to fetch in order to
perform the instruction. The opcode fetched from the memory is decoded for the
next steps and moved to the appropriate registers. The decoding is done by
the CPU's Control Unit.

Execute the Instruction

The Control Unit passes the information in the form of control signals to the
functional unit of CPU. The result generated is stored in main memory or sent to
an output device.
The cycle is then repeated by fetching the next instruction. Thus in this way the
instruction cycle is repeated continuously.
MICRO OPERATION
The operations executed on data stored in register are called as micro operations.
A micro operation is an elementary operation performed on the information stored
in one or more registers. The result of the operation may replace the previous
binary information of a register or may be transferred to another register. Examples
of micro operations are shift, count, clear and load.
Micro-operations (also known as micro-ops) are the functional or atomic,
operations of a processor. These are low level instructions used in some designs to
implement complex machine instructions. They transfer data between registers or
between external buses of the CPU, also performs arithmetic and logical operations
on registers. In executing a program, operation of a computer consists of a
sequence of instruction cycles, with one machine instruction per cycle. Each
instruction cycle is made up of a number of smaller units – Fetch, DECODE
Execute and store. Each of these cycles involves series of steps, each of which
involves the processor registers. These steps are referred as micro-operations. The
prefix micro refers to the fact that each of the step is very simple and accomplishes
very little. Figure below depicts the concept being discussed here.

Program Control Instructions are the machine codes that are used by machine or
in assembly language by user to command the processor act accordingly. These
instructions are of various types. These are used in assembly language by user also.
But in level language, user code is translated into machine code and thus
instructions are passed to instruct the processor do the task.
Types of Program Control Instructions:
There are different types of Program Control Instructions:
1. Compare Instruction:
Compare instruction is specifically provided, which is similar t a subtract
instruction except the result is not stored anywhere, but flags are set according to
the result.
Example:
CMP R1, R2 ;
2. Unconditional Branch Instruction:
It causes an unconditional change of execution sequence to a new location.
Example:
JUMP L2
Mov R3, R1 goto L2
3. Conditional Branch Instruction:
A conditional branch instruction is used to examine the values stored in the
condition code register to determine whether the specific condition exists and to
branch if it does.

Example:
Assembly Code : BE R1, R2, L1
Compiler allocates R1 for x and R2 for y
High Level Code: if (x==y) goto L1;
4. Subroutines:
A subroutine is a program fragment that lives in user space, performs a well-
defined task. It is invoked by another user program and returns control to the
calling program when finished.
Example:
CALL and RET
5. Halting Instructions:
 NOP Instruction – NOP is no operation. It cause no change in the processor
state other than an advancement of the program counter. It can be used to
synchronize timing.
 HALT – It brings the processor to an orderly halt, remaining in an idle state
until restarted by interrupt, trace, reset or external action.
6. Interrupt Instructions:
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal
execution of processor and get itself serviced.
 RESET – It reset the processor. This may include any or all setting registers
to an initial value or setting program counter to standard starting location.
 TRAP – It is non-maskable edge and level triggered interrupt. TRAP has the
highest priority and vectored interrupt.
 INTR – It is level triggered and maskable interrupt. It has the lowest
priority. It can be disabled by resetting the processor.

RISC
In the early 1980s, a number of computer designers recommended that
computers use fewer instructions with simple constructs so they can be
executed much faster within the CPU without having to use memory as often.
This type of computer is classified as a reduced instruction set computer or
RISC.
RISC is an abbreviation of Reduced Instruction Set Computer. RISC
processor has ‘instruction sets’ that is simple and has simple ‘addressing
modes’.
RISC Processor Architecture (Block diagram)
RISC processor is implemented using the hardwired control unit. The hardwired
control unit produces control signals which regulate the working of processors
hardware. RISC architecture emphasizes on using the registers rather than memory.

This is because the registers are the ‘fastest’ available memory source. The registers
are physically small and are placed on the same chip where the ALU and the control
unit are placed on the processor. The RISC instructions operate on the operands
present in processor’s registers.

Below we have the block diagram for the RISC architecture.

.
RISC Characteristics The concept of RISC architecture involves an attempt to
reduce execution time by simplifying the instruction set of the computer. The
major characteristics of a RISC processor are:

1. Relatively few instructions

2. Relatively few addressing modes

3. Memory access limited to load and store instructions

4. All operations done within the registers of the CPU

5. Fixed-length, easily decoded instruction format

6. Single-cycle instruction execution

7. Hardwired rather than micro programmed control

The small set of instructions of a typical RISC processor consists mostly of

register-to-register operations, with only simple load and store operations for
memory access. Thus each operand is brought into a processor register with a load
instruction. All computations are done among the data stored in processor registers
RISC Instruction Sets
RISC instructions are simple and are of fixed size. Each RISC instruction engages
a single memory word. RISC instructions operate on processor registers only. The
instructions that have arithmetic and logic operation should have their operand either
in the processor register or should be given directly in the instruction.

Like in both the instructions below we have the operands in registers

Add R2, R3

Add R2, R3, R4

The operand can be mentioned directly in the instruction as below:

Add R2, 100

But initially, at the start of execution of the program, all the operands are
in memory. So, to access the memory operands, the RISC instruction set
has Load and Store instruction.

The Load instruction loads the operand present in memory to the processor register.
The load instruction is of the form:

Load destination, Source

Example Load R2, A // memory to register

The load instruction above will load the operand present at memory location A to the
processor register R2.

The Store instruction stores the operand back to the memory. Generally, the Store
instruction is used to store the intermediate result or the final result in the memory. It
is of the form:

Store source, destination

Example Store R2, A // register to memory

The Store instruction above will store the content in register R2 into the A a memory
location.
You can observe that in the example of Load and Store instruction operand side of
both instructions appears the same as R2, A. But, the source and destination order of
Store instruction is reversed in Load instruction.

RISC instruction has simple addressing modes. Below we have a list of RISC
instruction type addressing modes. Let us discuss them one by one.

Immediate addressing mode: This addressing mode explicitly specifies the operand
in the instruction. Like

Add R4, R2, #200

The above instruction will add 200 to the content of R2 and store the result in R4.

Register addressing mode: This addressing mode describes the registers holding the
operands.

Add R3, R3, R4

The above instruction will add the content of register R4 to the content of register R3
and store the result in R3.

Absolute addressing mode: This addressing mode describes a name for a memory
location in the instruction. It is used to declare global variables in the program.

Integer A, B, SUM;

This instruction will allocate memory to variable A, B, SUM.

Register Indirect addressing mode: This addressing mode describes the register
which has the address of the actual operand in the instruction. It is similar
to pointers in HLL.

Load R2, (R3)

This instruction will load the register R2 with the content, whose address is mentioned
in register R3.

Index addressing mode: This addressing mode provides a register in the instruction,
to which when we add a constant, obtain the address of the actual operand. It is
similar to the array of HLL.
Load R2, 4(R3)

This instruction will load the register R2 with the content present at the location
obtained by adding 4 to the content of register R3.

CISC Processors Architecture

As we have studied above the main objective of a CISC processor is
to minimize the program size by reducing the number of instructions in a
program. This is done by ’embedding some of the low-level instructions in a single
complex instruction’. Later when decoded this instruction generates several
microinstructions to execute.

Now if a program/software is getting simplified then the hardware has to get on

work and must be able to perform the complex tasks. That’s why a CISC processor
has complex hardware. The block diagram of CISC architecture is given below:
Here, we have a special micro program control unit that uses a series of
microinstructions of the micro program stored in the “control memory” of
the microprogram control unit and generate the control signals.

The control units access the control signals produced by the micro program
control unit & operate the functioning of processors hardware.

Instruction and data path fetches the opcode and operands of the instructions
from the memory.

Cache and main memory is the location where the program instructions and
operands are stored.

Examples of CISC Processors are:

IBM 370/168, VAX 11/780, Intel 80486.

CISC Processors Instruction Sets

CISC instructions are complex in nature and occupy more than a single word in
memory. Like RISC uses Load/Store for accessing the memory operands, CISC
has Move instruction to access memory operands.

But, unlike Load and Store, the Move operation in CISC has wider scope. The
CISC instructions can “directly access memory operands”.

The general format of Move instruction is

Move destination, source

It can move an immediate operand, to a memory location or a register.

Move A, 100

Move R, 100

It can transfer the operand between two memory location.

Move A, B
It can transfer the operand between two registers.

Move R1, R2

Including the five basic addressing modes like:

Immediate mode, direct/absolute mode, register mode, Indirect mode and Index
mode.

CISC instruction set has some additional addressing modes. Those are “auto
increment mode”, “auto decrement mode” and “relative mode”.

Auto increment mode:

Here, the effective address of an operand is the content of the register. After
accessing the register’s content, it is automatically incremented to point the
memory location of next operand.

Auto decrement mode:

Here also, the effective address of an operand is the content of the register. But,
here initially, the content of register is decremented and then the content of register
is used as an effective address for an operand.

Relative Mode:

It is similar to “Index register mode” where the effective address is obtained by

adding a constant to the content of the general-purpose register. In relative mode
instead of a general-purpose register, the program counter is used. This kind of
addressing mode is used to refer large range of area in memory.

Now above we have mentioned that the CISC processor minimizes the number of
instructions which turns the length of code relatively shorter.

Let us see how the CISC style instructions minimize the code length?

Suppose, we have an operation

A= B+C

RISC instruction set for this would be:

 Load R2, B

Load R3, C

Add R4, R2, R3

Store R4, A

Now, let us see the CISC instruction set for the same operation.

Move A, B

Add A, C

The objective of four RISC style instructions is fulfilled by only two instructions of
the CISC style.

So we can say that CISC architecture effectively minimizes the number of

instructions in the program as a single instruction execution, executes several low-
level instructions in a program.

Differences between RISC and CISC:

CISC RISC

Very fewer instructions are present. The

A large number of instructions are number of instructions are generally less

present in the architecture. than 100.

Some instructions with long execution No instruction with a long execution time

times. These include instructions that due to very simple instruction set. Some

copy an entire block from one part of early RISC machines did not even have an

memory to another and others that copy integer multiply instruction, requiring
 CISC RISC

compilers to implement multiplication as a

multiple registers to and from memory. sequence of additions.

Variable-length encodings of the Fixed-length encodings of the instructions

instructions. are used.

Example: IA32 instruction size can Example: In IA32, generally all instructions

range from 1 to 15 bytes. are encoded as 4 bytes.

Multiple formats are supported for

specifying operands. A memory

operand specifier can have many Simple addressing formats are supported.

different combinations of displacement, Only base and displacement addressing is

base and index registers. allowed.

CISC supports array. RISC does not supports array.

Arithmetic and logical operations only use

register operands. Memory referencing is

only allowed by load and store instructions,

Arithmetic and logical operations can be i.e. reading from memory into a register and

applied to both memory and register writing from a register to memory

operands. respectively.

Implementation programs are hidden Implementation programs exposed to

from machine level programs. The ISA machine level programs. Few RISC
 CISC RISC

provides a clean abstraction between machines do not allow specific instruction

programs and how they get executed. sequences.

Condition codes are used. No condition codes are used.

Registers are being used for procedure

arguments and return addresses. Memory

The stack is being used for procedure references can be avoided by some

arguments and return addresses. procedures.

Hardwired Control Unit

It is implemented with the help of gates, flip flops, decoders etc. in the hardware. The inputs to
control unit are the instruction register, flags, timing signals etc. This organization can be very
complicated if we have to make the control unit large.
If the design has to be modified or changed, all the combinational circuits have to be modified
which is a very difficult task. The hardwired control unit is created with the hardware; it is
a circuitry approach. It is designed for the RISC style instruction set.

A hardwired circuit organization is shown in the figure below. Let us discuss all the components
one by one, in order to understand the “generation of control signals” from this circuitry
organization.
 The instruction register is a processors register that has the ‘instruction’
which is currently in execution. The instruction register generates the OP-code
bits respective of the operation and the addressing modes of the operands,
mentioned in the instruction.
 Instruction decoder receives the Op-code bits generated by the instruction
register and interprets the operation and addressing modes of the instruction.
Now, based on operation and addressing mode of the instruction in instruction
register it set the corresponding Instruction signal INSi to 1.
Each instruction is executed in step-like, instruction fetch, decode, operand
fetch, ALU, memory store.

Step Counter is implemented which has signals from T1, …, T5. The step counter
sets one of the signals T1 to T5 to 1 on the basis of the step, the instruction is in.

A clock is designed such that for each step the clock must complete its one clock
cycle.
 So, consider if the step counter has set T3 signal 1 then after a clock cycle
completes step counter will set T4 to 1.

The execution of an instruction depends on some condition or if it is branch

instruction. This is determined with the help of the Condition signals. The
Condition signals generate the signals for the conditions greater than, less than,
equal, greater than equal, less than equal etc.

 The remaining is External inputs, it acknowledges the control signal

generator of interrupts which affects the execution of the instruction.

Micro programmed control unit

It also produces the control signal but using the programs. This approach was very
popular in past during the evolution of CISC architecture. The program that
creates the ‘control signals’ is called Microprogram. This micro program is
placed on the processor chip which is fast memory, it is also called control
memory or control store.

A micro program has a set of microinstructions, or it is also termed as control

word. Each microinstruction is ‘n’ bit word. Each control signal differs from other
control signal depending on the bit pattern of the control word. Each control
word/microinstruction has a different bit pattern.

Instruction execution is performed in steps. So, for each step there is a control
word/ microinstruction in the micro program. A sequence of microinstructions
required to execute a particular instruction is called micro routine.

In the figure below, you can understand the organization of a control word/
microinstruction, microroutine and microprogram.
Now let us discuss the organization of the microprogram control unit. We will
discuss the flow of instruction execution in terms of instruction execution steps.
 1. In the first step (instruction fetch) the Microinstruction address
generator would fetch the instruction from ‘instruction register’ (IR).

1. In the second step, the microinstruction address generator decodes the

instruction obtained from IR and retrieves the starting address of the micro
routine required to perform the corresponding operation mentioned in the
instruction. It loads that starting address to microprogram counter.
2. In the third step, the ‘control word’ corresponding to the ‘starting
address’ of ‘micro program counter’ is read and as the execution proceeds, micro
program address generator will increment the value of micro program counter to
read the successive control words of the micro routine.
3. In the last microinstruction of a micro routine, there is a bit which we
call end bit. When end bit is set to 1 it denotes successful execution of that
microroutine.
4. After this, the micro program address generator would return back
to Step 1 again to fetch a new instruction. And the cycle goes on.

Control Store or Control memory is a memory used store the microprograms. A

microprogram control unit is simple to implement and flexible to modify but it is
slower than Hardwired control unit.

Key Differences Between Hardwired and Microprogrammed Control Unit

1. The hardwired control unit is implemented using a hardware circuit while a

microprogrammed control unit is implemented by programming.
2. A hardwired control unit is designed for RISC style instruction set. On the
other hand, a microprogrammed control unit is for CISC style instruction set.
3. Implementing modification in a microprogrammed control unit is easier as it
is easy to change the code. But implementing modification in Hardwired control
unit is difficult as changing the circuitry will add cost.
4. The hardwired control unit executes simple instructions easily but it finds
difficulty in executing complex instruction. The microprogrammed control unit
finds, executing complex instructions easy.
5. Building up a hardwired control unit requires the hardware circuit which
is costly. Building up microprogrammed control unit is cheaper as it only requires
coding.
6. The hardwired control unit does not require a control memory as here; the
control signal is generated by hardware. The microprogrammed control
unit requires the control memory as the microprograms which are responsible for
generating the control signals are stored in control memory.
7. Execution is fast as everything is in the hardware. But, the microprogram
control unit is slow as it has to access control memory for the execution of every
instruction.
Similarities

Both Hardwired and Microprogrammed control unit ‘generates’ the control

signals.
So this is all about the differences between hardwired and microprogrammed
control unit.

Micro program Sequencer

The next address generator is sometimes called a micro program sequencer, as it

determines the address sequence that is read from control memory. The address of
the next microinstruction can be specified in several ways, depending on the
sequencer inputs. Typical functions of a micro program sequencer are
incrementing the control address register by one, loading into the control address
register an address from control memory, transferring an external address, or
loading an initial address to start the control operations. The control data register
holds the present microinstruction while the next address is computed and read
from memory.

The purpose of a micro program sequencer is to present an address to the control

memory so that a microinstruction may be read and executed. The next-address
logic of the sequencer determines the specific address source to be loaded into the
control address register. The choice of the address source is guided by the next-
address information bits that the sequencer receives from the present
microinstruction. Commercial sequencers include within the unit an internal
register stack used for temporary storage of addresses during microprogram
looping and subroutine calls. Some sequencers provide an output register which
can function as the address register for the control memory.
The control memory is included in the diagram to show the interaction between the
sequencer and the memory attached to it. There are two multiplexers in the circuit.
The first multiplexer selects an address from one of four sources and routes it into
a control address register CAR. The second multiplexer tests the value of a
selected status bit and the result of the test is applied to an input logic circuit. The
output from CAR provides the address for the control memory. The content of
CAR is incremented and applied to one of the multiplexer inputs and to the
subroutine registers SBR. The other three inputs to multiplexer number 1 come
from the address field of the present microinstruction, from the output of SBR, and
from an external source that maps the instruction. Although the diagram shows a
single subroutine register, a typical sequencer will have a register stack about four
to eight levels deep. In this way, a number of subroutines can be active at the same
time. A push and pop operation, in conjunction with a stack pointer, stores and
retrieves the return address during the call and return microinstructions. The CD
(condition) field of the microinstruction select gs one of the status bits in the
second multiplexer. If the bit selected is equal to 1, the T (test) variable is equal to
1; otherwise, it is equal to 0. The T value together with the two bits from the BR
(branch) field goes to an input logic circuit. The input logic in a particular
sequencer will determine the type of operations that are available in the unit.
Typical sequencer operations are: increment, branch or jump, call and return from
subroutine, load an external address, push or pop the stack, and other address
sequencing operations. With three inputs, the sequencer can provide up to eight
address sequencing operations. Some commercial sequencers have three or four
inputs in addition to the T input and thus provide a wider range of operations. The
input logic circuit in Fig. has three inputs, l0, l1, and T, and three outputs, S0, S1,
and L. Variables So and S, select one of the source addresses for CAR. Variable L
enables the load input in SBR. The binary values of the two selection variables
determine the path in the multiplexer.

Control Address Register (CAR) :

Control address register receives the address from four different paths. For
receiving the addresses from four different paths, Multiplexer is used.
Multiplexer:
Multiplexer is a combinational circuit which contains many data inputs and single
data output depending on control or select inputs.
Branching:
Branching is achieved by specifying the branch address in one of the fields of the
micro instruction. Conditional branching is obtained by using part of the micro-
instruction to select a specific status bit in order to determine its condition.

Mapping Logic:
An external address is transferred into control memory via a mapping logic circuit.
Incrementer:
Incrementer increments the content of the control address register by one, to select
the next micro-instruction in sequence.
Subroutine Register (SBR) :
The return address for a subroutine is stored in a special register called Subroutine
Register whose value is then used when the micro-program wishes to return from
the subroutine.
Control Memory:
Control memory is a type of memory which contains addressable storage registers.
Data is temporarily stored in control memory. Control memory can be accessed
quicker than main memory.

HORIZONTAL AND VERTICAL MICROPROGRAMMING

In the micro-programmed control unit approach, the control signals that are
associated with the operations are stored in special memory units. It is convenient
to think of sets of control signals that cause specific micro-operations to occur as
being “microinstructions”. The sequences of microinstructions could be stored in
an internal “control” memory.
Micro-programmed control unit can be classified into two types based on the type
of Control Word stored in the Control Memory, viz., Horizontal micro-
programmed control unit and Vertical micro-programmed control unit.
 In Horizontal micro-programmed control unit, the control signals are
represented in the decoded binary format, i.e., 1 bit/CS. Here ‘n’ control
signals require n bit encoding. Horizontal microinstructions represent several
micro-operations that are executed at the same time. However, in extreme
cases, each horizontal microinstruction controls all the hardware resources of
the system

 In Vertical micro-programmed control unit, the control signals are

represented in the encoded binary format. Here ‘n’ control signals require
log2n bit encoding. The vertical microinstruction resembles the
conventional machine language format comprising one operation and a few
operands. As opposed to horizontal microinstructions, the vertical
microinstruction represents single micro-operations.
Comparison between Horizontal micro-programmed control unit and Vertical micro-programmed
control unit:

HORIZONTAL Μ-PROGRAMMED CU VERTICAL Μ-PROGRAMMED CU

It supports longer control word. It supports shorter control word.

It allows higher degree of

parallelism. If degree is n, then n

Control Signals are enabled at a It allows low degree of parallelism i.e.,

time. degree of parallelism is either 0 or 1.

Additional hardware in the form of

No additional hardware is decoders is required to generate control

required. signals.

It is faster than Vertical micro- it is slower than Horizontal micro-

programmed control unit. programmed control unit.

It is less flexible than Vertical It is more flexible than Horizontal micro-

micro-programmed control unit. programmed control unit.

Horizontal micro-programmed Vertical micro-programmed control unit

control unit uses horizontal uses vertical microinstruction, where a

microinstruction, where every bit code is used for each action to be

in the control field attaches to a performed and the decoder translates this
HORIZONTAL Μ-PROGRAMMED CU VERTICAL Μ-PROGRAMMED CU

control line. code into individual control signals.

Horizontal micro-programmed

control unit makes less use of Vertical micro-programmed control unit

ROM encoding than vertical makes more use of ROM encoding to

micro-programmed control unit. reduce the length of the control word.

Example: Consider a hypothetical Control Unit which supports 4 k words. The Hardware
contains 64 control signals and 16 Flags. What is the size of control word used in bits and control
memory in byte using:
a) Horizontal Programming
b) Vertical programming
Solution:

a) For Horizontal

64 bits for 64 signals

Control Word Size = 4 + 64 + 12 = 80 bits

Control Memory = 4 kW = ( (4* 80) / 8 ) = 40 kByte

a)For Vertical
6 bits for 64 signals i.e log264

Control Word Size = 4 + 6 + 12 = 22 bits

Control Memory = 4 kW = ( (4* 22) / 8 ) = 11 kByte