Received 2 October 2022, accepted 25 October 2022, date of publication 31 October 2022, date of current version 8 November 2022.

Digital Object Identifier 10.1109/ACCESS.2022.3218309

48-V Input DC-DC High Step-Down Converter

in GaN-Based Design
SZYMON FOLMER , MATEUSZ KOSAKOWSKI, AND ROBERT STALA , (Member, IEEE)
Department of Power Electronics and Energy Control Systems, AGH University of Science and Technology, 30-059 Krakow, Poland
Corresponding author: Szymon Folmer (folmer@agh.edu.pl)

ABSTRACT This paper presents a novel high step-down DC-DC converter based on a switched-capacitor
resonant topology. It is presented in a 48/8 V version, which was verified by simulations and experiments.
The most notable features specific to this converter are an almost non-iductive design and relatively low
voltage stress across switching devices. The proposed topology allows for zero-current-switching (ZCS) and
zero-voltage-switching (ZVS). Experimental tests confirm that ZVS operation brings a significant increase
in the efficiency of the proposed device. Taking into account all the advantages of the suggested converter,
it can be concluded that this device is suitable for any application where a high step-down voltage conversion
is required. In a prospective application, the proposed converter can be utilized as a part of the power supply
unit for data centers.

INDEX TERMS Buck converters, DC-DC converters, high voltage step-down gain converter, switched-
capacitor circuit.

I. INTRODUCTION
Providing a low-cost, high-efficiency power supply for data
center applications, can be considered a crucial problem for
new research. Due to the continuous increase in energy con-
sumption of data centers, the performance parameter of such
systems is becoming increasingly important [1]. To achieve
better efficiency of such systems, a new concept of 48 V DC
bus supply is strongly justified [2]. The utilization of such
an architecture leads to a limitation of conductive loss and
a decrease in device manufacturing costs by reducing busbar
cross sections, which is possible because of the lower loading
of power rails.
The application of the 48 V DC bus creates a significant
research problem in supplying point-of-load (POL) devices
directly. A general concept of the intermediate-bus architec-
ture is presented in Fig. 1. The system (Fig. 1) shows the
unit, which generates 12 V and 5 V supply voltages. A very
FIGURE 1. A concept of the centralized power system developed for data
low POL voltage for computing units supply is generated center applications, with high-step-down switched-capacitor-based
by parallel sections composed of high step-down converters, pre-regulators.
intermediate buses, and SMPS (Switch-Mode Power Supply)
converters on the output. Architectures with an intermediate bus and the evolution of supply systems concepts are demon-
strated in [3], along with an example of converter topologies.
The associate editor coordinating the review of this manuscript and The centralized architecture, with intermediate-bus con-
approving it for publication was Ahmed Aboushady . verters for power distribution among components of

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
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S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design
specialized computers and servers, demonstrates valuable
benefits in terms of efficiency increase and their further
improvements towards more compact, effective, modular,
reliable, and cheaper solutions for power distribution. Some
examples can be found in the research papers [3], [4], [5], [6],
[7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18],
[19], [20], [21], [22].
Intermediate bus converters, as devices, are responsible for
intermediate-bus voltage delivery. They play a very important
role in the whole power supply system, and their efficiency
needs to be kept at a sufficiently high level to ensure required
performance of the overall data center. Efficiency, as well
as optimization of intermediate bus converters, should be
considered an important research topic that has been dis-
cussed in recent publications. In [4], [5], [6], [7], [8], and [9],
48 V to 12 V converters for supply systems are presented.
Those papers demonstrate optimization of such parameters as
high-power density [4], [5], [6], high efficiency [5], [6], [7],
[8], [9], low voltage stress across components and reduction
of magnetic components [6], [7].
The articles [10], [11], [12], [13], [14], [15], [16], [17],
[18], [19], [20], [21], [22], [23], [24] present the results of
research conducted on converters from the family of high
step-down devices, which can be powered by a 48 V power
supply line. The idea behind the devices mentioned in the
referenced papers is to deliver a set of different voltages from
the range below 12 V. The following voltages can be delivered
by converters described in the quoted papers: 2.5-1 V in [10],
8 V in [11], 6 V in [12], 3.4 V in [13], and 1 V in [14], [15],
[16], and [17].
Some new research works related to the development of
power systems for data centers focus on switched capaci-
tor (SC) topologies [10], [11], [12], [13], [14], [15], [16],
[17], [18], [19], [20]. SC-based converters can be consid-
ered a solution for point-of-load supply systems due to their
favorable qualities, such as low volume, high voltage con-
version ratio, and reduced voltage stresses across switching
components. In [10], [11], SC series-parallel converters were
proposed. These devices operate in a multiresonant mode and
can achieve high efficiency and high power density. In [12]
and [13], hybrid converters that incorporate the SC stage are
suggested. The implementation of a Dickson SC topology for
high step-down power conversion is proposed in [14], where
it is incorporated with switched-inductor circuits, and in [15],
an optimized part with a single inductor. In [16], a topology
with an SC stage and a part based on coupled inductors allow
ZVS operation with improved efficiency. SC converters with
coupled inductors in a topology with a virtual intermediate
bus allow for a reduction of the volume of passive compo-
nents, as demonstrated in [17]. Publication [18] presents a
switched tank converter with an optimized number of reso-
nant inductors. Paper [19] shows a switched-capacitor step-
down circuit operating in resonant mode, and in [20], a pure
SC device in a multistage step-down DC-DC converter is
reported. In this case, SC converters operate in parallel and
are controlled in a closed loop.
VOLUME 10, 2022
In this paper, we propose a novel type of switch-capacitor
converter designed as an intermediate-bus converter for data
center applications. The proposed converter operates in reso-
nant mode and utilizes only very small chokes to operate with
oscillatory currents and reduced power losses. It achieves a
desirable voltage conversion ratio (1/6). Moreover, an advan-
tage of the topology presented in this paper is the nearly
non-inductive design, the low voltage stress across transistors
and diodes, as well as the low count of employed switching
devices. In [10] and [11], the authors propose converters
that basically are a variation of the topology of series-
parallel switched capacitor converters and can achieve the
voltage conversion ratio of 1/6 and 1/4, respectively. The device
proposed in this paper contains only five active switches
and achieves a conversion ratio comparable to topologies
described in [10] and [11], where twice as many transistors
are used. In [6], two converters are demonstrated where; the
first one contains seven transistors while the other is com-
posed of twelve active switches. Both converters can provide
a voltage conversion ratio, which is 1/4. In [7], a concept of
a novel high step-down converter, which combines switched
capacitors with coupled inductors in one topology, is demon-
strated. The converter has the ability to operate in ZVS mode,
which allows for improving its efficiency by switching loss
reduction. From the research presented in [7], it follows that
the maximum efficiency level measured for this converter is
approximately. 94%.
The research scopes of many scientists and engineers focus
not only on the development of new architectures for power
transmission, but also on the applications of new types of
devices utilized among such systems. The converter pre-
sented in this paper was designed on a GaN-based concept.
The GaN-based design with a properly selected converter’s
topology allows for achieving both switching and conduc-
tion loss limitation [8], [9], [23], [24], [27]. Moreover, this
approach allows for a decrease in the converter’s volume.
For the converter proposed in this paper, transistors were
mainly selected based on their low Coss capacitance and
low RDS(on) resistance. In the case of chosen transistors
(GS61008T-MR), the Coss capacitance is 250 pF and RDS(on) is
only 7 m. In [21], the parameters of a GaN-based syn-
chronous buck converter with a conversion of 48 V to the
adjustable voltage from the range between 5 V and 12 V
are presented. From the presented results, it follows that the
application of GaN switches allows the design of converters
characterized by an improved power density factor and high
performance. However, the efficiency results demonstrated
in [21] show a significant increase in power loss when com-
paring the operation with 12 V and 5 V across the output ter-
minals of the reported converter. Therefore, research towards
topologies for POL power supplies are justified from the
efficiency viewpoint.
The ZVS operation mode utilized in resonant SC convert-
ers is a technique that allows for turn-on loss reductions of
transistors. The main idea behind this approach is to discharge
the output capacitance of a particular transistor just before its
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 S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design
turns-on. The positive effects of the use of this method for
efficiency improvement were demonstrated in [25], where the
phase change control algorithm was employed to drive the
SC resonant converter and put them into the ZVS operation
mode. This method was also employed in other SC topolo-
gies, such as the converter presented in [26].
Thanks to the presence of resonant inductors in SC convert-
ers, the oscillatory current waveform can be achieved. If the
current is oscillating, this means that the transistor switching
can be performed at the time when the current value is equal
to zero (ZCS operation mode). This switching technique was
applied for converters described in publications [10], [11],
[13], [18], [23], and [26]. Additionally, resonant inductors
protect the converter against current spikes occurrence dur-
ing its start-up. Inrush current limitation also has a positive
impact on the device performance.
Apart from the characteristics mentioned above, the con-
verter proposed in this paper has the following qualities:
- High conversion ratio of the input voltage.
- Adjustable output voltage (step and continuous
adjustment).
- Nearly magnetic-less design. The examined converter
contains only 125 nH resonant chokes.
- Low weight.
- ZCS and ZVS operation.
- Wide input voltage range. For input voltage varying
from 40-60 V. The described converter produces the
output voltage in the range of 6.7 to 10 V.
- The proposed converter can also be applied in other
supply systems where a high step-down conversion ratio
is required.
The paper is organized as follows. Sections 2 to 4 present
the basic concept of the converter operation principle, as well
as the analysis of its voltage gain and voltage stresses across
components. Section 5 describes key facts related to the
component selection process. In Section 6, simulation results
are presented. The simulated waveforms demonstrate the
converter’s operation concept, the voltage stresses across the
converter’s crucial components, and its voltage gain. Analysis
of the converter efficiency is presented in section 7. The next
stage (8) provides the results of the experimental research
performed on the prototype unit of the proposed device. Some
comments related to the obtained results are also included
here. Finally, the paper ends with the summary section, where
conclusions and doubts are compiled.
II. THE TOPOLOGY AND PRINCIPLE OF OPERATION
The proposed converter, presented in Fig. 2, consists of five
active switches and five diodes. In addition to those ele-
ments, two switched capacitors (C3 and C4 ) are also used
in this topology. These capacitors, during each switching
period, charge and discharge to provide a suitable energy
flow. Because each resonant circuit (stage) contains a reso-
nant choke, the capacitor’s inrush current is avoided. From
the device’s operation principle, it follows that the exam-
ined circuit belongs to the family of resonant converters
115960
and is capable of operation in zero current and zero voltage
switching (ZCS, ZVS) modes. It is very beneficial, especially
when the proposed converter operates in ZVS mode, and the
reduction of COSS losses occurs.
FIGURE 2. The proposed DC-DC high step-down converter.
A. OPERATION IN THE ZERO CURRENT SWITCHING
MODE (ZCS)
In ZCS mode, the switched capacitors of the proposed con-
verter are periodically charged and discharged by oscillatory
currents. The switching frequency is low enough to ensure
complete recharging of the switched capacitors during each
switching period. The design concept of the proposed con-
verter in its basic version requires four different hardware
configurations (Fig. 3) to obtain a voltage conversion ratio
on the level of 1/6. The complete switching period consists of
six successive stages, which use four hardware configurations
shown in Fig. 3 (M1, M2, M3, or M4). In order to achieve the
desired voltage conversion ratio (1/6), the following sequence
needs to be applied in the switching pattern:
- Stage I: The hardware configuration M1 is used, where
only transistor Q1 is turned on. The input capacitor C1
charges the switched capacitors (C3 and C4 ) and the
output capacitor (Cout ) simultaneously.
- Stage II: The hardware configuration M3 is used, where
the Q3 and Q5 are turned on. Capacitor C3 discharges to
the output capacitor (Cout ).
- Stage III: The hardware configuration M4 is used,
where the Q4 and Q5 are turned on. Capacitor C4 dis-
charges to the output capacitor (Cout ).
- Stage IV: The hardware configuration M2 is used,
where only transistor Q2 is turned on. The input capacitor
C1 charges the switched capacitors (C3 and C4 ) and the
output capacitor (Cout ) simultaneously.
- Stage V: The M4 configuration is used once more.
- Stage VI: The M3 configuration is used once more.
In each stage of the proposed converter operation, the output
capacitor charges up. It ensures high frequency of the output
capacitor charging current and low output voltage ripples.
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B. OPERATION IN THE ZERO VOLTAGE SWITCHING

MODE (ZVS)
The proposed converter can also operate in ZVS mode, which
allows for switching loss reduction. In the ZVS mode, the
switching pattern is adjusted to ensure discharging of the
transistor’s output capacitances (COSS ) before it turns on.

FIGURE 4. ZVS operation in transition between Stage III and Stage IV. The
COSS discharging current is marked in blue.

The relationships (1) - (3) allow us to derive the following

formulas:
FIGURE 3. Basic hardware configurations (M1 – M4) used for the 0.5Uin = 3Uout (5)
operation of the converter with voltage gain GU = 1/6.
And finally:
To enable the ZVS operation mode, the switching Uout = (1/6)Uin (6)
frequency needs to be increased slightly above the circuit’s
self-oscillating frequency. When a transistor is turned off at a The analysis concludes that the relationship (6) indicates
non-zero current, the current of a resonant inductor starts to that the voltage conversion ratio of the proposed converter
flow through an output capacitance of a transistor, which is is 1/6.
the next one to be turned on according to the selected switch-
ing pattern. As a result, the transistor’s output capacitance IV. VOLTAGE STRESSES ACROSS TRANSISTORS AND
is discharged, and the transistor reaches favorable conditions DIODES
for zero voltage turn-on. The ZVS operation principle of the Another important issue related to SC converters, in general,
proposed converter is shown in Fig. 4. This diagram explains is the level of voltage stresses across transistors. For the pro-
how the current flows through the converter circuit when posed converter, the worst case in this matter can be identified
the transition between stage III and stage IV occurs. In the during the duration of stages I and IV. Based on the analysis of
proposed topology, ZVS can be applied by four of six stage the diagrams presented in Fig. 3, it can be seen that voltage
transitions during each switching period. It causes a part of stresses across the switches Q1 and Q2 can be described as
the switching losses (related to COSS ) to be reduced. follows:
UQ1max = UC1 (7)
III. VOLTAGE GAIN DERIVATION
The voltage gain of the converter can be derived from an UQ2max = UC2 (8)
idealized case of steady-state. Based on the simulation results 1
UC1 = UC2 = Uin (9)
(Fig. 5), it can be assumed that in every operation stage, the 2
energy is transferred to the output capacitor. Therefore, the 1
UQ1max = UQ2max = Uin (10)
following relationships can be derived: 2
In the M1 state, the D2 diode conducts, but no current flows
UC3 = Uout (1)
through the L2 choke. Therefore, the voltage across the Q2
UC4 = Uout (2) switch is equal to uC2 . Similarly, in the M2 state, when the
UC1 − UC3 − UC4 = Uout (3) D1 diode conducts, the voltage across the Q1 switch is equal
to uC1 . The maximum voltage stress across switches Q3 and
Assuming that:
Q4 occurs during stages II and V. For stage II in configuration
UC1 = 0.5Uin (4) M3 (Fig. 3), the voltage across the Q4 switch equals the

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voltage of capacitor C4 . The voltage of uC4 varies and reaches V. PARAMETERS OF COMPONENTS SELECTION
its maximum value when C3 and C4 capacitors are charged Transistors and diodes can be selected by taking into account
from the initial zero condition. Therefore, the voltage stresses the required level of input and output voltages of the con-
can be described as (assuming UC3min = UC4min = 0): verter. If these parameters are known, it is possible to eas-
2 (UC2 − Uout ) 1 1 ily determine the value of the expected voltage stresses on
UQ4max = UC4max = = U − U switching devices (Table 1). The type of employed semi-
2 2 in 6 in
1 conductor switches and diodes also depends on assumed
= Uin (11) optimization criteria and may have an influence on the over-
3 all performance of the converter. The experimental setup
Similarly, assuming that the C3 capacitor is completely dis- examined during this investigation was equipped with GaN
charged (uC3 = 0 V) at the beginning of the duration of transistors to minimize turn-on losses.
the M2 state, the voltage across the Q4 switch is UC2 -uC3 - The selection of passive components is determined by the
Uout = Uin /2-0-Uin /6 = Uin /3. expected power of the converter and the switching frequency.
During stage V, when the configuration M4 is used, the Input and output capacitors are selected in a typical way
maximum voltage stress across the Q4 transistor equals the to minimize voltage ripples present at the converter out-
voltage of uC3, which reaches the value 2(UC2 -Uout )/2. This put. The capacitance of the switched capacitors is crucial
occurs in cases where the switched capacitor is charged from for energy transfer and determines the maximum power of
zero. Therefore, the voltage stress on transistor Q3 can be the converter. The fully discharged switched capacitors are
calculated as follows: charged to the voltage value of 2(Uin -Uout ). Therefore, the
1 switching frequency and the capacitance of the switched
UQ3max = UC4max = Uin (12)
3 capacitors determine the maximum power of the converter
The maximum voltage stress across the switch Q5 is: as fsw CS (Uin -Uout )2 .
The design process of the proposed converter consists
1 of several steps. Firstly, the switching frequency should be
UQ5max = UC1 − UC3min − UC4min = Uin (13)
6 adjusted to achieve a sufficiently low level of switching
The maximum voltage stresses for diodes D1 and D2 can losses. Secondly, the inductance value of the resonant choke
occur in converter configurations M1 and M2, respectively. is defined. Finally, the resonant capacitors should be selected
Voltage stresses across those elements can be described as: properly. The chosen values of the switched capacitances
should provide an adequate self-resonant frequency (along
1
UD1max = UD2max = Uin (14) with a resonant inductor) and the converter’s maximum
2 power, which is above the demanded power for the designed
The highest voltage stress for diode D4 can be observed using device.
the M1 configuration. It can be calculated by the following
equation: TABLE 2. Parameters of the converter used for simulation and
experimental tests.
1
UD4max = UC1 − UC3 − UC4 − UQ4min == Uin (15)
6
Finally, the maximum value of the voltage stresses across
diodes D3 and D5 can be noticed in the M3 and M4 config-
urations, respectively. The exact value can be calculated as
follows:
1
UD3max = UD5max = UC3 = Uin (16)
6

TABLE 1. The voltage stress on the semiconductor devices in the

proposed converter is related to the input voltage Uin .

VI. SIMULATION RESULTS

The results of the calculations performed in terms of the
voltage stresses that occur across the semiconductor devices
in the proposed converter are summarized in Table 1 and
demonstrated in three groups according to the stress value.
The simulation research was performed to verify the con-
verter’s operation and its qualities. The scope of the sim-
ulation tests covers both the ZCS and ZVS operation of
the proposed converter. The device voltage gain cofactor
under 250 W of a resistive load was also examined. All the
assumed parameters used during this simulation research are
listed in Table 2.

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TABLE 3. Stray parameters of the converter components used for It confirms most of the analytical relationships previously
simulation waveforms analysis.
derived between the input voltage of the converter and
the voltage stresses that occur across the semiconductor
elements.
From the simulation results, it follows that the voltages on
transistors Q1 and Q2 , as well as on diodes D1 and D2 , are
slightly above the value derived from the theoretical predic-
tions. Voltages of about 30 V were noticed on these elements
A. SIMULATION RESEARCH ON THE PROPOSED (Fig. 6).
CONVERTER OPERATING IN ZCS MODE
During the first part of the simulation tests, the converter’s
operation in the whole switching cycle was verified. The
results of this research are shown in Fig. 5. The waveforms
were obtained with the parameters presented in Table 2 and
constant values of stray parameters presented in Table 3.
From the waveforms presented, it is seen that the converter
operates exactly in the same way as was assumed in the
theoretical predictions. On the basis of the recorded wave-
forms, it is possible to state that energy is transferred from
input capacitors to switched capacitors, where it is stored until
the next switching stage. Then, the energy from each of the
resonant capacitors (one by one) is transferred to the output
capacitor of the proposed converter.
The simulation results also confirm that the proposed con-
verter has the ability to reduce the voltage by six times.

FIGURE 6. Voltage stress across transistors and diodes in the proposed

converter.

B. SIMULATION RESEARCH ON PROPOSED CONVERTER

OPERATING IN ZVS MODE
The second part of the simulation research is focused on
verifying the operation of the proposed converter in ZVS
mode. Fig. 7 shows the entire switching cycle of the examined
device during the ZVS operation. From the waveforms pre-
sented in Fig. 7, it is seen that beneficial switching conditions
in the proposed circuit can be achieved during four of all
six transitions in each switching loop. The ZVS points are
marked in Fig. 7 and described in Table 4. From the results
obtained, it follows that the proposed converter also operates
in an assumed way in ZVS mode.

TABLE 4. ZVS operation summary.

FIGURE 5. Operation principle – a set of crucial waveforms present in the

proposed converter.

The voltage stresses across the switching devices were Fig. 8 presents a switching transition from the off-state
also verified. From the results obtained (Fig. 6), it is seen to the on-state of the transistor Q2 when the ZVS operation
that the proposed converter has very favorable properties mode is enabled. In the middle waveform in Fig. 8, it is clearly
in terms of voltage stresses across transistors and diodes. visible that the current of transistor Q2 for a short period

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 S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design
of time flows in the reverse direction. This is possible due
to the premature shutdown of the Q4 transistor. As a result
of this phenomenon, the QOSS charge, previously collected
in the output capacitance of the Q2 transistor, is removed.
The effect of this process is clearly visible as a rapid voltage
decrease across this transistor. Once the voltage on transistor
Q2 reaches zero, its output capacitance is discharged, and the
transistor itself can be switched on without additional losses
generation related to the discharging of the Q2 transistor’s
COSS capacitance.
FIGURE 7. Waveforms of the transistor’s currents and voltages recorded
during the converter’s operation in ZVS mode. All ZVS transitions were
marked.
FIGURE 8. A detailed comparison of Q4 and Q2 transistors switching
during converter operation in the ZVS mode. The transition between
mode M4 and M2 is presented.
The converter operation with the switching frequency
above the circuit’s self-resonant frequency resulted in volt-
age spikes across Q3 and Q4 transistors. The voltage across
these transistors is increased by the Uin /2 value after their
turn-off at the non-zero inductor’s current (Fig. 7). When
115964
the current of the inductor L1 flows in a path composed of
Q1 , C1 , and D1 , the voltage uC1 appears across the L1 , and
this voltage (Uin /2) adds to the voltage stress across the Q3 .
Similarly, when the Q4 transistor is turned off, the voltage
stress increases by the (Uin /2) component, which appears on
the L2 choke, and finally causes a voltage increase across
the Q4 . The level of voltage spikes can be predicted, which
is especially important when using GaN transistors to avoid
overvoltage and degradation of the switches. Furthermore, the
problem of mentioned voltage spikes occurs in switching time
periods that are not used for ZVS operation. A more complex
switching pattern can be designed where these time intervals
are extended in order to eliminate those voltage spikes. Simu-
lation research shows that this improvement works well, and
some results can be seen in Fig. 9.
FIGURE 9. Current and voltage waveforms on all transistors during the
converter operation in ZVS mode with an increased duration of the M2
and M3 states.
C. VOLTAGE GAIN OF THE CONVERTER
The voltage ratio of SC converters operating in an open
loop differs from the theoretical level due to voltage drops
across the circuit’s components. Variations in voltage gain
are also observed when the load of the converter changes.
This phenomenon was confirmed by the results of simula-
tion and experimental research. Simulation results allow for
investigating the impact of the converter’s parameters, such
as the circuit’s resistance and forward voltage of the diodes
VF , on its voltage gain. Figs. 10 – 11 present the converter’s
voltage gain and the output voltage versus its output power
(Pout ) for different RDS(on) and VF parameters. From the
results presented, it is seen that the parasitic resistances of the
converter, as well as voltage drops on the diodes, resulted in
a decrease in the device output voltage. This behavior is valid
for a wide range of converter output powers. The relationships
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S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design
between the voltage gain and the forward voltages (VF ) of the
diodes are linear. This property makes it possible to predict
a voltage gain change in the case of diodes replacement or
application of a synchronous converter (diodes replaced by
transistors). The output voltage of the device also depends on
the resistance of the converter branches; it decreases along
with the increase of the device output power. The voltage
gain drop at a given power is a linear function of transistors
resistance, as demonstrated in Fig. 11a. When a high-quality
design with low total parasitic resistances is considered, the
output voltage drop versus power may be insignificant.
An increase in the switching frequency above the resonant
frequency leads to a decrease in the voltage gain of the con-
verter. This trait may be used for the control of the converter’s
output voltage in the power supply system.
FIGURE 10. Voltage gain of the converter (a) and output voltage
(b) versus output power for different RDS(on) and VF parameters.
Uin = 48 V, ZVS operation.
FIGURE 11. Impact of RDS(on) of transistors (a) and VF of diodes (b) on
the voltage gain of the converter. Uin = 48 V, Pout = 70 W, ZVS operation.
Fig. 12 presents an example of how the voltage gain varies
when the converter operates with a switching frequency
above the resonant frequency. In the results presented in
Fig. 12, the switching frequency (fS ) is related to the fre-
quency applied in the ZCS operation (fr = fS /fSzcs ), where
the full current oscillation occurs in the resonant circuits (as
presented in Fig. 5).
In the second concept of regulation, the converter voltage
gain can be fixed at a value of 0.25Uin using the switching
modes M5 and M6 presented in Fig. 13. To operate with the
voltage conversion ratio G = 0.25, the modes M5 and M6
(Fig. 13) are used in the appropriate order along with the
states M3 and M4:
ModesOrder_GU0.25 = {M5, M3, M6, M4, M6, M4, . . .}
(17)
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FIGURE 12. Impact of the switching frequency on the voltage gain of the
converter. (a) Chart with the steady-state level of the gain, and (b) voltage
gain change after step increase of the switching frequency. Pout = 70 W,
Cout = 1.36 mF.
In the M5 and M6, the following equations are valid:
UC1 − UC3 = Uout (18)
UC2 − UC4 = Uout (19)
The relationships (1), (2), (4), and (18) - (19) allow us to
derive the following formula:
0.5Uin − Uout = Uout ⇒ Uout = 0.25Uin (20)
Fig. 14 presents simulation results of the converter operating
with a voltage gain G = 0.25. Obtained waveforms (Fig. 14)
confirm that the converter operates correctly with this voltage
conversion ratio as well.
FIGURE 13. The hardware configurations M5 and M6 are used for
converter operation with voltage gain GU = 1/4.
VII. EFFICIENCY ANALYSIS OF THE PROPOSED
CONVERTER
The circuit self-oscillation time is associated with the LC
parameters of the resonant branches, where the currents flow
during the charging and discharging processes of switched
capacitors. In the case of the proposed converter, during the
one switching period, several resonant branches are estab-
lished (Fig. 3). This means that several self-oscillation times
can also be observed in this converter. Since the proposed
converter is symmetrical in terms of the values of utilized
components, only two self-oscillating periods need to be
considered.
During the charging time of the switched capacitors
(C3, C4 )Tchar , the current flows in a circuit composed of one
inductor (L1 or L2 ) and two switched capacitors (C3 and C4 )
connected in series. When switched capacitors are discharged
115965
 S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design

Analyzing the waveforms obtained during the simulation

and shown in Fig. 15, we can determine the values of currents
of particular elements in the converter.
An amplitude of Im is calculated from:
ZTop
1
Iout_av = iout (t) dt
Top
0
4 Tchar 8 Tdischar 2 12A + 16B
= Im + Im = Im
π Top π Top 3 3π
(29)
Pout
Iout_av = (30)
Uout
Finally, Im can be calculated:
3π 3π Pout
Im = Iout_av = (31)
12A + 16B 12A + 16B Uout
The average values of the currents of the D1 , D3 , D4 diodes
are as follows:

FIGURE 14. Operation of the converter with voltage gain GU = 1/4.

ZTop
1
ID1av = iD1 (t) dt
Top
0
(Tdischar ), the current flows in a circuit composed of an induc- 2 Tchar 2
= Im = AIm (32)
tor L1 or L2 and a switched capacitor C3 or C4 . π Top π
Based on converter symmetry, the following relationships 4 Tchar 4 Tdischar 2 12A + 8B
can be written: ID3av = Im + Im = Im
π Top π Top 3 3π
C3 = C4 = C (21) (33)
8 Tdischar 2 16
ID4av = Im = BIm (34)
As well as for the inductors: π Top 3 3π
L1 = L2 = L (22) The RMS values of currents from the Q1 , Q3 and Q5 transis-
tors currents are:
Based on the above (21) and (22), the charging time (Tchar ) v
u
and the discharging time (Tdischar ) of switched capacitors can u Top
u 1 Z
be expressed as follows: IQ1rms = t
u i2Q1 (t) dt
r r Top
1 1 1 0
Tchar = · 2π LC = π LC (23) s
2 2 2
r
1 Tchar 2 1
1 √ √ = I = Im A (35)
Tdischar = · 2π LC = π LC (24) 2 Top m 2
2
The ratio of the two periods is as follows: Similarly, the calculation of the RMS current values of
√ the Q3 and Q5 transistors, the output current of the converter,
Tdischar = Tchar 2 (25) the current of the switched capacitor C3 , and the current of the
resonant inductor L1 are derived by the following formulas:
The overall operation period of the proposed converter is s
composed of six stages: 1 Tdischar 2 2 2 1 √
 
IQ3rms = Im = Im 2B (36)
Top = 2 · Tchar + 4 · Tdischar (26) 2 Top 3 3
s
The following ratios were used to simplify further 4 Tdischar
 2
2 2 √
calculations: IQ5rms = Im2 = Im 2B (37)
2 Top 3 3
Tchar
A= (27) v
Top u
u 2T  2 2
Tdischar t char 2 4Tdischar 2
Ioutrms = I + I
B= (28) 2Top m 2Top 3 m
Top

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S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design

r
9A + 8B
= Im (38)
9
v
u
u 2T  2 2
t char 2 2Tdischar 2
IC3rms = I + I
2Top m 2Top 3 m
r
9A + 4B
= Im (39)
9
v
u  2 2
t char 2 2Tdischar 2
uT
L1rms = Im + I
2Top 2Top 3 m
r
9A + 8B
= Im (40)
18
All derived current values were calculated on the waveforms
captured during simulation research, which, along with the
corresponding equations, can be seen in Fig. 15.
The approach chosen for the converter efficiency model
derivation assumes the analysis of RMS and average current
values in all branches of the proposed converter. During the
analysis of waveforms presented in Fig. 15, it can be observed
that amplitudes of all currents related to the switched capaci-
tors charging process have nearly the same value, which is Im .
This regularity also repeats for switched capacitor discharg-
ing processes, but in this case, the amplitude is smaller. Based
on the performed analysis of current waveforms presented
in Fig. 15, the value of this amplitude can be approximated
as 2/3 Im .
The total amount of conduction losses 1PC are described
by the sum of transistors conduction losses 1PC1 , losses
of diodes 1PC2 , ESR related losses in switched capacitors
1PC3 and losses caused by ESR of inductors and by the PCB
stray resistances 1PC4 :

1PC = 1PC1 + 1PC2 + 1PC3 + 1PC4

X4 X5
= 2
RDS(on)k IQk + 1U Dl IDlav
k=1 l=1
X2 X2
+ CESRn ICn2
+ (LESRm + rm ) ILm
2
n=1 m=1
(41)

where:
RDS(on)k is the drain-to-source on-resistance of the transis-
tor Qk. 1U Dl is the forward voltage drop across diodes Dl . FIGURE 15. Current stresses of diodes, switches, switched capacitors, and
inductors. The parameters of the model are as in Table 5.
CESRn is the resistance of switched capacitors and LESRm
is the resistance of inductors. Lm , rm are the stray resistance
of the PCB in the circuit of inductors. Lm . IQk , ICn and ILm
are RMS current values of the transistors and inductors, IDlav described by the following equation:
are average current values of diodes.
In addition, to achieve a reliable efficiency model of 1Wswon
1Pswon = (42)
the proposed converter, switching losses should also be Top
considered.
Turn-on related losses of transistors mainly depend on the where:
converter’s switching frequency and the output capacitance 1Wsw_on is the energy lost during the turn-on transition of
(COSS ) value of the transistors. This relationship can be the transistor in a single switching cycle Top .

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 S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design

For the purpose of this model derivation, we assumed

that the converter operates in ZCS mode, which causes that
turn-off related losses of the transistors can be neglected.
Switch loss calculations were performed based on the method
described in [28].
The overall efficiency of the proposed converter is
described by the following equation:
Pout
η= (43)
Pout + 1PC + 1Pswon
The efficiency curve of the proposed converter was com-
puted using equation (43). In Fig. 16, a graphical relationship
between the converter’s output power and its efficiency can
be seen.
For the calculations, it was assumed that:
L1 = L2 = L; C3 = C4 = C;
FIGURE 16. Derived efficiency model of the converter operating in ZCS
1UD1 = 1UD2 = 1UD3 = 1UD4 = 1UD5 = VF ; mode versus output power.
RDS(on)1 = RDS(on)2 = RDS(on)3
= RDS(on)4 = RDS(on)5 = RDS(on) ;
LESR1 = LESR2 = LESR ; CESR1 = CESR2 = CESR ;
r1 = r2 = r; (44)
The basic values of the efficiency model parameters are
collected in Table 5. For the purpose of efficiency analysis,
a variation of the converter’s voltage gain versus power was
considered. The increase in resistances versus power (because
of the temperature rise) is also covered in the efficiency
model. Moreover, the forward voltage versus the diode’s
current change is also implemented. A range of parameter
variations are presented in Tables 5 and 6.
FIGURE 17. Comparison between a) losses in diodes and other losses;
Based on Fig. 16, it is possible to state that the modeled b) other losses; c) losses in diodes; d) losses in transistors in the
efficiency peak value of the proposed converter is about 85%. proposed converter. Pout = 11 W.
Figs. 17 -18 show the power loss distribution among the
components of the proposed converter. From the pie chart
presented in Fig. 17a, it follows that a significant amount of
total converter losses came from diodes.

TABLE 5. Values of parameters used in efficiency model for ZCS

conditions (lower value of a parameter is at Pout = 0 W, higher value of a
parameter is at Pout = 85 W).

Further analysis of losses in diodes leads to the conclusion

that diodes (D3 , D4 , D5 ) located in the output branch of the
proposed converter are mostly responsible for large amounts
of generated losses. This conclusion is confirmed by the pie
chart presented in Fig. 17c, where this regularity can be easily
noticed. The two remaining graphs provide an overview of
other types of power loss present in this converter. Fig. 17b
visualizes the distribution of the switching and conduction
losses in the proposed device.
Conduction losses were divided into several groups
to show losses generated by the individual components.
FIGURE 18. Comparison between a) losses in diodes and other losses;
b) other losses; c) losses in diodes; d) losses in transistors in the
proposed converter. Pout = 70 W.
The biggest part of the losses related to this graph are deter-
mined by the circuit stray resistances (RLOSS ) and the RDS(on)
resistance. The two remaining parts of the chart exhibit losses
related to the equivalent series resistance of switched capac-
itors (CLOSS ) and resonant inductors (LLOSS ). The last graph
(Fig. 17d) shows only the distribution of RDS(on) related losses

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S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design

among all transistors in this converter. Fig. 18 shows the

distribution of power losses at higher output power (70 W).
To increase the efficiency of the proposed converter, sev-
eral improvements must be considered. As can be seen in
Fig. 17a, the diodes are responsible for 71% of the total losses
generated in this converter. Two possible improvements can
be made here. The first one is to use diodes characterized
by a very low forward voltage value. The second approach
is to replace the diodes with low RDS(on) transistors. Despite
the diodes, another possible improvement for the converter’s
performance increase is to reduce the stray resistance of the
PCB and passive components. These procedures allow for a
reduction in the amount of conduction losses generated by
this converter. An effect of the proposed improvements is
visible in the efficiency curves presented in Fig. 19.
The obtained efficiency model of the proposed con-
verter allows to evaluate all the efficiency improving actions
and deliver an overview of their effectiveness. In order to FIGURE 19. Model of efficiency results for the converter’s
achieve a wide view of benefits flowing from individual effi- implementation concepts in ZCS mode of operation.

ciency improving actions, the following four test cases were

developed:
Concept 1 Basic converter topology The results obtained from those particular concepts allow
Concept 2 Diodes D3 , D4 , D5 replaced by MOS- to state that the transistor’s resistance affects more signif-
FET transistors (data for model based on icantly the converter’s efficiency by higher power values.
ISC022N10NM6 documentation) Moreover, the application of diodes in the converter decreases
its efficiency for a whole range of device output powers.
Concept 3 All diodes replaced by MOSFET transis-
Based on the analysis of the characteristics obtained, it can
tors (as is Concept 2)
be concluded that concept 2 is the most optimal design due
Concept 4 All GaN transistors used (data for model
to the efficiency of the proposed converter, its manufacturing
based on EPC2302 documentation)
cost, and its complexity. This solution provides a signifi-
cant efficiency improvement and keeps this device relatively
TABLE 6. Parameters variation in analysed concepts of converter design simple and inexpensive. In the most expensive synchronous
(lower value of a parameter is at Pout = 0 W, higher value of a parameter converter designs (concepts 3 and 4), the expected efficiency
is at Pout = 85 W).
of the device can reach a relatively high value. On the basis
of the obtained results, further conclusions related to the
converter’s power density factor, output power range, and
manufacturing cost can be drawn and are collected in Table 7.

TABLE 7. Comparison of the analyzed concepts of the converter’s designs.

In Fig. 19, the efficiency curves computed for all assumed

test cases are presented. In concept 2, diodes D3 , D4 , D5
are replaced by MOSFET transistors – a significant increase
in the proposed converter efficiency is noticed. In this case,
the simulated efficiency peak value reaches 93%. The results
of the evaluation of concept 3 show an improvement in
efficiency of almost 2% compared to concept 2. Finally,
a set of simulations were conducted for the converter where
all diodes, as well as all switches, were replaced by GaN
transistors (concept 4).
In this case, a further improvement in device efficiency
was observed at a larger power. For this configuration, the
efficiency peak value of the proposed converter is above 96% VIII. EXPERIMENTAL RESULTS
and the efficiency versus power characteristics is much flatter An experimental test set-up was prepared to perform a verifi-
in comparison to other concepts. cation of the converter’s operation principle and its efficiency.

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 S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design
The photograph of the laboratory converter is presented in
Fig. 20.
FIGURE 20. Experimental test setup of the proposed step-down converter.
To achieve the best correlation between the simulation and
experimental results, the parameters of the laboratory con-
verter’s components are very close to those assumed during
simulations and theoretical investigations (Tab. 8).
TABLE 8. Parameters of the converter components.
The oscillogram presented in Fig. 21 shows a set of
basic converter waveforms, which are crucial for the under-
standing and verification of the proposed device operation
principle. From the presented waveforms, it is seen that
the converter’s operation principle assumed in the theo-
retical predictions was also met in practical application.
The shapes of the waveforms recorded on this scope cap-
ture are typical for resonant converters and fully in accor-
dance with the waveforms obtained during the simulation
research.
During the experiment, the voltage and current stresses of
the switching devices were also verified. The voltages mea-
sured across resonant capacitors, voltage and current stresses
of transistors Q1 (Fig. 22) and Q3 (Fig. 23) were captured.
From the results obtained, it is seen that the transistors oper-
ate under improved conditions. The voltage stresses across
the Q1 transistor are lower than half of the converter input
115970
FIGURE 21. Scope capture showing the basic waveforms recorded in the
proposed converter circuit. (CH1 – Voltage across the C3 resonant
capacitor; CH2 – Voltage across the C4 resonant capacitor; CH3 –
Inductor L1 current; CH4 – Current of the inductor L2). Operation in ZCS
mode. Switching frequency: 58 kHz.
voltage. It is a very appreciated feature. By analyzing the
waveforms shown in Fig. 23, it is possible to see that the
operating conditions of transistor Q3 are favorable as well.
The results presented in Figs. 21 -23 were recorded in the
ZCS operation. The full oscillation is seen in the current
waveforms. Presented waveforms allow to clearly confirm
the principle of the converter’s operation.
FIGURE 22. Scope capture showing the basic waveforms recorded in the
proposed converter circuit. (CH1 – Voltage across the C3 resonant
capacitor; CH2 – Voltage across the C4 resonant capacitor;
CH3 –Transistor Q1 voltage; CH4 –Transistor Q1 current). Operation in
ZCS mode.
Another test performed focused on ZVS operation with the
suggested converter. Fig. 24 shows a set of the converter’s
basic waveforms recorded when the examined circuit worked
in the ZVS mode. It is possible to observe that the device
switching frequency is higher than the self-resonant fre-
quency of an LC circuit. Similarly to the waveforms presented
in Fig. 7, a new switching state starts when the inductor cur-
rent is negative before it reaches zero. From this oscillogram,
it is seen that the ZVS operation mode has no undesirable
impact on the proposed converter operation.
VOLUME 10, 2022
S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design
TABLE 9. Comparison of parameters among published concepts of converters.
FIGURE 23. Scope capture showing basic waveforms recorded in the
proposed converter circuit. (CH1 – Voltage across the C3 resonant
capacitor; CH2 – Voltage across the C4 resonant capacitor;
CH3 –Transistor Q3 voltage; CH4 –Transistor Q3 current). Operation in
ZCS mode.
FIGURE 24. Scope capture showing basic waveforms recorded in the
proposed converter circuit during ZVS operation (CH1 – Voltage across
the C3 resonant capacitor; CH2 – Voltage across the C4 resonant
capacitor; CH3 – Inductor L1 current; CH4 – Inductor L2 current).
Switching frequency:68 kHz.
Fig. 25 presents the results of the efficiency measurement
performed on the experimental test setup while the converter
was operating in ZCS and then in ZVS modes. Both recorded
VOLUME 10, 2022
FIGURE 25. Comparison of converter efficiency during ZCS and ZVS
Operation.
efficiency curves were presented on the same plot plane to
emphasize the benefits of using the ZVS mode. The effi-
ciency increase noticed after ZVS switching mode enabling
is ca. 4%, which means that the efficiency peak value of
the proposed converter reaches 88%. Additionally, during
the experimental research, a test of the output voltage value
versus the output power was performed. The result of this
experiment is presented in Fig. 26. Based on this character-
istic, it can be noted that the voltage gain of the proposed
converter is affected by voltage drops on diodes and resis-
tances. Therefore, the output voltage is below the theoretical
value and falls as the power increases. In the laboratory setup,
an economical PCB board was designed based on thin copper
layers (35µm thick for the outer layers and 17.5µm for inner
layers). This is the area where future improvements can be
made. A portion of parasitic resistances can be significantly
reduced by optimizing the PCB board.
115971
 S. Folmer et al.: 48-V input DC-DC High Step-Down Converter in GaN-Based Design
FIGURE 26. Measured output voltage of the converter versus. the output
power of the converter.
IX. CONCLUSION
The presented analysis and results lead to the fol-
lowing conclusions related to the proposed concept of
a converter:
- The topology ensures low voltage stress across switches.
- Nearly non-inductive design can be applied to achieve
correct operation with ZCS and ZVS. The reso-
nant converter operates using small (125 nH SMD
chokes).
- In the design a minimal number of transistors is used,
the converter achieves an acceptable efficiency.
- Significant improvement in efficiency can be achieved
in the concept in which three diodes are replaced by
transistors with low RDS(on) .
- A step change of the converter voltage gain can be
achieved by changing the switching strategy. Operation
with the voltage gain G = 1/6 and G = 1/4 was
demonstrated.
- Continuous regulation of the output voltage is
possible.
- ZVS operation can be controlled to avoid voltage spikes.
- A comparison of the proposed converter among pub-
lished concepts (Tab. 9) shows that the proposed con-
verter can operate using a low number of transistors.
Moreover, output voltage regulation and the low num-
ber of internal capacitors utilized in the suggested
topology are beneficial properties of this converter as
well.
- The operation concept of this topology is confirmed and
verified by experiments.
- Experimental research shows an impact of the high cur-
rents distributed on the PCB on the voltage gain of the
converter.
115972
- Engineering issues related to stray resistance minimiza-
tion, components selection, and PCB design are very
important for the performance of such a converter.
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