// Code your design here

module piso(data_out,valid_out,ready_in,data_in,valid_in,ready_out,clk_rx,rst,clk_tx);

parameter width=4;

output reg[width-1:0] data_out;

output reg valid_out,ready_in;

input[width-1:0] data_in;

input valid_in,ready_out,clk_rx,rst,clk_tx;

reg[width-1:0] q;

always@(posedge clk_rx,negedge rst)begin

if(!rst)

begin

q<=0;

end

else

begin

if(valid_in)

begin

q<=data_in;

ready_in<=1;

end

else

begin

ready_in<=0;

end

end

end

always@(posedge clk_tx,negedge clk_tx,negedge rst)begin

if(!rst)
 begin

data_out<=0;

end

else

begin

if(ready_out)

begin

q[0]<=data_in[0];

q[width-3]<=q[0];

q[width-2]<=q[width-3];

q[width-1]<=q[width-2];

data_out<=q[width-1];

valid_out<=1;

end

else

begin

valid_out<=0;

end

end

end

endmodule

// Code your testbench here

// or browse Examples

module tb();

parameter width=4;

reg [width-1:0]data_in;

reg valid_in,ready_out,clk_rx,clk_tx,rst;
 wire [width-1:0] data_out;

wire valid_out,ready_in;

piso dt
(.data_in(data_in),.valid_in(valid_in),.ready_out(ready_out),.clk_tx(clk_tx),.clk_rx(clk_rx),.rst(rst),.data_o
ut(data_out),.valid_out(valid_out),.ready_in(ready_in));

initial begin

clk_rx=0;

forever #5 clk_rx = ~clk_rx;

end

initial begin

clk_tx=1;

forever #2.5 clk_tx = ~clk_tx;

end

initial begin

$dumpfile("dump.vcd");

$dumpvars(1);

rst=0;

data_in=4'b0111;

valid_in=1;

ready_out=1;

#10

rst=1;

data_in=4'b1011;

valid_in=1;

ready_out=1;

#15

data_in=4'b1001;

#20

data_in=4'b1111;
 valid_in=0;

ready_out =1;

data_in=4'b1101;#25

#30

data_in=4'b1001;

#35

data_in=4'b0111;

#100

$finish;

end

endmodule