0 IntroductionToComputing

www. Micro Digital Ed.
com
BIHE university
Introduction to Computing
Chapter 0
Sepehr Naimi
www.NicerLand.com
www.MicroDigitalEd.com
Topics
www. Micro Digital Ed. com
BIHE university
• Internal organization of computers

– The different parts of a computer
• I/O
• Memory
• CPU
– Connecting the different parts
• Connecting memory to CPU
• Connecting I/Os to CPU
– How computers work
2
Internal organization of computers
BIHE university
• CPU
• Memory
• I/O
– Input
• E.g. Keyboard, Mouse, Sensor
– Output
• E.g. LCD, printer, hands of a robot
3
Memory
BIHE university
• Everything that can store, retain, and recall

information.
– E.g. hard disk, a piece of paper, etc.
4
Memory characteristics
BIHE university
• Capacity
– The number of bits that a memory can store.
• E.g. 128 Kbits, 256 Mbits
• Organization
4 bits
– How the locations are organized 0
128 locations
1
• E.g. a 128 x 4 memory has 128 locations, 2
4 bits each
…
127
• Access time
– How long it takes to get data from memory
5
Memory
BIHE university
• Semiconductors
The pictures are copied from http://www.wikipedia.org/

• Non-semiconductors
6
Semiconductor memories
BIHE university
• ROM RAM •
– Mask ROM SRAM (Static RAM) –
– PROM (Programmable DRAM (Dynamic RAM) –
ROM) NV-RAM (Nonvolatile –
– EPROM (Erasable RAM)
PROM)
– EEPROM (Electronic
Erasable PROM)
– Flash EPROM
7
Memory\ROM\Mask ROM
BIHE university
• Programmed by the IC manufacturer
8
PROM (Programmable ROM)
Memory\ROM\
BIHE university
• OTP (One-Time Programmable)

– You can program it only once
9
Memory\ROM\ EPROM (Erasable Programmable ROM)
BIHE university
• UV-EPROM
– You can shine ultraviolet (UV) radiation
to erase it
– Erasing takes up to 20 minutes
– The entire contents of ROM are erased
2764
10
EEPROM (Electrically Erasable
Memory\ROM\

Programmable ROM) BIHE university
• Erased Electrically RDY/BSY

A12
VCC
WE
A7 NC
– Erased instantly A6 8K x 8 A8
A5 A9
– Each byte can be erased separately A4
A3
A11
OE
A2 A10
A1 CE
A0 I/O7
I/O0 I/O6
I/O1 I/O5
I/O2 I/O4
VSS I/O3
11
Flash ROM
Memory\ROM\
BIHE university
• Erased in a Flash
• the entire device is erased at once
12
Semiconductor memories
BIHE university
• ROM RAM •
– Mask ROM SRAM (Static RAM) –
– PROM (Programmable DRAM (Dynamic RAM) –
ROM) NV-RAM (Nonvolatile –
– EPROM (Erasable RAM)
PROM)
– EEPROM (Electronic
Erasable PROM)
– Flash EPROM
13
Memory\RAM\ SRAM (Static RAM)
BIHE university
• Made of flip-flops (Transistors)

• Advantages: 2K x 8
– Faster SRAM
– No need for refreshing

• Disadvantages:
– High power consumption
– Expensive
14
DRAM (Dynamic RAM)
Memory\RAM\
BIHE university
• Made of capacitors
• Advantages:
– Less power consumption
– Cheaper
– High capacity
• Disadvantages:
– Slower
– Refresh needed
15
NV-RAM (Nonvolatile RAM)
Memory\RAM\
BIHE university
• Made of SRAM, Battery, control circuitry

• Advantages:
– Very fast
– Infinite program/erase cycle
– Non-volatile
• Disadvantage:
– Expensive
16
Internal parts of computers\CPU
BIHE university
• Tasks:
– It should execute instructions
• It should recall the instructions one after another
and execute them
17
Connecting memory to CPU
BIHE university
• Memory pin out
VCC
GND VCC
8
D0-D7
n
A0-An-1
WE
OE
CS
18
Connecting memory
Writing
Reading memory to CPU
to memory
from
Address
Address
BIHE university
CS
CS
OE
Data
Data
WE
WE
Time
Time
VCC
GND VCC
8
D0-D7
CPU n
A0-An-1
WE
OE
CS
19
Connecting I/Os to CPU
BIHE university
• CPU should have

lots of pins! Mouse
Network
CPU Keyboard
Sound Card
Graphic Card
20
Connecting I/Os to CPU using bus
BIHE university
Address bus
Data bus
Write
Control bus Read
CPU
I/O 0 I/O 1 I/O 2 I/O n
21
Connecting I/Os and Memory to CPU
BIHE university
Address bus
Data bus
Write
Control bus Read
CPU I/O 0 I/O 1 I/O 2 I/O n

VCC
GND VCC
n
A0-An-1
8
D0-D7
WE
OE
CS
22
Connecting I/Os and memory to CPU using bus
BIHE university
VCC
1
How could we manage it? 2

3
A0-An-1
GND
D0-D7
WE
OE
CS
0
Address bus
Data bus
Write
Control bus Read
CPU
I/O 0 I/O 1 I/O 2 I/O n
23
Connecting I/Os and Memory to CPU using bus
(Peripheral I/O) BIHE university
VCC
0
1
..
63
A0-An-1
GND
D0-D7
WE
OE
CS
Address bus
Data bus
Write
Control bus Read
IO/MEM
CPU
I/O 0 I/O 1 I/O 2 I/O n
24
Connecting I/Os and Memory to CPU using bus
(Memory Mapped I/O) BIHE university
The logic circuit
VCC
0
1 enables CS
How could we make the logic ..
15
when address is
A0-An-1
circuit? between 0 and
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Solution
Control 1.
bus Write
Write the address range in binary
Read
2. Separate the fixed part of address
CPU3. Using a NAND, design a logic circuit whose output

activates when the fixed address is given to it.
a7 a6 a5 a4 a3 a2 a1 a0
From address 0  0 0 0 0 0 0 0 0 a4
I/O 16 I/O 17 I/O a5
18
a6
I/OCS
n
To address15  0 0 0 0 1 1 1 1 a7
25
Another example for address decoder
BIHE university
• Design an address decoder for address of 300H

to 3FFH.
Solution
1. Write the address range in binary
2. Separate the fixed part of address
3. Design the logic circuit.
a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a8
a9
From address 300H  0 0 1 1 0 0 0 0 0 0 0 0 a10 CS
a11
To address 3FFH  001111111111
An easy way of
designing
26
Inside the CPU
BIHE university
• PC (Program Counter)
• Instruction decoder
• ALU (Arithmetic Logic Unit)
• Registers
PC A
ALU B
CPU C
D
Instruction decoder registers
27
How computers work 0 31h
31
1 C4h A [17]
2 26h
BA BIHE university
A  [6]
VCC
3 81h
AA+B
4 EAh
[7]A
5 0h
A0-An-1
GND
6 5h
D0-D7
WE
7
OE
CS
Logic circuit
Address bus
Data bus
Write
Control bus Read
ALU
CPU A
B
PC: 10 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers
28
1 C4h A [17]
2 26h
A  [6]
VCC
3 81h
AA+B
4 EAh
[7]A
5 0h
A0-An-1
GND
6 5h
D0-D7
WE
7
OE
CS
Logic circuit
Address bus 17
Data bus
Write
Control bus Read
ALU
CPU A
B
PC: 1 C 9
D I/O 16 I/O 17 I/O 18 I/O n

31
29
1 C4
C4h A [17]
2 26
26h
A  [6]
VCC
3 81h
AA+B
4 EAh
[7]A
5 0h
A0-An-1
55h
GND
6
D0-D7
WE
7
OE
CS
Logic circuit
Address bus 176
Data bus
Write
Control bus Read
ALU
CPU 9
A
B
PC: 1
2
3 C
D I/O 16 I/O 17 I/O 18 I/O n
30
1 C4h A [17]
2 26h
A  [6]
VCC
3 81
81h
AA+B
4 EA
EAh
[7]A
5 0h
A0-An-1
GND
6 5h
D0-D7
WE
7
OE
CS
7 Logic circuit
Address bus
Eh
Data bus
Write
Control bus Read
+
ALU
E CPU A
9
B
E
5
PC: 4
35 C
D I/O 16 I/O 17 I/O 18 I/O n
31
How Instruction decoder works
BIHE university
Opcode Operand Opcode Operand
Instruction
Instruction
Operation Code Meaning

000 Ax
0011 0001 0 31h
1100 0100 1 C4h A [17] 001 A  [x]
0010 0110 26h
BA
2
A  [6] 010 A  A – register (x)
1000 0001 3 81h
AA+B 011 AA+x
1110 1010 4 EAh
[7]A
0000 0000 5 0h 100 A  A + register (x)
0000 0101 6 5h
7
101 AA–x
110 Register (xH)  Register (xL)
111 [x]  A
32
Von Neumann vs. Harvard architecture
BIHE university
Data bus Data bus

Code Data
Memory Address bus CPU Address bus Memory
Control bus Control bus
• Harvard architecture
Code Data
Memory Memory
Data bus
CPU Address bus
Control bus
• Von Neumann architecture

33

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0 IntroductionToComputing

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www. Micro Digital Ed.

• Internal organization of computers

• Everything that can store, retain, and recall

The pictures are copied from http://www.wikipedia.org/

• Programmed by the IC manufacturer

• OTP (One-Time Programmable)

www. Micro Digital Ed. com

• Erased Electrically RDY/BSY

• Made of flip-flops (Transistors)

– No need for refreshing

• Made of SRAM, Battery, control circuitry

• Memory pin out

• CPU should have

CPU I/O 0 I/O 1 I/O 2 I/O n

How could we manage it? 2

The logic circuit

CPU3. Using a NAND, design a logic circuit whose output

• Design an address decoder for address of 300H

D I/O 16 I/O 17 I/O 18 I/O n

Opcode Operand Opcode Operand

Operation Code Meaning

Data bus Data bus

• Von Neumann architecture

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