Physical Design Concept talk By Atun : (Negative hold time)

During my initial years of working, this topic was confusing me too much. So i am here clearing
all the doubts.

Can hold time of a flop be negative ?

And the Answer is YES.
Generall hold time of a sequential element is positive, however it can be 0 and also negative
values
Well, then how can hold time be negative ?
What is the meaning of negative hold time or what is the physical meaning of negative value?

All this happens , because of the internal structure of the register. A negative hold value will
come if there is an extra delay in the data pin internally to the register.
You all know very well that the hold time is the minimum time that an input signal must remain
stable after the active edge of clock , so that the data is understood properly.
Generally inside a flip-flop, there would be some buffers connected to the clock pin and data
pin.
Therefore there would be an internal delay of clock pin called D-clock and internal delay of data
pin called D-data inside the flip-flop.
And the difference between these two delays is what we call as the hold time of the flop .
Therefore the hold time (T-hold) will be D-clock - D-data.
Usually for the data pin the number of buffer is fewer or even zero, So T-hold is positive.
We have to do this so that our data remains unchanged during this time frame. If the data inner
delay is bigger than clock inner delay, we will have a negative hold-time, which means the data
can change before the clock edge, and the inner data buffer would delay the data such that there
is no overlap or collison of data inside the register.

Hope this clears your doubt. One more interesting topic is how the tool deals with the negative
hold time or how the timing calculations are done with negative hold time ? (Would love to hear
your answers in my comments section )

#physicaldesign #sta

C1-Physical Design Concept Talk : (Library Tracks)

We see for a technode there are multiple tracks of library. What are the Library tracks ? Which
Library tracks will give better performance and power ?

First Let's understand what the track means. In most tech nodes, these tracks of Library means
how many M2 tracks are present in the unit cell. Suppose we have 9Track Library and 12Track
Library in a tech node. When we say 9T library it means in a single height cell, 9 M2 tracks are
there. For example, suppose M2 track pitch is 40nm. Then the height of 9T cell will be 9*40 =
360nm and similarly, a 12T cell will be 12*40nm = 480nm in height.

Now , What is the significance of these M2 routing tracks in a standard cell ?

More routing tracks mean more routability of M2 layers. Standard cell pins are all in lower layers,
so ease of routing. Cell size is more for higher routing track libraries, which means delay is less
and these cells are comparatively faster. With fewer routing tracks, cells become dense, and
leakage power is comparatively reduced, but due to less number of M2 tracks, routing becomes
challenging.

So if your design requirements are high freq, use higher track library cells and if you want low
power or a balanced Performance and Power use the library with fewer tracks.

JUSTIFICATION: Yes , a 9T Library will have more number of instance than 12T library for the
same area. For a 7.5T Library, an offset in M2 track is there either in the top or bottom of the cell.
Suppose, there is a cell height of 300nm, and M2 track pitch is 40nm. So in that cell only 7
routable M2 tracks can be present (7*40 = 280nm) and 20nm M2 track offset will be there either
at the top or bottom boundary. This half offset of M2 is what we call as half-track library. This half
track wont be useful for cell level routing, but the 7.5 T libraries will be more dense and generally
the dynamic power of these libraries seems to be less.

#physicaldesign