DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA, SURATHKAL

EC702 ANALOG IC DESIGN
MID SEMESTER EXAMINATION - ODD 2020-21

Date: 02-12-2020 Time: 4.30-5.30 PM

Duration: 60 minutes Max. marks: 20

NOTE: Information about the mode of exam

• You shall write the exam with integrity.

• Write your name and roll number on the top of every answer sheet.

• Every page must be numbered at the bottom of the page.

• After the exam you are required to scan the document in a pdf form and upload onto Moodle.

• 10 minutes will be allowed for uploading the answer paper.

• You will be allowed to upload the paper upto 6 PM. However, there will be a penalty of 1 mark for
every two minutes delay beyond 10 min (i.e. beyond 5.40 PM).

NOTE: for answering the questions

• Clearly mention the assumptions made (if any) in derivations or solving problems.

• Assume following parameters for the transistors, unless otherwise specified in the problem.
µn Cox = 190 µA/V2 , µp Cox = 55 µA/V2 , Vth,n =0.6 V, |Vth,p |= 0.7 V, λn =λp =0.

• Choose, for all transistors, length L=0.6 µm.

• Missing data, if any, may be suitably assumed.

1. A voltage amplifier has a gain of 100, input resistance of 10 kΩ and output resistance of 200 Ω. This
amplifier is put in voltage-series feedback where 20% of the output terminal voltage is fed back.

(a) Find the closed loop voltage gain, input impedance and output impedance.
(b) If the cloased loop amplifier is driven by a voltage source of 2 V having a source resistance of
RS =10 kΩ and the load on the amplifier is RL =200 Ω what will be the voltage across RL .
[3+4]

2. For the circuit shown in Figure 1 sketch the current IX as a function of VX when VX varies from 0
to 1.5 V. Assume width of the transistor M1 to be W =48 µm. [4]

3. For the circuit shown in Figure 2. Find the following if VIN =1 V the width of Mn is 12 µm and that
of Mp is 36 µm

(a) The region of operation of both the transistors.

(b) Voltage across the current source
(c) Small signal voltage gain vout /vin [4+2+3]

1
 VDD=3 V
+ 1.2 V
−
M1 Mp
VOUT+vout
+ 1.5 V IX VIN+vin
−
Mn
+ V
− X

1.7 kΩ

Figure 1
Figure 2