A 3.2fJ/c.-s. 0.
35V 10b 100KS/s SAR ADC in 90nm CMOS
Hung-Yen Tai, Hung-Wei Chen and Hsin-Shu Chen
Graduate Institute of Electronics Engineering and Department of Electrical Engineering
National Taiwan University, Taipei, Taiwan
Email: hschen@cc.ee.ntu.edu.tw
Abstract
A low-voltage energy-efficient SAR ADC is presented in
this paper with four techniques. Arbitrary weight capacitor
array tolerates errors to reduce conversion time. To operate
under low voltage, DAC common mode level shift and
leakage reduction sample switch with a charge pump are
proposed. Differential control logic is used to save its digital
power. The prototype ADC consumes 170nW at 100KS/s
from a 0.35V supply. It achieves an SNDR of 56.3dB at
Nyquist rate and its FOM is 3.2fJ/c.-s.
Keywords: Low voltage, low power, SAR ADC
Introduction
Wireless sensor networks are frequently used to monitor
environmental conditions. Because power sources are often
limited in the field, energy efficiency is essential. The sensor
typically requires a 10b 100KS/s ADC to convert a natural
signal. Among various architectures, SAR has better energy
efficiency [1] and it can only dissipate dynamic power. Since
supply voltage and capacitance loading affect the dynamic
power, decreasing the supply voltage and simplifying
controller logic can enhance energy efficiency. However, a
low supply voltage decreases the gate-source voltage (Vgs)
and it causes design challenges. The S/H switch is hardly
turned on during sampling, for example. In addition, it results
in a long conversion time because the comparator is activated
by a low input voltage. Hence, a leakage from the DAC
capacitor array deteriorates the accuracy and it cannot be
neglected. This work adopts an arbitrary weight capacitor
array (AWCA), which allows comparator errors in MSB. The
DAC common mode level shift (DCMLS) technique is
proposed to increase Vgs of the comparator input pair; thus,
the comparator can operate at low voltage. Above two
techniques can reduce the conversion time and alleviate the
leakage effect. The leakage reduction sample switch (LRSS)
combined with the charge-pump improves the sample switch
performance under low voltage. It decreases drain-source
voltages to further minimize the leakage. For more digital
power saving purpose, the differential control logic is applied.
This paper presents a 10b 100KS/s SAR ADC that achieves a
FOM of 3.2fJ/c.-s. at a 0.35V supply.
Architecture and Circuit Implementation
The block diagram of the proposed ADC is shown in Fig. 1.
It consists of a charge-pump circuit, an LRSS, an AWCA, a
dynamic comparator, a SAR controller, and a clock generator.
When CLK is high, the input signal is sampled into the
AWCA by the LRSS circuit. The conversion starts when CLK
becomes low. Then, RES changes to high and enables the
dynamic comparator. By asynchronous technique, the
comparator sends a flag, DONE, to the clock generator once a
bit is resolved. The clock generator then resets RES to low.
The SAR controller latches the comparator result and
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manages the AWCA output for the next comparison. After the
AWCA settles, RES becomes high again. This procedure
repeats until the conversion is completed. The non-binary
technique [2] allows errors in MSB comparisons. Therefore,
the DAC settling and the signal-dependent dynamic offset of
comparator have less effect on performance. The AWCA
capacitance weight is {224, 128, 72, 40, 23, 12, 6, 4, 2, 1}.
Arbitrary weight for each bit and radix less than 2 are utilized
in the AWCA. Our work does not need a thermometer code
DAC and a complex logic controller for the next comparison.
The set-and-down technique [3] conserves switching
energy and decreases the conversion time. However, its DAC
output common mode voltage (Vocm) starts at the middle of
the supply voltage and it cannot operate at a low supply
voltage. To ensure that the comparator with NMOS input pair
resolves bits, the DCMLS technique is used to level-shift the
AWCA Vocm to a higher voltage during conversion. The
AWCA waveform with the DCMLS technique is illustrated in
Fig. 2. During sampling, the bottom plates of capacitors are
connected to the input, and the top plates are connected to
Vrefn. At Phase1, all top plates of capacitors switch from
Vrefn to Vrefp, except for the MSB capacitor. Cp+ and Cp-
are both level-shifted by (288/512)Vref where Vref is equal to
Vrefp-Vrefn. Hence, Vocm is level-shifted by the same
amount higher than the input signal common mode voltage
(Vicm). At Phase2, the AWCA associated with the lower
voltage between Cp+ and Cp- switches its MSB capacitor
from Vrefn to Vrefp. Vocm is then level-shifted to
(400/512)Vref higher than Vicm. At Phase3, the AWCA
associated with the higher voltage switches from Vrefp to
Vrefn. Vocm is level-shifted to (336/512)Vref higher than
Vicm. For the remaining phases, the AWCA associated with
the higher voltage switches from Vrefp to Vrefn. Thus, as the
conversion proceeds, Vocm reaches the voltage
approximately Vref/2 higher than Vicm.
Fig. 3 shows the LRSS with the charge-pump circuit. It
increases the ratio of switch turn-off and turn-on resistance. In
addition, it decreases the leakage and input disturbance. The
cross-coupled charge-pump generates SA and SAb with a
180° phase difference for the sample switch. During sampling,
SA reaches the double of the supply voltage and is used to
turn on NMOS, M1-M2. However, the NMOS turn-on
resistance is augmented when the input level is close to Vrefp
because the body effect increases the NMOS threshold, and
the leakage current reduces the SA voltage. Hence, PMOS is
added to ensure low turn-on resistance for rail-to-rail input
range. During conversion, SA is connected to ground. SAb
reaches the double of the supply voltage, and NET1 connects
to Vrefp. The LRSS with NET1 connecting to Vrefp can
prevent the input signals from coupling through device
drain-source capacitors. As the conversion continues, the
AWCA outputs approach Vrefp. NET1 connecting to Vrefp
also reduces M2-M3 drain-source voltages; therefore, the
2012 Symposium on VLSI Circuits Digest of Technical Papers 92
leakage is decreased. Moreover, since the M2 gate is at
ground and the M3 gate is at the highest voltage, M2 and M3
are in strong turn-off state to enlarge resistance.
The differential control logic for the AWCA in the SAR
controller is illustrated in Fig. 4. At the start of sampling, its
outputs are reset to Vrefn by setting LA to low. Once the
comparator outputs are ready to be sampled, the
corresponding LA becomes high. Then, either M1 or M2 is
turned on, and positive regeneration changes one of the latch
outputs to high. M3 and M4 are used to latch the output state, Fig. 2 AWCA waveform with DCMLS
even if the comparator outputs change afterward. Our
approach reduces the control logic device count by around
60% compared with the set-and-down work [3].

Experimental Results
The chip micrograph of the ADC fabricated in 90nm
CMOS process is shown in Fig. 5. The core circuit occupies
Fig. 3 Charge-pump and LRSS
an area of 0.03mm2 (128μm×252μm). The ADC, including
output synchronous registers, consists of 402 NMOS and 375
PMOS. Fig. 6 shows the DNL and INL with a 100KS/s 50%
duty clock at 0.35V, which are +0.2/-0.3 LSB and +0.6/-0.6
LSB, respectively. The FFT plot is illustrated in Fig. 7. At the
Nyquist rate input, the SFDR, THD, SNR, and SNDR are
71.0dB, 64.5dB, 57.0dB, and 56.3dB, respectively. The
measured total power dissipation is 170nW. It is broken down
as follows: the AWCA uses 40% of the power; the comparator
uses 23%; the charge-pump, the LRSS, the clock generator, Fig. 4 AWCA differential control logic
and the SAR controller use 37%. The FOM is 3.2fJ/c.-s. and
its standard deviation is 0.19fJ/c.-s. with all available 8 test
chips. The ADC achieves the lowest reported FOM result,
which is 27% less than [1].

Acknowledgment
The authors thank Taiwan Chip Implementation Center for
chip fabrication and National Science Council for supporting Fig. 5 Chip micrograph
of this work.

References
[1] M. V. Elzakker, et al., “A 1.9μW 4.4fJ/conversion-step 10b
1MS/s charge-redistribution ADC,” IEEE ISSCC Dig. Tech.
Papers, pp. 244-245, Feb. 2008.
[2] F. Kuttner, “A 1.2V 10b 20MSamples/s non-binary successive
approximation ADC in 0.13μm CMOS,” IEEE ISSCC Dig. Tech.
Papers, pp. 176-177, Feb. 2002.
[3] C. C. Liu, et al, “A 10-bit 50-MS/s SAR ADC with a monotonic
capacitor switching procedure,” IEEE Journal of Solid-State
Circuits, vol. 45, no.4, pp. 731-740, April 2010.

Fig. 6 Measured DNL and INL

Fig. 1 Proposed ADC architecture Fig. 7 FFT plot

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Authorized licensed use limited to: National Chung Cheng University. Downloaded on May 02,2022 at 00:13:30 UTC from IEEE Xplore. Restrictions apply.