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Electrostatic Discharge 개요

큐알티반도체

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• Electrostatic Discharge

• ESD model and Test mode

• LATCH-UP

• LATCH-UP Test 방법

• JEDEC & AEC Q-100 ESD Latch-up 비교

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What is ESD ?

• Electrostatic discharge (ESD)

• 대전된 물체의 전위가 다른 물체와 접촉하여 짧은 순간에


전하의 이동이 발생하는 것.

• 접지 체와의 접촉으로 인하여 대전 물체가 가진 에너지가


순간적으로 방출되는 현상.

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ESD Model

• Human Body Model (HBM)

• Machine Model (MM)

• Charged Device Model (CDM)

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ESD Model

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HBM Model

• Test standard : JESD22-A114F / AEC-Q100

charged person(사람)이 device와 접촉하면서 발생하는


정전기에 대한 저항성 평가. C=100pF, R=1.5kΩ

R
HV DUT
Supply
C

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MM Model

• Test standard : JESD22-A115A / AEC-Q100

charged equipment(장비)가 device와 접촉하면서 발생하는


정전기에 대한 저항성 평가. C=200pF, R=0Ω

R
HV DUT
Supply
C

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ESD Testing Mode

• VDD (Power) Mode : VDD Pin을 GND 化하고 Others Pin Zapping.

VDD VDD
V 0V

0V
-V

VSS VSS

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• VSS Mode : VSS Pin을 GND 化하고 Others Pin Zapping.

VDD VDD
0V V

0V
-V

VSS VSS

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• Non-power Pin (IO) Mode : Power & VSS Pin을 제외한


Non-power (IO) pin을 GND 化하고
Test 하고자 하는 1개의 I/O pin을 Zapping.

VDD VDD
V 0V

0V -V

VSS VSS

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CDM Model

• Test standard : JESD22-C101F / AEC-Q100

• charged device가 metallic GND와 접촉하면서 짧은 시간 안에


device에서 GND로 discharge 하면서 발생하는 정전기에 대한
저항성 평가.

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Field Induced (JESD22-C101F / AEC-Q100)


-Field charged plate의 전위를 높여 제품을 Charge 시키는 방법.

Field Induced Method


1Ω

Upper Ground plane


Discharge Probe
Insulating Fixture
containing Field
Charging electrode

EHT

☞ 금속 전극이 Device Package의 표면에 접촉하는 방법을 이용한 것으로 금속전극에


전압을 인가하고, 측정단자는 접지시켜 방전 경로를 형성시켜서 Device의 한계량을
평가하는 방법.

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Direct charged (AEC-Q100)


-Pin (VSS 또는 Power)을 통하여 Charge 시킨 후 Others pin으로 Discharge.

Direct Charge Method

1Ω

Upper Ground plane

EHT charge Probe Discharge Probe

☞ Device Pin을 통해 단자를 접촉시켜 전압을 인가한 후 접지된 측정단자로 방전 경로를


형성시켜 Device의 한계를 평가하는 방법.

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LATCH-UP ?

• CMOS 구조에서 외부의 전압 변동이나, 전기적 잡음 등으로


기생 bipolar Tr이 Turn on되어 소자의 동작을 방해 또는 파괴시키는 현상.
Vin

Vdd
Vout +

Vss

P+ N+ N+ P+ P+ N+
Rpw ②
⑤ R-n sub
Tr2 Tr4 Tr1 Tr3

P -Well


N -Well

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I-Test

„ Test standard : JESD 78B / AEC-Q100


- Current Injection mode

Trigger Source Vsupply


+ - + -
Positive + 100 mA
Trigger Test Conditions
Test terminal Negative - 100 mA
VDD
The output terminal
Connected to the input
Is opened
Terminal the power supply
If absolute Inom≤25 mA, then absoulute Inom+10 mA is used
Or the GND Terminal
GND or
If absolute Inom>25 mA, then > 1.4 x absoulete Inom is used

Isupply Measurement

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Vsupply over voltage test

„ Test standard : JESD 78B / AEC-Q100


- Voltage Injection mode

Vsupply(1.5 X max. Vsupply)


+ -

Trigger Test Conditions Positive 1.5 X max Vsupply

Connected to the input VDD The output terminal


Terminal the power supply Is opened
Or the GND Terminal If absolute Inom≤25 mA, then absoulute Inom+10 mA is used
or
GND
If absolute Inom>25 mA, then > 1.4 x absoulete Inom is used

Isupply Measurement

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JEDEC & AEC Q-100 ESD Latch-up 비교

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HUMAN BODY MODEL


Standard JEDEC AEC-Q-100

EOS/ESD Assoc STM5.


규격 JEDEC22-A114-F
EIA/JESD22-F114

Sample size 3 3

No of Zaps 1 positive &1 negative 1 or 3 positive & 1 or 3 negative

Pulse Interval ≥ 0.1s ≥ 0.5 s

Pin group

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HUMAN BODY MODEL _ Classification

JEDEC AEC-Q-100

Component Class. Maximum Voltage

CLASS 0 ≤ 250V

CLASS 1A 250 to < 500V

CLASS 1B 500 to < 1000V

CLASS 1C 1000 to < 2000V

CLASS 2 2000 to <4000V

CLASS 3A 4000 to < 8000V

CLASS 3B > 8000V

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MACHINE MODEL

Standard JEDEC AEC-Q-100


EOS/ESD Assoc STM5.
참고 규격 JEDEC22-A114-A
EIA/JESD22-F114

Sample size 3 3

No of Zaps 1 positive &1 negative 3 positive & 3 negative

Pulse Interval ≥ 0.5 s ≥ 1.0 s

Pin group

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MACHINE MODEL _ Classification

JEDEC AEC-Q-100

Component Class. Maximum Voltage

CLASS A < 200V

CLASS B 200 to < 400V

CLASS C ≥ 400V

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CHARGED DEVICE MODEL

Standard JEDEC AEC Q-100

EOS/ESD Assoc STM5.


참고규격 JEDEC22-A114-E
EIA/JESD22-D114

Sample size 3 3

No of Zaps 3 positive &3 negative 3 positive & 3 negative

Field-Induced Field-Induced Charge or Direct Charge


Charged
(Charge Cover : FR4) (Charge Cover : 130 Microns thick )

Test Pins All pins All pins

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CARGED DEVICE MODEL _ Classification

JEDEC AEC-Q-100

Component Class. Maximum Voltage

CLASS Ⅰ < 200V

CLASS Ⅱ 200 to < 500V

CLASS Ⅲ 500 to 1000V

CLASS Ⅳ ≥ 1000V

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LATCH-UP TEST
Standard JEDEC AEC-Q-100

참고규격 JEDEC 78B JEDEC 78B

Sample size 6 6

Test Temperature
Class Ⅰ or Class Ⅱ Class Ⅱ
Class

I-Test and Vsupply over voltage Test E-Test or I-Test

Test Matrix

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ESD is important
• Distribution of failure modes in silicon ICs

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