Lecture 4

Addressing modes of 8086

Introduction
• An addressing mode basically focuses on presenting the
address of the operand in the instructions.
• Addressing modes play a critical role in computer
architecture by enabling efficient access to data and
instructions in the memory and registers
• According to the flow of instruction execution, the
instructions may be categorized as:
i) Sequential control flow instructions and
ii) Control transfer instructions
Cont.,
• Sequential control flow instructions are the instructions,
which after execution, transfer control to the next
instruction appearing immediately after it (in the sequence)
in the program.
• For example, the arithmetic, logic, data transfer and
processor control instructions are sequential control flow
instructions.
• The control transfer instructions, on the other hand,
transfer control to some predefined address or the address
somehow specified in the instruction, after their execution.
• For example, INT, CALL, and JUMP instructions fall under
this category.
Instruction Format
• Instruction format is a binary format which
specifies a computer instruction.
• The format of an instruction is depicted in a
rectangular box symbolizing the bits of the binary
instruction.
• The bits are divided into groups called fields.
• The following are typical fields found in instruction
formats:
Cont.,
1. An opcode field, which specifies the operation to
be performed.
2. An address field, which provides either a memory
address or an address that selects a processor
register.
3. A mode field, which specifies the way the address
field is to be interpreted.
Instructions Classification according to
operand addressing:
1. Three-Address Instructions
• Consider an instruction such as ADD, which
specifies the addition of two operands to produce a
result.
• Suppose that the result of the addition is treated
as just another operand.
• Then the ADD instruction has three operands.
ADD T1, A, B , M[T1] <-- M[A] + M[B]
2- Two-Address Instructions
• For two-address instructions, each address field can
again specify either a possible register or a memory
address.
• The first operand address listed in the symbolic
instruction also serves as the implied address to
which the result of the operation is transferred.
• The program is as follows:
3- One-Address Instruction
4- Zero-Address Instructions
• To perform an ADD instruction with zero addresses,
all three addresses in the instruction must be
implied.
• A conventional way of achieving this goal is to use
a stack, which is a mechanism or structure that
stores information such that the item stored last is
the first retrieved.
Addressing modes:

• We can classify the 8086 addressing modes into:

- Register Addressing Modes
- Memory Addressing Modes
- Immediate Addressing Mode.
• Where Register & Memory addressing transfers a copy of a
byte or word from the source addressing register or
contents of a memory location to the destination register or
memory location.
• Immediate addressing transfers the source, an immediate
byte, word, into the destination register or memory
location.
Cont.,
• Because the MOV instruction is a very common and
flexible instruction, it provides a basis for the
explanation of the data-addressing modes.
mov destination, source
• This instruction copies the data from the source
operand to the destination operand.
Cont.,
• The eight- and 16-bit registers are certainly valid operands
for this instruction. The only restriction is that both
operands must be the same size.
• Now let's look at some actual 8086 mov instructions:
1. Immediate Addressing Mode
• In this type of addressing, immediate data is a part of
instruction and appears in the form of successive byte or
bytes.
• Ex:
MOV AX, 0005H
• In the above example, 0005H is the immediate data.
• The immediate data may be 8-bit or 16-bit in size.
• Ex:
Examples
2. Direct Addressing Mode
• Direct addressing moves a byte or word between a memory
location addressing and a register.
• In the direct addressing mode a 16-bit memory address
(offset) is directly specified in the instruction as a part of it.
• Ex: MOV AX, [5000H]
• Here, data resides in a memory location in the data
segment, whose effective address may be completed using
5000H as the offset address and content of DS as segment
address. The effective address here, is 10H * DS + 5000H.
• Ex:
3. Register Addressing Mode
• Register addressing mode is the most efficient addressing
mode because the operands are in the processor
itself (there is no need to access memory).
• In register addressing mode, the data is stored in a register
and is referred using the register.
• All the registers, except IP, may be used in this mode.
• Ex:
4. Register Indirect Addressing Mode

• Sometimes, the address of the memory location, which

contains data or operand, is determined in an indirect way,
using the offset register.
• This mode of addressing is known as register indirect mode.
• Register indirect addressing transfers a byte or word
between an addressing register and a memory location
addressed by an index or base register (offset).
• In this addressing mode, the offset address of data is in
either BX or SI or DI register.
• The default segment is either DS or ES.
Cont.,
• The data is supposed to be available at the address pointed
to by the content of any of the above registers in the default
data segment.
• Ex: MOV AX, [BX]
• Here, data is present in a memory location in DS whose
offset address is in BX. The effective address of the data is
given as 10H * DS+[BX].
• Ex:
5. Indexed Addressing Mode
• In this addressing mode, offset of the operand is stored in
one of the index registers.
• DS and ES are the default segments for index registers, SI
and DI respectively.
• This is a special case of register indirect addressing mode.
• Ex:
MOV AX, [SI]
• Here, data is available at an offset address stored in SI in DS.
• The effective address, in this case, is computed as:
10 H*DS+[SI].
6. Register Relative Addressing Mode
• Register relative addressing moves a byte or word
between a register addressing and the memory
location addressed by an index or base register plus
a displacement.
• In this addressing mode, the data is available at an
effective address formed by adding an 8-bit or 16-
bit displacement with the content of any one of the
registers BX, BP, SI and DI in the default (either DS
or ES) segment.
Cont.,
• Ex:
MOV AX, 50H[BX]
Here, the effective address is given as 10H *DS+50H+[BX]
Ex:
7. Based Indexed Addressing Mode
• The effective address of data is formed, in this addressing
mode, by adding content of a base register (any one of BX or
BP) to the content of an index register (any one of SI or DI).
• The default segment register may be ES or DS.
• Ex:
MOV AX, [BX][SI]
• Here, BX is the base register and SI is the index register the
effective address is computed as 10H * DS + [BX] + [SI].
8. Relative Based Indexed Addressing Mode

• The effective address is formed by adding an 8 or 16-bit

displacement with the sum of the contents of any one of the
base register (BX or BP) and any one of the index register, in
a default segment.
• Ex:
MOV AX, 50H [BX] [SI]
• Here, 50H is an immediate displacement, BX is base register
and SI is an index register the effective address of data is
computed as:
10H * DS + [BX] + [SI] + 50H
Note
• Table 1 lists the value of the effective address and the
operand loaded into the ACC for the seven addressing
modes.
• The table also shows the operation with a register
transfer statement and a symbolic convention for each
addressing mode.
• LDA is the symbol for the load-to-accumulator opcode.
• In the direct mode, we use the symbol ADRS for the
address part of the instruction.
• The # symbol precedes the operand NBR (is a number
or operand) in the immediate mode.
• The symbol ADRS enclosed in square brackets
symbolizes an indirect address, which some compilers
or assemblers designate with the symbol @.
Cont.,
• The symbol $ before the address makes the
effective address relative to the PC.
• An index-mode instruction is recognized by the
symbol of a register placed in parentheses after the
address symbol.
• The register mode is indicated by giving the name
of the processor register following LDA.
• In the register- indirect mode, the name of the
register that holds the effective address is enclosed
in parentheses.
Complex Instruction Set
Computer (CISC)
A purely CISC architecture has the following
properties:
1. Memory access is directly available to most types
of instructions.
2. Addressing modes are substantial.
3. Instruction formats are of different lengths.
4. Instructions perform both elementary and
complex operations.
Reduced instruction set
computers (RISCs)
A RISC architecture has the following properties:
1. All operations on data apply to data in registers
and typically change the entire register (32 or 64 bits
per register).
2. Memory accesses are restricted to load and store
instructions, and data manipulation instructions are
register-to-register.
3. Addressing modes are limited.
4. Instruction formats are all of the same length.
5. Instructions perform elementary operations.
Classes of Instructions:
• The goal of a RISC architecture is high throughput and
fast execution.
• To achieve these goals, accesses to memory, which
typically take longer than other elementary operations,
are to be avoided, except for fetching instructions.
• Most RISC architectures, have three classes of
instructions:
1- ALU instructions—These instructions take either two
registers or a register and a sign-extended immediate.
2- Load and store instructions
3- Branches and jumps
Assignment
• The contents of different registers are given below.
Form effective addresses for different addressing modes.
• Offset (displacement)=5000H
• [AX] = 1000H, [BX]= 2000H,
• [SI] = 3000H, [DI] = 4000H,
• [BP] = 5000H, [SP] = 6000H,
• [CS] = 0000H, [DS] =1000H,
• [SS] = 2000H, [IP] = 7000H
i. Direct addressing mode: MOV AX,[5000H]
ii. Register indirect: MOV AX, [BX]
iii. v. Relative based index: MOV AX, 5000[BX][SI]