Optik - International Journal for Light and Electron Optics 260 (2022) 169036

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Optik
journal homepage: www.elsevier.com/locate/ijleo

A deep analysis of the image and video processing techniques

using nanoscale quantum-dots cellular automata
Xiaoli Xu *, Chenghua Fan, Lijun Wang
Academy of Electronic Information and Electrical Engineering, Provincial Key Laboratory of Electronic Information, Hefei Normal College, HeiFei,
AnHui 230601, China

A R T I C L E I N F O A B S T R A C T

Keywords: The advancement of small electrical components into the nanoscale range opens up opportunities
Digital Signal Processing for massively parallel computing systems. Quantum-dot Cellular Automata (QCA) is a potential
Discrete Cosine Transform novel nanoelectronics technique that fits image processing requirements well. QCA circuits are
Filtering
typically highly stable, quick, and utilize little energy. Because studies about QCA logic image
Image processing
Mathematical morphology
processing are starting up, the suggested contribution will initiate a new line of inquiry in the
Nanoelectronic real-time video and image processing domain. Noise reduction, face identification, feature
Quantum-dot Cellular Automata extraction, segmentation, skeletonizing, thickening, thinning, object detection, form extraction,
and tracking are all examples of image processing. This article describes how to use QCA tech­
nology for image processing in various ways. The fundamentals of image processing approaches
and the function of QCA in them are covered. The findings demonstrate that a more effective
layout based on QCA technology would reduce power consumption and computational
complexity in the long run. We anticipate that this compendium will give readers an overview of
the advances made in quantum image processing and pique their curiosity in doing a more
complex investigation in the field.

1. Introduction

Silicon-based technology has seen many modifications and significant advancements to date. However, the need for less power and
higher speed in future applications has led to the development of newer technologies [1,2]. Furthermore, increasing feature sizes
improves heat generation and transistor density. The chip may be damaged as a result of the extreme heat [3]. After more than 50 years
of survival, Complementary Metal–Oxide Semiconductor (CMOS) is now experiencing problems in the submicron region [4]. Ac­
cording to Landauer (1961), a KTln2 Joules of energy waste exist for every bit of information lost that cannot be recovered in any way
[5]. In CMOS, scaling has reached a higher threshold, resulting in negative consequences from technological, physical, economic, and
material standpoints. This shift motivates investigators to seek more potential CMOS alternatives that promise improved density,
performance, and power consumption. Quantum-dot Cellular Automata (QCA) is a promising CMOS replacement to digital design [4].
Lent et al., 1993 developed a novel technology, QCA, to address all of the aforementioned concerns [3,6]. QCA is a technology that
relies on electronic interaction among cells rather than current transfer.
Video processing methods that necessitate intensified computations have been broadly implemented using Large Scale Integration
(VLSI) parallel frameworks [7]. Nevertheless, the physical limits of CMOS technology indicate that future designs will have trouble

* Corresponding author.
E-mail address: lilyxu@hfnu.edu.cn (X. Xu).

https://doi.org/10.1016/j.ijleo.2022.169036
Received 30 November 2021; Received in revised form 19 March 2022; Accepted 3 April 2022
Available online 6 April 2022
0030-4026/© 2022 Elsevier GmbH. All rights reserved.
X. Xu et al. Optik 260 (2022) 169036

Fig. 1. QCA cell.

Fig. 2. Two type of wired in QCA. a 90-degree QCA wire, b 45-degree QCA wire.

lowering device size, power consumption, and increasing operating speed. By keeping interconnections short and local, VLSI design
aims towards a highly regular construction [8].
The QCA technology and its computing strategy take advantage of heavily pipelined systems and breakneck speeds. The infor­
mation is encoded using the locations of electrical charges inside the QCA cells rather than electric current flow. Thus, using QCA
technology to build circuits efficiently will reduce power usage and computational complexity. Hence, QCA is regarded as a promising
nano-electronic technology in development [9–12]. Circuits built with these technologies do not involve typical connectors and
dissipate very little power. Numerous investigators have completely built and evaluated the QCA cells and their circuits [13]. Utilizing
QCA technology, integration densities of 1012 cells/cm2 may be achieved, with circuit switching frequencies approaching terahertz.
The key benefits of QCA systems are the speed, size, and power consumption reductions they provide. However, there are several
additional features of QCA technology that make it more advantageous, like the potential to cross wires in a plane and a novel
calculation and info display approach known as processing-in-wire [10,12]. Adders, multiplexers, shift registers, multipliers, in­
crements, fault-tolerance circuits, subtractors, and arithmetic logic units have all been constructed in QCA-depended logic circuits
[14].

1.1. A- QCA overview

Some essential ideas of QCA technology, including cells, wire, logic gates, and clock pulse, are revealed in this subsection.

1.2. QCA cell

The information storage and transit on QCA are founded on the local positions of charged particles within a tiny segment of the
circuit termed a cellular automaton, with no electrical particle current. The quantum dots that the particles can fill in the QCA cell are
restricted; these dots are placed so that the cell can only have two polarizations (two degenerate quantum mechanical ground states),
indicating binary values zero and one. A cell can flip between the two states by allowing charged particles to tunnel quantum
physically among the dots. Classical coulombic contact is used by the cells to share information. Because this state combination
contains the least energy in the electric field among the charged particles in nearby cells, an input cell forces the adjacent cell into the
same polarization. In a wire made up of cell automata, information is replicated and disseminated [15,16]. Fig. 1 shows the QCA cell.

1.3. QCA wire

The QCA wire, made up of QCA cells, is needed to transport the input value to the output. Polarization spreads from one cell to

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Fig. 3. Majority (a) and Inverter (b) gates.

Fig. 4. QCA clocking [22].

another because of the coulombic contact among electrons [17]. To accomplish wire cross on the identical circuit layer, the QCA wire
comes in two configurations: normal and rotating. Clocking control is used to cross single layer wires [18,19].
Fig. 2 illustrates these wires:

1.4. QCA inverter and majority gate

The other two most critical elements in QCA are the majority and inverter gates. Fig. 3 depicts the whole of these components. The
45◦ cell at the corner of the layout is used to create the inverter. Because of this shift in the cell, the cell alignment with opposite
polarization experiences the least coulombic pressures, resulting in an inverter.

1.5. QCA clocking

QCA clocking is utilized to calculate and guarantee that the data direction flows against the output. Clocking is also necessary to
power the QCA circuit and control the data flow direction [20]. The clock is in charge of the dot-to-dot obstacle. The cell polarization
stays ambiguous when the clock is small. When the clock is large, the cell acquires its constant polarization. To achieve adiabatic cell
switching, the clock signal is made up of four clock phases: switch hold, release, and relax [21]. As illustrated in Fig. 4, the QCA circuit
may be separated into four clock zones, each with four phases.
The organization of the article is as follows: First, a background is stated. Afterward, the articles are divided into categories, and the
existing methods are described according to the methods available in the literature. The literature review results and the existing
challenges are then stated, followed by the conclusions and open issues.

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Table 1
Some features of selected articles.
Work Title Citation Year Publisher Journal Authors

[29] An Efficient Design of Multiplier 2 2021 EJMCM European Journal of N. BHAVANI SUDHA, GAMINI
and Adder in QCA Technology Molecular & Clinical Medicine SRIDEVI
Using Majority Logic
[36] Design and Implementation of 4 2020 IEEE IEEE Transactions on Very Ali Newaz Bahar, Khan A.
Approximate DCT Architecture in VLSI Systems Wahid
QCA
[37] QCA in Image Classification – 2020 IJAEMA The International journal of M.SUBHASHINI
Employed for Medical Diagnosis analytical and experimental
modal analysis
[38] An Efficient Design of DCT 4 2019 HINDAWI Journal of Electrical and Ismail Gassoumi, Lamjed Touil,
Approximation Based on QCA Computer Engineering Bouraoui Ouni, Abdellatif
Technology Mtibaa
[39] Design of efficient QCA multiply- 6 2019 WILEY IET Circuits, Devices & Ismail Gassoumi, Lamjed Touil,
accumulate (MAC) unit with Systems Bouraoui Ouni
power dissipation analysis
[40] An efficient design of CORDIC in 5 2019 TAYLOR & FRANCIS International Journal of Ismail Gassoumi, Lamjed Touil,
QCA technology Electronics Bouraoui Ouni, Abdellatif
Mtibaa
[41] Design of Efficient QCA MAC Unit – 2018 IEEE International Conference on Ismail Gassoumi, Lamjed Touil,
Microelectronics (ICM) Bouraoui Ouni
[42] Efficient design of BinDCT in QCA 9 2018 IEEE IET Image Processing Lamjed Touil, Ismail Gassoumi,
technology Radhouane Laajimi, Bouraoui
Ouni
[43] Designing Efficient Configurable – 2018 IOP Journal of Physics: Conference Shiv Bhusan Tripathi, Aron
QCA Nano Circuit for Series Narzary, Rahul Toppo, Mrinal
Morphological Operations in Goswami, Bibhash Sen
Image Processing
[44] Implementation of Real-Time 22 2016 IEEE International Conference on M V Ganeswara Rao, P Rajesh
Image Processing System with Microelectronics, Computing Kumar, A Mallikarjuna Prasad
FPGA and DSP and Communications
(MicroCom)
[45] Correlation and convolution for 14 2016 ICEVIRTUALLIBRARY Nanomaterials and Energy Bikash Debnath, Jadav Chandra
binary image filter using QCA Das, Debashis De
[46] A Configurable Design for 8 2016 SEMANTICSCHOLAR Journal of Engineering Science V. Mardiris, V. Chatzis
Morphological Erosion and & Technology Review
Dilation Operations in Image
Processing using QCA
[47] Image Processing Algorithms 4 2014 SPRINGER Cellular Automata in Image Vassilios Mardiris, Vassilios
Implementation Using Quantum Processing and Geometry Chatzis
Cellular Automata
[48] Morphological edge detector 3 2013 IEEE IEEE International Conference V. Mardiris
implemented in Quantum Cellular on Imaging Systems and
Automata Techniques (IST)
[49] New Scan Method and Pipeline 6 2008 IEEE TENCON 2008–2008 IEEE Basant K.Mohanty, Promod K.
Architecture for VLSI Region 10 Conference Meher2
Implementation of Separable 2-D
FIR Filters without Transposition
[50] QCA Implementation of a 27 2002 TAYLOR & FRANCIS Mathematical Problems in J. L. CARDENAS-BARRERA, K.
Multichannel Filter for Image Engineering N. PLATANIOTIS, A. N.
Processing VENETSANOPOULOS
[51] Quantum-Dot Cells and Their 7 1999 CITESEER NSIP Mika Helsingius, Pauli
Suitability for Nonlinear Signal Kuosmanen, Jaakko Astola
Processing

2. Background

In [23], on binary images, QCA is utilized to conduct median filtration. In [24], the secret message is replaced by the LSB bits of a
grayscale picture in LSB-based steganography using QCA, which is shown. Unlike [24,25] proposes a reversible structure for LSB-based
steganography. Because of the fast growth in the use of personal computers, the Internet, and digital multimedia technologies, digital
data media may now be readily shared. The existence of multiple image processing tools, on the other hand, makes illicit exploitation
of such data easier [26]. Unauthorized individuals have easy access to digital data and may simply copy, delete, or modify it. Because
of the unauthorized alteration and replication of digital data, various approaches have been developed to protect digital data media’s
intellectual property rights [27].
A hybridized watermarking approach was proposed by Arora [27]. In their suggested technique, the marker was embedded in the
frequency and spatial domains utilizing Singular Value Decomposition (SVD) and Discrete Wavelet Transform (DWT). The watermark
was placed across the sub-bands of the cover image’s unique values. According to simulation data, the approach achieved good

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imperceptibility, as the perceptual quality was not impaired. The findings of the investigation revealed that there were significant
advances in imperceptibility. When exposed to various image/signal processing assaults, the obtained PSNR, MSE, and SSIM values
revealed that DWT-SVD supplies substantial resilience.
Xie et al. [28] proposed a novel method for preventing quick response code counterfeiting. DWT was utilized to split into
non-overlapping rectangular sections in their watermarking process.
Besides, Sudha and Sridevi [29] suggested using majority logic to create a one-bit approximation full adder. In addition, multi-bit
approximation full adders were suggested and investigated, implementing these architectures to QCA as an example. Hardware
measurements (such as delay and area) and error metrics were used to assess the layouts. The Brent Kung multiplier and adder were
implemented using the half adder and full adder combinations. Fast adders, such as Ripple-carry (RCA) adders, are used in the current
work, while multiplication operations are conducted utilizing majority gates. Utilizing the suggested majority-based full adder, Sudha
and Sridevi [29] devised the Wallace tree multiplier. The developed multiplier is efficient and effective regarding area-delay trade-off,
power usage, and delay (speed). Verilog hardware description language was used to create this project. The synthesis and simulation
were carried out using the Xilinx integrated synthesis environment tool.
Numerous approaches for quantum image watermarking have been suggested so far, whereas quantum audio watermarking has
seen a few breakthroughs [30]. Several transform approaches, such as the Discrete Cosine Transform (DCT), fast fourier transform
(FFT), and DWT, have seen a significant study in recent years, which are widely utilized in Digital Signal Processing (DSP) tasks.
The need for low-power executions of complicated signal processing algorithms is skyrocketing because of the fast rise of multi­
media apps [31]. Furthermore, developers must evaluate the power consumption and area occupied by complicated applications
quickly and precisely. Developers have found QCA technology to be an appealing alternative for addressing this difficulty at the
nanoscale level. Lately, image processing has become more important in solving challenges in domains like medicine, security,
authentication, industry, and remote sensing [32,33]. With the introduction of novel nanoscale material qualities, we may anticipate a
breakthrough in medical equipment with increased biocompatibility and precision for treating and diagnosing severe medical situ­
ations [34,35].
In this article, through the literature review, we aim to illustrate the utilization of QCA in a particular area of science, namely image
processing. We have described the utilized methods along with their limitations. This article will categorize some dominant methods
used for QCA image and video processing. It will help future researchers to better orient themselves.
QCA has mostly avoided the realm of image processing. Articles available in international databases such as Scopus, Google
Scholar, etc., were searched. We did this search using some keywords. These keywords are as follows:

- quantum-dots cellular automata

- QCA
- QCA AND image and video processing
- quantum-dots cellular automata AND image and video processing
- QCA AND Filtering
- QCA AND DCT
- QCA AND Mathematical morphology
- QCA AND DSP

Then, the stage of reviewing the titles and summarizing the articles began. The articles were selected from the searched articles for
final review. The list of selected articles is presented in Table 1. Some existing sources might be removed in this review due to a lack of
access to the articles. Also, English language sources were the only option in conducting the research.

3. Achievements

This paper will respond to the questions below:

- Question 1: What is the role of QCA circuits in processing image and video signals? Section 1 answers this question.
- Question 2: What are the methods for image processing in this field? This question is answered in Section 4.
- Question 3: What are the challenges of this field? We have outlined the issues in Section 4.2.

4. Image processing methods

Previously, VLSI technology has been demonstrated to be a solid method for enhancing the performance of video and image
processing systems. Today, QCA is a potential nano-electronic technology that might be utilized in several image processing tasks. The
majority of video and image processing methods are time and computationally intensive. The next section analyzes the methods
available in the literature.

4.1. Discrete Cosine Transform (DCT)

In [42], depending on QCA technology, the investigators provided a hardware design for a rapid multiplierless forward Binary DCT
(BinDCT). This innovative technique has some advantages, including ultralow-power usage, a tiny size, and the ability to operate at

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Table 2
Results of existing articles by DCT method.
Work Motivation Finding Proposed Architectures

[42] Introducing a novel BinDCT
architecture built on QCA
technology.
[36] They provided several efficient
computing units to implement the
BinDCT paradigm in QCA.
[38] Developing digital circuits that are
ultra-low-power and extremely fast.
The suggested circuit performs properly and may be 1. Xor half adder/subtractor
employed in QCA technology as a high-performance 2. 1 bit F-A/F-S, 8 bits half
architecture.The suggested QCA-based BinDCT module has 3. adder/subtractor
the distinctive property of flexibility, which allows it to be
4. Multiplexer 4–1
expanded to any high-order layout or even employed as a
fundamental building block for general-purpose
5. 4- Shift register
nanocomputer video and image processors.
The suggested QCA BinDCT structure will serve as a 1. D flip-flop
blueprint for constructing BinDCT coprocessors in the nano 2. 4:1 multiplexer
computing framework, including single-electron transistor, 3. 1:4 DeMultiplexer, 1-bit FA
QCA, and tunneling phase logic.Furthermore, the linked
4. 1-bit FS, 8-bit RCA
building blocks will be particularly appealing to QCA
investigators due to their layout simplicity and decreased
5. 8-bit RBS
complexity. 6. 6–8-bit QCA parallel-in parallel-out
right-shift register
The suggested architecture uses 0.091 milliwatts of 1. 3 inputs XOR gate
electricity.The technology’s operating frequency can be 2. 3 inputs majority gate
higher than 1 THz.This approach delivers very low power 3. 8-bit ripple carry adder circuit
usage, great circuit performance, and very small
4. D flip-flop circuit
dimensions compared to standard VLSI technology.The
outcomes of this research have the potential to bring up a
5. The parallel-in parallel-out shift register
new opportunity for low-power audiovisual architecture. circuit is designed using this DFF circuit
as the building block

1 THz. The outcomes of the QCA BinDCT execution revealed that the suggested paradigm outperformed the previous technique based
on classic metal-oxide (complementary metal-oxide-semiconductor technology). The researchers present a substantially scalable
BinDCT module that consumes very little power. Compared to earlier models, the suggested circuit used half the amount of energy. The
suggested structure has an 800 megapixel per second throughput. The QCAPro and QCADesigner tools are used to determine power
usage and synthesis to develop and test the suggested layout.
In [36], a single-layer binary BinDCT with high efficiency has been described. Besides, Bahar and Wahid [36] presented numerous
low-complexity sequential and combinational logic components to implement the BinDCT paradigm in QCA. QCADesigner was used to
develop and verify all of the described circuit configurations. QCAPro was also utilized to calculate the power loss. Regarding covered
area, cell complexity, and energy loss, all comparison studies demonstrated that the presented layouts outperformed prior ones.
Furthermore, the suggested QCA BinDCT wastes 1.394 × 10 − 4 mW; however, CMOS- and QCA-based BinDCT designs utilized 0.195
and 0.091 mW, respectively, regarding power usage.
Additionally, in [38], in QCA technology, the researchers presented a multiplier-less DCT design. The suggested design out­
performed current traditional architectures in terms of low power usage, circuit performance, and small size. All layouts in the paper
were created using the QCADesigner program for QCA functional verification and circuit design. QCAPro, a widely used energy
estimation tool, was used to calculate the suggested circuit’s energy loss. In terms of power, the proposed approach outperformed the
standard solution by 53%. The research’s findings had the potential to open up new doors for low-power image processing devices.
At the end, Table 2 shows the analysis results of these articles.

4.2. Digital Signal Processing (DSP)

Multiply Accumulate (MAC) procedures are required for various applications in real-time DSP systems, such as video coding, voice
processing, and digital filtering. The most important elements of these systems are area and power wastage [39].
Here, based on QCA technology, Gassoumi et al. [39] created a low-power MAC device. The suggested circuit’s accuracy was tested
using QCADesigner version 2.0.3. The unit’s dependability was tested at various temperatures. QCAPro was employed to calculate the
power loss. The device used 2.183 microwatts of electricity in total. In terms of power, the suggested circuit outperformed CMOS
circuits by 90%. In [41], QCA technology was used to create a low-power MAC Unit. QCADesigner 2.0.3 was employed to verify the
recommended circuit’s accuracy. QCAPro was used to calculate the power loss. This device used a maximum of 4.03 mW of power. It
was discovered that the suggested layout was superior to alternative concepts based on traditional technologies. The suggested
contribution will initiate a new strand of study in the real-time signal processing domain since the study in QCA logic signal processing
has progressed. Furthermore, Gassoumi et al. [40] demonstrated a new Coordinate Rotation Digital Computer (CORDIC) circuit layout
using QCA technology. Numerous suggested QCA sub-modules, such as FlipFlop and adder, were used to create the suggested circuit.
QCADesigner was applied to create and validate the suggested layout, while QCAPro evaluated power usage. The suggested QCA
CORDIC accomplished a 69% drop in area and power compared to earlier technologies. The findings may open up other avenues for
constructing the CORDIC module, which might be employed in low-power signal and image processing systems.
Rao et al. [44] proposed image processing solutions based on the TMS320DM642 heterogeneous framework. The DSP processor
was utilized for important image processing, and the FPGA chip was employed as a functional element for image display and sampling.
In [44], they talked about the suggested hardware design and its use and some important difficulties with the external memory

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Table 3
Results of existing articles by DSP method.
Work Motivation Finding Proposed Architectures

[39] Needing multimedia and communication
technologies and high-speed computer
architecture.
[41] Designing a high-speed and low-power
MAC unit.
[40] Designing low-power and high-
performance digital circuits meeting
power, area, and speed metrics
[44] Presenting a real-time image processing
system.
Compared to standard VLSI technology, the work delivers very 1. 4-bit Vedic multiplier
low power usage, great circuit performance, and very small 2. 8-bits parallel binary full adder
dimensions.Because of these advantages, the suggested unit is 3. Accumulator (parallel in parallel
suitable for signal and image processing systems in mobile
out shift register)
devices that require low real-time processing and power usage.
The comparative findings show that the suggested sub-modules 1. 8-bit Vedic Multiplier
benefit the area and cell count over other circuits.Compared to 2. 16-bits parallel binary full adder
typical VLSI technology, the work delivered very low power 3. 16-bits parallel-In-parallel-out
usage, great circuit performance, and very small dimensions.
shift register
The planned QCA CORDIC takes up 765.72 µm2 of post- 1. Half adder
arrangement space and uses 107.9 µm2 of power.This unit’s 2. Full adder
operational frequency can surpass 1 THz.Compared to 3. D flip-flop and
standard VLSI technology, this work delivers very low power
4. Multiplexer 2:1 in QCA based on
usage, great circuit performance, and very small dimensions.
universal, scalable, efficient
clockin
5. N-bit adder
6. N-bit universal shift register
Edge detected video frames are presented on a PAL display 1. A TMS320DM642 board
monitor after the suggested system properly completes the 2. A charged-coupled device cam­
algorithm.The suggested system allows for a wide range of era and
computationally expensive image processing methods to be
3. A video graphics array display
implemented.

interface. Eventually, an image edge detection technique was shown to demonstrate the suggested framework’s functionality. The
created platform can capture live shots from a camera, show them on a video graphics array monitor or a National Television Standards
Committee/Phase Alternating Line (NTSC/PAL) television, and perform image processing services such as color model conversion and
pixel-based operations. It has also been demonstrated that the created technology is capable of meeting real-time performance
requirements.
The review results of the DSP method are summarized in Table 3.

4.3. Mathematical Morphological Operations

Mathematical morphology is a nonlinear image processing technique [52]. The form of an item included in a picture is the basis for
mathematical morphology, which is closely connected to set theory and Minkowski algebra [53]. Mathematical morphology was first
used on binary pictures, but subsequent modifications and changes were developed to be used on gray-level or colored photos [54,55].
The key benefits are the effectiveness of mathematical morphology methods simulating the form of a thing and their quick hardware
executions. They have been employed for edge detection, form description, object or character identification, and reconstruction,
among other things [23,56–58].
Tripathi et al. [43] demonstrated a reconfigurable QCA nano circuit for morphological image processing tasks. Dilation and erosion
may be done on two cascaded 5-input majority voters in the established QCA system by employing a control line. The suggested layout
indicates a significant advance regarding the delay, area, and cell count compared to prior outcomes. The simulation findings
confirmed the suggested architecture’s appropriate function. Also, Mardiris and Chatzis [47] demonstrated how to use QCA tech­
nology in image processing to perform mathematical morphological procedures. The core elements of QCA circuit design and the
approach that must be adopted for a reliable construction of increasingly complicated circuits were described. Two QCA circuits for
dilation execution and morphological erosion were built, simulated, and evaluated. The QCA layout outperformed the competition by
utilizing parallel processing, simplicity of mask production, clock speed maximization, greater silicon-area use, and reduced power
usage.
By utilizing parallel processing, clock speed maximization, greater silicon-area usage, and very low power usage, the QCA para­
digm will give higher performance [46]. Mardiris and Chatzis [46] briefly covered QCA technology and circuit design principles and
the basic procedures of mathematical morphology. A novel creative QCA structure capable of implementing either the erosion or
morphological dilation operation, determined by the value of one-bit input, has been successfully constructed, simulated, and eval­
uated. Also, Subhashini [37] explained QCA, an upcoming technology of nanoelectronics. The technology maximizes clock speed, low
power usage, low silicon area utilization, and performance-enriching parallel processing techniques. They are employed in image
processing techniques such as masking, thresholding, enhancement, and classification [59]. Subhashini [37] discussed the various
steps of image processing and the applicational role of QCA, a transistor less architecture in each unique process as a mathematical
morphology model that helps in binary information exchange to perform computation.
To summarize the review results in this section, Table 4 provides an overview of the available information.

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Table 4
Results of existing articles by Mathematical Morphological Operations method.
Work Motivation Finding Proposed Architectures

[43] Need computing systems with processing speed and low The new architecture was 11.76% more space-efficient, 1. Non-configurable
power consumption. 25% more cost-effective, and 40% quicker than the prior design
version. 2. Configurable design for
erosion and dilation
[47] Efficient circuit design based on very high-speed pipeline Compared to similar architectures using traditional VLSI 1. Implementation of
architecture and reducing computational complexity and technology, this solution provides parallel processing, morphological erosion
power consumption. excellent circuit performance, a small footprint, and low 2. Implementation of
power usage.
morphological dilation
[46] Providing parallel processing, high circuit performance, The satisfactory simulations and evaluations performed 1. Implementation of
very low dimension, and very low power consumption in the QCADesigner indicate that the suggested model morphological erosion
compared to conventional VLSI technology. may perform either erosion or dilation morphological 2. Implementation of
operations, depending on the value of one of its inputs.
morphological dilation
[37] Improving the target localization capability of QCA is used in the construction of the VLSI structure for 1. QCA tT flip-flop
nanorobots by employing control over its speed and image processing, leading to lower power usage and 2. 5 input majority gates
sensibility nature of various parameters such signal mathematical complexity. 3. Serial communication
intensity of E-cadherin signals, blood pressure, and body
system
cell temperature.
4. 2 n to 1 multiplexer

Table 5
Results of existing articles by Filtering Techniques.
Work Motivation Finding Proposed Architectures

[49] Suggesting a novel technique to access to data for
transposition-free construction of 2-D FIR filters
with the limited input block size for finite input
block size.
[48] Suppression noise during the edge.
[45] From the ground up, implementation of a
correlation and convolution circuit for image
filtering using QCA at the nanoscale level.
[51] Investigation of the suitability of QCA
architecture for nonlinear signal processing
[50] Creating a DSP approach capable of detecting
picture deterioration in real-time and ensuring
the quality of service provided to customers
Thus, if 2-D FIR filters are built utilizing the 1- Utilizing the recommended data-access
suggested approach, a considerable amount of technique, creating a pipeline layout
chip surface and energy usage related to
intermediate buffering can be avoided.The
suggested construct would provide a low-cost
and low-power alternative to existing separable
devices for implementing 2-D FIR filters with
finite input sizes.
High circuit performance, parallel processing, 1. Binary median filter
extremely compact size, and low power usage 2. Dilation and erosion
were all supplied by the architecture. 3. QCA subtraction
4. QCA dilation and erosion residue
The suggested constructed circuit’s functioning 1. Matlab is employed to acquire an
was determined by comparing simulation image’s matrix form.
outcomes to theoretical data.The suggested 2. To develop and execute the suggested
correlation/convolution circuit needed only
circuit at a low-power nanoscale level,
17 MV, 208 cells, a 244,944 nm2 area, and four
clock zones.
the intrinsic characteristic of QCA is
used.
They discovered that the modern tech appears to 1. Majority logic
be highly promising, but that additional 2. Adiabatic pipeline
advancements in physics, circuit design, and
algorithm design are required.If these problems
can be solved, it would greatly influence
nonlinear signal processing.
With the introduction of all-digital television, 1. Threshold decomposition,
such filters can result in systems that maintain 2. Binary median filters and
correct visual reproduction fidelity despite any 3. Adding
unanticipated transmission changes.

4.4. Filtering techniques

In several image processing tasks, it is necessary to reduce noise while preserving specific photo features in order to improve the
ultimate result. Nonlinear filtering approaches can remove many forms of noise while preserving certain necessary picture features
[23]. Finite Impulse Response (FIR) filters are crucial components in a variety of DSP tasks. Low-power and high-performance digital
filter architectures have lately become essential due to portable battery-powered wireless communication gadgets [60,61]. Designing a
low-power, high-speed FIR filter for DSP applications is always a problem [62].
In [49], For finite input matrices, Mohanty and Meher [49] devised a strategy to access data for the execution of 2-D FIR filters. The
suggested data access approach confirmed the operation of a 2-D FIR filter using MATLAB simulation. For effective and productive
execution, a pipelined method was developed. The suggested architecture has down intricacy than the best current systems.

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X. Xu et al. Optik 260 (2022) 169036

Fig. 5. Some of Image Processing Methods in QCA.

Furthermore, because of its short clock period, it conducted the filtering process at a high pace. The suggested technique did not need a
line buffer to store intermediate outcomes. A high chip space and energy will be preserved if the 2-D FIR filters are constructed utilizing
the recommended approach. Also, in [48], a unique nonlinear morphological edge detector was developed when constructed as a
compact circuit on QCA in a crossbar nano-electronic structure. High circuit performance, parallel processing, very small dimensions,
and low power usage were all offered by the suggested QCA execution. Furthermore, the given QCA circuit design follows the QCA
design guidelines while emphasizing circuit functioning robustness and providing real-time image processing. The simulation findings
demonstrated the suggested circuit’s effectiveness.
Debnath et al. [45] suggested a capable low-power nanoscale design for binary image filters that perform correlation and
convolution. For the first time, a design incorporating QCA technology was realized. The outcomes were compared to theoretical
values, resulting in functional correctness for the suggested architecture. To develop and execute the suggested circuit at a low-power
nanoscale level, the intrinsic properties of QCA were used. The pixel intensity values of a picture were obtained using Matlab software,
and these data were then utilized as an input to the suggested circuit. Moreover, Helsingius et al. [51] investigated the suitability of
QCA architecture for nonlinear signal processing. Helsingius et al. [51] were shown several examples and discussed the general us­
ability of the concept. Also, Cardenas-Barrera et al. [50] presented a novel adaptive filter. The novel filter was employed to eliminate
impulsive noise and other degradation from color television signals, and it was designed to work in real-time. The outcomes of the
experiments were utilized to clarify their arguments and the efficacy of their strategy.
Table 5 clearly shows the inferred results.

5. Discuss and results

In the previous section, a number of articles were selected and reviewed. The reviewed articles are classified according to Fig. 5.
Systems relying on some electrons and molecules, by definition, must have some type of built-in error-correcting capability. The
most important issue is that QCA creates a genuinely digital system. Only two steps are possible, which may be thought of as binary
zeroes and ones. In this design, all conventional logical gates are incredibly basic and regular. It is perfect DSP hardware, and it is
particularly well-suited to numerous nonlinear digital filters, such as order statistics and morphological filters. It is interesting to
consider how previous algorithms may be implemented with this novel technology. Compared to typical digital circuits, majority logic
and the homogeneity of wires and processing parts introduce significant modifications [51].
Spatial filters are employed in picture-enhancing methods in a variety of ways. Smoothing filters are employed in preprocessing
processes for blurring and noise minimization, and they eliminate minor features from the picture. Rather than blurring a pixel’s gray
level, median filters are employed in noise removal to substitute the median of the pixel’s neighbor’s gray level. It keeps the sharpness
of the edges. As part of the picture acquisition process, sharpening filters are employed to emphasize small features and increase
blurred detail. Inverse filtering and the least mean square filter, also known as the Weiner filter, are used in image restoration. In
contrast, the Laplacian filter and Dijkstra’s uniform cost method are used in image segmentation. Local and global thresholding ap­
proaches are used in the thresholding procedure. Cubic convolution and zero-order interpolation are two types of gray level inter­
polation. Prewet operator, Robert cross gradient operator, and Sobel operator are used in derivative filters [37]. In several modern
applications, calculation time restricts the utility of potentially effective nonlinear filters. Nonlinear filters may become more
competitive than linear filters due to the high velocities of quantum processing. It is particularly applicable for numerous video, image,
and radar signal processing applications, which may be computationally demanding. Several linear signal processing methods work in
the transform realms as well. Utilizing QCA, designing scalable transform systems should be pretty simple [63].
The complexity of the filter circuit in terms of density and power consumption is a complex problem to address when discussing

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X. Xu et al. Optik 260 (2022) 169036

Table 6
Features of methods.
Method Features

DCT - For visual data, it can pack energy at lower frequencies.

Mathematical Morphological
Operations
2-D FIR filtering
- The DCT can reduce the blocking artifact impact, which occurs when the borders among sub-images become
evident.
- In moving picture experts group and joint photographic experts group encoded video sequences, scene
movements may be readily recognized utilizing DCT coefficients.
- The DCT may be utilized in image processing to retrieve television news stories based on scene cut
recognition.
- As a tool for extracting image components that may be used to depict and describe the picture region in more
detail.
- It is concerned with the relative ordering of pixel values rather than the actual pixel values.
- Erosion, dilation, opening, and closing are examples of these processes.
- The basic processes in morphological image processing are erosion and dilation.
- Because of their stability and ease of construction, 2-D FIR filters are more common than infinite impulse
response filters.
As a result, a critical job is the fast construction of 2-D FIR filters to match actual usage timing requirements of actual usage.

image filtering at the hardware level.

By arranging QCA cells so that their coulombic interactions provide the appropriate output, all Boolean logic operations can
possibly be executed on a QCA combinational circuit [64]. However, in QCA circuit design, it is critical to create a circuit with a high
level of stability [65]. When tiny QCA layouts are not related to other systems, they often succeed in simulation but collapse when
employed as part of a bigger design. In other circumstances, developers modify simulation model settings to govern their circuits and
ensure simulation success. Thus, numerous QCA layouts are not reliable and operational [47].
Numerous data-hiding and watermarking algorithms now exist that work by altering the LSB of the watermarked signal [66].
Although both approaches have advantages in terms of capacity, their security is lacking. An attacker might use the LSB of water­
marked audio signal amplitudes to get encoded data or clean the LSB of audio signal samples to get rid of the watermark [30].
The majority of image processing platforms are built on a desktop personal computer, which is more general for image processing
tasks; these systems may not fulfill real-time performance requirements.
At the end, the characteristics of some methods available in the literature used for image processing are given in Table 6.

6. Conclusion and future directions

The advancement of digital recording technology has made digital image and video apps a major part of everyday life lately [67].
However, the quality of digital photographs and videos sometimes deteriorates to unacceptable levels for several reasons. Unrestrained
camera mobility, unmanaged interior or outdoor surroundings, clutter, and noise exposure throughout signal transmission are all
common causes of signal corruption. Various methods have been developed in the literature to enhance the quality of corrupted photos
[68]. Image processing is a difficult subject in VLSI architecture because it necessitates a large amount of computer power.
CMOS-based VLSI innovation has been widely employed to increase the quality of image processing equipment to this point. Various
executions have been documented in this area, including nonlinear filters, multi-functional applications, mathematical morphological
processes, and so on. Compared to previous designs using traditional VLSI technology, the new QCA versions feature parallel pro­
cessing, excellent circuit performance, extremely small size, and low power usage. Because of these benefits, the suggested methods are
suitable for image processing systems used on mobile or autonomous devices. The image processing techniques investigated in this
work are limited to basic techniques that can only be utilized on binary images. However, more complex strategies will be addressed in
upcoming investigations. More complicated binary image filters will be able to be developed at the nanometer scale in the near future,
thanks to the circuit.
Firstly, image classification from a given image necessitates noise reduction, which is best accomplished by turning the image to
grayscale. This grayscale image is a binary image that may be exposed to various computer algorithms that work with binary data [69].
For the picture classification procedure, the QCA approach would be used to the image in grayscale or binary data format [70].
In the future, more advanced mathematical morphological algorithms might be tackled with additional investigation. Furthermore,
image and video applications necessitate costly calculations because processing must often be done to each image pixel and the whole
image in certain situations. Advanced QCA circuits, for instance, might be used to build nonlinear filtering processes like medians,
ranked-order statistic filters, L-filters, and stack filters, among other order statistics filters. Processing velocity and minimal power
usage are now the most crucial requirements of any computing machine. Practical application of designed circuits in the real world
needs to ensure very low energy usage and high clock frequency.

Declaration of Competing Interest

The authors declare no conflict of interest.

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X. Xu et al. Optik 260 (2022) 169036

Data Availability Statement

All data are reported in the paper.

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