PROPOSED MODULE

TEMPLATE
FACULTY Applied Science

DEPARTMENT Computer Science

PROGRAMME
BSC Honours in Computer Science
LEVEL Part 1

Module TITLE Fundamentals of Digital Electronics

Module CODE SCS1112

FACILITATOR Mr. S Ngwenya

MODULE OVERVIEW Fundamentals of Digital Electronics Module is meant to

provide the students with the knowledge to analyse and
implement combinational circuits and sequential circuits.
Based on the requirement, we can use either
combinational circuit or sequential circuit or
combination of both. This module is design oriented. We
will cover in detail the fundamental concepts of logic
theory and switching circuits and emphasise developing
logic design skills The module covers key topics like,
introduction to digital design, number systems and
codes, digital circuits, combinational logic design
principles and practices, combinational circuit design
examples, sequential logic design principles and
practices, and sequential circuit design examples.
Memory (ROM, RAM, static and dynamic RAMs),
CPLDs and FPGAs, and computer-aided design tools.

MODULE AIM After completing this module, students will be able to learn
the type of digital circuit, which is suitable for specific
application and techniques in problem-solving and program
development in Computer Science and IT-related areas.

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LEARNING OUTCOMES Logic design skills, Switching circuits skills, Programming
skills, Problem solving.

OBJECTIVES • To understand the fundamental building blocks of

computer units
• To understand the theoretical underlying principles
of logic circuits
• To develop logic design techniques to solve
electronic logic problems.

RESOURCES/TECHNOLOGY Laptops, Smartphones, Internet.

ASSESSMENT TYPE One assignment submitted.

Two tests.
Final examination.

W Module content subtopics

K
1 Topic 1: NUMERATION SYSTEMS

1.1. Introduction:
This topic will focus on the popular number systems and how to represent a number in the
respective number system. The following number systems are the most commonly used.
• Decimal Number system
• Binary Number system
• Octal Number system
• Hexadecimal Number system

Key terms
Base/ Radix, Roman numerals, decimals, and binary numbers.
Base or radix: Is the number of different digits or combination of digits and letters that a
system of counting uses to represent numbers.
Roman numerals: any of the symbols used in a system of numerical notation based on the
ancient Roman system.

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 Decimals: the numbers, which consist of two parts namely, a whole number part and a
fractional part separated by a decimal point.
Binary numbers: contain only the digits 0 or 1, or bits, where each bit represents a power of
two.

1.2 Sub-topic 1: Number Systems

Decimal numbers
The base or radix of the Decimal number system is 10. So, the numbers ranging from 0 to 9
are used in this number system. The part of the number that lies to the left of the decimal
point is known as the integer part. Similarly, the part of the number that lies to the right of
the decimal point is known as the fractional part.

In this number system, the successive positions to the left of the decimal point have
weights of 100 , 101 , 102 , 103 and so on. Similarly, the successive positions to the right of
the decimal point have weights of 10-1, 10-2, 10-3, and so on. That means, each position has
a specific weight, which is the power of base 10.
Consider the decimal number 1358.246. Integer part of this number is 1358 and fractional
part of this number is 0.246.
Mathematically, we can write it as:

Binary Number System

All digital circuits and systems use this binary number system. The base or radix of this
number system is 2. So, the numbers 0 and 1 are used in this number system.

The part of the number, which lies to the left of the binary point is known as integer part.
Similarly, the part of the number, which lies to the right of the binary point is known as
fractional part. In this number system, the successive positions to the left of the binary point
having weights of 20 , 21 , 22 , 23 and so on. Similarly, the successive positions to the right
of the binary point having weights of 2-1, 2-2, 2-3and so on. That means, each position has a
specific weight, which is the power of base 2.
The binary number 1101.011. Integer part of this number is 1101 and fractional part of this
number is 0.011.
Mathematically, we can write it as:

Octal Number system

The base or radix of octal number system is 8. So, the numbers ranging from 0 to 7 are used
in this number system. The part of the number that lies to the left of the octal point is known
as integer part. Similarly, the part of the number that lies to the right of the octal point is
known as fractional part.

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 Consider the octal number 1457.236. Integer part of this number is 1457 and fractional part
of this number is 0.236. The digits 7, 5, 4 and 1 have weights of 80 , 81 , 82, and 83
respectively. Similarly, the digits 2, 3 and 6 have weights of 8-1, 8-2, and 8-3 respectively.
Mathematically, we can write it as:

Hexadecimal Number system

The base or radix of Hexa-decimal number system is 16. So, the numbers ranging from 0 to
9 and the letters from A to F are used in this number system. The decimal equivalent of
Hexa-decimal digits from A to F are 10 to 15.

The part of the number, which lies to the left of the hexadecimal point is known as integer
part. Similarly, the part of the number, which lies to the right of the Hexa-decimal point is
known as fractional part.
Consider the Hexa-decimal number 1A05.2C4. Integer part of this number is 1A05 and
fractional part of this number is 0.2C4. The digits 5, 0, A and 1 have weights of 160 , 161 ,
162, and 163 respectively. Similarly, the digits 2, C and 4 have weights of 16-1, 16-2, and 16-3
respectively.
Mathematically, we can write it as:

1.3 Sub-topic 2: Base Conversions

Binary To Octal Conversion

We had to group the bits in threes, from the binary point left, and from the binary point
right, adding (implied) zeros as necessary to make complete 3-bit groups. Each octal
digit was translated from the 3-bit binary groups.

Convert 10110111.1 binary to octal:

implied zero implied zeros
| ||
010 110 111 100
Convert each group of bits ### ### ### ###
to its octal equivalent: 2 6 7 4
Answer: 10110111.12 = 267.48

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 Binary To Hexadecimal Conversion
Here we had to group the bits in fours, from the binary point left, and from the binary
point right, adding (implied) zeros as necessary to make complete 4-bit groups: the
conversion from either octal or hexadecimal to binary is done by taking each octal or
hexadecimal digit and converting it to its equivalent binary (3 or 4-bit) group, then
putting all the binary bit groups together.
Hexadecimal notation is more popular, because binary bit groupings in digital
equipment are common multiples of eight (8, 16, 32, 64, and 128 bit), which are also
multiples of 4. Octal, being based on binary bit groups of 3, doesn’t work out evenly
with those common bit group sizes.

Convert 10110111.12 to hexadecimal:

implied zeros
|||
1011 0111 1000
Convert each group of bit ---- ---- . ----
to its hexadecimal equivalent: B 7 8
.
Answer: 10110111.12 = B7.816

Octal And Hexadecimal To Decimal Conversion

Although the prime intent of octal and hexadecimal numeration systems is for the
“shorthand” representation of binary numbers in digital electronics, we sometimes have
the need to convert from either of those systems to decimal form.
Of course, we could simply convert the hexadecimal or octal format to binary, then
convert from binary to decimal, since we already know how to do both, but we can also
convert directly.
Because octal is a base-eight numeration system, each place-weight value differs from
either adjacent place by a factor of eight.
For example, the octal number 245.37 can be broken down into place values as such:

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 The decimal value of each octal place-weight times its respective cipher multiplier can
be determined as follows:

Hexadecimal to Decimal Conversion

The technique for converting hexadecimal notation to decimal is the same, except that
each successive place-weight changes by a factor of sixteen.
Simply denote each digit’s weight, multiply each hexadecimal digit value by its
respective weight (in decimal form), and then add up all the decimal values to get a total.
For example, the hexadecimal number 30F.A916 can be converted like this:

These basic techniques may be used to convert a numerical notation of any base into
decimal form if you know the value of that numeration system’s base.

Activity 1a
Consider the following numbers:
1. Convert octal number 145.23 to binary.
2. Convert binary number 1101.11 to octal.
3. Convert binary number 1101.11 to hexadecimal.

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 Reading sources/links
1. Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
2. Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th
edition, 2002, Prentice Hall, ISBN 0-13-089592X.
3. Textbook for Electrical Engineering & Electronics (allaboutcircuits.com)

2 Topic 2: BINARY ARITHMETIC

2.1. Introduction:
Binary arithmetic is an essential part of all digital computers and many other digital
systems. There are ways that electronic circuits can be built to perform different tasks of
addition, subtraction, etc by representing each bit of each binary number as a voltage
signal (either “high,” for a 1; or “low” for a 0).
This is the very foundation of all the arithmetic which modern digital computers
perform. We’ll explore the techniques used to perform simple arithmetic functions on
binary numbers since these techniques will be employed in the design of electronic
circuits to do the same. You might take longhand addition and subtraction for granted,
having used a calculator for so long, but deep inside that calculator’s circuitry, all those
operations are performed “longhand,” using binary numeration.

2.2. Key terms

Binary Addition, Binary Subtraction.
• The binary addition operation works similarly to the base 10 decimal system, except that
it is a base 2 system. The binary system consists of only two digits, 1 and 0.
• Subtraction of binary numbers is an arithmetic operation similar to the subtraction of
decimal numbers or base 10 numbers. For example, 1 + 1 + 1 = 3 in base 10 and 1 + 1 +
1 = 11 in binary number system. When you add and subtract binary numbers, you will
need to be careful when borrowing as these will take place more often.

2.3. Sub-topic 1: Binary operations

Binary addition is a key for binary subtraction, multiplication, and division. There are
four rules of binary addition.
In the fourth case, a binary addition is creating a sum of (1 + 1 = 10) i.e. 0 is written in
the given column and a carry of 1 over to the next column.

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For example

Binary Subtraction
Subtraction and borrowing, these two words will be used very frequently for binary
subtraction. There are four rules of binary subtraction.

For example:

Negative Binary Numbers

Since we already know how to represent positive numbers in binary, all we need to
know now is how to represent their negative counterparts and we’ll be able to subtract.
Representing negative five as 11012 is an example of the sign-magnitude system of
negative binary numeration.

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Representation of Signed Binary Numbers
There are three types of representations for signed binary numbers.
Sign-Magnitude form
1’s complement form
2’s complement form
The representation of a positive number in all these 3 forms is the same. But, only the
representation of negative numbers will differ in each form.

Sign-Magnitude form
Consider the positive decimal number +108. The binary equivalent the of magnitude of
this number is 1101100. These 7 bits represent the magnitude of the number 108. Since
it is a positive number, consider the sign bit as zero, which is placed on the leftmost side
of magnitude.
The signed binary representation of the positive decimal number +108 is 01101100
So, the same representation is valid in sign-magnitude form, 1’s complement form, and
2’s complement form for positive decimal number +108. n-magnitude representation of -
108 is 01101100.

Consider the negative decimal number -108. The magnitude of this number is 108. We
know the unsigned binary representation of 108 is 1101100.
It has 7 bits. All these bits represent the magnitude. Since the given number is negative,
consider the sign bit as one, which is placed on left most side of magnitude.
Therefore, the sign-magnitude representation of -108 is 11101100. -108 is (11101100)2.

1’s complement form

The 1’s complement of a number is obtained by complementing all the bits of signed
binary number. So, 1’s complement of positive number gives a negative number.
Similarly, 1’s complement of negative number gives a positive number.

2’s complement form

The 2’s complement of a binary number is obtained by adding one to the 1’s
complement of signed binary number. So, 2’s complement of positive number gives a
negative number. Similarly, 2’s complement of negative number gives a positive
number.
Consider the negative decimal number -108. We know the 1’s complement of (108)10 is
(10010011)2
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10010011+1 = (10010100)2.

Binary Overflow
Binary overflow is when the answer to an addition or subtraction problem exceeds the
magnitude that can be represented with the allotted number of bits. Remember that the
place of the sign bit is fixed from the beginning of the problem.

Bit Grouping
Bit: A single, bivalent unit of binary notation. Equivalent to a decimal “digit.”
Crumb, Tydbit, or Tayste: Two bits.
Nibble, or Nybble: Four bits.
Nickle: Five bits.
Byte: Eight bits.
Deckle: Ten bits.
Playte: Sixteen bits.
Dynner: Thirty-two bits.
Word: (system dependent).

Activity 2a

1. Given binary numbers, Calculate

a). 1001101 + 0010010
b). 1000111 + 0010110
c). 1001001 + 0011001

2. Using binary overflow concept, Calcullate

Restrictions of the Six-bit Number Field
Example: -17 - 19
Using the Seventh Bit for a Sign Bit
Example: -17 - 19

Reading sources /links

1. Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
2. Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th
edition, 2002, Prentice Hall, ISBN 0-13-089592X.
3. Textbook for Electrical Engineering & Electronics (allaboutcircuits.com)

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3 Topic 3: LOGIC GATES

3.1 Introduction
In digital circuits, binary bit values of 0 and 1 are represented by voltage signals.
The absence of voltage represents a binary “0” and the presence of full DC supply
voltage represents a binary “1.”
A logic gate, or simply gate, is a special form of amplifier circuit designed to input and
output logic level voltages (voltages intended to represent binary bits).
A truth table is a standard way of representing the input/output relationships of a gate
circuit.

3.2 Key terms

Logic Gate, Transistor, Electrical signal, Digital signal, Analog signal
Logic gate: Is an idealised or physical device that performs a Boolean function.
Transistor: Is a semiconductor device used to amplify or switch electrical signals and
power.
Electrical signal: Is an electromagnetic wave time varying voltage that carries data from
one system or network to another, it can take other forms such as current.
Digital signal; Is a signal that represents data as a sequence of discrete values. It can
only take one value from a finite set of possible values at a given time.
Analog signal: an analog signal is time varying and generally bound to a range (+12v to
-12v), but there is an infinite number of values within that range.

o Sub topic1: An inverter, or NOT

A single transistor is known as an inverter, or NOT gate because it outputs the exact
opposite digital signal as what is input.
Is one that outputs the opposite state as what is input. That is, a “low” input (0) gives a
“high” output (1), and vice versa.

The “Buffer” Gate

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Two inverter gates are connected together so that the output of one fed into the input of
another, and the two inversion functions would “cancel” each other.

Buffer gates merely serve the purpose of signal amplification: taking a “weak” signal
source that isn’t capable of sourcing or sinking much current, and boosting the current
capacity of the signal so as to be able to drive a load.

Multiple-input Gates
Rule for an AND gate: output is “high” only if first input and second input are both
“high.”

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Rule for an OR gate: output is “high” if input A or input B are “high.

NAND, NOR
Rule for a NAND gate: output is not “high” if both the first input and the second input
are “high.”

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Rule for a NOR gate: output is not “high” if either the first input or the second input is
“high.”

Negative-AND, Negative-OR
A Negative-AND gate behaves like a NOR gate.

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A Negative-OR gate behaves like a NAND gate.

Exclusive-OR, Exclusive-NOR
Rule for an Exclusive-OR gate: output is “high” if the input logic levels are different.

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The rule for an Exclusive-NOR gate: output is “high” if the input logic levels are
the same.

CMOS Gate Circuitry

Each gate is constructed using small electronic elements such as transistors, diodes and
resistors.
The set of logic gates constructed using coupled transistors and resistors are collectively
known as the TTL gate family.
TTL logic gates are built of bipolar function transistors and resisters.
CMOS logic gates are constructed using field effect transistors (FET), and the circuit is
mostly devoid of resistors. As a result, CMOS gates do not consume any power at all
during a static state.
CMOS components are more sensitive to electromagnetic description than TTL.

TTL AND, and NAND

If both A and B are 0 no current flows, and transistors will be open.
If A is high and B is low, the current will not flow. When both are high, then the output
will be high, current will flow.
A TTL NAND gate can be made by taking a TTL inverter circuit and adding another
input.

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TTL OR/ NOR Gate
An OR gate may be created by adding an inverter stage to the output of the NOR gate
circuit.
If both A and B are 0 no current flows, and transistors will be open. If A is high and B is
low, the current will flows, and then the output will be high, likewise if B is high and A
low, current will flows and then the output will be high. If both high current flows.

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Special-output Gates
It is sometimes desirable to have a logic gate that provides both inverted and non-
inverted outputs. For example, a single-input gate that is both a buffer and an inverter,
with a separate output terminal for each function.
Complementary gates provide both inverted and non-inverted output signals, in such a
way that neither one is delayed with respect to the other.

Gate Universality
NAND and NOR gates possess a special property: they are universal. That is, given
enough gates, either type of gate is able to mimic the operation of any other gate type if
interconnected in sufficient numbers.
For example, it is possible to build a circuit exhibiting the OR function using three
interconnected NAND gates.

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Implementation of three basic gates using NAND and NOR gates

XOR gate, NAND, and NOR implementation

1. Implemented Using NAND

2. Implemented using NOR

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 Activity 3a
Q 1: Design Circuit Operation for
a).NAND
b). NOR gates.
Q2 Construct the
a). NOT, Buffer, OR, AND function using the universal gates.
b). NAND function using NOR gates.

Reading sources/links

1. https://www.allaboutcircuits.com/textbook/digital/#chpt-2
2. Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
3. Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th edition,
2002, Prentice Hall, ISBN 0-13-089592X

Topic 4: BOOLEAN ALGEBRA

4.1 Introduction
Mathematical rules are based on the defining limits we place on the particular numerical
quantities dealt with. When we say that 1 + 1 = 2 or 3 + 4 = 7, we are implying the use of
integer quantities: the same types of numbers we all learned to count in elementary
education. What most people assume to be self-evident rules of arithmetic—valid at all
times and for all purposes—actually depend on what we define a number to be. No, it just
means that the rules of “real” numbers do not apply to the kinds of quantities encountered
in AC circuits, where every variable has both a magnitude and a phase. For AC circuits, we
must use a different kind of numerical quantity, or object, (complex numbers, rather
than real numbers), and along with this different system of numbers comes a different set
of rules telling us how they relate to one another. An expression such as “3 + 4 = 5” is
nonsense within the scope and definition of real numbers, but it fits nicely within the scope
and definition of complex numbers (think of a right triangle with opposite and adjacent
sides of 3 and 4, with a hypotenuse of 5). Because complex numbers are two-dimensional,
they are able to “add” with one another trigonometrically as single-dimension real numbers
cannot.

4.2 Key terms Key terms

The Rule of Sum, The Rule of Product

• The Rule of Sum

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 If a first task can be performed in m, ways, while a second task can be performed in n
ways and the two

4.3 Sub topic 1: Laws of Boolean Algebra

Binary 1 is for High and binary 0 for low.
If B = 0, then not B = 1
• ORing variable is represented by a plus (+) sign between them. e.g A + B + C. (OR
Law)
• Logical AND of two or more variables is represented by A . B . C (AND Law)

Identity law

3. Commutative Property
A+B=B+A

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4. Associative Property
A + (B + C) = (A + B) + C

Circuit Simplification

5. Distributive Property
A ( B + C ) = AB + AC

Circuit Simplification

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 Redundancy Theorem

• A.(A+B)= A
• A + ( A . B) = A
• (A +B).(A +B)=A
• A.B+A.B=A

4.3 Sub topic 2: Converting Truth Tables into Boolean Expressions

Sum-Of-Products, or SOP
Boolean expressions may be generated from truth tables quite easily, by determining
which rows of the table have an output of 1, writing one product term for each row, and
finally summing all the product terms.
This creates a Boolean expression representing the truth table as a whole.
Sum-Of-Products Boolean expression is literally a set of Boolean terms added (summed)
together, each term being a multiplicative (product) combination of Boolean variables.
ABC + BC + DF, the sum of products “ABC,” “BC,” and “DF.”

SOP to a truth table and Binary Circuit

Sum-Of-Products expressions lend themselves well to implementation as a set of AND
gates (products) feeding into a single OR gate (sum).

4.4 Sub topic 3: Product-Of-Sums, or POS

Product-Of-Sums, or POS, Boolean expressions may also be generated from truth tables
quite easily, by determining which rows of the table have an output of 0, writing one
sum term for each row, and finally multiplying all the sum terms.
This creates a Boolean expression representing the truth table as a whole.

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Product-Of-Sums expression is a set of added terms (sums), which are multiplied
(product) together.
An example of a POS expression would be (A + B)(C + D), the product of the sums
“A + B” and “C + D”.

POS Truth table

SOP conversions focus on rows with one output, whilst POS conversions focus on rows
with zero output.
To convert a POS expression to a truth table, examine each of the sums to determine
where the sum is equal to zero.
When the sum is equal to zero, a zero will be present at the final output of the circuit.

POS Binary Circuit

Product-Of-Sums expressions lend themselves well to implementation as a set of OR

gates (sums) feeding into a single AND gate (product).

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The Exclusive-OR Function: The XOR Gate
The OR function is equivalent to Boolean addition, the AND function to Boolean
multiplication, and the NOT function (inverter) to Boolean complementation, there is no
direct Boolean equivalent for Exclusive-OR.
However, there is a way to represent the Exclusive-OR function in terms of OR and
AND, as: AB’ + A’B

The XOR Gate

Any expression following the AB’ + A’B form (two AND gates and an OR gate) may be
replaced by a single Exclusive-OR gate.

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 Activity 4a
Example Boolean expression
When “breaking” a complementation bar in a Boolean expression, the
operation directly underneath the break (addition or multiplication) reverses,
and the broken bar pieces remain over the respective terms

Reading sources/links

• https://www.allaboutcircuits.com/textbook/digital/#chpt-2
• Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
• Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th edition, 2002,
Prentice Hall, ISBN 0-13-089592X

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 Topic 5: KARNAUGH MAPPING

Introduction
The Karnaugh map, like Boolean algebra, is a simplification tool applicable to digital
logic. It is a graphical method, which consists of 2n cells for ‘n’ variables. The adjacent
cells are differed only in single bit position. Karnaugh maps are both faster and easier.
Karnaugh maps work well for up to six input variables,

5.2 Key terms

K-Map, Atomic
Proposition: sentence/statement that is true or false.
Atomic: a statement that cannot be logically broken into smaller statements.

5.3 Sub topic1: 2 Variable K-Map

The number of cells in 2 variable K-map is four, since the number of variables is two.
The following figure shows 2 variable K-Map.

The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m2, m3),
(m0, m2) and (m1, m3)}.

For the Truth table below, transfer the outputs to the Karnaugh, then write the Boolean
expression for the result.

The Sum-Of-Products of the above two terms Output = A+B

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5.4 Sub topic 2: 3 Variable K-Map
The number of cells in 3 variable K-map is eight since the number of variables is three.
The following figure shows 3 variable K-Map.

The possible combinations of grouping 4 adjacent min terms are {(m0, m1, m3, m2),
(m4, m5, m7, m6), (m0, m1, m4, m5), (m1, m3, m5, m7), (m3, m2, m7, m6) and (m2,
m0, m6, m4)}.
The possible combinations of grouping 2 adjacent min terms are {(m0, m1), (m1, m3),
(m3, m2), (m2, m0), (m4, m5), (m5, m7), (m7, m6), (m6, m4), (m0, m4), (m1, m5),
(m3, m7) and (m2, m6)}.

Example 1: Simplify the logic diagram below.

Solution: DeMorgan’s Theorems describe the equivalence between gates with inverted
inputs and gates with inverted outputs.

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Example 2: Simplify the logic diagram below and Draw simplified logic diagram.

Solution

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 SOP to K-map

If we consider the combination of inputs for which the Boolean function is ‘1’, then we
will get the Boolean function, which is in the standard sum of products.
Example 3
Let us simplify the following Boolean function,

f(W, X, Y, Z)= WX’Y’ + WY + W’YZ’ using K-map. 4 variable K-map.

Here, 1s are placed in the following cells of K-map.

The cells, which are common to the intersection of Row 4 and columns 1 & 2 are
corresponding to the product term, WX’Y’.
The cells, which are common to the intersection of Rows 3 & 4 and columns 3 & 4 are
corresponding to the product term, WY.
The cells, which are common to the intersection of Rows 1 & 2 and column 4 are
corresponding to the product term, W’YZ’.

Minterm for SOP

A minterm is a Boolean expression resulting in 1 for the output of a single cell, and 0s
for all other cells in a Karnaugh map, or truth table.
If a minterm has a single 1 and the remaining cells as 0s, it would appear to cover a
minimum area of 1s.

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 Maxterm, POS Expression
A minterm is a Boolean expression resulting in 1 for the output of a single cell, and 0s
for all other cells in a Karnaugh map, or truth table.
If a minterm has a single 1 and the remaining cells as 0s, it would appear to cover a
minimum area of 1s. A maxterm is a Boolean expression resulting in a 0 for the output
of a single cell expression, and 1s for all other cells in the Karnaugh map, or truth table.

Activity 5a
Question
Simplify the following Boolean function, f(W, X, Y, Z)= ΠM(0,1,2,4)

Reading sources/links

• https://www.allaboutcircuits.com/textbook/digital/#chpt-2
• Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
• Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th edition, 2002,
Prentice Hall, ISBN 0-13-089592X

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Topic 6: COMBINATIONAL LOGIC FUNCTIONS

Introduction
The combinational circuit is a circuit in which we combine the different gates in the
circuit, for example, encoder, decoder, multiplexer, and demultiplexer. The output of a
combinational circuit at any instant of time, depends only on the levels present at input
terminals. The combinational circuit does not use any memory. The previous state of
input does not have any effect on the present state of the circuit. A combinational circuit
can have an n number of inputs and an m number of outputs.

6.2 Key terms

Truth table, block diagram
Vertices: End points.
Edges/ Arcs: Line segments, connect to end points, connect vertices, have directions/no
directions.

6.2 Sub topic1: Half Adder

• Half adder is a combinational logic circuit with two inputs and two outputs.
• The half adder circuit is designed to add two single-bit binary numbers.
graphs/pseudographs: Multiple edges connecting the same vertices. A communication
link connects a computer to itself-feedback loop for diagnostic purposes.
• It is the basic building block for the addition of two single-bit numbers. This circuit has
two outputs carry and sum.

Block diagram

Truth Table

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Half Adder Gate diagram

Circuit diagram

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 Full Adder
• Full adder is developed to overcome the drawback of the Half Adder circuit. It can add
two one-bit numbers A and B, and carry c. The full adder is a three-input and two-output
combinational circuit.

Block diagram

34
Truth Table

Full Adder Logic Gate

Following is the circuit, using a block diagram for a full adder may be used.

35
 8 Bit Adder

6.3 Sub topic 2: Multiplexers

• Multiplexer is a special type of combinational circuit. There are n-data inputs, one
output, and m select inputs with 2m = n.
• It is a digital circuit that selects one of the n data inputs and routes it to the output.
• The selection of one of the n inputs is done by the selected inputs.
• Depending on the digital code applied at the selected inputs, one out of n data sources is
selected and transmitted to the single output Y. E is called the strobe or enable input
which is useful for the cascading.

Block diagram

Truth Table

36
 Demultiplexers
• A demultiplexer performs the reverse operation of a multiplexer.
• It receives one input and distributes it over several outputs.
• It has only one input, n outputs, and m select input.
• At a time only one output line is selected by the select lines and the input is transmitted
to the selected output line.
• A de-multiplexer is equivalent to a single pole multiple-way switch.
Demultiplexers come in multiple variations.
• 1: 2 demultiplexer
• 1: 4 demultiplexer
• 1: 16 demultiplexer
• 1: 32 demultiplexer

Demultiplexers Block diagram

37
 Truth Table

6.4 Sub topic 3: Decoder

• A decoder is a combinational circuit.

• It has n input and to a maximum m = 2n outputs.
• Decoder is identical to a demultiplexer without any data input. It performs operations
that are exactly opposite to those of an encoder.

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 Block diagram

Examples of Decoders
• Code converters.
• BCD to seven segment decoders.
• Nixie tube decoders.
• Relay actuator.
2 to 4 Line Decoder
• The block diagram of the 2 to 4-line decoder.
• A and B are the two inputs where D through D are the four outputs.

Decoder Block diagram and Truth Table

• Truth table explains the operations of a decoder. It shows that each output is 1 for only a
specific combination of inputs.

Circuit Diagram

39
 Encoder

Activity 6a
Come up with a Truth table for an encoder and draw the circuit diagram.

Reading sources/links

• https://www.allaboutcircuits.com/textbook/digital/#chpt-2
• Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
• Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th edition, 2002,
Prentice Hall, ISBN 0-13-089592X

40
Topic 7: MULTIVIBRATORS

Introduction
Any digital circuit employing feedback is called a multivibrator. They have two outputs Q and
notQ. These devices only have two possible states {Q = 0, notQ = 1} or { Q =1, not Q = 0}

Three Types
• Monostable - Also called “One-Shots”. It has one stable state, the Q output is normally
0 (that other state being momentary).
An input signal triggers the monostable and the output rises to 1. Remains in this state
for a fixed period of time. Then returns to its stable state of 0.
• Bistable - It is called “bistable” because it can hold stable in one of two possible output
states, either 0 or 1.
Types of bistable are SR, D, JK and Master/ Slaves.
• Astable - astable multivibrators, have no stable state (oscillating back and forth between
an output of 0 and 1).
Used for oscillators and square wave generators.

7.1 Sub topic1: Gated S-R Latch

• A pre-order traversal prints the contents of a sorted tree in pre-order. The contents of the
root node are printed first, followed by the left subtree, and finally the right subtree.
• In an in-order traversal the contents of the sorted tree are printed in order. It starts with
the lowest value first and then increases its value as it traverses the tree. If the tree uses
strings or characters and would be increasing numerically from 0 if the tree contains
numerical values.
• A post-order traversal prints the contents of a sorted tree in post-order. The contents of
the left subtree are printed first followed by the right subtree and finally the root node.
• It is sometimes useful in logic circuits to have a multivibrator which changes state only
when certain conditions are met, regardless of its S and R input states.
• The conditional input is called the enable, and is symbolized by the letter E.
Gated SR- Latch Truth Table

41
 Gated SR- Latch and Truth Table

• When the E=0, the outputs of the two AND gates are forced to 0, regardless of the states
of either S or R.
• Consequently, the circuit behaves as though S and R were both 0, latching the Q and
not-Q outputs in their last states.
• Only when the enable input is activated (1) will the latch respond to the S and R inputs.

S-R Gated Latch Symbol

7.2 Sub topic 2: D Latch

• Since the enable input on a gated S-R latch provides a way to latch the Q and not-Q
outputs without regard to the status of S or R, we can eliminate one of those inputs to
create a multivibrator latch circuit with no “illegal” input states.
• Such a circuit is called a D latch.
• The D latch is nothing more than a gated S-R latch with an inverter added to make R the
complement (inverse) of S.
• D latches can be used as 1-bit memory circuits, storing either a “high” or a “low” state
when disabled, and “reading” new data from the D input when enabled.

42
 Block diagram

Logic diagram and Truth Table

7.3 Sub topic 3: Edge-triggered Latches: Flip-Flops

• Both S-R and D latch circuits have the enable inputs.

• The latch responds to the data inputs (S-R or D) only when the enable input is activated.
• In many digital applications, however, it is desirable to limit the responsiveness of a
latch circuit to a very short period of time instead of the entire duration that the enabling
input is activated.
• One method of enabling a multivibrator circuit is called edge triggering, where the
circuit’s data inputs have control only during the time that the enabled input
is transitioning from one state to another.

43
Sub topic 4: Positive edge-triggered D-latch response

• The outputs only respond to the D input during that brief moment of time when the
enable signal changes, or transitions, from low to high.
• This is known as positive edge-triggering.

Negative edge-triggered D-latch response

• The negative edge triggering as well produces the following response to the same input
signals

44
 S, R, and D Flip Flop

• Whenever we enable a multivibrator circuit on the transitional edge of a square-wave

enable signal, we call it a flip-flop instead of a latch.
• Consequently, an edge-triggered S-R circuit is more properly known as an S-R flip-flop,
and an edge-triggered D circuit is a D flip-flop.
• The enable signal is renamed to the clock signal.
• Also, we refer to the data inputs (S, R, and D, respectively) of these flip-flops
as synchronous inputs, because they have an effect only at the time of the clock pulse
edge (transition), thereby synchronizing any output changes with that clock pulse, rather
than at the whim of the data inputs.
• Only when the clock signal (C) is transitioning from low to high is the circuit responsive
to the S and R inputs.
• For any other condition of the clock signal (“x”) the circuit will be latched.

Truth Table and Logic gate circuit for S-R flip-flop

Truth table to Logic simplification

• It is important to note that the invalid state for the S-R flip-flop is maintained only for
the short period of time that the pulse detector circuit allows the latch to be enabled.
• After that brief time period has elapsed, the outputs will latch into either the set or the
reset state.
• The problem of a race condition manifests itself. With no enable signal, an invalid
output state cannot be maintained.
• However, the valid “latched” states of the multivibrator—set and reset—are mutually
exclusive to one another.

45
• Therefore, the two gates of the multivibrator circuit will “race” each other for
supremacy, and whichever one attains a high output state first will “win.”

Block symbols for flip-flops

• The triangle symbol next to the clock inputs tells us that these are edge-triggered
devices, and consequently that these are flip-flops rather than latches.
• The symbols below are positive edge-triggered: that is, they “clock” on the rising edge
(low-to-high transition) of the clock signal.

• Negative edge-triggered devices are symbolized with a bubble on the clock input line
• Both of the below flip-flops will “clock” on the falling edge (high-to-low transition) of
the clock signal.

J-K Flip-Flop

• A J-K flip-flop is an S-R flip-flop with an added layer of feedback.

• This feedback selectively enables one of the two set/reset inputs so that they cannot both
carry an active signal to the multivibrator circuit, thus eliminating the invalid condition.
• J – K Flip flop permits the J input to have effect only when the circuit is reset, and
permits the K input to have effect only when the circuit is set.
• When both J and K inputs are activated, and the clock input is pulsed, the outputs (Q and
not-Q) will swap states. That is, the circuit will toggle from a set state to a reset state or
vice versa.
• In other words, the two inputs are interlocked, to use a relay logic term, so that they
cannot both be activated simultaneously.
• Without the edge-triggering of the clock input, the circuit would continuously toggle
between its two output states when both J and K were held high (1), making it an astable
device instead of a bistable device in that circumstance.

46
• If we want to preserve bistable operation for all combinations of input states,
we must use edge-triggering so that it toggles only when we tell it to, one step (clock
pulse) at a time.

Asynchronous flip-flop inputs

• Asynchronous inputs on a flip-flop have control over the outputs (Q and not-Q)
regardless of clock input status.
• These inputs are called the preset (PRE) and clear (CLR). The preset input drives the
flip-flop to a set state while the clear input drives it to a reset state.
• It is possible to drive the outputs of a J-K flip-flop to an invalid condition using the
asynchronous inputs because all feedback within the multivibrator circuit is overridden.
• When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of
any of the synchronous inputs or the clock.
• When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless
of any of the synchronous inputs or the clock.
• When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of
any of the synchronous inputs or the clock. When the clear input is activated, the flip-
flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the
clock.

47
Asynchronous inputs

• Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high

or active-low.
• If they’re active-low, there will be an inverting bubble at that input lead on the block
symbol, just like the negative edge-trigger clock inputs
• Sometimes the designations “PRE” and “CLR” will be shown with inversion bars above
them, to further denote the negative logic of these inputs.

Activity 7a

Solution

Reading sources/links

• https://www.allaboutcircuits.com/textbook/digital/#chpt-2
• Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
• Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th edition, 2002,
Prentice Hall, ISBN 0-13-089592X

48
Topic 8: COUNTERS

8.1 Introduction
A Counter is a device that stores (and sometimes displays) the number of times a particular event
or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purposes, they can count specific events happening in the circuit. Not
only counting, a counter can follow a certain sequence based on our design like any random
sequence 0,1,3,2… They can also be designed with the help of flip-flops. They are used as
frequency dividers where the frequency of a given pulse waveform is divided. Counters are
sequential circuits that count the number of pulses can be either in binary code or BCD form. The
main properties of a counter are timing, sequencing, and counting. Counter works in two modes
up counter and down counter

8.2 Key terms

Reset, Enable, Direction, Data, Load
Reset – sets counts to zero. Some IC manufacturers name it "clear" or "master reset
(MR)".
Enable – allows or inhibits counting.
Direction – determines whether counts will increment or decrement.
Data – parallel input data which represents a particular counts value.
Load – copies parallel input data to the counts.

Binary Counter
An ‘N’ bit binary counter consists of ‘N’ T flip-flops. If the counter counts from 0 to 2N
− 1, then it is called as binary up counter. Similarly, if the counter counts down from 2N
− 1 to 0, then it is called as binary down counter.
There are two types of counters based on the flip-flops that are connected in
synchronous or not.
• Asynchronous counters
• Synchronous counters

8.3 Sub topic 1: Asynchronous Counters

If the flip-flops do not receive the same clock signal, then that counter is called as
Asynchronous counter. The output of system clock is applied as clock signal only to
the first flip-flop. The remaining flip-flops receive the clock signal from output of its
previous stage flip-flop. Hence, the outputs of all flip-flops do not change (affect) at the
same time.

Asynchronous Binary up counter

An ‘N’ bit Asynchronous binary up counter consists of ‘N’ T flip-flops. It counts from
0 to 2N − 1. The block diagram of 3-bit Asynchronous binary up counter is shown in
the following figure.

49
The 3-bit Asynchronous binary up counter contains three T flip-flops and the T-input
of all the flip-flops are connected to ‘1’. All these flip-flops are negative edge triggered
but the outputs change asynchronously. The clock signal is directly applied to the first
T flip-flop. So, the output of the first T flip-flop toggles for every negative edge of
clock signal. The output of first T flip-flop is applied as the clock signal for second T
flip-flop. So, the output of second T flip-flop toggles for every negative edge of output
of first T flip-flop.

Asynchronous Binary down counter

An ‘N’ bit Asynchronous binary down counter consists of ‘N’ T flip-flops. It counts
from 2N – 1 to 0. The block diagram of 3-bit Asynchronous binary down counter is
shown in the following figure.

The block diagram of the 3-bit Asynchronous binary down counter is similar to the
block diagram of the 3-bit Asynchronous binary up counter. But, the only difference is
that instead of connecting the normal outputs of one stage flip-flop as the clock signal
for next stage flip-flop, connect the complemented outputs of the stage flip-flop as
clock signal for next stage flip-flop. The complemented output goes from 1 to 0 is same
as the normal output goes from 0 to 1.

50
8.4 Sub topic 2: Synchronous Counters
If all the flip-flops receive the same clock signal, then that counter is called as
Synchronous counter. Hence, the outputs of all flip-flops change (affect) at the same
time.

Synchronous Binary Up Counter

An ‘N’ bit Synchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0
to 2N− 1. The block diagram of 3-bit Synchronous binary up counter is shown in the
following figure.

The 3-bit Synchronous binary up counter contains three T flip-flops & one 2-input AND
gate. All these flip-flops are negative edge triggered and the outputs of flip-flops change
(affect) synchronously. The T inputs of first, second and third flip-flops are 1, Q0’ & Q1’
Q0’ respectively. The output of first T flip-flop toggles for every negative edge of clock
signal. The output of second T flip-flop toggles for every negative edge of clock signal if
Q0’ is 1. The output of third T flip-flop toggles for every negative edge of clock signal if
both Q0’ & Q1’ are 1.

Synchronous Binary Down Counter

An ‘N’ bit Synchronous binary down counter consists of ‘N’ T flip-flops. It counts from
2N− 1to 0. The block diagram of 3-bit Synchronous binary down counter is shown in the
following figure.

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 Counter modulus

• The modulus (or just modulo) is the number of states the counter counts and is the
dividing number of the counter. Modulus Counters, or simply MOD counters, are
defined based on the number of states that the counter will sequence through before
returning back to its original value.
• Modulus Counters, or simply MOD counters, are defined based on the number of
states that the counter will sequence through before returning back to its
original value.
For example, a 2-bit counter that counts from 002 to 112 in binary, that is 0 to 3 in
decimal, has a modulus value of 4 ( 00 → 1 → 10 → 11, and return back to 00 ) so
would therefore be called a modulo-4, or mod-4, counter. Note also that it has taken four
clock pulses to get from 00 to 11

Example

Modulo-5 Mod Counters

Suppose we want to design a MOD-5 counter, how could we do that. First we know that
“m = 5”, so 2n must be greater than 5. As 21 = 2, 22 = 4, 23 = 8, and 8 is greater than 5,
then we need a counter with at least three flip-flops (N = 3) to give us a natural binary
count of 000 to 111 (0 to 7 decimal).

Activity 8a
Question 1

a. With the aid of a truth table explain how Asynchronous counters

work.
b. How many flip-flops are required to make a MOD-32 binary counter?

Reading sources/links

• https://www.allaboutcircuits.com/textbook/digital/#chpt-2
• Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
• Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th edition, 2002,
Prentice Hall, ISBN 0-13-089592X

52
Topic 9: SHIFT REGISTERS

Introduction
A shift register is a type of digital circuit using a cascade of flip-flops where the output of one
flip-flop is connected to the input of the next. They share a single clock signal, which causes the
data stored in the system to shift from one location to the next. By connecting the last flip-flop
back to the first, the data can cycle within the shifters for extended periods, and in this form,
they were used as a form of computer memory. Shift registers can have both parallel and serial
inputs and outputs. These are often configured as "serial-in, parallel-out" (SIPO) or as "parallel-
in, serial-out" (PISO). There are also types that have both serial and parallel input and types
with serial and parallel output. There are also "bidirectional" shift registers, which allow shifting
in both directions: L → R or R → L. The serial input and last output of a shift register can also
be connected to create a "circular shift register". A PIPO register (parallel in, parallel out) is
very fast – an output is given within a single clock pulse

9.1 Sub topic1: Serial-in/serial-out shift register

• The term “SISO” stands for “Serial-In Serial-Out”.
• The SISO shift register circuit accepts serial data on its input pin and shifts it out serially
on its output pin.
• The number of bits that can be shifted out before the next bit arrives depends on the
speed of the clock signal that controls the operation of the shift register.
• This type of shift register can be used as a buffer between two asynchronous devices that
communicate with each other using signals with different frequencies or phases.
• The SISO shift register block diagram is shown below which includes 3-D flip-flops.

53
• The connection of these FFs can be done by connecting the one Flip Flops output to the
next flip flop input.
• So these FFs are synchronous through each other because the equal CLK signal is
applied in each Flip Flop.

3-bit SISO shift register

• The initial status of the D flip-flops in the absence of a clock signal is Q2 Q1 Q0 =000.
• Here, the serial output is coming from Q0. So, the LSB 1 is received at the 3rd positive
edge of the clock and the MSB 0 is received at the 5th positive edge of the clock.
• Therefore, the 3-bit SISO shift register requires five clock pulses in order to produce the
valid output. Similarly, the N-bit SISO shift register requires 2N-1 clock pulses in order
to shift ‘N’ bit information.

Serial In - Parallel Out SIPO Shift Register

• The shift register, which allows serial input and produces parallel output is known as the
Serial In – Parallel Out (SIPO) shift register.
• This circuit consists of three D flip-flops, which are cascaded. That means the output of
one D flip-flop is connected to the input of the next D flip-flop.
• All these flip-flops are synchronous with each other since the same clock signal is
applied to each one.
• In this shift register, we can send the bits serially from the input of the leftmost D flip-
flop. Hence, this input is also called serial input.
• For every positive edge triggering of a clock signal, the data shifts from one stage to the
next.
• In this case, we can access the outputs of each D flip-flop in parallel. So, we will get
parallel outputs from this shift register.

54
• The block diagram of the 3-bit SIPO shift register is shown below.

Parallel In - Serial Out (PISO) Shift Register

• The shift register, which allows parallel input and produces serial output is known as the
Parallel In – Serial Out (PISO) shift register.
• This circuit consists of three D flip-flops, which are cascaded. That means the output of
one D flip-flop is connected to the input of the next D flip-flop.
• All these flip-flops are synchronous with each other since the same clock signal is
applied to each one.
• In this shift register, we can apply the parallel inputs to each D flip-flop by making
Preset Enable to 1.
• For every positive edge triggering of a clock signal, the data shifts from one stage to the
next. So, we will get the serial output from the rightmost D flip-flop.
• The block diagram of 3-bit PISO shift register is shown in the following figure.

55
 Parallel In - Parallel Out (PIPO) Shift Register
• The shift register, which allows parallel input and produces parallel output is known as
the Parallel In – Parallel Out (PIPO) shift register.
• This circuit consists of three D flip-flops, which are cascaded. That means the output of
one D flip-flop is connected to the input of the next D flip-flop.
• All these flip-flops are synchronous with each other since the same clock signal is
applied to each one. In this shift register, we can apply the parallel inputs to each D flip-
flop by making Preset Enable to 1.
• We can apply the parallel inputs through preset or clear.
• These two are asynchronous inputs. That means, the flip-flops produce the
corresponding outputs, based on the values of asynchronous inputs.
• In this case, the effect of outputs is independent of the clock transition.
• So, we will get the parallel outputs from each D flip-flop.
• The block diagram of 3-bit PIPO shift register is shown in the following figure.

56
9.2 Sub topic2: Universal Shift Register
• A Universal Shift register is a register that can store the data and /or shift the data
towards the right and left along with the parallel load capability known as a universal
shift register.
• It can be used to perform input/output operations in both serial and parallel modes.
• Unidirectional shift registers and bidirectional shift registers are combined together to
get the design of the universal shift register.
It is also known as a parallel-in-parallel-out shift register or shift register with the
parallel load.
• Parallel load operation – stores the data in parallel as well as the data in parallel
• Shift left operation – stores the data and transfers the data shifting towards left in the
serial path
• Shift right operation – stores the data and transfers the data by shifting towards the
right in the serial path.
• Hence, Universal shift registers can perform input/output operations with both serial and
parallel loads.

Ring counter
• A ring counter is a type of counter composed of flip flops connected into a shift register
with the output of the last flip flop fed into the input of the first making a circular or ring
structure.
• The flip flops are connected in such a way that information shifts either from left to right
and back around
• The ring counter is almost the same as the shift counter, the only difference is that the
output of the last flip-flop is connected to the input of the first flip-flop but with shift
counters it is taken as the output.
• The block diagram of 3-bit Ring counter is shown in the following figure.

57
 Johnson Counter
• The operation of Johnson Ring counter is similar to that of Ring counter.
• But, the only difference is that the complemented output of rightmost D flip-flop is
given as input of leftmost D flip-flop instead of normal output.
• Therefore, ‘N’ bit Johnson Ring counter produces a sequence of states (pattern of zeros
and ones) and it repeats for every ‘2N’ clock cycles.
• Johnson Ring counter is also called as Twisted Ring counter and switch tail Ring
counter.

Activity 9a
1 Differentiate between Ring Type Counter and Johnson Type Counter
2 Explain the difference between:
a. PISO and SIPO Shift Registers
b. PIPO and SISO Shift Registers.

Reading sources/links

• https://www.allaboutcircuits.com/textbook/digital/#chpt-2
• Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
• Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th edition, 2002,
Prentice Hall, ISBN 0-13-089592X

58
 Topic 10: DIGITAL STORAGE (MEMORY)

Introduction
When we store information in a circuit or device, we not only need some way to store and
retrieve it but also to locate precisely where in the device it is. Most, if not all, memory devices
can be thought of as a series of mailboxes, folders in a file cabinet, or some other metaphor
where information can be located in a variety of places.

10.1 Sub topic 1: Digital Memory Terms and Concepts

• When we refer to the actual information being stored in the memory device, we usually
refer to it as the data. The location of this data within the storage device is typically
called the address.
• A vinyl record platter is an example of a random-access device: to skip to any song, you
just position the stylus arm at whatever location on the record that you want.
• Cassette tape, on the other hand, is sequential. You have to wait to go past the other
songs in sequence before you can access or address the song that you want to skip to.
• The process of storing a piece of data on a memory device is called writing, and the
process of retrieving data is called reading.
• Some devices do not allow for the writing of new data and are purchased “pre-written”
from the manufacturer.
• Such is the case for vinyl records and compact audio disks, and this is typically referred
to in the digital world as read-only memory, or ROM.
• Cassette audio and video tape, on the other hand, can be re-recorded (re-written) or
purchased blank and recorded fresh by the user. This is often called read-write memory.
• Many electronic memory devices store binary data by means of circuits that are either
latched in a “high” or “low” state, and this latching effect holds only as long as electric
power is maintained to those circuits.
• Such memory would be properly referred to as volatile. Storage media such as
magnetized disks or tape is nonvolatile because no source of power is needed to
maintain data storage.

10.2 Sub topic 2: ROM

• ROM stands for Read Only Memory. The memory from which we can only read but
cannot write on it. This type of memory is non-volatile. The information is stored
permanently in such memories during manufacture.
• A ROM, stores such instructions as are required to start a computer when electricity is
first turned on, this operation is referred to as bootstrap.
• ROM chips are not only used in the computer but also in other electronic items like
washing machines and microwave ovens.

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Memory With Moving Parts

• Modern disk drives use multiple platters made of hard material (hence the name, “hard
drive”) with multiple read/write heads for every platter.
• The gap between the head and platter is much smaller than the diameter of a human hair.
• If the hermetically-sealed environment inside a hard disk drive is contaminated with
outside air, the hard drive will be rendered useless.
• Dust will lodge between the heads and the platters, causing damage to the surface of the
media.
• Here is a hard drive with four platters, although the angle of the shot only allows
viewing of the top platter.
• This unit is complete with drive motor, read/write heads, and associated electronics. It
has a storage capacity of 340 Mbytes

CDs and DVDs

• The advantages of CDs over magnetic tape are legion.
• Being digital, the information is highly resistant to corruption. Being non-contact in
operation, there is no wear incurred through playing. Being optical, they are immune to
magnetic fields (which can easily corrupt data on magnetic tape or disks).
• It is possible to purchase CD “burner” drives that contain the high-power laser necessary
to write to a blank disc.
• The video entertainment industry has leveraged the technology of optical storage with
the introduction of the Digital Video Disc, or DVD.
• Using a similar-sized plastic disc as the music CD, a DVD employs closer spacing of
pits to achieve much greater storage density.
• This increased density allows feature-length movies to be encoded on DVD media.

Reading sources/links

• https://www.allaboutcircuits.com/textbook/digital/#chpt-2
• Lessons In Electric Circuits, Volume IV – Digital, Tony R. Kuphaldt
• Introduction to Electronic Circuits, Samuel P. Harbison, Guy L. Steele, 5th edition, 2002,
Prentice Hall, ISBN 0-13-089592X

60
 11.0 Module Summary/Conclusion
By the end of this module, ss will be able to solve logic and proof techniques, set theory,
elementary number theory, functions and relations, graphs, trees, modeling computations and
abstract algebra expressions. Techniques of counting: permutations, combinations, recurrences,
algorithms are also covered to help students have a broader scope of real world problem
solving techniques.

12 PRACTICUUM
13 REVISION
14 EXAMINATION

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