Case Study One: 8085

Microprocessor Architecture
Lesson 04
Ch 2 & Ch3

Dr. Mohammed Majid Al Khalidy

8085 Microprocessor Architecture & Pin
configuration

 8085 and 8086 comparison

 Pin configuration of 8085
 Limitations of 8085
 MPU Communication
 Internal Architecture of 8085
 8085Single board Microcomputer System
8085 and 8086 Comparison

Dr. Mohammed Majid Al Khalidy 3

Dr. Mohammed Majid Al Khalidy 4
Dr. Mohammed Majid Al Khalidy 5
So, if you understand the
concept of 8085 MP, all
the other MPs will be easy
for you to understand.

6
Pin configuration of 8085

➢8-bit general purpose

μp
➢Capable of addressing
64 k of memory
➢Has 40 pins
➢Requires +5 v power
supply
➢Can operate with 3 MHz
clock
Internal Architecture of 8085

 It includes-
◦ ALU
◦ Timing & Control Unit
◦ Instruction Register and Decoder
◦ Register Array
◦ Interrupt Control
◦ Serial I/O Control
Pin configuration of 8085

All the signals can be

classified into
Six groups –
1. Address Bus
2. Data Bus
3. Control & Status
signals
4. Power signal &
frequency signals
5. Externally initiated
signals
6. Serial I/O ports
1. Address & 2. data bus
 8085 μp consists of 16 signal pins use as address
bus.
 Divide into 2 part: A15 – A8 (upper)
AD7 – AD0 (lower).
◦ A15 – A8 : Unidirectional, known as ‘high order
address’.

◦ AD7 – AD0 : bidirectional and dual purpose

(address and data placed once at a time).

◦ AD7 – AD0 also known as ‘low order address’.

◦ To execute an instruction, at early stage AD7 –
AD0 uses as address bus and alternately as
data bus for the next cycle.
◦ The method to change from address bus to data
bus known as ‘bus multiplexing’.
3. Control & Status signals
This group of signal includes-
▪ Two control signals (RD’ & WR’)
▪ Three status signals (IO/M’ , S1 & S0)
▪ One special signal (ALE)

 RD’ – Read (active low). To indicate that the I/O or

memory selected is to be read and data are available
on the bus.

 WR’ – Write (Active low). This is to indicate that the

data available on the bus are to be written to memory
or I/O ports.

 IO/M’ – To differentiate I/O operation or memory

operations.
◦ ‘0’ - indicates a memory operation.
◦ ‘1’-indicates an I/O operation.
◦ IO/M’ combined with RD and WR to generate I/O and memory
control signals.
•S1 and S0: Status signals, similar to IO/M, can identify
various operations as shown on the following table :
•ALE (Address Latch Enable) signal :

✓ ALE used to de-multiplex address/data bus

✓ Active high signal - generated to show the start of 8085
operation.
✓ When transition 1-to-0: indicate that lines AD7-AD0
(AD7-AD0 = A7-A0) act as address lines.
4. Power signal & frequency signals
▪ Vcc : +5 V power supply

▪ Vss : Ground reference

▪ X1 & X2 : A crystal is connected

at these two pins. The frequency
is divided by two.
Therefore, to operate a system
at 3 MHz, the crystal should
have a frequency of 6 MHz.

▪ CLK OUT : This signal is used

as the system clock for other
devices.
5. Interrupts In 8085

What is Interrupt?
Interrupt is a mechanism by which an I/O or an instruction
can suspend the normal execution of processor and get
itself serviced. Generally, a particular task is assigned to
that interrupt signal. In the microprocessor based system
the interrupts are used for data transfer between the
peripheral devices and the microprocessor.

Interrupt Service Routine (ISR)

A small program or a routine that when executed services
the corresponding interrupting source is called as an ISR.
16
Maskable/Non-Maskable Interrupt
An interrupt that can be disabled by writing some instruction
is known as Maskable Interrupt otherwise it is called Non-
Maskable Interrupt.

There are 5 pins available in 8085 for interrupt:

1. TRAP
2. RST 7.5
3. RST6.5
4. RST5.5
5. INTR

17
Execution of Interrupts
➢ When there is an interrupt requests to the
Microprocessor then after accepting the interrupts
Microprocessor send the INTA (active low) signal to the
peripheral.
➢ The vectored address of particular interrupt is stored in
Program Counter PC.
➢ The processor executes an interrupt service routine
(ISR) addressed in program counter PC.

There are two types of interrupts used in 8085

Microprocessor:
1. Software Interrupts
2. Hardware Interrupts
18
1. Software Interrupts
➢ A software interrupts is a particular instructions that can be inserted
into the desired location in the program. There are 8 Software
interrupts in 8085 Microprocessor. From RST0 to RST7.
1. RST0
2. RST1
3. RST2
4. RST3
5. RST4
6. RST5
7. RST6
8. RST7
➢ They allow the microprocessor to transfer program control from the main
program to the subroutine program. After completing the subroutine
program, the program control returns back to the main program. 19
We can calculate the vector address of these interrupts
using the formula given below:
Vector Address = Interrupt Number * 8

Example:
RST2: vector address =2*8 = 16
RST1: vector address =1*8 = 08
RST3: vector address =3*8 = 24

20
2. Hardware Interrupt
As we have already discussed that there are 5 interrupt pins
in the microprocessor used as Hardware Interrupts given
below:
1. TRAP
2. RST7.5
3. RST6.5
4. RST5.5
5. INTR

Note:
6. INTR
INTA is not an interrupt. INTA is used by the Microprocessor
for sending the acknowledgement. TRAP has highest priority and
RST7.5 has second highest priority and so on.
21
22
On receipt of an interrupt, the microprocessor
acknowledges the interrupt by the active low INTA
(Interrupt Acknowledge) signal.
Reset In (input, active low)
· This signal is used to reset the microprocessor.
· The program counter inside the microprocessor is set
to zero.
· The buses are tri-stated.
Reset Out (Output)
· It indicates CPU is being reset.
· Used to reset all the connected devices when the
microprocessor is reset.

23
RESET IN’ : When the signal on this
pin goes low,
✓the program counter is set to
zero.
✓the buses are tri-sated.
✓MPU is reset.

RESET OUT : This signal is used to

reset other devices.
Externally initiated Signals including
Interrupt
  An interrupt is a hardware-initiated subroutine CALL.
 When interrupt pin is activated, an ISR will be called,
interrupting the program that is currently executing.

Pin Subroutine Location

TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
INTR *
Note: * the address of the ISR is determined by the external
hardware.
 INTR input is enabled when EI instruction
is executed.
 The status of the RST 7.5, RST 6.5 and
RST 5.5 pins are determined by both EI
instruction and the condition of the mask
bits in the interrupt mask register.
6. Serial I/O ports

The 8085 has two signals to implement the

serial transmission:
▪SID: Serial Input Data
▪SOD: Serial Output Data

These signals are used for serial communication.

Limitations of 8085

 The low order address bus is multiplexed

with the data bus. The buses need to be
de-multiplexed.

 Appropriate control signals need to be

generated to interface memory and I/O
with the 8085.
Generating Control Signals
De-multiplexing Address/Data Lines
De-multiplexed Address & Data bus with
Control Signals
Registers
These are general purposes registers. Microprocessor
consists 6 general purpose registers of 8-bit each named
as B,C,D,E,H and L. Generally theses registers are not
used for storing the data permanently. It carries the 8-
bits data. These are used only during the execution of the
instructions.
These registers can also be used to carry the 16 bits data
by making the pair of 2 registers. The valid register pairs
available are BC,DE, and HL. We cannot use other pairs
except BC,DE and HL. These registers are programmed
by user.

34
Accumulator
Accumulator A is a 8-bit register which is used to perform
arithmetical and logical operation. It stores the output of
any operation. It also works as registers for i/o accesses.

Temporary Register
It is a 8-bit register which is used to hold the data on which
the accumulator is computing operation. It is also called as
operand register because it provides operands to ALU.

35
 µPU Communication (Instruction-Cycle)

1.The μp placed a 16 bit memory address from PC

(program counter) to address bus.
– The high order address, 20H, is placed at A15 – A8.
– the low order address, 05H, is placed at AD7 - AD0
and ALE is active high.
– Synchronously the IO/M is in active low condition to
show it is a memory operation.

2.Then, active low control signal, RD, is activated so

as to activate read operation; it is to indicate that
the MPU is in fetch mode operation.
3. The active low RD signal enabled the byte
instruction, 4FH, to be placed on AD7 – AD0 and
transferred to the MPU. While RD high, the data
bus will be in high impedance mode.

4. The machine code, 4FH, will then be decoded in

instruction decoder. The content of accumulator
(A) will then copied into C register.
MPU Communication

Figure : Moving data form memory to MPU using instruction MOV C, A

(code machine 4FH = 0100 1111)
Internal Architecture of 8085
8085Single board Microcomputer
System