The National Higher School of Artificial Intelligence 2022/2023

Computer Architecture II Second Year

Assignment 04

True or false with explanation

The single cycle datapath makes use of all hardware units for each instruction.
False. All units are active in each cycle, but their output may be ignored (gated) by control signals.

It is possible to execute the stages of the single cycle datapath in parallel to speed up execution of a
single instruction.
False. Each stage depends on the value produced by the stage before it (e.g., instruction decode
depends on the instruction fetched).

If the delay of reading from IMEM is reduced, then any (non-empty) program using the single cycle
datapath will speed up.
True. Since every instruction must read from IMEM during the instruction fetch stage, making the IMEM
faster will speed up every single instruction.

The control signals used throughout all datapath stages to guide a correct ’execution line’ all come from
decoding an instruction’s unique binary encoding only.
False. PCSel is used to determine what instruction will be executed next, which is not immediately
known for a branch instruction. This is discovered in the Branch Comparator after the register values
are retrieved from the RegFile. The comparator then produces the BrEq (branch equal) and BrLt (branch
less than) flags, which are used in the control logic with the instruction encoding to produce the PCSel
signal.

Storing instructions and loading instructions are the only instructions that require input/output from
DMEM.
True. For all other instructions, we don’t need to read the data that is read out from DMEM, and thus
don’t need to wait for the output of the MEM stage.

It is possible to use both the output of the immediate generator and the value in register rs2.
False. You may only use either the immediate generator or the value in register rs2. Notice in our
datapath, there is a mux with a signal (BSel) that decides whether we use the output of the immediate
generator or the value in rs2.

Exercise 01

Fill out the following table with the control signals for each instruction based on the datapath on the last
page. If the value of the signal does not affect the execution of an instruction, use the * (don’t care)
symbol to indicate this. If the value of the signal does affect the execution, but can be different depending
on the program, list all possible values (for example, for a signal with possible values of 0 and 1, write
0/1).
 The National Higher School of Artificial Intelligence 2022/2023
Computer Architecture II Second Year

BrEq BrLT PCSel ImmSel BrUn ASel BSel ALUSel MemRW RegWEn WBSel
add * * 0 (PC + 4) * * 0 (Reg) 0 (Reg) add 0 1 1 (ALU)

ori * * 0 I * 0 (Reg) 1 (Imm) or 0 1 1 (ALU)

lw * * 0 I * 0 (Reg) 1 (Imm) add 0 1 2 (MEM)

sw * * 0 S * 0 (Reg) 1 (Imm) add 1 0 *

beq 0/1 * 0/1 B * 1 (PC) 1 (Imm) add 0 0 *
jal * * 1 (ALU) J * 1 (PC) 1 (Imm) add 0 1 0 (PC + 4)
blt * 0/1 0/1 B 0 1 (PC) 1 (Imm) add 0 0 *

A state element is an element connected to the clock (denoted by a triangle at the bottom). The input
signal to each state element must stabilize before each rising edge.
• The critical path is the longest delay path between state elements in the circuit. The circuit cannot
be clocked faster than this, since anything faster would mean that the correct value is not guaranteed
to reach the state element in the alloted time. If we place registers in the critical path, we can shorten
the period by reducing the amount of logic between registers.

For this exercise, assume the delay for each stage in the datapath is as follows:
IF: 200 ps ID: 100 ps EX: 200 ps MEM: 200 ps WB: 100 ps

a) Mark the stages of the datapath that the following instructions use and calculate the total time
needed to execute the instruction.

IF ID EX MEM WB Total Time

add X X X X 600 ps
ori X X X X 600 ps
lw X X X X X 800
sw X X X X 700
beq X X X 500 ps
jal X X X X 600 ps
bltu X X X 500 ps
 The National Higher School of Artificial Intelligence 2022/2023
Computer Architecture II Second Year

b) Which instruction(s) exercise the critical path?

Load word (lw), which uses all 5 stages.

c) What is the fastest you could clock this single cycle datapath?
1/800 picoseconds = 1/ (800 ∗ 10−12 )seconds = 1, 250, 000, 000s−1 = 1.25GHz

d) Why is the single cycle datapath inefficient?

At any given time, most of the parts of the single cycle datapath are sitting unused. Also, even though not
every instruction exercises the critical path, the datapath can only be clocked as fast as the slowest
instruction.

e) How can you improve its performance?

Performance can be improved with pipelining, or putting registers between stages so that the amount of
combinational logic between registers is reduced, allowing for a faster clock time. We’ll talk more about this
next week!

Exercise 02
Consider the single cycle datapath as it relates to a new RISC-V instruction, memory add:

madd rd, rs, rt

The instruction does the following:

 Reads the value of memory at the address stored in rs.

 Adds the value in the register specified by rt to the memory value and stores the resulting value in
rd.

1) Write the Register Transfer Level (RTL) corresponding to madd rd, rs, rt
R[rd] = Mem[R[rs]] + R[rt];
PC = PC + 4;

2) Change as little as possible in the datapath below to enable madd. Draw your changes right in the
figure and list all your changes below. Your modification may use muxes, wires, constants, and
new control signals, but nothing else.

Solution:

a. Add a mux to select between A mux output and ALU output for addr into Data Mem.
b. Add a mux to select between A mux output and DataR output for top input into ALU.

We now want to set all the control lines appropriately. List what each signal should be, either by an
intuitive name or 0, 1, *(”don’t care”). Include any new control signals you added.

PCsel = 0 (pc+4); Immsel = *; RegWEn = 1; BrUn = *; BrEq = *; BrLt = *; Asel = 0; Bsel = 0; Alusel = add;
MemRW = 0 (Read); WBsel = 1;

For new control (a) & (b): Adrsel = 1 (A mux output); A2sel = 1 (DataR output);
 The National Higher School of Artificial Intelligence 2022/2023
Computer Architecture II Second Year

Exercise 03
We wish to introduce a new instruction into our RISC-V datapath. badd (branch and add). This
instruction is a conditional add instruction. The instruction works as follows.
if (R[rs1] > R[rs2]) {
R[rd]++
} else {
R[rd] = R[rd]
}
The instruction badd is encoded as follows:

0x10 rs2 rs1 0x0 = f3 rd 0001011

It combines the semantics of branch and R-type instruction

Given the single cycle datapath below, select the correct modifications in parts such that the datapath
executes correctly for this new instruction (and all other instructions!).

What is the logic for badd signal ?

 The National Higher School of Artificial Intelligence 2022/2023
Computer Architecture II Second Year

What is the number of registers badd needs to access in a single cycle ?

3
What is the RegWen signal for badd
0
What is the comparison logic we are interested in ?
EQ OR LT

Consider the following modifications to the Reg[] register file. Which configuration will allow this
instruction to execute correctly without breaking the execution of other instructions in our instruction
set?

What is ASel and BSel (2)

Don't care

What are the changes to mux-A: Which configuration will allow this instruction to execute correctly
without breaking the execution of other instructions in our instruction set?

B
 The National Higher School of Artificial Intelligence 2022/2023
Computer Architecture II Second Year

What are the changes to mux-B ? Which configuration will allow this instruction to execute correctly
without breaking the execution of other instructions in our instruction set?

B
The WBsel select is _____ ?
ALU

Exercise 04
We wish to introduce a new instruction into our RISC-V datapath. RELU . This is related to the relu
operation in assignment 3. The instruction works as follows.
# rd_rs2, is a register that acts as a source
# and destination register

RELU rd_rs2, offset(rs1)

if (0<=R[rd_rs2])
MEM[R[rs1]+offset] = R[rd_rs2]
else
MEM[RS[rs1]+offset] = 0
R[rd_rs2] = 0

It combines the semantics of branch, load and store.

 Like a load it performs arithmetic using the ALU for calculating R[rs1]+offset the memory
address to be modified.
 Like a store it updates the MEM[address] with a value (either rd or 0).
 Like a branch it performs comparison. However the operands used are different. In a typical
branch operation A<=B A is obtained from rs1 and B is obtained from rd_rs2. In RELU, A is
always 0 and B is rd_rs2.
 Typically, the branch comparison will modify PC. However, here the branch comparison
influences what value is stored to Memory, either R[rd_rs2] or 0.
 Further, the branch comparison influences the value of rd in a load operation, if the branch
comparison fails the R[rd_rs2] is 0.
Given the single cycle datapath below, select the correct modifications in parts such that the datapath
executes correctly for this new instruction (and all other instructions!). You can make the following
assumptions:

 We have a new control signal RELU which is 1 if the instruction being decoded is a RELU
 ALUsel is add when we have a RELU instruction
 The immediate generate sign extends the offset similar to load instructions.
 The National Higher School of Artificial Intelligence 2022/2023
Computer Architecture II Second Year

What type of instruction is RELU ?

I-type Load. 1 source, 1 destinaton, 1 immediate. However the instruction also uses rd as a rs2 for
branch comparisons and writing to memory. We use rd as rs2 since rs2 is the only register that is
forwarded to memory as well in stores.

Consider the following modifications to the source Reg[] inputs. Which configuration will allow this
instruction to execute correctly without breaking the ex-ecution of other instructions in our instruction
set?

A
 The National Higher School of Artificial Intelligence 2022/2023
Computer Architecture II Second Year

Consider the following modifications to the Branch. Which con-figuration will allow this instruction to
execute correctly without breaking the execution of other instructions in our instruction set? Branch
calculates A==B and A<B

Consider the following modifications to the DMEM inputs. Which configuration will allow this instruction
to execute correctly without breaking the execution of other instructions in our instruction set?

Consider the following modifications to the DMEM control signal. Which configuration will allow this
instruction to execute correctly without breaking the execution of other instructions in our instruction
set?

D
 The National Higher School of Artificial Intelligence 2022/2023
Computer Architecture II Second Year

Consider the following modifications to the WB . Which configuration will allow this instruction to
execute correctly

Consider the following modifications to the RegWEn mux inputs. Which configuration will allow this
instruction to execute correctly

What is the value of ASel?

What is the value of BSel?