FPGA Design_27_Spartran FPGA Implementation

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FPGA Implementation
Specification

RTL design and

Simulation

Logic Synthesis

Gate Level Simulation

ASIC Layout FPGA Implementation

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Why Top-Down?
• Design of complex systems
• Reduce time-to-market
• shorten the design verification loop
• focus on functionality
• Easier and cheaper to explore different design option

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RTL Design
• Characteristics
• fully clock driven RTL code with some behavioral constructs
• contain complete functional description
• cycle accurate
• Coding style
• structural description (component connections/net-list)
• data flow description (continuous assignment)
• RTL description (always block)
• combinational RTL
• sequential RTL

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Logic Synthesis
• Translate synthesizable RTL code to gate-level design
Always @(posedge clk) begin
if(sel1) begin
if(sel2)
out = in1 ;
else
out = in2 ;
else if(sel3)
if(sel4) Gate-level circuits
out = in3 ;
else
out = in4 ;
end
endmodule

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Structural Mapping

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Resource Sharing
• Example
if (op_code ==0)
r=a+c;
else
r=a+b;
• Sharing
• a single ALU for the two additions
• a MUX for the second input of the ALU
• No-Sharing
• two adders for the two additions
• an output MUX to select the output

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Register Inferencing
• Determines which signals must be preserved across cycle boundaries
• incomplete logic specification (missing branches)
• explicit register instantiation
• always @(posedge clk)
• signal used before assigned

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Two-level Logic Optimization
• AND-OR representations
• easy implementation as PLAs and PLDs
• a key optimization technique
• efficient algorithms and heuristics exist
• in commercial use for several years
• minimize the number of product terms
• Example
• F = XYZ + XY’Z’ + XY’Z + X’YZ + XYZ
• F = XY’ + YZ

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Multi-Level Logic Optimization
• Meet performance or area constraints through restructuring and
simplifications
• two-level minimization
• common factor extraction
• common expression resubstitution
• Trade-off between area and delay
• In commercial use for several years
• f1 = abcd+abce+ab’cd’+ab’c’d+a’c+cdf+abc’d’e’+ab’c’df’
• f2 = bdg + b’dfg + b’d’g+bd’eg

• f1 = c(a’+x)+ac’x’
• f2 = gx
• x = d(b+f) + d’(b’+e)

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Technology Mapping
• Translation of a technology independent representation of a circuit
into a circuit in a given technology with optimal cost
• Optimization criteria
• minimum area
• minimum delay
• meeting specified timing constraints
• meeting specified timing constraints with minimum area
• Usages
• Technology mapping after technology independent logic optimization

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Sample covers

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State Machine Synthesis
• Translate state table or graph
• state minimization
• state assignment to minimize the cost function
• Challenges
• state machine decomposition
• state assignment for performance
• state assignment for testability
• extract state graph from implementation

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Spartan II Features
◆ Plentiful logic and memory resources
• 15K to 200K system gates (up to 5,292 logic cells)
• Up to 57 Kb block RAM storage
◆ Flexible I/O interfaces
• From 86 to 284 I/Os
• 16 signal standards
◆ Advanced 0.25/0.22um 6-Layer Metal Process
◆ High performance
• System frequency as high as 200 MHz
◆ Advanced Clock Control with 4 Dedicated DLLs
◆ Unlimited Re-programmability
◆ Fully PCI Compliant

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Spartan-II Top-level Architecture
• Configurable logic blocks
• Implement logic here!
• I/O blocks
• Communicate with other chips
• Choose from 16 signal
standards
• Block RAM
• On-chip memory for higher
performance
Spartan-II Top-level Architecture
• Clocks and delay locked loops
• Synchronize to clock on and off
chip
• Rich interconnect resources
• Three-state internal buses
• Power down mode
• Lower quiescent power
 CLB Slice (Simplified)
• 1 CLB holds 2 slices
• Each slice contains two sets of
the following:
• Four-input LUT
• Any 4-input logic function
• Or 16-bit x 1 RAM
• Or 16-bit shift register
 CLB Slice (cont’d)
• Each slice contains two sets of
the following:
• Carry & control
• Fast arithmetic logic
• Multiplier logic
• Multiplexer logic
• Storage element
• Latch or flip-flop
• Set and reset
• True or inverted inputs
• Sync. or async. control
 Dedicated Expansion Multiplexers
• MUXF5 combines 2 LUTs to form
• 4x1 multiplexer
• Or any 5-input function CLB

Slice
• MUXF6 combines 2 slices to
form LUT MUXF6

• 8x1 multiplexer
LUT
• Or any 6-input function MUXF5

Slice

LUT

LUT
MUXF5
 I/O Block (Simplified)

• Registered input, output, 3-state control

• Programmable slew rate, pull-up, pull-down, keeper and input delay

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 I/O Interface Standards

• I/O can be programmed for 16 different signal standards

• VCCO controls maximum output swing
• VREF sets input, output, three-state control
• Different banks can support different standards at the same time
• Logic level translation
• Boards with mixed standards

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IOBs Organized As Independent Banks
• As many as eight banks on a
device
• Package dependent
• Each bank can be assigned any
of the 16 signal standards
 High Performance Routing
• Hierarchical routing
• Singles, hexes, longs
• Sparse connections on longer
interconnects for high speed
• Routing delay depends primarily
on distance 2ns
• Direction independent
• Device-size independent
• Predictable for early design
analysis

CLB Array
Power-down Mode
• Controlled by single power down pin
• All inputs blocked, appear low internally
• All outputs disabled
• All register states preserved
• Power-down status pin
• Synchronous wake up
• 100 uA typical

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Configuration Modes
Config. Direction of
Data Synchronizing
Mode Format Clock Use
Slave Serial FPGA receives • Processor or CPLD or another FPGA ( in Master
Serial CCLK mode) controls configuration of slave FPGA
• Also for configuring multiple slave FPGAs in a
daisy chain (2ND, 3RD FPGA, etc.).
Master Serial FPGA generates • FPGA in Master mode configures itself from a
Serial CCLK serial PROM.
• Also, 1st FPGA (master) in daisy chain controls
configuration of slave FPGA(s) in a daisy chain.
Slave Byte FPGA receives Processor or CPLD controls the fast configuration of
Parallel CCLK slave FPGA.

JTAG Serial FPGA receives Make use of existing boundary scan port
TCK

There are four ways to program a Spartan-II FPGA

Spartan-II Family Overview
Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200
Logic Cells 432 972 1728 2700 3888 5292
Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344
Block RAM Qty. 4 6 8 10 12 14
Max. User I/Os 86 132 176 196 260 284
Package VQ100 VQ100
CS144 CS144
TQ144 TQ144 TQ144 TQ144
PQ208 PQ208 PQ208 PQ208 PQ208
FG256 FG256 FG256 FG256
FG456 FG456 FG456

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Spartan-II Architecture Summary

◆ Delivers all the key requirements for ASIC replacement

• 200,000 gates
• 200 MHz
• Flexible I/O interfaces
• On-chip distributed and block RAM
• Clock management
• Low power
• Complete development system support

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 Design Tools
• Standard CAE entry and verification tools
• Xilinx Implementation software implements the
design
• The design is optimized for best performance and minimal
size
• Graphical User Interface and Command Line Interface
• Easy access to other Xilinx programs
• Manages and tracks design revisions
Foundation Functional Simulation
or Alliance Design Simulator
Entry
Back Annotation
Schematic, State Mach., HDL Verification
Code, LogiBLOX, CORE Gen

Static Timing Analysis,

M1 Design Manager In-Circuit Testing
Xilinx Design Implementation

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Foundation Project Manager
• Integrates all tools into one environment

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Schematic Entry

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ABEL, Verilog and VHDL Text Entry
• From schematic menu (or
via HDL Editor), select
Hierarchy -> New Symbol
Wizard… to create symbol.
• Select HDL Editor &
Language Assistant to learn
1 by example, then define
block.
• Synthesize to EDIF.

2 5
4

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State Machine Graphical Editor

Graphical editor synthesizes into ABEL or VHDL code

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 Simulation - Easy to Use and Learn
• Generate stimulus
easily and quickly
– Keyboard toggling
– Simple clock stimulus
– Custom formulas
• Easy debugging
– Waveform viewer
– Signals easily added and
removed
– Simulator access from
schematic
– Color-coded values on
schematic
• Script Editor

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What is Implementation?
• More than just “Place & Route”
• Implementation includes many phases
• Translate: Merge multiple design files into a single netlist
• Map: Group logical symbols from the netlist (gates) into physical components
(CLBs and IOBs)
• Place & Route: Place components onto the chip, connect them, and extract
timing data into reports
• Timing (Sim): Generate a back-annotated netlist for timing simulation tools
• Configure: Generate a bitstream for device configuration

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Terminology
• Project
• Source file; has a defined working directory and family
• Version
• A Xilinx netlist translation of the schematic
• Multiple Versions result from iterative schematic changes
• Revision
• An implementation of a Xilinx netlist
• Multiple revisions typically result from different options
• Part type
• Specified at translation; can be changed in a new revision

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Starting the Flow Engine
Foundation Project Manager

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 The Flow Engine
Implementation
phases

Implementation
status

Message area

Flow control buttons

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XSA-50 Board
• Xilinx XC2S50
• 7-seg LED
• 100 MHz prog. osc.
• SDRAM
• 8M*8
• Flash
• 128K bytes
• XC9572XL
• Parallel port
• PS/2 port
• VGA port

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Xstend Board
• 2 7-seg LED
• Bargraph LED
• Dip switch
• Pushbuttons
• Stereo Audio I/O
• RS-232
• USB 1.1

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Lab 4: 7-Segment Decoder
• input [3:0] sig ; // 0-F
• output [6:0] control ; // active high
a LED1 LED 2
f b a 56 48
g
b 51 27
e c
d
c 65 40
d 64 47
e 76 28
f 54 42
g 50 29

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4-bit Magnitude Comparator
• input [3:0] a, b ; • XSA-50 board SW1
S1 Pin
• input agb, alb, aeb ; SW1 Pin
Number
• 11 input pins 1
Number
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• XSTend Board S1 2
1 54
58
2 64
3 74
3 63
4 75
4 56
5 66
6 77
7 80
8 79

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4-bit Magnitude Comparator
Pin
Number
• output agbo, albo, aebo ;
D1 68
• Use XSTend Board
• Bar LEDs D2 44
D3 46
D4 49
D5 57
D6 62
D7 60
D8 67
D9 39
D10 59

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Thank You

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