High Temperature CMOS Process with Dielectric Isolation
Uwe Paschen, Dirk Dittrich, Holger Vogt, Norbert Kordas
Fraunhofer Institute of Microelectronic Circuits and Systems,
Finkenstr. 61, D-47057 Duisburg, Germany
email: paschen@ims.fhg.de
Abstract
The temperature range required for many demanding
modern applications exceeds by far the maximum
operation temperature of devices fabricated with
standard CMOS processes. In order to increase the
temperature range while still using existing designs and
cell libraries we employed a process with complete
dielectric isolation between well and substrate that is
fully compatible with the underlying CMOS process. An
Analog-to-Digital converter was designed und
fabricated in both the high temperature process and in
the standard process for comparison. The performance
of the circuit and its temperature dependence was
investigated.
1. Introduction
The maximum operation temperature for standard CMOS
devices usually does not exceed 125°C. However, a
variety of applications require significantly higher
operation temperatures. Especially temperature ranges of
up to 180°C are very interesting since they enable new
concepts in the automotive field (sensor applications,
motor management). Above 125°C, however, leakage
currents in bulk CMOS processes become so large that
circuits do not work reliably or are at least severely
limited in performance. Especially the leakage currents
of the substrate/well diodes in the circuit which are
strongly temperature dependent play a dominant
detrimental role. These leakage currents can be avoided
entirely by realizing a dielectric isolation between the n-
wells and the p-substrate [1,2,3], thus extending the
useable temperature range. Another significant advantage
of the dielectric isolation is the complete suppression of
parasitic bipolar effects (latch-up), especially in
electrically harsh environments like automotive
applications or motor drivers.
At IMS we have developed a CMOS process on SOI
substrate and verified its high temperature performance
with mixed signal circuits.
The paper is organized as follows. First we present an
overview of the technological steps employed to realize a
CMOS process with dielectric isolation (SOI wafers
together with trench isolation). Secondly, we compare
measurements of the devices fabricated on SOI with
those of the standard CMOS process. Following that we
briefly describe an Analog to Digital converter (ADC) as
an example for a successful application of this technique
and present some experimental data where the ADC
performance is compared between circuits employing
bulk and SOI technology, respectively.
2. Technology
Bonded SOI (BSOI) wafers are used to provide
dielectric isolation and thus suppress the well/substrate
diode leakage current entirely. The buried oxide layer
provides the vertical isolation between the n-well and the
substrate. An additional lateral isolation is established by
trenches which are etched down to the buried oxide layer
around each well and filled with an insulating material.
Subsequently, the standard process (a 1.2µm process
with high voltage capability in this case) is used to
fabricate the CMOS circuits (Figure 1). Table 1 gives an
overview of the schematic process flow for the trench
module.
A hard mask is used since resist masks would limit the
maximum trench depth to a value well below the silicon
film thickness of 4 micron. The hard mask is deposited
and then structured with a resist mask. After removal of
the resist the hard mask is used for the trench etch. The
shape of the trench must be controlled carefully in order
to enable a void free trench fill afterwards. The following
dielectric trench fill is achieved by a wet oxidation and a
Source Gate Drain
Well
p+ p+ n+
n-well
Trench
Buried oxide
Fig. 1: Pmos transistor in n-well with complete
dielectric isolation
Table 1: Process flow for the trench module sufficient distance between the trenches and
neighbouring active areas. Therefore, existing designs
1 Hard mask deposition
can easily be fabricated with the BSOI process without
2 Resist deposition and any layout modifications except the addition of the
patterning trench mask.
3 Etch of trench hard mask While the transistor parameters are identical for both
4 Resist strip substrate types the important advantage of the BSOI
5 Trench etch process with trench isolation is the complete suppression
6 Field oxidation of the leakage currents of the well-to-substrate diode.
7 Removal of mask strip The temperature dependence of the well-to-substrate
8 Deposition of polysilicon diodes leakage currents in bulk wafers is depicted in
9 Polysilicon back etch Figure 4 for a diode area of 3200µm2. Since in a typical
10 CMOS process sequence

1,0E-02
subsequent polysilicon deposition. The polysilicon is
then etched back until it is completely removed from the 1,0E-03
surface. The overetch must be carefully minimised in
1,0E-04
order to yield a smooth surface with a minimum of
topography for the following process steps. Figure 2 1,0E-05
shows the trench structure on BSOI after field oxidation, drain current [A]
1,0E-06
polysilicon deposition and back etch.
After the completion of the trench module the CMOS 1,0E-07
process sequence to integrate the devices in the silicon 1,0E-08
film follows. No modifications of the standard process
flow are necessary. Since the trench module is realized in 1,0E-09
Epi w afer: T=25°C
advance of the CMOS part, it has no influence on the 1,0E-10
SOI w afer: T=25°C
active transistor parameters or on the field devices. As an
example the comparison of the weak inversion curves are 1,0E-11 Epi w afer: T=180°C
SOI w afer: T=180°C
shown in Figure 3 for a 1.2µm pmos transistor on bulk 1,0E-12
and SOI wafers at temperatures of 25 and 180°C,
1,0E-13
respectively. With increasing temperature the transistors
in both substrate types exhibit the usual decrease of 1,0E-14
threshold voltage and subthreshold slope as well as the 0 1 2 3 4 5
increase in off-state current. The important point is that
no significant difference for any electrical parameter of gate voltage [V]
the devices in the two substrate types occurs which is
essential for the simple transfer of circuit designs from Fig. 3: Drain current of pmos (W/L=20/1.2) at room
the bulk CMOS process to the SOI process. The reason temperature and 180°C for epi and SOI wafer.
for this indifference of the device parameters to the
dielectric isolation is the large film thickness and 1,0E-06

1,0E-07

1,0E-08
leakage current [A]

1,0E-09

1,0E-10

1,0E-11

1,0E-12

1,0E-13

1,0E-14
0 50 100 150 200
T [°C]

Fig. 4: Temperature dependence of the leakage

current of the well-to-substrate diode for bulk
wafers. The diode area is 3200µm2. This leakage
Fig. 2: Trench for lateral isolation after sidewall
current is suppressed completely on the SOI wafer.
oxidation and polysilicon fill
CMOS circuit the total area of the well-to-substrate
diodes is of the order of 50% of the chip size
considerable leakage currents occur at elevated
temperatures. The dielectric isolation is of special
importance for analog and particularly switched
capacitor circuits where poly/n+ capacitors are used.
With the n+ electrode placed inside of a well area the
charge loss by leakage currents at high temperatures is
completely avoided. This is a major reason for the
improved high temperature performance of analog
CMOS circuits fabricated with the SOI process.
3. High Temperature Operation of an
Analog to Digital Converter
Thus, the desired number of bits is generated serially.
The concept theoretically allows the conversion with an
unlimited number of bits, however, influences from
various parameters and from matching behaviour of the
elements limit the resolution of the converter. In this
case, a 10 bit resolution was realized.
The resulting circuit is shown in the block diagram in
Figure 5. The A/D-converter has 8 analog inputs, two of
them for internal voltages and 6 available from outside.
The reference voltage of 2.5 volts is also available at an
output pin for the use with further ASICs of the system.
An on-chip temperature sensor gives information about
the ASIC’s temperature and also generates a switch-off
signal at 110°C for external use. Table 2 lists the key
features of the IC.

Although a large variety of electronic systems have Table 2: Key features of the AD converter at room
been developed for various applications in the temperature
automotive field, some modules had to be left out so far.
The main reason for this is that due to the high resolution 10 Bits
temperatures it was not possible to get direct access to input range 0.1 – 4.9 V
some sub-systems because standard electronic devices
conversion time 1 ms
fail to work at high temperatures. The ADC discussed in
reference voltage 2.5 V
this paper is part of a larger system aimed to provide a
linearity 0.2 Bit
means to electronically measure the oil quality in the
resolution of temp. sensor 0.25 °C
engine of a car. Not only for reliability and safety
reasons, but also for the reduction of cost information temp. switch-off level 110 °C
about viscosity, conductivity and dielectrical behaviour
is highly desirable. An optimal use of the life span of the After the completion of the layout the trench layer was
motor oil can only be achieved if these parameters are generated from the n-well mask data. For a comparison
available for the motor management system. The whole of performance ADC circuits were fabricated on Bulk-
oil sensor module consists of a number of components. silicon and BSOI substrates and characterized at room
An interdigital capacitor type sensor is responsible for temperature and 180°C. The results of the ADC
the measurement of the oil’s conductivity and dielectrical resolution are depicted in Table 3.
constant. A second sensor realized in the form of a At low temperatures the performance of the devices
surface acoustic wave sensor yields information about on the two substrate types was identical, i.e. the modified
the viscosity of the oil. An Analog to Digital converter is process and the different substrate did not change the
used to transform all sensor signals and an additional functionality and performance of the circuit. This
temperature signal into a digital format. The interface is demonstrates that standard CMOS designs can easily be
of a simple SPI-type allowing configuration and data fabricated in the high temperature process without
transfer with a high noise immunity. special adaptions. At elevated temperatures, however, it
The Analogue to Digital converter [4,5] with 10 bit
resolution at room temperature was designed with the
Digital Communication
design setup of the standard CMOS process. The
converter uses a cyclic principle for the generation of the
digital output. The analog voltage at the input is Oscillator SPI - Interface
compared with a reference voltage, which is half of the A/D-
supply voltage. By use of a comparator, a decision is Converter
Kernel
made whether the input voltage is above or below the Test-
reference voltage. In the first case, the most significant Interface
bit (MSB) is set „high“, if not, the MSB is „low“. In the
Temp.
next step, in the case of a „high“-bit, the reference Shutdown
voltage is subtracted from the input voltage and the Voltage
Reference Input - Multiplexer Temperature-
remainder is amplified by a factor of two. If the bit was Sensor
„low“, only the amplification by two is performed
without subtraction of the reference voltage. The Analog Inputs
amplified voltage is then applied to the converter’s input
as a new input voltage and the procedure is repeated.
Fig. 5: Schematic circuit diagram of the ADC
 Table 3: Temperature dependence of the ADC Acknowledgements
resolution
Financial support for this project from the Bayerische
Temperature ADC accuracy ADC accuracy Forschungsstiftung is gratefully acknowledged.
Epi wafer SOI wafer
25° C 10 bit 10 bit
180 °C 5-6 bit 9 bit References
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the use of dielectric isolation.