ELET 232

APPENDIX B

MODEL PROJECT
 LAB MANUAL
APPENDIX-B: MODEL PROJECT

PROBLEM STATEMENT
Design an asynchronous lock operated by five input buttons labelled A, B, C, D, and R (the Reset
button). The unlocking operation can only take place if only one button is activated at a time and in
order B, D, A, C. Draw a state diagram and develop a logic circuit. Verify your design in MULTISIM
before submission.

SAFETY WARNING / CAUTION

Save your work frequently and take regular backups of important code.
Always create a new folder whenever you start work on a new project. Terrible things go
wrong if you attempt to store more than one project in the same directory!
Never make any connection(s) when power is ON!
The power should be turned off after completing each individual measurement

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LAB MANUAL
APPENDIX-B: MODEL PROJECT

SOLUTION

STATE-DIAGRAM

Lock=0 Lock=0
S0 S1
(000 (001 D=C=B=A=0
D=0
) C=0 )
D=C=B=A=0 B=1
A=0 D=1
C=0
B=0
A=0
@ RESET=1,
All others Lock=0
S2
DEFAULT STATE (010 D=C=B=A=0
=
S0
)
Reset=1
D=0
C=0
D=0 B=0
C=1 A=1
Lock=1
B=0
S4 A=0 S3
D=X
C=X (100 (011 D=C=B=A=0
B=X ) Lock=0 )
A=X

ELET 232 - DIGITAL ELECTRONICS II 223

 LAB MANUAL
APPENDIX-B: MODEL PROJECT

STATE-TABLE

D C B A P.State N.State Lock D2D1D0

S0
0 0 0 0 ooo ooo o ooo
0 0 0 1 ooo ooo o ooo
0 0 1 0 ooo ooI o ooI
0 0 1 1 ooo ooo o ooo
0 1 0 0 ooo ooo o ooo
0 1 0 1 ooo ooo o ooo
0 1 1 0 ooo ooo o ooo
0 1 1 1 ooo ooo o ooo
1 0 0 0 ooo ooo o ooo
1 0 0 1 ooo ooo o ooo
1 0 1 0 ooo ooo o ooo
1 0 1 1 ooo ooo o ooo
1 1 0 0 ooo ooo o ooo
1 1 0 1 ooo ooo o ooo
1 1 1 0 ooo ooo o ooo
1 1 1 1 ooo ooo o ooo

D C B A P.State N.State Lock D2D1D0

S1
0 0 0 0 ooI ooI o ooI
0 0 0 1 ooI ooo o ooo
0 0 1 0 ooI ooo o ooo
0 0 1 1 ooI ooo o ooo
0 1 0 0 ooI ooo o ooo
0 1 0 1 ooI ooo o ooo
0 1 1 0 ooI ooo o ooo
0 1 1 1 ooI ooo o ooo
1 0 0 0 ooI oIo o oIo
1 0 0 1 ooI ooo o ooo
1 0 1 0 ooI ooo o ooo
1 0 1 1 ooI ooo o ooo
1 1 0 0 ooI ooo o ooo
1 1 0 1 ooI ooo o ooo
1 1 1 0 ooI ooo o ooo
1 1 1 1 ooI ooo o ooo

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D C B A P.State N.State Lock D2D1D0

S2
0 0 0 0 oIo oIo o oIo
0 0 0 1 oIo oII o oII
0 0 1 0 oIo ooo o ooo
0 0 1 1 oIo ooo o ooo
0 1 0 0 oIo ooo o ooo
0 1 0 1 oIo ooo o ooo
0 1 1 0 oIo ooo o ooo
0 1 1 1 oIo ooo o ooo
1 0 0 0 oIo ooo o ooo
1 0 0 1 oIo ooo o ooo
1 0 1 0 oIo ooo o ooo
1 0 1 1 oIo ooo o ooo
1 1 0 0 oIo ooo o ooo
1 1 0 1 oIo ooo o ooo
1 1 1 0 oIo ooo o ooo
1 1 1 1 oIo ooo o ooo

D C B A P.State N.State Lock D2D1D0

S3
0 0 0 0 oII oII o oII
0 0 0 1 oII ooo o ooo
0 0 1 0 oII ooo o ooo
0 0 1 1 oII ooo o ooo
0 1 0 0 oII Ioo o Ioo
0 1 0 1 oII ooo o ooo
0 1 1 0 oII ooo o ooo
0 1 1 1 oII ooo o ooo
1 0 0 0 oII ooo o ooo
1 0 0 1 oII ooo o ooo
1 0 1 0 oII ooo o ooo
1 0 1 1 oII ooo o ooo
1 1 0 0 oII ooo o ooo
1 1 0 1 oII ooo o ooo
1 1 1 0 oII ooo o ooo
1 1 1 1 oII ooo o ooo

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APPENDIX-B: MODEL PROJECT

D C B A P.State N.State Lock D2D1D0

S4
0 0 0 0 Ioo Ioo I Ioo
0 0 0 1 Ioo Ioo I Ioo
0 0 1 0 Ioo Ioo I Ioo
0 0 1 1 Ioo Ioo I Ioo
0 1 0 0 Ioo Ioo I Ioo
0 1 0 1 Ioo Ioo I Ioo
0 1 1 0 Ioo Ioo I Ioo
0 1 1 1 Ioo Ioo I Ioo
1 0 0 0 Ioo Ioo I Ioo
1 0 0 1 Ioo Ioo I Ioo
1 0 1 0 Ioo Ioo I Ioo
1 0 1 1 Ioo Ioo I Ioo
1 1 0 0 Ioo Ioo I Ioo
1 1 0 1 Ioo Ioo I Ioo
1 1 1 0 Ioo Ioo I Ioo
1 1 1 1 Ioo Ioo I Ioo

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APPENDIX-B: MODEL PROJECT

LOGIC FUNCTIONS:

Flip-flop = D-type
State: Q2Q1Q0
Output=Lock
Inputs= D, C, B, A

D C B A P.State N.State Lock D2D1D0

0 0 1 0 ooo ooI o ooI

0 0 0 0 ooI ooI o ooI

1 0 0 0 ooI oIo o oIo

0 0 0 0 oIo oIo o oIo

0 0 0 1 oIo oII o oII

0 0 0 0 oII oII o oII

0 1 0 0 oII Ioo o Ioo

x x x x Ioo Ioo I Ioo

D0= D’C’BA’Q2’Q1’Q0’ + D’C’B’A’Q2’Q1’Q0 +

D’C’B’AQ2’Q1Q0’ + D’C’B’A’Q2’Q1Q0

D1= DC’B’A’Q2’Q1’Q0 + D’C’B’A’Q2’Q1Q0’ +

D’C’B’AQ2’Q1Q0’ + D’C’B’A’Q2’Q1Q0

D2=D’CB’A’Q2’Q1Q0 + Q2Q1’Q0’

Lock=Q2Q1’Q0’

Simplified functions:

Lock=Q2Q1’Q0’

D0= D’C’A’Q2’Q1’ (BQ0’ + B’Q0) + D’C’B’ Q2’Q1 (AQ0’ + A’Q0)

D1= C’B’A’Q2’ (DQ1’Q0 + D’Q1Q0’) + D’C’B’Q2’Q1 (AQ0’ + A’Q0)

D2=D’CB’A’Q2’Q1Q0 + Lock

Realization:
Construct state machine circuit in MULTISIM, and verify the design behaviour as per given specs in
the problem statement.

Hint: Get three D- flip flops, five toggle switches, and four lamps.

ELET 232 - DIGITAL ELECTRONICS II 227

 LAB MANUAL
APPENDIX-B: MODEL PROJECT

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LAB MANUAL
APPENDIX-B: MODEL PROJECT

MULTISIM DESIGN REALIZATION

Dn

Cn
X3 X1 X2
Bn
2.5 V 2.5 V 2.5 V An

U7A U5A U4A U3A

7404N 7404N 7404N 7404N
VCC
5V
VCC

D
4 U1A 4 U2A C
XFG1 D2 4 U6A D1 D0
Q2 ~1PR Q1 ~1PR Q0 X9 X7
~1PR
2 1Q 5 2 1Q 5
B
2
1D 1D X8
1D 1Q 5
2.5 V 2.5 V X6 A
3 ~1Q 6
Q1n 3 ~1Q 6
Q0n
0 4 3 Q2n 1CLK 1CLK 2.5 V
1CLK ~1Q 6
~1CLR ~1CLR 2.5 V
~1CLR
1 74LS74N 1 74LS74N
1 74LS74N J1 J3 J4 J5
VCC
5V
Key = D Key = C Key = B Key = A
VCC0
J6
7
Key = R
0

X4 Dn U10
Cn
An U21A
2.5 V 37
Q2n D0
U8A Q1n
Q2 U14A Lock B
Q1n Q0n 7410N
Q0n
74LS30N
7410N
7410N 38
1 U17
Dn
Dn U37 Cn
U15A An
C
Bn D2 Q2n
2 Q1n
An Bn
Q2n 7410N U11 Q0
Q1
Q0 Dn 74LS30N
Cn
74LS30N Bn
Q2n
U20A Q1
A
3
Q0 XXX
74LS30N
7486N Cn U12
Bn U9A
An
5 D1
Q2n
D
Q1n 7410N
Q0
74LS30N
6

Cn U13
Bn
An
Q2n
Dn
Q1
Q0n
74LS30N

For details of this realization, refer to

the state-tables and the logic functions
next.
ELET 232 - DIGITAL ELECTRONICS II 229